linux/arch/powerpc/include/asm/ppc-opcode.h
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   1/*
   2 * Copyright 2009 Freescale Semiconductor, Inc.
   3 *
   4 * This program is free software; you can redistribute it and/or
   5 * modify it under the terms of the GNU General Public License
   6 * as published by the Free Software Foundation; either version
   7 * 2 of the License, or (at your option) any later version.
   8 *
   9 * provides masks and opcode images for use by code generation, emulation
  10 * and for instructions that older assemblers might not know about
  11 */
  12#ifndef _ASM_POWERPC_PPC_OPCODE_H
  13#define _ASM_POWERPC_PPC_OPCODE_H
  14
  15#include <linux/stringify.h>
  16#include <asm/asm-compat.h>
  17
  18#define __REG_R0        0
  19#define __REG_R1        1
  20#define __REG_R2        2
  21#define __REG_R3        3
  22#define __REG_R4        4
  23#define __REG_R5        5
  24#define __REG_R6        6
  25#define __REG_R7        7
  26#define __REG_R8        8
  27#define __REG_R9        9
  28#define __REG_R10       10
  29#define __REG_R11       11
  30#define __REG_R12       12
  31#define __REG_R13       13
  32#define __REG_R14       14
  33#define __REG_R15       15
  34#define __REG_R16       16
  35#define __REG_R17       17
  36#define __REG_R18       18
  37#define __REG_R19       19
  38#define __REG_R20       20
  39#define __REG_R21       21
  40#define __REG_R22       22
  41#define __REG_R23       23
  42#define __REG_R24       24
  43#define __REG_R25       25
  44#define __REG_R26       26
  45#define __REG_R27       27
  46#define __REG_R28       28
  47#define __REG_R29       29
  48#define __REG_R30       30
  49#define __REG_R31       31
  50
  51#define __REGA0_0       0
  52#define __REGA0_R1      1
  53#define __REGA0_R2      2
  54#define __REGA0_R3      3
  55#define __REGA0_R4      4
  56#define __REGA0_R5      5
  57#define __REGA0_R6      6
  58#define __REGA0_R7      7
  59#define __REGA0_R8      8
  60#define __REGA0_R9      9
  61#define __REGA0_R10     10
  62#define __REGA0_R11     11
  63#define __REGA0_R12     12
  64#define __REGA0_R13     13
  65#define __REGA0_R14     14
  66#define __REGA0_R15     15
  67#define __REGA0_R16     16
  68#define __REGA0_R17     17
  69#define __REGA0_R18     18
  70#define __REGA0_R19     19
  71#define __REGA0_R20     20
  72#define __REGA0_R21     21
  73#define __REGA0_R22     22
  74#define __REGA0_R23     23
  75#define __REGA0_R24     24
  76#define __REGA0_R25     25
  77#define __REGA0_R26     26
  78#define __REGA0_R27     27
  79#define __REGA0_R28     28
  80#define __REGA0_R29     29
  81#define __REGA0_R30     30
  82#define __REGA0_R31     31
  83
  84/* opcode and xopcode for instructions */
  85#define OP_TRAP 3
  86#define OP_TRAP_64 2
  87
  88#define OP_31_XOP_TRAP      4
  89#define OP_31_XOP_LWZX      23
  90#define OP_31_XOP_DCBST     54
  91#define OP_31_XOP_LWZUX     55
  92#define OP_31_XOP_TRAP_64   68
  93#define OP_31_XOP_DCBF      86
  94#define OP_31_XOP_LBZX      87
  95#define OP_31_XOP_STWX      151
  96#define OP_31_XOP_STBX      215
  97#define OP_31_XOP_LBZUX     119
  98#define OP_31_XOP_STBUX     247
  99#define OP_31_XOP_LHZX      279
 100#define OP_31_XOP_LHZUX     311
 101#define OP_31_XOP_MFSPR     339
 102#define OP_31_XOP_LHAX      343
 103#define OP_31_XOP_LHAUX     375
 104#define OP_31_XOP_STHX      407
 105#define OP_31_XOP_STHUX     439
 106#define OP_31_XOP_MTSPR     467
 107#define OP_31_XOP_DCBI      470
 108#define OP_31_XOP_LWBRX     534
 109#define OP_31_XOP_TLBSYNC   566
 110#define OP_31_XOP_STWBRX    662
 111#define OP_31_XOP_LHBRX     790
 112#define OP_31_XOP_STHBRX    918
 113
 114#define OP_LWZ  32
 115#define OP_LD   58
 116#define OP_LWZU 33
 117#define OP_LBZ  34
 118#define OP_LBZU 35
 119#define OP_STW  36
 120#define OP_STWU 37
 121#define OP_STD  62
 122#define OP_STB  38
 123#define OP_STBU 39
 124#define OP_LHZ  40
 125#define OP_LHZU 41
 126#define OP_LHA  42
 127#define OP_LHAU 43
 128#define OP_STH  44
 129#define OP_STHU 45
 130
 131/* sorted alphabetically */
 132#define PPC_INST_BHRBE                  0x7c00025c
 133#define PPC_INST_CLRBHRB                0x7c00035c
 134#define PPC_INST_DCBA                   0x7c0005ec
 135#define PPC_INST_DCBA_MASK              0xfc0007fe
 136#define PPC_INST_DCBAL                  0x7c2005ec
 137#define PPC_INST_DCBZL                  0x7c2007ec
 138#define PPC_INST_ICBT                   0x7c00002c
 139#define PPC_INST_ICSWX                  0x7c00032d
 140#define PPC_INST_ICSWEPX                0x7c00076d
 141#define PPC_INST_ISEL                   0x7c00001e
 142#define PPC_INST_ISEL_MASK              0xfc00003e
 143#define PPC_INST_LDARX                  0x7c0000a8
 144#define PPC_INST_LSWI                   0x7c0004aa
 145#define PPC_INST_LSWX                   0x7c00042a
 146#define PPC_INST_LWARX                  0x7c000028
 147#define PPC_INST_LWSYNC                 0x7c2004ac
 148#define PPC_INST_SYNC                   0x7c0004ac
 149#define PPC_INST_SYNC_MASK              0xfc0007fe
 150#define PPC_INST_LXVD2X                 0x7c000698
 151#define PPC_INST_MCRXR                  0x7c000400
 152#define PPC_INST_MCRXR_MASK             0xfc0007fe
 153#define PPC_INST_MFSPR_PVR              0x7c1f42a6
 154#define PPC_INST_MFSPR_PVR_MASK         0xfc1fffff
 155#define PPC_INST_MFTMR                  0x7c0002dc
 156#define PPC_INST_MSGSND                 0x7c00019c
 157#define PPC_INST_MSGCLR                 0x7c0001dc
 158#define PPC_INST_MSGSNDP                0x7c00011c
 159#define PPC_INST_MTTMR                  0x7c0003dc
 160#define PPC_INST_NOP                    0x60000000
 161#define PPC_INST_POPCNTB                0x7c0000f4
 162#define PPC_INST_POPCNTB_MASK           0xfc0007fe
 163#define PPC_INST_POPCNTD                0x7c0003f4
 164#define PPC_INST_POPCNTW                0x7c0002f4
 165#define PPC_INST_RFCI                   0x4c000066
 166#define PPC_INST_RFDI                   0x4c00004e
 167#define PPC_INST_RFMCI                  0x4c00004c
 168#define PPC_INST_MFSPR_DSCR             0x7c1102a6
 169#define PPC_INST_MFSPR_DSCR_MASK        0xfc1fffff
 170#define PPC_INST_MTSPR_DSCR             0x7c1103a6
 171#define PPC_INST_MTSPR_DSCR_MASK        0xfc1fffff
 172#define PPC_INST_MFSPR_DSCR_USER        0x7c0302a6
 173#define PPC_INST_MFSPR_DSCR_USER_MASK   0xfc1fffff
 174#define PPC_INST_MTSPR_DSCR_USER        0x7c0303a6
 175#define PPC_INST_MTSPR_DSCR_USER_MASK   0xfc1fffff
 176#define PPC_INST_SLBFEE                 0x7c0007a7
 177
 178#define PPC_INST_STRING                 0x7c00042a
 179#define PPC_INST_STRING_MASK            0xfc0007fe
 180#define PPC_INST_STRING_GEN_MASK        0xfc00067e
 181
 182#define PPC_INST_STSWI                  0x7c0005aa
 183#define PPC_INST_STSWX                  0x7c00052a
 184#define PPC_INST_STXVD2X                0x7c000798
 185#define PPC_INST_TLBIE                  0x7c000264
 186#define PPC_INST_TLBILX                 0x7c000024
 187#define PPC_INST_WAIT                   0x7c00007c
 188#define PPC_INST_TLBIVAX                0x7c000624
 189#define PPC_INST_TLBSRX_DOT             0x7c0006a5
 190#define PPC_INST_XXLOR                  0xf0000510
 191#define PPC_INST_XXSWAPD                0xf0000250
 192#define PPC_INST_XVCPSGNDP              0xf0000780
 193#define PPC_INST_TRECHKPT               0x7c0007dd
 194#define PPC_INST_TRECLAIM               0x7c00075d
 195#define PPC_INST_TABORT                 0x7c00071d
 196
 197#define PPC_INST_NAP                    0x4c000364
 198#define PPC_INST_SLEEP                  0x4c0003a4
 199#define PPC_INST_WINKLE                 0x4c0003e4
 200
 201/* A2 specific instructions */
 202#define PPC_INST_ERATWE                 0x7c0001a6
 203#define PPC_INST_ERATRE                 0x7c000166
 204#define PPC_INST_ERATILX                0x7c000066
 205#define PPC_INST_ERATIVAX               0x7c000666
 206#define PPC_INST_ERATSX                 0x7c000126
 207#define PPC_INST_ERATSX_DOT             0x7c000127
 208
 209/* Misc instructions for BPF compiler */
 210#define PPC_INST_LBZ                    0x88000000
 211#define PPC_INST_LD                     0xe8000000
 212#define PPC_INST_LHZ                    0xa0000000
 213#define PPC_INST_LHBRX                  0x7c00062c
 214#define PPC_INST_LWZ                    0x80000000
 215#define PPC_INST_STD                    0xf8000000
 216#define PPC_INST_STDU                   0xf8000001
 217#define PPC_INST_STW                    0x90000000
 218#define PPC_INST_STWU                   0x94000000
 219#define PPC_INST_MFLR                   0x7c0802a6
 220#define PPC_INST_MTLR                   0x7c0803a6
 221#define PPC_INST_CMPWI                  0x2c000000
 222#define PPC_INST_CMPDI                  0x2c200000
 223#define PPC_INST_CMPLW                  0x7c000040
 224#define PPC_INST_CMPLWI                 0x28000000
 225#define PPC_INST_ADDI                   0x38000000
 226#define PPC_INST_ADDIS                  0x3c000000
 227#define PPC_INST_ADD                    0x7c000214
 228#define PPC_INST_SUB                    0x7c000050
 229#define PPC_INST_BLR                    0x4e800020
 230#define PPC_INST_BLRL                   0x4e800021
 231#define PPC_INST_MULLW                  0x7c0001d6
 232#define PPC_INST_MULHWU                 0x7c000016
 233#define PPC_INST_MULLI                  0x1c000000
 234#define PPC_INST_DIVWU                  0x7c000396
 235#define PPC_INST_RLWINM                 0x54000000
 236#define PPC_INST_RLDICR                 0x78000004
 237#define PPC_INST_SLW                    0x7c000030
 238#define PPC_INST_SRW                    0x7c000430
 239#define PPC_INST_AND                    0x7c000038
 240#define PPC_INST_ANDDOT                 0x7c000039
 241#define PPC_INST_OR                     0x7c000378
 242#define PPC_INST_XOR                    0x7c000278
 243#define PPC_INST_ANDI                   0x70000000
 244#define PPC_INST_ORI                    0x60000000
 245#define PPC_INST_ORIS                   0x64000000
 246#define PPC_INST_XORI                   0x68000000
 247#define PPC_INST_XORIS                  0x6c000000
 248#define PPC_INST_NEG                    0x7c0000d0
 249#define PPC_INST_BRANCH                 0x48000000
 250#define PPC_INST_BRANCH_COND            0x40800000
 251#define PPC_INST_LBZCIX                 0x7c0006aa
 252#define PPC_INST_STBCIX                 0x7c0007aa
 253
 254/* macros to insert fields into opcodes */
 255#define ___PPC_RA(a)    (((a) & 0x1f) << 16)
 256#define ___PPC_RB(b)    (((b) & 0x1f) << 11)
 257#define ___PPC_RS(s)    (((s) & 0x1f) << 21)
 258#define ___PPC_RT(t)    ___PPC_RS(t)
 259#define __PPC_RA(a)     ___PPC_RA(__REG_##a)
 260#define __PPC_RA0(a)    ___PPC_RA(__REGA0_##a)
 261#define __PPC_RB(b)     ___PPC_RB(__REG_##b)
 262#define __PPC_RS(s)     ___PPC_RS(__REG_##s)
 263#define __PPC_RT(t)     ___PPC_RT(__REG_##t)
 264#define __PPC_XA(a)     ((((a) & 0x1f) << 16) | (((a) & 0x20) >> 3))
 265#define __PPC_XB(b)     ((((b) & 0x1f) << 11) | (((b) & 0x20) >> 4))
 266#define __PPC_XS(s)     ((((s) & 0x1f) << 21) | (((s) & 0x20) >> 5))
 267#define __PPC_XT(s)     __PPC_XS(s)
 268#define __PPC_T_TLB(t)  (((t) & 0x3) << 21)
 269#define __PPC_WC(w)     (((w) & 0x3) << 21)
 270#define __PPC_WS(w)     (((w) & 0x1f) << 11)
 271#define __PPC_SH(s)     __PPC_WS(s)
 272#define __PPC_MB(s)     (((s) & 0x1f) << 6)
 273#define __PPC_ME(s)     (((s) & 0x1f) << 1)
 274#define __PPC_BI(s)     (((s) & 0x1f) << 16)
 275#define __PPC_CT(t)     (((t) & 0x0f) << 21)
 276
 277/*
 278 * Only use the larx hint bit on 64bit CPUs. e500v1/v2 based CPUs will treat a
 279 * larx with EH set as an illegal instruction.
 280 */
 281#ifdef CONFIG_PPC64
 282#define __PPC_EH(eh)    (((eh) & 0x1) << 0)
 283#else
 284#define __PPC_EH(eh)    0
 285#endif
 286
 287/* Deal with instructions that older assemblers aren't aware of */
 288#define PPC_DCBAL(a, b)         stringify_in_c(.long PPC_INST_DCBAL | \
 289                                        __PPC_RA(a) | __PPC_RB(b))
 290#define PPC_DCBZL(a, b)         stringify_in_c(.long PPC_INST_DCBZL | \
 291                                        __PPC_RA(a) | __PPC_RB(b))
 292#define PPC_LDARX(t, a, b, eh)  stringify_in_c(.long PPC_INST_LDARX | \
 293                                        ___PPC_RT(t) | ___PPC_RA(a) | \
 294                                        ___PPC_RB(b) | __PPC_EH(eh))
 295#define PPC_LWARX(t, a, b, eh)  stringify_in_c(.long PPC_INST_LWARX | \
 296                                        ___PPC_RT(t) | ___PPC_RA(a) | \
 297                                        ___PPC_RB(b) | __PPC_EH(eh))
 298#define PPC_MSGSND(b)           stringify_in_c(.long PPC_INST_MSGSND | \
 299                                        ___PPC_RB(b))
 300#define PPC_MSGCLR(b)           stringify_in_c(.long PPC_INST_MSGCLR | \
 301                                        ___PPC_RB(b))
 302#define PPC_MSGSNDP(b)          stringify_in_c(.long PPC_INST_MSGSNDP | \
 303                                        ___PPC_RB(b))
 304#define PPC_POPCNTB(a, s)       stringify_in_c(.long PPC_INST_POPCNTB | \
 305                                        __PPC_RA(a) | __PPC_RS(s))
 306#define PPC_POPCNTD(a, s)       stringify_in_c(.long PPC_INST_POPCNTD | \
 307                                        __PPC_RA(a) | __PPC_RS(s))
 308#define PPC_POPCNTW(a, s)       stringify_in_c(.long PPC_INST_POPCNTW | \
 309                                        __PPC_RA(a) | __PPC_RS(s))
 310#define PPC_RFCI                stringify_in_c(.long PPC_INST_RFCI)
 311#define PPC_RFDI                stringify_in_c(.long PPC_INST_RFDI)
 312#define PPC_RFMCI               stringify_in_c(.long PPC_INST_RFMCI)
 313#define PPC_TLBILX(t, a, b)     stringify_in_c(.long PPC_INST_TLBILX | \
 314                                        __PPC_T_TLB(t) | __PPC_RA0(a) | __PPC_RB(b))
 315#define PPC_TLBILX_ALL(a, b)    PPC_TLBILX(0, a, b)
 316#define PPC_TLBILX_PID(a, b)    PPC_TLBILX(1, a, b)
 317#define PPC_TLBILX_VA(a, b)     PPC_TLBILX(3, a, b)
 318#define PPC_WAIT(w)             stringify_in_c(.long PPC_INST_WAIT | \
 319                                        __PPC_WC(w))
 320#define PPC_TLBIE(lp,a)         stringify_in_c(.long PPC_INST_TLBIE | \
 321                                               ___PPC_RB(a) | ___PPC_RS(lp))
 322#define PPC_TLBSRX_DOT(a,b)     stringify_in_c(.long PPC_INST_TLBSRX_DOT | \
 323                                        __PPC_RA0(a) | __PPC_RB(b))
 324#define PPC_TLBIVAX(a,b)        stringify_in_c(.long PPC_INST_TLBIVAX | \
 325                                        __PPC_RA0(a) | __PPC_RB(b))
 326
 327#define PPC_ERATWE(s, a, w)     stringify_in_c(.long PPC_INST_ERATWE | \
 328                                        __PPC_RS(s) | __PPC_RA(a) | __PPC_WS(w))
 329#define PPC_ERATRE(s, a, w)     stringify_in_c(.long PPC_INST_ERATRE | \
 330                                        __PPC_RS(s) | __PPC_RA(a) | __PPC_WS(w))
 331#define PPC_ERATILX(t, a, b)    stringify_in_c(.long PPC_INST_ERATILX | \
 332                                        __PPC_T_TLB(t) | __PPC_RA0(a) | \
 333                                        __PPC_RB(b))
 334#define PPC_ERATIVAX(s, a, b)   stringify_in_c(.long PPC_INST_ERATIVAX | \
 335                                        __PPC_RS(s) | __PPC_RA0(a) | __PPC_RB(b))
 336#define PPC_ERATSX(t, a, w)     stringify_in_c(.long PPC_INST_ERATSX | \
 337                                        __PPC_RS(t) | __PPC_RA0(a) | __PPC_RB(b))
 338#define PPC_ERATSX_DOT(t, a, w) stringify_in_c(.long PPC_INST_ERATSX_DOT | \
 339                                        __PPC_RS(t) | __PPC_RA0(a) | __PPC_RB(b))
 340#define PPC_SLBFEE_DOT(t, b)    stringify_in_c(.long PPC_INST_SLBFEE | \
 341                                        __PPC_RT(t) | __PPC_RB(b))
 342#define PPC_ICBT(c,a,b)         stringify_in_c(.long PPC_INST_ICBT | \
 343                                       __PPC_CT(c) | __PPC_RA0(a) | __PPC_RB(b))
 344/* PASemi instructions */
 345#define LBZCIX(t,a,b)           stringify_in_c(.long PPC_INST_LBZCIX | \
 346                                       __PPC_RT(t) | __PPC_RA(a) | __PPC_RB(b))
 347#define STBCIX(s,a,b)           stringify_in_c(.long PPC_INST_STBCIX | \
 348                                       __PPC_RS(s) | __PPC_RA(a) | __PPC_RB(b))
 349
 350/*
 351 * Define what the VSX XX1 form instructions will look like, then add
 352 * the 128 bit load store instructions based on that.
 353 */
 354#define VSX_XX1(s, a, b)        (__PPC_XS(s) | __PPC_RA(a) | __PPC_RB(b))
 355#define VSX_XX3(t, a, b)        (__PPC_XT(t) | __PPC_XA(a) | __PPC_XB(b))
 356#define STXVD2X(s, a, b)        stringify_in_c(.long PPC_INST_STXVD2X | \
 357                                               VSX_XX1((s), a, b))
 358#define LXVD2X(s, a, b)         stringify_in_c(.long PPC_INST_LXVD2X | \
 359                                               VSX_XX1((s), a, b))
 360#define XXLOR(t, a, b)          stringify_in_c(.long PPC_INST_XXLOR | \
 361                                               VSX_XX3((t), a, b))
 362#define XXSWAPD(t, a)           stringify_in_c(.long PPC_INST_XXSWAPD | \
 363                                               VSX_XX3((t), a, a))
 364#define XVCPSGNDP(t, a, b)      stringify_in_c(.long (PPC_INST_XVCPSGNDP | \
 365                                               VSX_XX3((t), (a), (b))))
 366
 367#define PPC_NAP                 stringify_in_c(.long PPC_INST_NAP)
 368#define PPC_SLEEP               stringify_in_c(.long PPC_INST_SLEEP)
 369#define PPC_WINKLE              stringify_in_c(.long PPC_INST_WINKLE)
 370
 371/* BHRB instructions */
 372#define PPC_CLRBHRB             stringify_in_c(.long PPC_INST_CLRBHRB)
 373#define PPC_MFBHRBE(r, n)       stringify_in_c(.long PPC_INST_BHRBE | \
 374                                                __PPC_RT(r) | \
 375                                                        (((n) & 0x3ff) << 11))
 376
 377/* Transactional memory instructions */
 378#define TRECHKPT                stringify_in_c(.long PPC_INST_TRECHKPT)
 379#define TRECLAIM(r)             stringify_in_c(.long PPC_INST_TRECLAIM \
 380                                               | __PPC_RA(r))
 381#define TABORT(r)               stringify_in_c(.long PPC_INST_TABORT \
 382                                               | __PPC_RA(r))
 383
 384/* book3e thread control instructions */
 385#define TMRN(x)                 ((((x) & 0x1f) << 16) | (((x) & 0x3e0) << 6))
 386#define MTTMR(tmr, r)           stringify_in_c(.long PPC_INST_MTTMR | \
 387                                               TMRN(tmr) | ___PPC_RS(r))
 388#define MFTMR(tmr, r)           stringify_in_c(.long PPC_INST_MFTMR | \
 389                                               TMRN(tmr) | ___PPC_RT(r))
 390
 391/* Coprocessor instructions */
 392#define PPC_ICSWX(s, a, b)      stringify_in_c(.long PPC_INST_ICSWX |   \
 393                                               ___PPC_RS(s) |           \
 394                                               ___PPC_RA(a) |           \
 395                                               ___PPC_RB(b))
 396#define PPC_ICSWEPX(s, a, b)    stringify_in_c(.long PPC_INST_ICSWEPX | \
 397                                               ___PPC_RS(s) |           \
 398                                               ___PPC_RA(a) |           \
 399                                               ___PPC_RB(b))
 400
 401
 402#endif /* _ASM_POWERPC_PPC_OPCODE_H */
 403