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14#include <linux/device.h>
15#include <linux/interrupt.h>
16#include <crypto/internal/hash.h>
17
18#include "common.h"
19#include "core.h"
20#include "sha.h"
21
22
23#define SHA_PADDING 64
24#define SHA_PADDING_MASK (SHA_PADDING - 1)
25
26static LIST_HEAD(ahash_algs);
27
28static const u32 std_iv_sha1[SHA256_DIGEST_SIZE / sizeof(u32)] = {
29 SHA1_H0, SHA1_H1, SHA1_H2, SHA1_H3, SHA1_H4, 0, 0, 0
30};
31
32static const u32 std_iv_sha256[SHA256_DIGEST_SIZE / sizeof(u32)] = {
33 SHA256_H0, SHA256_H1, SHA256_H2, SHA256_H3,
34 SHA256_H4, SHA256_H5, SHA256_H6, SHA256_H7
35};
36
37static void qce_ahash_done(void *data)
38{
39 struct crypto_async_request *async_req = data;
40 struct ahash_request *req = ahash_request_cast(async_req);
41 struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
42 struct qce_sha_reqctx *rctx = ahash_request_ctx(req);
43 struct qce_alg_template *tmpl = to_ahash_tmpl(async_req->tfm);
44 struct qce_device *qce = tmpl->qce;
45 struct qce_result_dump *result = qce->dma.result_buf;
46 unsigned int digestsize = crypto_ahash_digestsize(ahash);
47 int error;
48 u32 status;
49
50 error = qce_dma_terminate_all(&qce->dma);
51 if (error)
52 dev_dbg(qce->dev, "ahash dma termination error (%d)\n", error);
53
54 dma_unmap_sg(qce->dev, req->src, rctx->src_nents, DMA_TO_DEVICE);
55 dma_unmap_sg(qce->dev, &rctx->result_sg, 1, DMA_FROM_DEVICE);
56
57 memcpy(rctx->digest, result->auth_iv, digestsize);
58 if (req->result)
59 memcpy(req->result, result->auth_iv, digestsize);
60
61 rctx->byte_count[0] = cpu_to_be32(result->auth_byte_count[0]);
62 rctx->byte_count[1] = cpu_to_be32(result->auth_byte_count[1]);
63
64 error = qce_check_status(qce, &status);
65 if (error < 0)
66 dev_dbg(qce->dev, "ahash operation error (%x)\n", status);
67
68 req->src = rctx->src_orig;
69 req->nbytes = rctx->nbytes_orig;
70 rctx->last_blk = false;
71 rctx->first_blk = false;
72
73 qce->async_req_done(tmpl->qce, error);
74}
75
76static int qce_ahash_async_req_handle(struct crypto_async_request *async_req)
77{
78 struct ahash_request *req = ahash_request_cast(async_req);
79 struct qce_sha_reqctx *rctx = ahash_request_ctx(req);
80 struct qce_sha_ctx *ctx = crypto_tfm_ctx(async_req->tfm);
81 struct qce_alg_template *tmpl = to_ahash_tmpl(async_req->tfm);
82 struct qce_device *qce = tmpl->qce;
83 unsigned long flags = rctx->flags;
84 int ret;
85
86 if (IS_SHA_HMAC(flags)) {
87 rctx->authkey = ctx->authkey;
88 rctx->authklen = QCE_SHA_HMAC_KEY_SIZE;
89 } else if (IS_CMAC(flags)) {
90 rctx->authkey = ctx->authkey;
91 rctx->authklen = AES_KEYSIZE_128;
92 }
93
94 rctx->src_nents = sg_nents_for_len(req->src, req->nbytes);
95 ret = dma_map_sg(qce->dev, req->src, rctx->src_nents, DMA_TO_DEVICE);
96 if (ret < 0)
97 return ret;
98
99 sg_init_one(&rctx->result_sg, qce->dma.result_buf, QCE_RESULT_BUF_SZ);
100
101 ret = dma_map_sg(qce->dev, &rctx->result_sg, 1, DMA_FROM_DEVICE);
102 if (ret < 0)
103 goto error_unmap_src;
104
105 ret = qce_dma_prep_sgs(&qce->dma, req->src, rctx->src_nents,
106 &rctx->result_sg, 1, qce_ahash_done, async_req);
107 if (ret)
108 goto error_unmap_dst;
109
110 qce_dma_issue_pending(&qce->dma);
111
112 ret = qce_start(async_req, tmpl->crypto_alg_type, 0, 0);
113 if (ret)
114 goto error_terminate;
115
116 return 0;
117
118error_terminate:
119 qce_dma_terminate_all(&qce->dma);
120error_unmap_dst:
121 dma_unmap_sg(qce->dev, &rctx->result_sg, 1, DMA_FROM_DEVICE);
122error_unmap_src:
123 dma_unmap_sg(qce->dev, req->src, rctx->src_nents, DMA_TO_DEVICE);
124 return ret;
125}
126
127static int qce_ahash_init(struct ahash_request *req)
128{
129 struct qce_sha_reqctx *rctx = ahash_request_ctx(req);
130 struct qce_alg_template *tmpl = to_ahash_tmpl(req->base.tfm);
131 const u32 *std_iv = tmpl->std_iv;
132
133 memset(rctx, 0, sizeof(*rctx));
134 rctx->first_blk = true;
135 rctx->last_blk = false;
136 rctx->flags = tmpl->alg_flags;
137 memcpy(rctx->digest, std_iv, sizeof(rctx->digest));
138
139 return 0;
140}
141
142static int qce_ahash_export(struct ahash_request *req, void *out)
143{
144 struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
145 struct qce_sha_reqctx *rctx = ahash_request_ctx(req);
146 unsigned long flags = rctx->flags;
147 unsigned int digestsize = crypto_ahash_digestsize(ahash);
148 unsigned int blocksize =
149 crypto_tfm_alg_blocksize(crypto_ahash_tfm(ahash));
150
151 if (IS_SHA1(flags) || IS_SHA1_HMAC(flags)) {
152 struct sha1_state *out_state = out;
153
154 out_state->count = rctx->count;
155 qce_cpu_to_be32p_array((__be32 *)out_state->state,
156 rctx->digest, digestsize);
157 memcpy(out_state->buffer, rctx->buf, blocksize);
158 } else if (IS_SHA256(flags) || IS_SHA256_HMAC(flags)) {
159 struct sha256_state *out_state = out;
160
161 out_state->count = rctx->count;
162 qce_cpu_to_be32p_array((__be32 *)out_state->state,
163 rctx->digest, digestsize);
164 memcpy(out_state->buf, rctx->buf, blocksize);
165 } else {
166 return -EINVAL;
167 }
168
169 return 0;
170}
171
172static int qce_import_common(struct ahash_request *req, u64 in_count,
173 const u32 *state, const u8 *buffer, bool hmac)
174{
175 struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
176 struct qce_sha_reqctx *rctx = ahash_request_ctx(req);
177 unsigned int digestsize = crypto_ahash_digestsize(ahash);
178 unsigned int blocksize;
179 u64 count = in_count;
180
181 blocksize = crypto_tfm_alg_blocksize(crypto_ahash_tfm(ahash));
182 rctx->count = in_count;
183 memcpy(rctx->buf, buffer, blocksize);
184
185 if (in_count <= blocksize) {
186 rctx->first_blk = 1;
187 } else {
188 rctx->first_blk = 0;
189
190
191
192
193
194 if (hmac)
195 count += SHA_PADDING;
196 }
197
198 rctx->byte_count[0] = (__force __be32)(count & ~SHA_PADDING_MASK);
199 rctx->byte_count[1] = (__force __be32)(count >> 32);
200 qce_cpu_to_be32p_array((__be32 *)rctx->digest, (const u8 *)state,
201 digestsize);
202 rctx->buflen = (unsigned int)(in_count & (blocksize - 1));
203
204 return 0;
205}
206
207static int qce_ahash_import(struct ahash_request *req, const void *in)
208{
209 struct qce_sha_reqctx *rctx = ahash_request_ctx(req);
210 unsigned long flags = rctx->flags;
211 bool hmac = IS_SHA_HMAC(flags);
212 int ret = -EINVAL;
213
214 if (IS_SHA1(flags) || IS_SHA1_HMAC(flags)) {
215 const struct sha1_state *state = in;
216
217 ret = qce_import_common(req, state->count, state->state,
218 state->buffer, hmac);
219 } else if (IS_SHA256(flags) || IS_SHA256_HMAC(flags)) {
220 const struct sha256_state *state = in;
221
222 ret = qce_import_common(req, state->count, state->state,
223 state->buf, hmac);
224 }
225
226 return ret;
227}
228
229static int qce_ahash_update(struct ahash_request *req)
230{
231 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
232 struct qce_sha_reqctx *rctx = ahash_request_ctx(req);
233 struct qce_alg_template *tmpl = to_ahash_tmpl(req->base.tfm);
234 struct qce_device *qce = tmpl->qce;
235 struct scatterlist *sg_last, *sg;
236 unsigned int total, len;
237 unsigned int hash_later;
238 unsigned int nbytes;
239 unsigned int blocksize;
240
241 blocksize = crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm));
242 rctx->count += req->nbytes;
243
244
245 total = req->nbytes + rctx->buflen;
246
247 if (total <= blocksize) {
248 scatterwalk_map_and_copy(rctx->buf + rctx->buflen, req->src,
249 0, req->nbytes, 0);
250 rctx->buflen += req->nbytes;
251 return 0;
252 }
253
254
255 rctx->src_orig = req->src;
256 rctx->nbytes_orig = req->nbytes;
257
258
259
260
261
262 if (rctx->buflen)
263 memcpy(rctx->tmpbuf, rctx->buf, rctx->buflen);
264
265
266 hash_later = total % blocksize;
267 if (hash_later) {
268 unsigned int src_offset = req->nbytes - hash_later;
269 scatterwalk_map_and_copy(rctx->buf, req->src, src_offset,
270 hash_later, 0);
271 }
272
273
274 nbytes = total - hash_later;
275
276 len = rctx->buflen;
277 sg = sg_last = req->src;
278
279 while (len < nbytes && sg) {
280 if (len + sg_dma_len(sg) > nbytes)
281 break;
282 len += sg_dma_len(sg);
283 sg_last = sg;
284 sg = sg_next(sg);
285 }
286
287 if (!sg_last)
288 return -EINVAL;
289
290 sg_mark_end(sg_last);
291
292 if (rctx->buflen) {
293 sg_init_table(rctx->sg, 2);
294 sg_set_buf(rctx->sg, rctx->tmpbuf, rctx->buflen);
295 sg_chain(rctx->sg, 2, req->src);
296 req->src = rctx->sg;
297 }
298
299 req->nbytes = nbytes;
300 rctx->buflen = hash_later;
301
302 return qce->async_req_enqueue(tmpl->qce, &req->base);
303}
304
305static int qce_ahash_final(struct ahash_request *req)
306{
307 struct qce_sha_reqctx *rctx = ahash_request_ctx(req);
308 struct qce_alg_template *tmpl = to_ahash_tmpl(req->base.tfm);
309 struct qce_device *qce = tmpl->qce;
310
311 if (!rctx->buflen)
312 return 0;
313
314 rctx->last_blk = true;
315
316 rctx->src_orig = req->src;
317 rctx->nbytes_orig = req->nbytes;
318
319 memcpy(rctx->tmpbuf, rctx->buf, rctx->buflen);
320 sg_init_one(rctx->sg, rctx->tmpbuf, rctx->buflen);
321
322 req->src = rctx->sg;
323 req->nbytes = rctx->buflen;
324
325 return qce->async_req_enqueue(tmpl->qce, &req->base);
326}
327
328static int qce_ahash_digest(struct ahash_request *req)
329{
330 struct qce_sha_reqctx *rctx = ahash_request_ctx(req);
331 struct qce_alg_template *tmpl = to_ahash_tmpl(req->base.tfm);
332 struct qce_device *qce = tmpl->qce;
333 int ret;
334
335 ret = qce_ahash_init(req);
336 if (ret)
337 return ret;
338
339 rctx->src_orig = req->src;
340 rctx->nbytes_orig = req->nbytes;
341 rctx->first_blk = true;
342 rctx->last_blk = true;
343
344 return qce->async_req_enqueue(tmpl->qce, &req->base);
345}
346
347struct qce_ahash_result {
348 struct completion completion;
349 int error;
350};
351
352static void qce_digest_complete(struct crypto_async_request *req, int error)
353{
354 struct qce_ahash_result *result = req->data;
355
356 if (error == -EINPROGRESS)
357 return;
358
359 result->error = error;
360 complete(&result->completion);
361}
362
363static int qce_ahash_hmac_setkey(struct crypto_ahash *tfm, const u8 *key,
364 unsigned int keylen)
365{
366 unsigned int digestsize = crypto_ahash_digestsize(tfm);
367 struct qce_sha_ctx *ctx = crypto_tfm_ctx(&tfm->base);
368 struct qce_ahash_result result;
369 struct ahash_request *req;
370 struct scatterlist sg;
371 unsigned int blocksize;
372 struct crypto_ahash *ahash_tfm;
373 u8 *buf;
374 int ret;
375 const char *alg_name;
376
377 blocksize = crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm));
378 memset(ctx->authkey, 0, sizeof(ctx->authkey));
379
380 if (keylen <= blocksize) {
381 memcpy(ctx->authkey, key, keylen);
382 return 0;
383 }
384
385 if (digestsize == SHA1_DIGEST_SIZE)
386 alg_name = "sha1-qce";
387 else if (digestsize == SHA256_DIGEST_SIZE)
388 alg_name = "sha256-qce";
389 else
390 return -EINVAL;
391
392 ahash_tfm = crypto_alloc_ahash(alg_name, CRYPTO_ALG_TYPE_AHASH,
393 CRYPTO_ALG_TYPE_AHASH_MASK);
394 if (IS_ERR(ahash_tfm))
395 return PTR_ERR(ahash_tfm);
396
397 req = ahash_request_alloc(ahash_tfm, GFP_KERNEL);
398 if (!req) {
399 ret = -ENOMEM;
400 goto err_free_ahash;
401 }
402
403 init_completion(&result.completion);
404 ahash_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG,
405 qce_digest_complete, &result);
406 crypto_ahash_clear_flags(ahash_tfm, ~0);
407
408 buf = kzalloc(keylen + QCE_MAX_ALIGN_SIZE, GFP_KERNEL);
409 if (!buf) {
410 ret = -ENOMEM;
411 goto err_free_req;
412 }
413
414 memcpy(buf, key, keylen);
415 sg_init_one(&sg, buf, keylen);
416 ahash_request_set_crypt(req, &sg, ctx->authkey, keylen);
417
418 ret = crypto_ahash_digest(req);
419 if (ret == -EINPROGRESS || ret == -EBUSY) {
420 ret = wait_for_completion_interruptible(&result.completion);
421 if (!ret)
422 ret = result.error;
423 }
424
425 if (ret)
426 crypto_ahash_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
427
428 kfree(buf);
429err_free_req:
430 ahash_request_free(req);
431err_free_ahash:
432 crypto_free_ahash(ahash_tfm);
433 return ret;
434}
435
436static int qce_ahash_cra_init(struct crypto_tfm *tfm)
437{
438 struct crypto_ahash *ahash = __crypto_ahash_cast(tfm);
439 struct qce_sha_ctx *ctx = crypto_tfm_ctx(tfm);
440
441 crypto_ahash_set_reqsize(ahash, sizeof(struct qce_sha_reqctx));
442 memset(ctx, 0, sizeof(*ctx));
443 return 0;
444}
445
446struct qce_ahash_def {
447 unsigned long flags;
448 const char *name;
449 const char *drv_name;
450 unsigned int digestsize;
451 unsigned int blocksize;
452 unsigned int statesize;
453 const u32 *std_iv;
454};
455
456static const struct qce_ahash_def ahash_def[] = {
457 {
458 .flags = QCE_HASH_SHA1,
459 .name = "sha1",
460 .drv_name = "sha1-qce",
461 .digestsize = SHA1_DIGEST_SIZE,
462 .blocksize = SHA1_BLOCK_SIZE,
463 .statesize = sizeof(struct sha1_state),
464 .std_iv = std_iv_sha1,
465 },
466 {
467 .flags = QCE_HASH_SHA256,
468 .name = "sha256",
469 .drv_name = "sha256-qce",
470 .digestsize = SHA256_DIGEST_SIZE,
471 .blocksize = SHA256_BLOCK_SIZE,
472 .statesize = sizeof(struct sha256_state),
473 .std_iv = std_iv_sha256,
474 },
475 {
476 .flags = QCE_HASH_SHA1_HMAC,
477 .name = "hmac(sha1)",
478 .drv_name = "hmac-sha1-qce",
479 .digestsize = SHA1_DIGEST_SIZE,
480 .blocksize = SHA1_BLOCK_SIZE,
481 .statesize = sizeof(struct sha1_state),
482 .std_iv = std_iv_sha1,
483 },
484 {
485 .flags = QCE_HASH_SHA256_HMAC,
486 .name = "hmac(sha256)",
487 .drv_name = "hmac-sha256-qce",
488 .digestsize = SHA256_DIGEST_SIZE,
489 .blocksize = SHA256_BLOCK_SIZE,
490 .statesize = sizeof(struct sha256_state),
491 .std_iv = std_iv_sha256,
492 },
493};
494
495static int qce_ahash_register_one(const struct qce_ahash_def *def,
496 struct qce_device *qce)
497{
498 struct qce_alg_template *tmpl;
499 struct ahash_alg *alg;
500 struct crypto_alg *base;
501 int ret;
502
503 tmpl = kzalloc(sizeof(*tmpl), GFP_KERNEL);
504 if (!tmpl)
505 return -ENOMEM;
506
507 tmpl->std_iv = def->std_iv;
508
509 alg = &tmpl->alg.ahash;
510 alg->init = qce_ahash_init;
511 alg->update = qce_ahash_update;
512 alg->final = qce_ahash_final;
513 alg->digest = qce_ahash_digest;
514 alg->export = qce_ahash_export;
515 alg->import = qce_ahash_import;
516 if (IS_SHA_HMAC(def->flags))
517 alg->setkey = qce_ahash_hmac_setkey;
518 alg->halg.digestsize = def->digestsize;
519 alg->halg.statesize = def->statesize;
520
521 base = &alg->halg.base;
522 base->cra_blocksize = def->blocksize;
523 base->cra_priority = 300;
524 base->cra_flags = CRYPTO_ALG_ASYNC;
525 base->cra_ctxsize = sizeof(struct qce_sha_ctx);
526 base->cra_alignmask = 0;
527 base->cra_module = THIS_MODULE;
528 base->cra_init = qce_ahash_cra_init;
529 INIT_LIST_HEAD(&base->cra_list);
530
531 snprintf(base->cra_name, CRYPTO_MAX_ALG_NAME, "%s", def->name);
532 snprintf(base->cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s",
533 def->drv_name);
534
535 INIT_LIST_HEAD(&tmpl->entry);
536 tmpl->crypto_alg_type = CRYPTO_ALG_TYPE_AHASH;
537 tmpl->alg_flags = def->flags;
538 tmpl->qce = qce;
539
540 ret = crypto_register_ahash(alg);
541 if (ret) {
542 kfree(tmpl);
543 dev_err(qce->dev, "%s registration failed\n", base->cra_name);
544 return ret;
545 }
546
547 list_add_tail(&tmpl->entry, &ahash_algs);
548 dev_dbg(qce->dev, "%s is registered\n", base->cra_name);
549 return 0;
550}
551
552static void qce_ahash_unregister(struct qce_device *qce)
553{
554 struct qce_alg_template *tmpl, *n;
555
556 list_for_each_entry_safe(tmpl, n, &ahash_algs, entry) {
557 crypto_unregister_ahash(&tmpl->alg.ahash);
558 list_del(&tmpl->entry);
559 kfree(tmpl);
560 }
561}
562
563static int qce_ahash_register(struct qce_device *qce)
564{
565 int ret, i;
566
567 for (i = 0; i < ARRAY_SIZE(ahash_def); i++) {
568 ret = qce_ahash_register_one(&ahash_def[i], qce);
569 if (ret)
570 goto err;
571 }
572
573 return 0;
574err:
575 qce_ahash_unregister(qce);
576 return ret;
577}
578
579const struct qce_algo_ops ahash_ops = {
580 .type = CRYPTO_ALG_TYPE_AHASH,
581 .register_algs = qce_ahash_register,
582 .unregister_algs = qce_ahash_unregister,
583 .async_req_handle = qce_ahash_async_req_handle,
584};
585
