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24#ifndef __CZ_DPM_H__
25#define __CZ_DPM_H__
26
27#include "smu8_fusion.h"
28
29#define CZ_AT_DFLT 30
30#define CZ_NUM_NBPSTATES 4
31#define CZ_NUM_NBPMEMORY_CLOCK 2
32#define CZ_MAX_HARDWARE_POWERLEVELS 8
33#define CZ_MAX_DISPLAY_CLOCK_LEVEL 8
34#define CZ_MAX_DISPLAYPHY_IDS 10
35
36#define PPCZ_VOTINGRIGHTSCLIENTS_DFLT0 0x3FFFC102
37
38#define SMC_RAM_END 0x40000
39
40#define DPMFlags_SCLK_Enabled 0x00000001
41#define DPMFlags_UVD_Enabled 0x00000002
42#define DPMFlags_VCE_Enabled 0x00000004
43#define DPMFlags_ACP_Enabled 0x00000008
44#define DPMFlags_ForceHighestValid 0x40000000
45#define DPMFlags_Debug 0x80000000
46
47
48#define SMU_EnabledFeatureScoreboard_AcpDpmOn 0x00000001
49#define SMU_EnabledFeatureScoreboard_SclkDpmOn 0x00200000
50#define SMU_EnabledFeatureScoreboard_UvdDpmOn 0x00800000
51#define SMU_EnabledFeatureScoreboard_VceDpmOn 0x01000000
52
53
54
55
56#define CZ_MIN_DEEP_SLEEP_SCLK 800
57
58enum cz_pt_config_reg_type {
59 CZ_CONFIGREG_MMR = 0,
60 CZ_CONFIGREG_SMC_IND,
61 CZ_CONFIGREG_DIDT_IND,
62 CZ_CONFIGREG_CACHE,
63 CZ_CONFIGREG_MAX
64};
65
66struct cz_pt_config_reg {
67 uint32_t offset;
68 uint32_t mask;
69 uint32_t shift;
70 uint32_t value;
71 enum cz_pt_config_reg_type type;
72};
73
74struct cz_dpm_entry {
75 uint32_t soft_min_clk;
76 uint32_t hard_min_clk;
77 uint32_t soft_max_clk;
78 uint32_t hard_max_clk;
79};
80
81struct cz_pl {
82 uint32_t sclk;
83 uint8_t vddc_index;
84 uint8_t ds_divider_index;
85 uint8_t ss_divider_index;
86 uint8_t allow_gnb_slow;
87 uint8_t force_nbp_state;
88 uint8_t display_wm;
89 uint8_t vce_wm;
90};
91
92struct cz_ps {
93 struct cz_pl levels[CZ_MAX_HARDWARE_POWERLEVELS];
94 uint32_t num_levels;
95 bool need_dfs_bypass;
96 uint8_t dpm0_pg_nb_ps_lo;
97 uint8_t dpm0_pg_nb_ps_hi;
98 uint8_t dpmx_nb_ps_lo;
99 uint8_t dpmx_nb_ps_hi;
100 bool force_high;
101};
102
103struct cz_displayphy_entry {
104 uint8_t phy_present;
105 uint8_t active_lane_mapping;
106 uint8_t display_conf_type;
107 uint8_t num_active_lanes;
108};
109
110struct cz_displayphy_info {
111 bool phy_access_initialized;
112 struct cz_displayphy_entry entries[CZ_MAX_DISPLAYPHY_IDS];
113};
114
115struct cz_sys_info {
116 uint32_t bootup_uma_clk;
117 uint32_t bootup_sclk;
118 uint32_t dentist_vco_freq;
119 uint32_t nb_dpm_enable;
120 uint32_t nbp_memory_clock[CZ_NUM_NBPMEMORY_CLOCK];
121 uint32_t nbp_n_clock[CZ_NUM_NBPSTATES];
122 uint8_t nbp_voltage_index[CZ_NUM_NBPSTATES];
123 uint32_t display_clock[CZ_MAX_DISPLAY_CLOCK_LEVEL];
124 uint16_t bootup_nb_voltage_index;
125 uint8_t htc_tmp_lmt;
126 uint8_t htc_hyst_lmt;
127 uint32_t uma_channel_number;
128};
129
130struct cz_power_info {
131 uint32_t active_target[CZ_MAX_HARDWARE_POWERLEVELS];
132 struct cz_sys_info sys_info;
133 struct cz_pl boot_pl;
134 bool disable_nb_ps3_in_battery;
135 bool battery_state;
136 uint32_t lowest_valid;
137 uint32_t highest_valid;
138 uint16_t high_voltage_threshold;
139
140 uint32_t sram_end;
141 uint32_t dpm_table_start;
142 uint32_t soft_regs_start;
143
144 uint8_t uvd_level_count;
145 uint8_t vce_level_count;
146 uint8_t acp_level_count;
147 uint32_t fps_high_threshold;
148 uint32_t fps_low_threshold;
149
150 uint32_t dpm_flags;
151 struct cz_dpm_entry sclk_dpm;
152 struct cz_dpm_entry uvd_dpm;
153 struct cz_dpm_entry vce_dpm;
154 struct cz_dpm_entry acp_dpm;
155
156 uint8_t uvd_boot_level;
157 uint8_t uvd_interval;
158 uint8_t vce_boot_level;
159 uint8_t vce_interval;
160 uint8_t acp_boot_level;
161 uint8_t acp_interval;
162
163 uint8_t graphics_boot_level;
164 uint8_t graphics_interval;
165 uint8_t graphics_therm_throttle_enable;
166 uint8_t graphics_voltage_change_enable;
167 uint8_t graphics_clk_slow_enable;
168 uint8_t graphics_clk_slow_divider;
169
170 uint32_t low_sclk_interrupt_threshold;
171 bool uvd_power_gated;
172 bool vce_power_gated;
173 bool acp_power_gated;
174
175 uint32_t active_process_mask;
176
177 uint32_t mgcg_cgtt_local0;
178 uint32_t mgcg_cgtt_local1;
179 uint32_t clock_slow_down_step;
180 uint32_t skip_clock_slow_down;
181 bool enable_nb_ps_policy;
182 uint32_t voting_clients;
183 uint32_t voltage_drop_threshold;
184 uint32_t gfx_pg_threshold;
185 uint32_t max_sclk_level;
186
187 bool didt_enabled;
188 bool video_start;
189 bool cac_enabled;
190 bool bapm_enabled;
191 bool nb_dpm_enabled_by_driver;
192 bool nb_dpm_enabled;
193 bool auto_thermal_throttling_enabled;
194 bool dpm_enabled;
195 bool need_pptable_upload;
196
197 bool caps_cac;
198 bool caps_power_containment;
199 bool caps_sq_ramping;
200 bool caps_db_ramping;
201 bool caps_td_ramping;
202 bool caps_tcp_ramping;
203 bool caps_sclk_throttle_low_notification;
204 bool caps_fps;
205 bool caps_uvd_dpm;
206 bool caps_uvd_pg;
207 bool caps_vce_dpm;
208 bool caps_vce_pg;
209 bool caps_acp_dpm;
210 bool caps_acp_pg;
211 bool caps_stable_power_state;
212 bool caps_enable_dfs_bypass;
213 bool caps_sclk_ds;
214 bool caps_voltage_island;
215
216 struct amdgpu_ps current_rps;
217 struct cz_ps current_ps;
218 struct amdgpu_ps requested_rps;
219 struct cz_ps requested_ps;
220
221 bool uvd_power_down;
222 bool vce_power_down;
223 bool acp_power_down;
224
225 bool uvd_dynamic_pg;
226};
227
228
229uint32_t cz_get_argument(struct amdgpu_device *adev);
230int cz_send_msg_to_smc(struct amdgpu_device *adev, uint16_t msg);
231int cz_send_msg_to_smc_with_parameter(struct amdgpu_device *adev,
232 uint16_t msg, uint32_t parameter);
233int cz_read_smc_sram_dword(struct amdgpu_device *adev,
234 uint32_t smc_address, uint32_t *value, uint32_t limit);
235int cz_smu_upload_pptable(struct amdgpu_device *adev);
236int cz_smu_download_pptable(struct amdgpu_device *adev, void **table);
237#endif
238
