1#ifndef MDP4_XML
2#define MDP4_XML
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48enum mdp4_pipe {
49 VG1 = 0,
50 VG2 = 1,
51 RGB1 = 2,
52 RGB2 = 3,
53 RGB3 = 4,
54 VG3 = 5,
55 VG4 = 6,
56};
57
58enum mdp4_mixer {
59 MIXER0 = 0,
60 MIXER1 = 1,
61 MIXER2 = 2,
62};
63
64enum mdp4_intf {
65 INTF_LCDC_DTV = 0,
66 INTF_DSI_VIDEO = 1,
67 INTF_DSI_CMD = 2,
68 INTF_EBI2_TV = 3,
69};
70
71enum mdp4_cursor_format {
72 CURSOR_ARGB = 1,
73 CURSOR_XRGB = 2,
74};
75
76enum mdp4_frame_format {
77 FRAME_LINEAR = 0,
78 FRAME_TILE_ARGB_4X4 = 1,
79 FRAME_TILE_YCBCR_420 = 2,
80};
81
82enum mdp4_scale_unit {
83 SCALE_FIR = 0,
84 SCALE_MN_PHASE = 1,
85 SCALE_PIXEL_RPT = 2,
86};
87
88enum mdp4_dma {
89 DMA_P = 0,
90 DMA_S = 1,
91 DMA_E = 2,
92};
93
94#define MDP4_IRQ_OVERLAY0_DONE 0x00000001
95#define MDP4_IRQ_OVERLAY1_DONE 0x00000002
96#define MDP4_IRQ_DMA_S_DONE 0x00000004
97#define MDP4_IRQ_DMA_E_DONE 0x00000008
98#define MDP4_IRQ_DMA_P_DONE 0x00000010
99#define MDP4_IRQ_VG1_HISTOGRAM 0x00000020
100#define MDP4_IRQ_VG2_HISTOGRAM 0x00000040
101#define MDP4_IRQ_PRIMARY_VSYNC 0x00000080
102#define MDP4_IRQ_PRIMARY_INTF_UDERRUN 0x00000100
103#define MDP4_IRQ_EXTERNAL_VSYNC 0x00000200
104#define MDP4_IRQ_EXTERNAL_INTF_UDERRUN 0x00000400
105#define MDP4_IRQ_PRIMARY_RDPTR 0x00000800
106#define MDP4_IRQ_DMA_P_HISTOGRAM 0x00020000
107#define MDP4_IRQ_DMA_S_HISTOGRAM 0x04000000
108#define MDP4_IRQ_OVERLAY2_DONE 0x40000000
109#define REG_MDP4_VERSION 0x00000000
110#define MDP4_VERSION_MINOR__MASK 0x00ff0000
111#define MDP4_VERSION_MINOR__SHIFT 16
112static inline uint32_t MDP4_VERSION_MINOR(uint32_t val)
113{
114 return ((val) << MDP4_VERSION_MINOR__SHIFT) & MDP4_VERSION_MINOR__MASK;
115}
116#define MDP4_VERSION_MAJOR__MASK 0xff000000
117#define MDP4_VERSION_MAJOR__SHIFT 24
118static inline uint32_t MDP4_VERSION_MAJOR(uint32_t val)
119{
120 return ((val) << MDP4_VERSION_MAJOR__SHIFT) & MDP4_VERSION_MAJOR__MASK;
121}
122
123#define REG_MDP4_OVLP0_KICK 0x00000004
124
125#define REG_MDP4_OVLP1_KICK 0x00000008
126
127#define REG_MDP4_OVLP2_KICK 0x000000d0
128
129#define REG_MDP4_DMA_P_KICK 0x0000000c
130
131#define REG_MDP4_DMA_S_KICK 0x00000010
132
133#define REG_MDP4_DMA_E_KICK 0x00000014
134
135#define REG_MDP4_DISP_STATUS 0x00000018
136
137#define REG_MDP4_DISP_INTF_SEL 0x00000038
138#define MDP4_DISP_INTF_SEL_PRIM__MASK 0x00000003
139#define MDP4_DISP_INTF_SEL_PRIM__SHIFT 0
140static inline uint32_t MDP4_DISP_INTF_SEL_PRIM(enum mdp4_intf val)
141{
142 return ((val) << MDP4_DISP_INTF_SEL_PRIM__SHIFT) & MDP4_DISP_INTF_SEL_PRIM__MASK;
143}
144#define MDP4_DISP_INTF_SEL_SEC__MASK 0x0000000c
145#define MDP4_DISP_INTF_SEL_SEC__SHIFT 2
146static inline uint32_t MDP4_DISP_INTF_SEL_SEC(enum mdp4_intf val)
147{
148 return ((val) << MDP4_DISP_INTF_SEL_SEC__SHIFT) & MDP4_DISP_INTF_SEL_SEC__MASK;
149}
150#define MDP4_DISP_INTF_SEL_EXT__MASK 0x00000030
151#define MDP4_DISP_INTF_SEL_EXT__SHIFT 4
152static inline uint32_t MDP4_DISP_INTF_SEL_EXT(enum mdp4_intf val)
153{
154 return ((val) << MDP4_DISP_INTF_SEL_EXT__SHIFT) & MDP4_DISP_INTF_SEL_EXT__MASK;
155}
156#define MDP4_DISP_INTF_SEL_DSI_VIDEO 0x00000040
157#define MDP4_DISP_INTF_SEL_DSI_CMD 0x00000080
158
159#define REG_MDP4_RESET_STATUS 0x0000003c
160
161#define REG_MDP4_READ_CNFG 0x0000004c
162
163#define REG_MDP4_INTR_ENABLE 0x00000050
164
165#define REG_MDP4_INTR_STATUS 0x00000054
166
167#define REG_MDP4_INTR_CLEAR 0x00000058
168
169#define REG_MDP4_EBI2_LCD0 0x00000060
170
171#define REG_MDP4_EBI2_LCD1 0x00000064
172
173#define REG_MDP4_PORTMAP_MODE 0x00000070
174
175#define REG_MDP4_CS_CONTROLLER0 0x000000c0
176
177#define REG_MDP4_CS_CONTROLLER1 0x000000c4
178
179#define REG_MDP4_LAYERMIXER2_IN_CFG 0x000100f0
180#define MDP4_LAYERMIXER2_IN_CFG_PIPE0__MASK 0x00000007
181#define MDP4_LAYERMIXER2_IN_CFG_PIPE0__SHIFT 0
182static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE0(enum mdp_mixer_stage_id val)
183{
184 return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE0__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE0__MASK;
185}
186#define MDP4_LAYERMIXER2_IN_CFG_PIPE0_MIXER1 0x00000008
187#define MDP4_LAYERMIXER2_IN_CFG_PIPE1__MASK 0x00000070
188#define MDP4_LAYERMIXER2_IN_CFG_PIPE1__SHIFT 4
189static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE1(enum mdp_mixer_stage_id val)
190{
191 return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE1__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE1__MASK;
192}
193#define MDP4_LAYERMIXER2_IN_CFG_PIPE1_MIXER1 0x00000080
194#define MDP4_LAYERMIXER2_IN_CFG_PIPE2__MASK 0x00000700
195#define MDP4_LAYERMIXER2_IN_CFG_PIPE2__SHIFT 8
196static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE2(enum mdp_mixer_stage_id val)
197{
198 return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE2__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE2__MASK;
199}
200#define MDP4_LAYERMIXER2_IN_CFG_PIPE2_MIXER1 0x00000800
201#define MDP4_LAYERMIXER2_IN_CFG_PIPE3__MASK 0x00007000
202#define MDP4_LAYERMIXER2_IN_CFG_PIPE3__SHIFT 12
203static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE3(enum mdp_mixer_stage_id val)
204{
205 return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE3__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE3__MASK;
206}
207#define MDP4_LAYERMIXER2_IN_CFG_PIPE3_MIXER1 0x00008000
208#define MDP4_LAYERMIXER2_IN_CFG_PIPE4__MASK 0x00070000
209#define MDP4_LAYERMIXER2_IN_CFG_PIPE4__SHIFT 16
210static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE4(enum mdp_mixer_stage_id val)
211{
212 return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE4__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE4__MASK;
213}
214#define MDP4_LAYERMIXER2_IN_CFG_PIPE4_MIXER1 0x00080000
215#define MDP4_LAYERMIXER2_IN_CFG_PIPE5__MASK 0x00700000
216#define MDP4_LAYERMIXER2_IN_CFG_PIPE5__SHIFT 20
217static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE5(enum mdp_mixer_stage_id val)
218{
219 return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE5__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE5__MASK;
220}
221#define MDP4_LAYERMIXER2_IN_CFG_PIPE5_MIXER1 0x00800000
222#define MDP4_LAYERMIXER2_IN_CFG_PIPE6__MASK 0x07000000
223#define MDP4_LAYERMIXER2_IN_CFG_PIPE6__SHIFT 24
224static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE6(enum mdp_mixer_stage_id val)
225{
226 return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE6__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE6__MASK;
227}
228#define MDP4_LAYERMIXER2_IN_CFG_PIPE6_MIXER1 0x08000000
229#define MDP4_LAYERMIXER2_IN_CFG_PIPE7__MASK 0x70000000
230#define MDP4_LAYERMIXER2_IN_CFG_PIPE7__SHIFT 28
231static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE7(enum mdp_mixer_stage_id val)
232{
233 return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE7__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE7__MASK;
234}
235#define MDP4_LAYERMIXER2_IN_CFG_PIPE7_MIXER1 0x80000000
236
237#define REG_MDP4_LAYERMIXER_IN_CFG_UPDATE_METHOD 0x000100fc
238
239#define REG_MDP4_LAYERMIXER_IN_CFG 0x00010100
240#define MDP4_LAYERMIXER_IN_CFG_PIPE0__MASK 0x00000007
241#define MDP4_LAYERMIXER_IN_CFG_PIPE0__SHIFT 0
242static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE0(enum mdp_mixer_stage_id val)
243{
244 return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE0__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE0__MASK;
245}
246#define MDP4_LAYERMIXER_IN_CFG_PIPE0_MIXER1 0x00000008
247#define MDP4_LAYERMIXER_IN_CFG_PIPE1__MASK 0x00000070
248#define MDP4_LAYERMIXER_IN_CFG_PIPE1__SHIFT 4
249static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE1(enum mdp_mixer_stage_id val)
250{
251 return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE1__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE1__MASK;
252}
253#define MDP4_LAYERMIXER_IN_CFG_PIPE1_MIXER1 0x00000080
254#define MDP4_LAYERMIXER_IN_CFG_PIPE2__MASK 0x00000700
255#define MDP4_LAYERMIXER_IN_CFG_PIPE2__SHIFT 8
256static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE2(enum mdp_mixer_stage_id val)
257{
258 return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE2__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE2__MASK;
259}
260#define MDP4_LAYERMIXER_IN_CFG_PIPE2_MIXER1 0x00000800
261#define MDP4_LAYERMIXER_IN_CFG_PIPE3__MASK 0x00007000
262#define MDP4_LAYERMIXER_IN_CFG_PIPE3__SHIFT 12
263static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE3(enum mdp_mixer_stage_id val)
264{
265 return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE3__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE3__MASK;
266}
267#define MDP4_LAYERMIXER_IN_CFG_PIPE3_MIXER1 0x00008000
268#define MDP4_LAYERMIXER_IN_CFG_PIPE4__MASK 0x00070000
269#define MDP4_LAYERMIXER_IN_CFG_PIPE4__SHIFT 16
270static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE4(enum mdp_mixer_stage_id val)
271{
272 return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE4__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE4__MASK;
273}
274#define MDP4_LAYERMIXER_IN_CFG_PIPE4_MIXER1 0x00080000
275#define MDP4_LAYERMIXER_IN_CFG_PIPE5__MASK 0x00700000
276#define MDP4_LAYERMIXER_IN_CFG_PIPE5__SHIFT 20
277static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE5(enum mdp_mixer_stage_id val)
278{
279 return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE5__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE5__MASK;
280}
281#define MDP4_LAYERMIXER_IN_CFG_PIPE5_MIXER1 0x00800000
282#define MDP4_LAYERMIXER_IN_CFG_PIPE6__MASK 0x07000000
283#define MDP4_LAYERMIXER_IN_CFG_PIPE6__SHIFT 24
284static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE6(enum mdp_mixer_stage_id val)
285{
286 return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE6__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE6__MASK;
287}
288#define MDP4_LAYERMIXER_IN_CFG_PIPE6_MIXER1 0x08000000
289#define MDP4_LAYERMIXER_IN_CFG_PIPE7__MASK 0x70000000
290#define MDP4_LAYERMIXER_IN_CFG_PIPE7__SHIFT 28
291static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE7(enum mdp_mixer_stage_id val)
292{
293 return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE7__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE7__MASK;
294}
295#define MDP4_LAYERMIXER_IN_CFG_PIPE7_MIXER1 0x80000000
296
297#define REG_MDP4_VG2_SRC_FORMAT 0x00030050
298
299#define REG_MDP4_VG2_CONST_COLOR 0x00031008
300
301#define REG_MDP4_OVERLAY_FLUSH 0x00018000
302#define MDP4_OVERLAY_FLUSH_OVLP0 0x00000001
303#define MDP4_OVERLAY_FLUSH_OVLP1 0x00000002
304#define MDP4_OVERLAY_FLUSH_VG1 0x00000004
305#define MDP4_OVERLAY_FLUSH_VG2 0x00000008
306#define MDP4_OVERLAY_FLUSH_RGB1 0x00000010
307#define MDP4_OVERLAY_FLUSH_RGB2 0x00000020
308
309static inline uint32_t __offset_OVLP(uint32_t idx)
310{
311 switch (idx) {
312 case 0: return 0x00010000;
313 case 1: return 0x00018000;
314 case 2: return 0x00088000;
315 default: return INVALID_IDX(idx);
316 }
317}
318static inline uint32_t REG_MDP4_OVLP(uint32_t i0) { return 0x00000000 + __offset_OVLP(i0); }
319
320static inline uint32_t REG_MDP4_OVLP_CFG(uint32_t i0) { return 0x00000004 + __offset_OVLP(i0); }
321
322static inline uint32_t REG_MDP4_OVLP_SIZE(uint32_t i0) { return 0x00000008 + __offset_OVLP(i0); }
323#define MDP4_OVLP_SIZE_HEIGHT__MASK 0xffff0000
324#define MDP4_OVLP_SIZE_HEIGHT__SHIFT 16
325static inline uint32_t MDP4_OVLP_SIZE_HEIGHT(uint32_t val)
326{
327 return ((val) << MDP4_OVLP_SIZE_HEIGHT__SHIFT) & MDP4_OVLP_SIZE_HEIGHT__MASK;
328}
329#define MDP4_OVLP_SIZE_WIDTH__MASK 0x0000ffff
330#define MDP4_OVLP_SIZE_WIDTH__SHIFT 0
331static inline uint32_t MDP4_OVLP_SIZE_WIDTH(uint32_t val)
332{
333 return ((val) << MDP4_OVLP_SIZE_WIDTH__SHIFT) & MDP4_OVLP_SIZE_WIDTH__MASK;
334}
335
336static inline uint32_t REG_MDP4_OVLP_BASE(uint32_t i0) { return 0x0000000c + __offset_OVLP(i0); }
337
338static inline uint32_t REG_MDP4_OVLP_STRIDE(uint32_t i0) { return 0x00000010 + __offset_OVLP(i0); }
339
340static inline uint32_t REG_MDP4_OVLP_OPMODE(uint32_t i0) { return 0x00000014 + __offset_OVLP(i0); }
341
342static inline uint32_t __offset_STAGE(uint32_t idx)
343{
344 switch (idx) {
345 case 0: return 0x00000104;
346 case 1: return 0x00000124;
347 case 2: return 0x00000144;
348 case 3: return 0x00000160;
349 default: return INVALID_IDX(idx);
350 }
351}
352static inline uint32_t REG_MDP4_OVLP_STAGE(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE(i1); }
353
354static inline uint32_t REG_MDP4_OVLP_STAGE_OP(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE(i1); }
355#define MDP4_OVLP_STAGE_OP_FG_ALPHA__MASK 0x00000003
356#define MDP4_OVLP_STAGE_OP_FG_ALPHA__SHIFT 0
357static inline uint32_t MDP4_OVLP_STAGE_OP_FG_ALPHA(enum mdp_alpha_type val)
358{
359 return ((val) << MDP4_OVLP_STAGE_OP_FG_ALPHA__SHIFT) & MDP4_OVLP_STAGE_OP_FG_ALPHA__MASK;
360}
361#define MDP4_OVLP_STAGE_OP_FG_INV_ALPHA 0x00000004
362#define MDP4_OVLP_STAGE_OP_FG_MOD_ALPHA 0x00000008
363#define MDP4_OVLP_STAGE_OP_BG_ALPHA__MASK 0x00000030
364#define MDP4_OVLP_STAGE_OP_BG_ALPHA__SHIFT 4
365static inline uint32_t MDP4_OVLP_STAGE_OP_BG_ALPHA(enum mdp_alpha_type val)
366{
367 return ((val) << MDP4_OVLP_STAGE_OP_BG_ALPHA__SHIFT) & MDP4_OVLP_STAGE_OP_BG_ALPHA__MASK;
368}
369#define MDP4_OVLP_STAGE_OP_BG_INV_ALPHA 0x00000040
370#define MDP4_OVLP_STAGE_OP_BG_MOD_ALPHA 0x00000080
371#define MDP4_OVLP_STAGE_OP_FG_TRANSP 0x00000100
372#define MDP4_OVLP_STAGE_OP_BG_TRANSP 0x00000200
373
374static inline uint32_t REG_MDP4_OVLP_STAGE_FG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000004 + __offset_OVLP(i0) + __offset_STAGE(i1); }
375
376static inline uint32_t REG_MDP4_OVLP_STAGE_BG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000008 + __offset_OVLP(i0) + __offset_STAGE(i1); }
377
378static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000000c + __offset_OVLP(i0) + __offset_STAGE(i1); }
379
380static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000010 + __offset_OVLP(i0) + __offset_STAGE(i1); }
381
382static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000014 + __offset_OVLP(i0) + __offset_STAGE(i1); }
383
384static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000018 + __offset_OVLP(i0) + __offset_STAGE(i1); }
385
386static inline uint32_t __offset_STAGE_CO3(uint32_t idx)
387{
388 switch (idx) {
389 case 0: return 0x00001004;
390 case 1: return 0x00001404;
391 case 2: return 0x00001804;
392 case 3: return 0x00001b84;
393 default: return INVALID_IDX(idx);
394 }
395}
396static inline uint32_t REG_MDP4_OVLP_STAGE_CO3(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE_CO3(i1); }
397
398static inline uint32_t REG_MDP4_OVLP_STAGE_CO3_SEL(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE_CO3(i1); }
399#define MDP4_OVLP_STAGE_CO3_SEL_FG_ALPHA 0x00000001
400
401static inline uint32_t REG_MDP4_OVLP_TRANSP_LOW0(uint32_t i0) { return 0x00000180 + __offset_OVLP(i0); }
402
403static inline uint32_t REG_MDP4_OVLP_TRANSP_LOW1(uint32_t i0) { return 0x00000184 + __offset_OVLP(i0); }
404
405static inline uint32_t REG_MDP4_OVLP_TRANSP_HIGH0(uint32_t i0) { return 0x00000188 + __offset_OVLP(i0); }
406
407static inline uint32_t REG_MDP4_OVLP_TRANSP_HIGH1(uint32_t i0) { return 0x0000018c + __offset_OVLP(i0); }
408
409static inline uint32_t REG_MDP4_OVLP_CSC_CONFIG(uint32_t i0) { return 0x00000200 + __offset_OVLP(i0); }
410
411static inline uint32_t REG_MDP4_OVLP_CSC(uint32_t i0) { return 0x00002000 + __offset_OVLP(i0); }
412
413
414static inline uint32_t REG_MDP4_OVLP_CSC_MV(uint32_t i0, uint32_t i1) { return 0x00002400 + __offset_OVLP(i0) + 0x4*i1; }
415
416static inline uint32_t REG_MDP4_OVLP_CSC_MV_VAL(uint32_t i0, uint32_t i1) { return 0x00002400 + __offset_OVLP(i0) + 0x4*i1; }
417
418static inline uint32_t REG_MDP4_OVLP_CSC_PRE_BV(uint32_t i0, uint32_t i1) { return 0x00002500 + __offset_OVLP(i0) + 0x4*i1; }
419
420static inline uint32_t REG_MDP4_OVLP_CSC_PRE_BV_VAL(uint32_t i0, uint32_t i1) { return 0x00002500 + __offset_OVLP(i0) + 0x4*i1; }
421
422static inline uint32_t REG_MDP4_OVLP_CSC_POST_BV(uint32_t i0, uint32_t i1) { return 0x00002580 + __offset_OVLP(i0) + 0x4*i1; }
423
424static inline uint32_t REG_MDP4_OVLP_CSC_POST_BV_VAL(uint32_t i0, uint32_t i1) { return 0x00002580 + __offset_OVLP(i0) + 0x4*i1; }
425
426static inline uint32_t REG_MDP4_OVLP_CSC_PRE_LV(uint32_t i0, uint32_t i1) { return 0x00002600 + __offset_OVLP(i0) + 0x4*i1; }
427
428static inline uint32_t REG_MDP4_OVLP_CSC_PRE_LV_VAL(uint32_t i0, uint32_t i1) { return 0x00002600 + __offset_OVLP(i0) + 0x4*i1; }
429
430static inline uint32_t REG_MDP4_OVLP_CSC_POST_LV(uint32_t i0, uint32_t i1) { return 0x00002680 + __offset_OVLP(i0) + 0x4*i1; }
431
432static inline uint32_t REG_MDP4_OVLP_CSC_POST_LV_VAL(uint32_t i0, uint32_t i1) { return 0x00002680 + __offset_OVLP(i0) + 0x4*i1; }
433
434#define REG_MDP4_DMA_P_OP_MODE 0x00090070
435
436static inline uint32_t REG_MDP4_LUTN(uint32_t i0) { return 0x00094800 + 0x400*i0; }
437
438static inline uint32_t REG_MDP4_LUTN_LUT(uint32_t i0, uint32_t i1) { return 0x00094800 + 0x400*i0 + 0x4*i1; }
439
440static inline uint32_t REG_MDP4_LUTN_LUT_VAL(uint32_t i0, uint32_t i1) { return 0x00094800 + 0x400*i0 + 0x4*i1; }
441
442#define REG_MDP4_DMA_S_OP_MODE 0x000a0028
443
444static inline uint32_t REG_MDP4_DMA_E_QUANT(uint32_t i0) { return 0x000b0070 + 0x4*i0; }
445
446static inline uint32_t __offset_DMA(enum mdp4_dma idx)
447{
448 switch (idx) {
449 case DMA_P: return 0x00090000;
450 case DMA_S: return 0x000a0000;
451 case DMA_E: return 0x000b0000;
452 default: return INVALID_IDX(idx);
453 }
454}
455static inline uint32_t REG_MDP4_DMA(enum mdp4_dma i0) { return 0x00000000 + __offset_DMA(i0); }
456
457static inline uint32_t REG_MDP4_DMA_CONFIG(enum mdp4_dma i0) { return 0x00000000 + __offset_DMA(i0); }
458#define MDP4_DMA_CONFIG_G_BPC__MASK 0x00000003
459#define MDP4_DMA_CONFIG_G_BPC__SHIFT 0
460static inline uint32_t MDP4_DMA_CONFIG_G_BPC(enum mdp_bpc val)
461{
462 return ((val) << MDP4_DMA_CONFIG_G_BPC__SHIFT) & MDP4_DMA_CONFIG_G_BPC__MASK;
463}
464#define MDP4_DMA_CONFIG_B_BPC__MASK 0x0000000c
465#define MDP4_DMA_CONFIG_B_BPC__SHIFT 2
466static inline uint32_t MDP4_DMA_CONFIG_B_BPC(enum mdp_bpc val)
467{
468 return ((val) << MDP4_DMA_CONFIG_B_BPC__SHIFT) & MDP4_DMA_CONFIG_B_BPC__MASK;
469}
470#define MDP4_DMA_CONFIG_R_BPC__MASK 0x00000030
471#define MDP4_DMA_CONFIG_R_BPC__SHIFT 4
472static inline uint32_t MDP4_DMA_CONFIG_R_BPC(enum mdp_bpc val)
473{
474 return ((val) << MDP4_DMA_CONFIG_R_BPC__SHIFT) & MDP4_DMA_CONFIG_R_BPC__MASK;
475}
476#define MDP4_DMA_CONFIG_PACK_ALIGN_MSB 0x00000080
477#define MDP4_DMA_CONFIG_PACK__MASK 0x0000ff00
478#define MDP4_DMA_CONFIG_PACK__SHIFT 8
479static inline uint32_t MDP4_DMA_CONFIG_PACK(uint32_t val)
480{
481 return ((val) << MDP4_DMA_CONFIG_PACK__SHIFT) & MDP4_DMA_CONFIG_PACK__MASK;
482}
483#define MDP4_DMA_CONFIG_DEFLKR_EN 0x01000000
484#define MDP4_DMA_CONFIG_DITHER_EN 0x01000000
485
486static inline uint32_t REG_MDP4_DMA_SRC_SIZE(enum mdp4_dma i0) { return 0x00000004 + __offset_DMA(i0); }
487#define MDP4_DMA_SRC_SIZE_HEIGHT__MASK 0xffff0000
488#define MDP4_DMA_SRC_SIZE_HEIGHT__SHIFT 16
489static inline uint32_t MDP4_DMA_SRC_SIZE_HEIGHT(uint32_t val)
490{
491 return ((val) << MDP4_DMA_SRC_SIZE_HEIGHT__SHIFT) & MDP4_DMA_SRC_SIZE_HEIGHT__MASK;
492}
493#define MDP4_DMA_SRC_SIZE_WIDTH__MASK 0x0000ffff
494#define MDP4_DMA_SRC_SIZE_WIDTH__SHIFT 0
495static inline uint32_t MDP4_DMA_SRC_SIZE_WIDTH(uint32_t val)
496{
497 return ((val) << MDP4_DMA_SRC_SIZE_WIDTH__SHIFT) & MDP4_DMA_SRC_SIZE_WIDTH__MASK;
498}
499
500static inline uint32_t REG_MDP4_DMA_SRC_BASE(enum mdp4_dma i0) { return 0x00000008 + __offset_DMA(i0); }
501
502static inline uint32_t REG_MDP4_DMA_SRC_STRIDE(enum mdp4_dma i0) { return 0x0000000c + __offset_DMA(i0); }
503
504static inline uint32_t REG_MDP4_DMA_DST_SIZE(enum mdp4_dma i0) { return 0x00000010 + __offset_DMA(i0); }
505#define MDP4_DMA_DST_SIZE_HEIGHT__MASK 0xffff0000
506#define MDP4_DMA_DST_SIZE_HEIGHT__SHIFT 16
507static inline uint32_t MDP4_DMA_DST_SIZE_HEIGHT(uint32_t val)
508{
509 return ((val) << MDP4_DMA_DST_SIZE_HEIGHT__SHIFT) & MDP4_DMA_DST_SIZE_HEIGHT__MASK;
510}
511#define MDP4_DMA_DST_SIZE_WIDTH__MASK 0x0000ffff
512#define MDP4_DMA_DST_SIZE_WIDTH__SHIFT 0
513static inline uint32_t MDP4_DMA_DST_SIZE_WIDTH(uint32_t val)
514{
515 return ((val) << MDP4_DMA_DST_SIZE_WIDTH__SHIFT) & MDP4_DMA_DST_SIZE_WIDTH__MASK;
516}
517
518static inline uint32_t REG_MDP4_DMA_CURSOR_SIZE(enum mdp4_dma i0) { return 0x00000044 + __offset_DMA(i0); }
519#define MDP4_DMA_CURSOR_SIZE_WIDTH__MASK 0x0000007f
520#define MDP4_DMA_CURSOR_SIZE_WIDTH__SHIFT 0
521static inline uint32_t MDP4_DMA_CURSOR_SIZE_WIDTH(uint32_t val)
522{
523 return ((val) << MDP4_DMA_CURSOR_SIZE_WIDTH__SHIFT) & MDP4_DMA_CURSOR_SIZE_WIDTH__MASK;
524}
525#define MDP4_DMA_CURSOR_SIZE_HEIGHT__MASK 0x007f0000
526#define MDP4_DMA_CURSOR_SIZE_HEIGHT__SHIFT 16
527static inline uint32_t MDP4_DMA_CURSOR_SIZE_HEIGHT(uint32_t val)
528{
529 return ((val) << MDP4_DMA_CURSOR_SIZE_HEIGHT__SHIFT) & MDP4_DMA_CURSOR_SIZE_HEIGHT__MASK;
530}
531
532static inline uint32_t REG_MDP4_DMA_CURSOR_BASE(enum mdp4_dma i0) { return 0x00000048 + __offset_DMA(i0); }
533
534static inline uint32_t REG_MDP4_DMA_CURSOR_POS(enum mdp4_dma i0) { return 0x0000004c + __offset_DMA(i0); }
535#define MDP4_DMA_CURSOR_POS_X__MASK 0x0000ffff
536#define MDP4_DMA_CURSOR_POS_X__SHIFT 0
537static inline uint32_t MDP4_DMA_CURSOR_POS_X(uint32_t val)
538{
539 return ((val) << MDP4_DMA_CURSOR_POS_X__SHIFT) & MDP4_DMA_CURSOR_POS_X__MASK;
540}
541#define MDP4_DMA_CURSOR_POS_Y__MASK 0xffff0000
542#define MDP4_DMA_CURSOR_POS_Y__SHIFT 16
543static inline uint32_t MDP4_DMA_CURSOR_POS_Y(uint32_t val)
544{
545 return ((val) << MDP4_DMA_CURSOR_POS_Y__SHIFT) & MDP4_DMA_CURSOR_POS_Y__MASK;
546}
547
548static inline uint32_t REG_MDP4_DMA_CURSOR_BLEND_CONFIG(enum mdp4_dma i0) { return 0x00000060 + __offset_DMA(i0); }
549#define MDP4_DMA_CURSOR_BLEND_CONFIG_CURSOR_EN 0x00000001
550#define MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT__MASK 0x00000006
551#define MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT__SHIFT 1
552static inline uint32_t MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT(enum mdp4_cursor_format val)
553{
554 return ((val) << MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT__SHIFT) & MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT__MASK;
555}
556#define MDP4_DMA_CURSOR_BLEND_CONFIG_TRANSP_EN 0x00000008
557
558static inline uint32_t REG_MDP4_DMA_CURSOR_BLEND_PARAM(enum mdp4_dma i0) { return 0x00000064 + __offset_DMA(i0); }
559
560static inline uint32_t REG_MDP4_DMA_BLEND_TRANS_LOW(enum mdp4_dma i0) { return 0x00000068 + __offset_DMA(i0); }
561
562static inline uint32_t REG_MDP4_DMA_BLEND_TRANS_HIGH(enum mdp4_dma i0) { return 0x0000006c + __offset_DMA(i0); }
563
564static inline uint32_t REG_MDP4_DMA_FETCH_CONFIG(enum mdp4_dma i0) { return 0x00001004 + __offset_DMA(i0); }
565
566static inline uint32_t REG_MDP4_DMA_CSC(enum mdp4_dma i0) { return 0x00003000 + __offset_DMA(i0); }
567
568
569static inline uint32_t REG_MDP4_DMA_CSC_MV(enum mdp4_dma i0, uint32_t i1) { return 0x00003400 + __offset_DMA(i0) + 0x4*i1; }
570
571static inline uint32_t REG_MDP4_DMA_CSC_MV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003400 + __offset_DMA(i0) + 0x4*i1; }
572
573static inline uint32_t REG_MDP4_DMA_CSC_PRE_BV(enum mdp4_dma i0, uint32_t i1) { return 0x00003500 + __offset_DMA(i0) + 0x4*i1; }
574
575static inline uint32_t REG_MDP4_DMA_CSC_PRE_BV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003500 + __offset_DMA(i0) + 0x4*i1; }
576
577static inline uint32_t REG_MDP4_DMA_CSC_POST_BV(enum mdp4_dma i0, uint32_t i1) { return 0x00003580 + __offset_DMA(i0) + 0x4*i1; }
578
579static inline uint32_t REG_MDP4_DMA_CSC_POST_BV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003580 + __offset_DMA(i0) + 0x4*i1; }
580
581static inline uint32_t REG_MDP4_DMA_CSC_PRE_LV(enum mdp4_dma i0, uint32_t i1) { return 0x00003600 + __offset_DMA(i0) + 0x4*i1; }
582
583static inline uint32_t REG_MDP4_DMA_CSC_PRE_LV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003600 + __offset_DMA(i0) + 0x4*i1; }
584
585static inline uint32_t REG_MDP4_DMA_CSC_POST_LV(enum mdp4_dma i0, uint32_t i1) { return 0x00003680 + __offset_DMA(i0) + 0x4*i1; }
586
587static inline uint32_t REG_MDP4_DMA_CSC_POST_LV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003680 + __offset_DMA(i0) + 0x4*i1; }
588
589static inline uint32_t REG_MDP4_PIPE(enum mdp4_pipe i0) { return 0x00020000 + 0x10000*i0; }
590
591static inline uint32_t REG_MDP4_PIPE_SRC_SIZE(enum mdp4_pipe i0) { return 0x00020000 + 0x10000*i0; }
592#define MDP4_PIPE_SRC_SIZE_HEIGHT__MASK 0xffff0000
593#define MDP4_PIPE_SRC_SIZE_HEIGHT__SHIFT 16
594static inline uint32_t MDP4_PIPE_SRC_SIZE_HEIGHT(uint32_t val)
595{
596 return ((val) << MDP4_PIPE_SRC_SIZE_HEIGHT__SHIFT) & MDP4_PIPE_SRC_SIZE_HEIGHT__MASK;
597}
598#define MDP4_PIPE_SRC_SIZE_WIDTH__MASK 0x0000ffff
599#define MDP4_PIPE_SRC_SIZE_WIDTH__SHIFT 0
600static inline uint32_t MDP4_PIPE_SRC_SIZE_WIDTH(uint32_t val)
601{
602 return ((val) << MDP4_PIPE_SRC_SIZE_WIDTH__SHIFT) & MDP4_PIPE_SRC_SIZE_WIDTH__MASK;
603}
604
605static inline uint32_t REG_MDP4_PIPE_SRC_XY(enum mdp4_pipe i0) { return 0x00020004 + 0x10000*i0; }
606#define MDP4_PIPE_SRC_XY_Y__MASK 0xffff0000
607#define MDP4_PIPE_SRC_XY_Y__SHIFT 16
608static inline uint32_t MDP4_PIPE_SRC_XY_Y(uint32_t val)
609{
610 return ((val) << MDP4_PIPE_SRC_XY_Y__SHIFT) & MDP4_PIPE_SRC_XY_Y__MASK;
611}
612#define MDP4_PIPE_SRC_XY_X__MASK 0x0000ffff
613#define MDP4_PIPE_SRC_XY_X__SHIFT 0
614static inline uint32_t MDP4_PIPE_SRC_XY_X(uint32_t val)
615{
616 return ((val) << MDP4_PIPE_SRC_XY_X__SHIFT) & MDP4_PIPE_SRC_XY_X__MASK;
617}
618
619static inline uint32_t REG_MDP4_PIPE_DST_SIZE(enum mdp4_pipe i0) { return 0x00020008 + 0x10000*i0; }
620#define MDP4_PIPE_DST_SIZE_HEIGHT__MASK 0xffff0000
621#define MDP4_PIPE_DST_SIZE_HEIGHT__SHIFT 16
622static inline uint32_t MDP4_PIPE_DST_SIZE_HEIGHT(uint32_t val)
623{
624 return ((val) << MDP4_PIPE_DST_SIZE_HEIGHT__SHIFT) & MDP4_PIPE_DST_SIZE_HEIGHT__MASK;
625}
626#define MDP4_PIPE_DST_SIZE_WIDTH__MASK 0x0000ffff
627#define MDP4_PIPE_DST_SIZE_WIDTH__SHIFT 0
628static inline uint32_t MDP4_PIPE_DST_SIZE_WIDTH(uint32_t val)
629{
630 return ((val) << MDP4_PIPE_DST_SIZE_WIDTH__SHIFT) & MDP4_PIPE_DST_SIZE_WIDTH__MASK;
631}
632
633static inline uint32_t REG_MDP4_PIPE_DST_XY(enum mdp4_pipe i0) { return 0x0002000c + 0x10000*i0; }
634#define MDP4_PIPE_DST_XY_Y__MASK 0xffff0000
635#define MDP4_PIPE_DST_XY_Y__SHIFT 16
636static inline uint32_t MDP4_PIPE_DST_XY_Y(uint32_t val)
637{
638 return ((val) << MDP4_PIPE_DST_XY_Y__SHIFT) & MDP4_PIPE_DST_XY_Y__MASK;
639}
640#define MDP4_PIPE_DST_XY_X__MASK 0x0000ffff
641#define MDP4_PIPE_DST_XY_X__SHIFT 0
642static inline uint32_t MDP4_PIPE_DST_XY_X(uint32_t val)
643{
644 return ((val) << MDP4_PIPE_DST_XY_X__SHIFT) & MDP4_PIPE_DST_XY_X__MASK;
645}
646
647static inline uint32_t REG_MDP4_PIPE_SRCP0_BASE(enum mdp4_pipe i0) { return 0x00020010 + 0x10000*i0; }
648
649static inline uint32_t REG_MDP4_PIPE_SRCP1_BASE(enum mdp4_pipe i0) { return 0x00020014 + 0x10000*i0; }
650
651static inline uint32_t REG_MDP4_PIPE_SRCP2_BASE(enum mdp4_pipe i0) { return 0x00020018 + 0x10000*i0; }
652
653static inline uint32_t REG_MDP4_PIPE_SRCP3_BASE(enum mdp4_pipe i0) { return 0x0002001c + 0x10000*i0; }
654
655static inline uint32_t REG_MDP4_PIPE_SRC_STRIDE_A(enum mdp4_pipe i0) { return 0x00020040 + 0x10000*i0; }
656#define MDP4_PIPE_SRC_STRIDE_A_P0__MASK 0x0000ffff
657#define MDP4_PIPE_SRC_STRIDE_A_P0__SHIFT 0
658static inline uint32_t MDP4_PIPE_SRC_STRIDE_A_P0(uint32_t val)
659{
660 return ((val) << MDP4_PIPE_SRC_STRIDE_A_P0__SHIFT) & MDP4_PIPE_SRC_STRIDE_A_P0__MASK;
661}
662#define MDP4_PIPE_SRC_STRIDE_A_P1__MASK 0xffff0000
663#define MDP4_PIPE_SRC_STRIDE_A_P1__SHIFT 16
664static inline uint32_t MDP4_PIPE_SRC_STRIDE_A_P1(uint32_t val)
665{
666 return ((val) << MDP4_PIPE_SRC_STRIDE_A_P1__SHIFT) & MDP4_PIPE_SRC_STRIDE_A_P1__MASK;
667}
668
669static inline uint32_t REG_MDP4_PIPE_SRC_STRIDE_B(enum mdp4_pipe i0) { return 0x00020044 + 0x10000*i0; }
670#define MDP4_PIPE_SRC_STRIDE_B_P2__MASK 0x0000ffff
671#define MDP4_PIPE_SRC_STRIDE_B_P2__SHIFT 0
672static inline uint32_t MDP4_PIPE_SRC_STRIDE_B_P2(uint32_t val)
673{
674 return ((val) << MDP4_PIPE_SRC_STRIDE_B_P2__SHIFT) & MDP4_PIPE_SRC_STRIDE_B_P2__MASK;
675}
676#define MDP4_PIPE_SRC_STRIDE_B_P3__MASK 0xffff0000
677#define MDP4_PIPE_SRC_STRIDE_B_P3__SHIFT 16
678static inline uint32_t MDP4_PIPE_SRC_STRIDE_B_P3(uint32_t val)
679{
680 return ((val) << MDP4_PIPE_SRC_STRIDE_B_P3__SHIFT) & MDP4_PIPE_SRC_STRIDE_B_P3__MASK;
681}
682
683static inline uint32_t REG_MDP4_PIPE_SSTILE_FRAME_SIZE(enum mdp4_pipe i0) { return 0x00020048 + 0x10000*i0; }
684#define MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT__MASK 0xffff0000
685#define MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT__SHIFT 16
686static inline uint32_t MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT(uint32_t val)
687{
688 return ((val) << MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT__SHIFT) & MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT__MASK;
689}
690#define MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH__MASK 0x0000ffff
691#define MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH__SHIFT 0
692static inline uint32_t MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH(uint32_t val)
693{
694 return ((val) << MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH__SHIFT) & MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH__MASK;
695}
696
697static inline uint32_t REG_MDP4_PIPE_SRC_FORMAT(enum mdp4_pipe i0) { return 0x00020050 + 0x10000*i0; }
698#define MDP4_PIPE_SRC_FORMAT_G_BPC__MASK 0x00000003
699#define MDP4_PIPE_SRC_FORMAT_G_BPC__SHIFT 0
700static inline uint32_t MDP4_PIPE_SRC_FORMAT_G_BPC(enum mdp_bpc val)
701{
702 return ((val) << MDP4_PIPE_SRC_FORMAT_G_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_G_BPC__MASK;
703}
704#define MDP4_PIPE_SRC_FORMAT_B_BPC__MASK 0x0000000c
705#define MDP4_PIPE_SRC_FORMAT_B_BPC__SHIFT 2
706static inline uint32_t MDP4_PIPE_SRC_FORMAT_B_BPC(enum mdp_bpc val)
707{
708 return ((val) << MDP4_PIPE_SRC_FORMAT_B_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_B_BPC__MASK;
709}
710#define MDP4_PIPE_SRC_FORMAT_R_BPC__MASK 0x00000030
711#define MDP4_PIPE_SRC_FORMAT_R_BPC__SHIFT 4
712static inline uint32_t MDP4_PIPE_SRC_FORMAT_R_BPC(enum mdp_bpc val)
713{
714 return ((val) << MDP4_PIPE_SRC_FORMAT_R_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_R_BPC__MASK;
715}
716#define MDP4_PIPE_SRC_FORMAT_A_BPC__MASK 0x000000c0
717#define MDP4_PIPE_SRC_FORMAT_A_BPC__SHIFT 6
718static inline uint32_t MDP4_PIPE_SRC_FORMAT_A_BPC(enum mdp_bpc_alpha val)
719{
720 return ((val) << MDP4_PIPE_SRC_FORMAT_A_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_A_BPC__MASK;
721}
722#define MDP4_PIPE_SRC_FORMAT_ALPHA_ENABLE 0x00000100
723#define MDP4_PIPE_SRC_FORMAT_CPP__MASK 0x00000600
724#define MDP4_PIPE_SRC_FORMAT_CPP__SHIFT 9
725static inline uint32_t MDP4_PIPE_SRC_FORMAT_CPP(uint32_t val)
726{
727 return ((val) << MDP4_PIPE_SRC_FORMAT_CPP__SHIFT) & MDP4_PIPE_SRC_FORMAT_CPP__MASK;
728}
729#define MDP4_PIPE_SRC_FORMAT_ROTATED_90 0x00001000
730#define MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT__MASK 0x00006000
731#define MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT__SHIFT 13
732static inline uint32_t MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT(uint32_t val)
733{
734 return ((val) << MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT__SHIFT) & MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT__MASK;
735}
736#define MDP4_PIPE_SRC_FORMAT_UNPACK_TIGHT 0x00020000
737#define MDP4_PIPE_SRC_FORMAT_UNPACK_ALIGN_MSB 0x00040000
738#define MDP4_PIPE_SRC_FORMAT_FETCH_PLANES__MASK 0x00180000
739#define MDP4_PIPE_SRC_FORMAT_FETCH_PLANES__SHIFT 19
740static inline uint32_t MDP4_PIPE_SRC_FORMAT_FETCH_PLANES(uint32_t val)
741{
742 return ((val) << MDP4_PIPE_SRC_FORMAT_FETCH_PLANES__SHIFT) & MDP4_PIPE_SRC_FORMAT_FETCH_PLANES__MASK;
743}
744#define MDP4_PIPE_SRC_FORMAT_SOLID_FILL 0x00400000
745#define MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP__MASK 0x0c000000
746#define MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP__SHIFT 26
747static inline uint32_t MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP(enum mdp_chroma_samp_type val)
748{
749 return ((val) << MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP__SHIFT) & MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP__MASK;
750}
751#define MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT__MASK 0x60000000
752#define MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT__SHIFT 29
753static inline uint32_t MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT(enum mdp4_frame_format val)
754{
755 return ((val) << MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT__SHIFT) & MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT__MASK;
756}
757
758static inline uint32_t REG_MDP4_PIPE_SRC_UNPACK(enum mdp4_pipe i0) { return 0x00020054 + 0x10000*i0; }
759#define MDP4_PIPE_SRC_UNPACK_ELEM0__MASK 0x000000ff
760#define MDP4_PIPE_SRC_UNPACK_ELEM0__SHIFT 0
761static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM0(uint32_t val)
762{
763 return ((val) << MDP4_PIPE_SRC_UNPACK_ELEM0__SHIFT) & MDP4_PIPE_SRC_UNPACK_ELEM0__MASK;
764}
765#define MDP4_PIPE_SRC_UNPACK_ELEM1__MASK 0x0000ff00
766#define MDP4_PIPE_SRC_UNPACK_ELEM1__SHIFT 8
767static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM1(uint32_t val)
768{
769 return ((val) << MDP4_PIPE_SRC_UNPACK_ELEM1__SHIFT) & MDP4_PIPE_SRC_UNPACK_ELEM1__MASK;
770}
771#define MDP4_PIPE_SRC_UNPACK_ELEM2__MASK 0x00ff0000
772#define MDP4_PIPE_SRC_UNPACK_ELEM2__SHIFT 16
773static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM2(uint32_t val)
774{
775 return ((val) << MDP4_PIPE_SRC_UNPACK_ELEM2__SHIFT) & MDP4_PIPE_SRC_UNPACK_ELEM2__MASK;
776}
777#define MDP4_PIPE_SRC_UNPACK_ELEM3__MASK 0xff000000
778#define MDP4_PIPE_SRC_UNPACK_ELEM3__SHIFT 24
779static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM3(uint32_t val)
780{
781 return ((val) << MDP4_PIPE_SRC_UNPACK_ELEM3__SHIFT) & MDP4_PIPE_SRC_UNPACK_ELEM3__MASK;
782}
783
784static inline uint32_t REG_MDP4_PIPE_OP_MODE(enum mdp4_pipe i0) { return 0x00020058 + 0x10000*i0; }
785#define MDP4_PIPE_OP_MODE_SCALEX_EN 0x00000001
786#define MDP4_PIPE_OP_MODE_SCALEY_EN 0x00000002
787#define MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL__MASK 0x0000000c
788#define MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL__SHIFT 2
789static inline uint32_t MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL(enum mdp4_scale_unit val)
790{
791 return ((val) << MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL__SHIFT) & MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL__MASK;
792}
793#define MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL__MASK 0x00000030
794#define MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL__SHIFT 4
795static inline uint32_t MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL(enum mdp4_scale_unit val)
796{
797 return ((val) << MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL__SHIFT) & MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL__MASK;
798}
799#define MDP4_PIPE_OP_MODE_SRC_YCBCR 0x00000200
800#define MDP4_PIPE_OP_MODE_DST_YCBCR 0x00000400
801#define MDP4_PIPE_OP_MODE_CSC_EN 0x00000800
802#define MDP4_PIPE_OP_MODE_FLIP_LR 0x00002000
803#define MDP4_PIPE_OP_MODE_FLIP_UD 0x00004000
804#define MDP4_PIPE_OP_MODE_DITHER_EN 0x00008000
805#define MDP4_PIPE_OP_MODE_IGC_LUT_EN 0x00010000
806#define MDP4_PIPE_OP_MODE_DEINT_EN 0x00040000
807#define MDP4_PIPE_OP_MODE_DEINT_ODD_REF 0x00080000
808
809static inline uint32_t REG_MDP4_PIPE_PHASEX_STEP(enum mdp4_pipe i0) { return 0x0002005c + 0x10000*i0; }
810
811static inline uint32_t REG_MDP4_PIPE_PHASEY_STEP(enum mdp4_pipe i0) { return 0x00020060 + 0x10000*i0; }
812
813static inline uint32_t REG_MDP4_PIPE_FETCH_CONFIG(enum mdp4_pipe i0) { return 0x00021004 + 0x10000*i0; }
814
815static inline uint32_t REG_MDP4_PIPE_SOLID_COLOR(enum mdp4_pipe i0) { return 0x00021008 + 0x10000*i0; }
816
817static inline uint32_t REG_MDP4_PIPE_CSC(enum mdp4_pipe i0) { return 0x00024000 + 0x10000*i0; }
818
819
820static inline uint32_t REG_MDP4_PIPE_CSC_MV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024400 + 0x10000*i0 + 0x4*i1; }
821
822static inline uint32_t REG_MDP4_PIPE_CSC_MV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024400 + 0x10000*i0 + 0x4*i1; }
823
824static inline uint32_t REG_MDP4_PIPE_CSC_PRE_BV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024500 + 0x10000*i0 + 0x4*i1; }
825
826static inline uint32_t REG_MDP4_PIPE_CSC_PRE_BV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024500 + 0x10000*i0 + 0x4*i1; }
827
828static inline uint32_t REG_MDP4_PIPE_CSC_POST_BV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024580 + 0x10000*i0 + 0x4*i1; }
829
830static inline uint32_t REG_MDP4_PIPE_CSC_POST_BV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024580 + 0x10000*i0 + 0x4*i1; }
831
832static inline uint32_t REG_MDP4_PIPE_CSC_PRE_LV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024600 + 0x10000*i0 + 0x4*i1; }
833
834static inline uint32_t REG_MDP4_PIPE_CSC_PRE_LV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024600 + 0x10000*i0 + 0x4*i1; }
835
836static inline uint32_t REG_MDP4_PIPE_CSC_POST_LV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024680 + 0x10000*i0 + 0x4*i1; }
837
838static inline uint32_t REG_MDP4_PIPE_CSC_POST_LV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024680 + 0x10000*i0 + 0x4*i1; }
839
840#define REG_MDP4_LCDC 0x000c0000
841
842#define REG_MDP4_LCDC_ENABLE 0x000c0000
843
844#define REG_MDP4_LCDC_HSYNC_CTRL 0x000c0004
845#define MDP4_LCDC_HSYNC_CTRL_PULSEW__MASK 0x0000ffff
846#define MDP4_LCDC_HSYNC_CTRL_PULSEW__SHIFT 0
847static inline uint32_t MDP4_LCDC_HSYNC_CTRL_PULSEW(uint32_t val)
848{
849 return ((val) << MDP4_LCDC_HSYNC_CTRL_PULSEW__SHIFT) & MDP4_LCDC_HSYNC_CTRL_PULSEW__MASK;
850}
851#define MDP4_LCDC_HSYNC_CTRL_PERIOD__MASK 0xffff0000
852#define MDP4_LCDC_HSYNC_CTRL_PERIOD__SHIFT 16
853static inline uint32_t MDP4_LCDC_HSYNC_CTRL_PERIOD(uint32_t val)
854{
855 return ((val) << MDP4_LCDC_HSYNC_CTRL_PERIOD__SHIFT) & MDP4_LCDC_HSYNC_CTRL_PERIOD__MASK;
856}
857
858#define REG_MDP4_LCDC_VSYNC_PERIOD 0x000c0008
859
860#define REG_MDP4_LCDC_VSYNC_LEN 0x000c000c
861
862#define REG_MDP4_LCDC_DISPLAY_HCTRL 0x000c0010
863#define MDP4_LCDC_DISPLAY_HCTRL_START__MASK 0x0000ffff
864#define MDP4_LCDC_DISPLAY_HCTRL_START__SHIFT 0
865static inline uint32_t MDP4_LCDC_DISPLAY_HCTRL_START(uint32_t val)
866{
867 return ((val) << MDP4_LCDC_DISPLAY_HCTRL_START__SHIFT) & MDP4_LCDC_DISPLAY_HCTRL_START__MASK;
868}
869#define MDP4_LCDC_DISPLAY_HCTRL_END__MASK 0xffff0000
870#define MDP4_LCDC_DISPLAY_HCTRL_END__SHIFT 16
871static inline uint32_t MDP4_LCDC_DISPLAY_HCTRL_END(uint32_t val)
872{
873 return ((val) << MDP4_LCDC_DISPLAY_HCTRL_END__SHIFT) & MDP4_LCDC_DISPLAY_HCTRL_END__MASK;
874}
875
876#define REG_MDP4_LCDC_DISPLAY_VSTART 0x000c0014
877
878#define REG_MDP4_LCDC_DISPLAY_VEND 0x000c0018
879
880#define REG_MDP4_LCDC_ACTIVE_HCTL 0x000c001c
881#define MDP4_LCDC_ACTIVE_HCTL_START__MASK 0x00007fff
882#define MDP4_LCDC_ACTIVE_HCTL_START__SHIFT 0
883static inline uint32_t MDP4_LCDC_ACTIVE_HCTL_START(uint32_t val)
884{
885 return ((val) << MDP4_LCDC_ACTIVE_HCTL_START__SHIFT) & MDP4_LCDC_ACTIVE_HCTL_START__MASK;
886}
887#define MDP4_LCDC_ACTIVE_HCTL_END__MASK 0x7fff0000
888#define MDP4_LCDC_ACTIVE_HCTL_END__SHIFT 16
889static inline uint32_t MDP4_LCDC_ACTIVE_HCTL_END(uint32_t val)
890{
891 return ((val) << MDP4_LCDC_ACTIVE_HCTL_END__SHIFT) & MDP4_LCDC_ACTIVE_HCTL_END__MASK;
892}
893#define MDP4_LCDC_ACTIVE_HCTL_ACTIVE_START_X 0x80000000
894
895#define REG_MDP4_LCDC_ACTIVE_VSTART 0x000c0020
896
897#define REG_MDP4_LCDC_ACTIVE_VEND 0x000c0024
898
899#define REG_MDP4_LCDC_BORDER_CLR 0x000c0028
900
901#define REG_MDP4_LCDC_UNDERFLOW_CLR 0x000c002c
902#define MDP4_LCDC_UNDERFLOW_CLR_COLOR__MASK 0x00ffffff
903#define MDP4_LCDC_UNDERFLOW_CLR_COLOR__SHIFT 0
904static inline uint32_t MDP4_LCDC_UNDERFLOW_CLR_COLOR(uint32_t val)
905{
906 return ((val) << MDP4_LCDC_UNDERFLOW_CLR_COLOR__SHIFT) & MDP4_LCDC_UNDERFLOW_CLR_COLOR__MASK;
907}
908#define MDP4_LCDC_UNDERFLOW_CLR_ENABLE_RECOVERY 0x80000000
909
910#define REG_MDP4_LCDC_HSYNC_SKEW 0x000c0030
911
912#define REG_MDP4_LCDC_TEST_CNTL 0x000c0034
913
914#define REG_MDP4_LCDC_CTRL_POLARITY 0x000c0038
915#define MDP4_LCDC_CTRL_POLARITY_HSYNC_LOW 0x00000001
916#define MDP4_LCDC_CTRL_POLARITY_VSYNC_LOW 0x00000002
917#define MDP4_LCDC_CTRL_POLARITY_DATA_EN_LOW 0x00000004
918
919#define REG_MDP4_LCDC_LVDS_INTF_CTL 0x000c2000
920#define MDP4_LCDC_LVDS_INTF_CTL_MODE_SEL 0x00000004
921#define MDP4_LCDC_LVDS_INTF_CTL_RGB_OUT 0x00000008
922#define MDP4_LCDC_LVDS_INTF_CTL_CH_SWAP 0x00000010
923#define MDP4_LCDC_LVDS_INTF_CTL_CH1_RES_BIT 0x00000020
924#define MDP4_LCDC_LVDS_INTF_CTL_CH2_RES_BIT 0x00000040
925#define MDP4_LCDC_LVDS_INTF_CTL_ENABLE 0x00000080
926#define MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE0_EN 0x00000100
927#define MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE1_EN 0x00000200
928#define MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE2_EN 0x00000400
929#define MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE3_EN 0x00000800
930#define MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE0_EN 0x00001000
931#define MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE1_EN 0x00002000
932#define MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE2_EN 0x00004000
933#define MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE3_EN 0x00008000
934#define MDP4_LCDC_LVDS_INTF_CTL_CH1_CLK_LANE_EN 0x00010000
935#define MDP4_LCDC_LVDS_INTF_CTL_CH2_CLK_LANE_EN 0x00020000
936
937static inline uint32_t REG_MDP4_LCDC_LVDS_MUX_CTL(uint32_t i0) { return 0x000c2014 + 0x8*i0; }
938
939static inline uint32_t REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(uint32_t i0) { return 0x000c2014 + 0x8*i0; }
940#define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0__MASK 0x000000ff
941#define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0__SHIFT 0
942static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0(uint32_t val)
943{
944 return ((val) << MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0__MASK;
945}
946#define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1__MASK 0x0000ff00
947#define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1__SHIFT 8
948static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1(uint32_t val)
949{
950 return ((val) << MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1__MASK;
951}
952#define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2__MASK 0x00ff0000
953#define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2__SHIFT 16
954static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2(uint32_t val)
955{
956 return ((val) << MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2__MASK;
957}
958#define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3__MASK 0xff000000
959#define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3__SHIFT 24
960static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3(uint32_t val)
961{
962 return ((val) << MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3__MASK;
963}
964
965static inline uint32_t REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(uint32_t i0) { return 0x000c2018 + 0x8*i0; }
966#define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4__MASK 0x000000ff
967#define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4__SHIFT 0
968static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4(uint32_t val)
969{
970 return ((val) << MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4__MASK;
971}
972#define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5__MASK 0x0000ff00
973#define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5__SHIFT 8
974static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5(uint32_t val)
975{
976 return ((val) << MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5__MASK;
977}
978#define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6__MASK 0x00ff0000
979#define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6__SHIFT 16
980static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6(uint32_t val)
981{
982 return ((val) << MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6__MASK;
983}
984
985#define REG_MDP4_LCDC_LVDS_PHY_RESET 0x000c2034
986
987#define REG_MDP4_LVDS_PHY_PLL_CTRL_0 0x000c3000
988
989#define REG_MDP4_LVDS_PHY_PLL_CTRL_1 0x000c3004
990
991#define REG_MDP4_LVDS_PHY_PLL_CTRL_2 0x000c3008
992
993#define REG_MDP4_LVDS_PHY_PLL_CTRL_3 0x000c300c
994
995#define REG_MDP4_LVDS_PHY_PLL_CTRL_5 0x000c3014
996
997#define REG_MDP4_LVDS_PHY_PLL_CTRL_6 0x000c3018
998
999#define REG_MDP4_LVDS_PHY_PLL_CTRL_7 0x000c301c
1000
1001#define REG_MDP4_LVDS_PHY_PLL_CTRL_8 0x000c3020
1002
1003#define REG_MDP4_LVDS_PHY_PLL_CTRL_9 0x000c3024
1004
1005#define REG_MDP4_LVDS_PHY_PLL_LOCKED 0x000c3080
1006
1007#define REG_MDP4_LVDS_PHY_CFG2 0x000c3108
1008
1009#define REG_MDP4_LVDS_PHY_CFG0 0x000c3100
1010#define MDP4_LVDS_PHY_CFG0_SERIALIZATION_ENBLE 0x00000010
1011#define MDP4_LVDS_PHY_CFG0_CHANNEL0 0x00000040
1012#define MDP4_LVDS_PHY_CFG0_CHANNEL1 0x00000080
1013
1014#define REG_MDP4_DTV 0x000d0000
1015
1016#define REG_MDP4_DTV_ENABLE 0x000d0000
1017
1018#define REG_MDP4_DTV_HSYNC_CTRL 0x000d0004
1019#define MDP4_DTV_HSYNC_CTRL_PULSEW__MASK 0x0000ffff
1020#define MDP4_DTV_HSYNC_CTRL_PULSEW__SHIFT 0
1021static inline uint32_t MDP4_DTV_HSYNC_CTRL_PULSEW(uint32_t val)
1022{
1023 return ((val) << MDP4_DTV_HSYNC_CTRL_PULSEW__SHIFT) & MDP4_DTV_HSYNC_CTRL_PULSEW__MASK;
1024}
1025#define MDP4_DTV_HSYNC_CTRL_PERIOD__MASK 0xffff0000
1026#define MDP4_DTV_HSYNC_CTRL_PERIOD__SHIFT 16
1027static inline uint32_t MDP4_DTV_HSYNC_CTRL_PERIOD(uint32_t val)
1028{
1029 return ((val) << MDP4_DTV_HSYNC_CTRL_PERIOD__SHIFT) & MDP4_DTV_HSYNC_CTRL_PERIOD__MASK;
1030}
1031
1032#define REG_MDP4_DTV_VSYNC_PERIOD 0x000d0008
1033
1034#define REG_MDP4_DTV_VSYNC_LEN 0x000d000c
1035
1036#define REG_MDP4_DTV_DISPLAY_HCTRL 0x000d0018
1037#define MDP4_DTV_DISPLAY_HCTRL_START__MASK 0x0000ffff
1038#define MDP4_DTV_DISPLAY_HCTRL_START__SHIFT 0
1039static inline uint32_t MDP4_DTV_DISPLAY_HCTRL_START(uint32_t val)
1040{
1041 return ((val) << MDP4_DTV_DISPLAY_HCTRL_START__SHIFT) & MDP4_DTV_DISPLAY_HCTRL_START__MASK;
1042}
1043#define MDP4_DTV_DISPLAY_HCTRL_END__MASK 0xffff0000
1044#define MDP4_DTV_DISPLAY_HCTRL_END__SHIFT 16
1045static inline uint32_t MDP4_DTV_DISPLAY_HCTRL_END(uint32_t val)
1046{
1047 return ((val) << MDP4_DTV_DISPLAY_HCTRL_END__SHIFT) & MDP4_DTV_DISPLAY_HCTRL_END__MASK;
1048}
1049
1050#define REG_MDP4_DTV_DISPLAY_VSTART 0x000d001c
1051
1052#define REG_MDP4_DTV_DISPLAY_VEND 0x000d0020
1053
1054#define REG_MDP4_DTV_ACTIVE_HCTL 0x000d002c
1055#define MDP4_DTV_ACTIVE_HCTL_START__MASK 0x00007fff
1056#define MDP4_DTV_ACTIVE_HCTL_START__SHIFT 0
1057static inline uint32_t MDP4_DTV_ACTIVE_HCTL_START(uint32_t val)
1058{
1059 return ((val) << MDP4_DTV_ACTIVE_HCTL_START__SHIFT) & MDP4_DTV_ACTIVE_HCTL_START__MASK;
1060}
1061#define MDP4_DTV_ACTIVE_HCTL_END__MASK 0x7fff0000
1062#define MDP4_DTV_ACTIVE_HCTL_END__SHIFT 16
1063static inline uint32_t MDP4_DTV_ACTIVE_HCTL_END(uint32_t val)
1064{
1065 return ((val) << MDP4_DTV_ACTIVE_HCTL_END__SHIFT) & MDP4_DTV_ACTIVE_HCTL_END__MASK;
1066}
1067#define MDP4_DTV_ACTIVE_HCTL_ACTIVE_START_X 0x80000000
1068
1069#define REG_MDP4_DTV_ACTIVE_VSTART 0x000d0030
1070
1071#define REG_MDP4_DTV_ACTIVE_VEND 0x000d0038
1072
1073#define REG_MDP4_DTV_BORDER_CLR 0x000d0040
1074
1075#define REG_MDP4_DTV_UNDERFLOW_CLR 0x000d0044
1076#define MDP4_DTV_UNDERFLOW_CLR_COLOR__MASK 0x00ffffff
1077#define MDP4_DTV_UNDERFLOW_CLR_COLOR__SHIFT 0
1078static inline uint32_t MDP4_DTV_UNDERFLOW_CLR_COLOR(uint32_t val)
1079{
1080 return ((val) << MDP4_DTV_UNDERFLOW_CLR_COLOR__SHIFT) & MDP4_DTV_UNDERFLOW_CLR_COLOR__MASK;
1081}
1082#define MDP4_DTV_UNDERFLOW_CLR_ENABLE_RECOVERY 0x80000000
1083
1084#define REG_MDP4_DTV_HSYNC_SKEW 0x000d0048
1085
1086#define REG_MDP4_DTV_TEST_CNTL 0x000d004c
1087
1088#define REG_MDP4_DTV_CTRL_POLARITY 0x000d0050
1089#define MDP4_DTV_CTRL_POLARITY_HSYNC_LOW 0x00000001
1090#define MDP4_DTV_CTRL_POLARITY_VSYNC_LOW 0x00000002
1091#define MDP4_DTV_CTRL_POLARITY_DATA_EN_LOW 0x00000004
1092
1093#define REG_MDP4_DSI 0x000e0000
1094
1095#define REG_MDP4_DSI_ENABLE 0x000e0000
1096
1097#define REG_MDP4_DSI_HSYNC_CTRL 0x000e0004
1098#define MDP4_DSI_HSYNC_CTRL_PULSEW__MASK 0x0000ffff
1099#define MDP4_DSI_HSYNC_CTRL_PULSEW__SHIFT 0
1100static inline uint32_t MDP4_DSI_HSYNC_CTRL_PULSEW(uint32_t val)
1101{
1102 return ((val) << MDP4_DSI_HSYNC_CTRL_PULSEW__SHIFT) & MDP4_DSI_HSYNC_CTRL_PULSEW__MASK;
1103}
1104#define MDP4_DSI_HSYNC_CTRL_PERIOD__MASK 0xffff0000
1105#define MDP4_DSI_HSYNC_CTRL_PERIOD__SHIFT 16
1106static inline uint32_t MDP4_DSI_HSYNC_CTRL_PERIOD(uint32_t val)
1107{
1108 return ((val) << MDP4_DSI_HSYNC_CTRL_PERIOD__SHIFT) & MDP4_DSI_HSYNC_CTRL_PERIOD__MASK;
1109}
1110
1111#define REG_MDP4_DSI_VSYNC_PERIOD 0x000e0008
1112
1113#define REG_MDP4_DSI_VSYNC_LEN 0x000e000c
1114
1115#define REG_MDP4_DSI_DISPLAY_HCTRL 0x000e0010
1116#define MDP4_DSI_DISPLAY_HCTRL_START__MASK 0x0000ffff
1117#define MDP4_DSI_DISPLAY_HCTRL_START__SHIFT 0
1118static inline uint32_t MDP4_DSI_DISPLAY_HCTRL_START(uint32_t val)
1119{
1120 return ((val) << MDP4_DSI_DISPLAY_HCTRL_START__SHIFT) & MDP4_DSI_DISPLAY_HCTRL_START__MASK;
1121}
1122#define MDP4_DSI_DISPLAY_HCTRL_END__MASK 0xffff0000
1123#define MDP4_DSI_DISPLAY_HCTRL_END__SHIFT 16
1124static inline uint32_t MDP4_DSI_DISPLAY_HCTRL_END(uint32_t val)
1125{
1126 return ((val) << MDP4_DSI_DISPLAY_HCTRL_END__SHIFT) & MDP4_DSI_DISPLAY_HCTRL_END__MASK;
1127}
1128
1129#define REG_MDP4_DSI_DISPLAY_VSTART 0x000e0014
1130
1131#define REG_MDP4_DSI_DISPLAY_VEND 0x000e0018
1132
1133#define REG_MDP4_DSI_ACTIVE_HCTL 0x000e001c
1134#define MDP4_DSI_ACTIVE_HCTL_START__MASK 0x00007fff
1135#define MDP4_DSI_ACTIVE_HCTL_START__SHIFT 0
1136static inline uint32_t MDP4_DSI_ACTIVE_HCTL_START(uint32_t val)
1137{
1138 return ((val) << MDP4_DSI_ACTIVE_HCTL_START__SHIFT) & MDP4_DSI_ACTIVE_HCTL_START__MASK;
1139}
1140#define MDP4_DSI_ACTIVE_HCTL_END__MASK 0x7fff0000
1141#define MDP4_DSI_ACTIVE_HCTL_END__SHIFT 16
1142static inline uint32_t MDP4_DSI_ACTIVE_HCTL_END(uint32_t val)
1143{
1144 return ((val) << MDP4_DSI_ACTIVE_HCTL_END__SHIFT) & MDP4_DSI_ACTIVE_HCTL_END__MASK;
1145}
1146#define MDP4_DSI_ACTIVE_HCTL_ACTIVE_START_X 0x80000000
1147
1148#define REG_MDP4_DSI_ACTIVE_VSTART 0x000e0020
1149
1150#define REG_MDP4_DSI_ACTIVE_VEND 0x000e0024
1151
1152#define REG_MDP4_DSI_BORDER_CLR 0x000e0028
1153
1154#define REG_MDP4_DSI_UNDERFLOW_CLR 0x000e002c
1155#define MDP4_DSI_UNDERFLOW_CLR_COLOR__MASK 0x00ffffff
1156#define MDP4_DSI_UNDERFLOW_CLR_COLOR__SHIFT 0
1157static inline uint32_t MDP4_DSI_UNDERFLOW_CLR_COLOR(uint32_t val)
1158{
1159 return ((val) << MDP4_DSI_UNDERFLOW_CLR_COLOR__SHIFT) & MDP4_DSI_UNDERFLOW_CLR_COLOR__MASK;
1160}
1161#define MDP4_DSI_UNDERFLOW_CLR_ENABLE_RECOVERY 0x80000000
1162
1163#define REG_MDP4_DSI_HSYNC_SKEW 0x000e0030
1164
1165#define REG_MDP4_DSI_TEST_CNTL 0x000e0034
1166
1167#define REG_MDP4_DSI_CTRL_POLARITY 0x000e0038
1168#define MDP4_DSI_CTRL_POLARITY_HSYNC_LOW 0x00000001
1169#define MDP4_DSI_CTRL_POLARITY_VSYNC_LOW 0x00000002
1170#define MDP4_DSI_CTRL_POLARITY_DATA_EN_LOW 0x00000004
1171
1172
1173#endif
1174
