LXR linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c

   1/*
   2 * Copyright 2013 Red Hat Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Authors: Ben Skeggs <bskeggs@redhat.com>
  23 */
  24#include "gf100.h"
  25#include "ctxgf100.h"
  26
  27#include <nvif/class.h>
  28
  29/*******************************************************************************
  30 * PGRAPH register lists
  31 ******************************************************************************/
  32
  33const struct gf100_gr_init
  34gk104_gr_init_main_0[] = {
  35        { 0x400080,   1, 0x04, 0x003083c2 },
  36        { 0x400088,   1, 0x04, 0x0001ffe7 },
  37        { 0x40008c,   1, 0x04, 0x00000000 },
  38        { 0x400090,   1, 0x04, 0x00000030 },
  39        { 0x40013c,   1, 0x04, 0x003901f7 },
  40        { 0x400140,   1, 0x04, 0x00000100 },
  41        { 0x400144,   1, 0x04, 0x00000000 },
  42        { 0x400148,   1, 0x04, 0x00000110 },
  43        { 0x400138,   1, 0x04, 0x00000000 },
  44        { 0x400130,   2, 0x04, 0x00000000 },
  45        { 0x400124,   1, 0x04, 0x00000002 },
  46        {}
  47};
  48
  49static const struct gf100_gr_init
  50gk104_gr_init_ds_0[] = {
  51        { 0x405844,   1, 0x04, 0x00ffffff },
  52        { 0x405850,   1, 0x04, 0x00000000 },
  53        { 0x405900,   1, 0x04, 0x0000ff34 },
  54        { 0x405908,   1, 0x04, 0x00000000 },
  55        { 0x405928,   2, 0x04, 0x00000000 },
  56        {}
  57};
  58
  59static const struct gf100_gr_init
  60gk104_gr_init_sked_0[] = {
  61        { 0x407010,   1, 0x04, 0x00000000 },
  62        {}
  63};
  64
  65static const struct gf100_gr_init
  66gk104_gr_init_cwd_0[] = {
  67        { 0x405b50,   1, 0x04, 0x00000000 },
  68        {}
  69};
  70
  71static const struct gf100_gr_init
  72gk104_gr_init_gpc_unk_1[] = {
  73        { 0x418d00,   1, 0x04, 0x00000000 },
  74        { 0x418d28,   2, 0x04, 0x00000000 },
  75        { 0x418f00,   1, 0x04, 0x00000000 },
  76        { 0x418f08,   1, 0x04, 0x00000000 },
  77        { 0x418f20,   2, 0x04, 0x00000000 },
  78        { 0x418e00,   1, 0x04, 0x00000060 },
  79        { 0x418e08,   1, 0x04, 0x00000000 },
  80        { 0x418e1c,   2, 0x04, 0x00000000 },
  81        {}
  82};
  83
  84const struct gf100_gr_init
  85gk104_gr_init_tpccs_0[] = {
  86        { 0x419d0c,   1, 0x04, 0x00000000 },
  87        { 0x419d10,   1, 0x04, 0x00000014 },
  88        {}
  89};
  90
  91const struct gf100_gr_init
  92gk104_gr_init_pe_0[] = {
  93        { 0x41980c,   1, 0x04, 0x00000010 },
  94        { 0x419844,   1, 0x04, 0x00000000 },
  95        { 0x419850,   1, 0x04, 0x00000004 },
  96        { 0x419854,   2, 0x04, 0x00000000 },
  97        {}
  98};
  99
 100static const struct gf100_gr_init
 101gk104_gr_init_l1c_0[] = {
 102        { 0x419c98,   1, 0x04, 0x00000000 },
 103        { 0x419ca8,   1, 0x04, 0x00000000 },
 104        { 0x419cb0,   1, 0x04, 0x01000000 },
 105        { 0x419cb4,   1, 0x04, 0x00000000 },
 106        { 0x419cb8,   1, 0x04, 0x00b08bea },
 107        { 0x419c84,   1, 0x04, 0x00010384 },
 108        { 0x419cbc,   1, 0x04, 0x28137646 },
 109        { 0x419cc0,   2, 0x04, 0x00000000 },
 110        { 0x419c80,   1, 0x04, 0x00020232 },
 111        {}
 112};
 113
 114static const struct gf100_gr_init
 115gk104_gr_init_sm_0[] = {
 116        { 0x419e00,   1, 0x04, 0x00000000 },
 117        { 0x419ea0,   1, 0x04, 0x00000000 },
 118        { 0x419ee4,   1, 0x04, 0x00000000 },
 119        { 0x419ea4,   1, 0x04, 0x00000100 },
 120        { 0x419ea8,   1, 0x04, 0x00000000 },
 121        { 0x419eb4,   4, 0x04, 0x00000000 },
 122        { 0x419edc,   1, 0x04, 0x00000000 },
 123        { 0x419f00,   1, 0x04, 0x00000000 },
 124        { 0x419f74,   1, 0x04, 0x00000555 },
 125        {}
 126};
 127
 128const struct gf100_gr_init
 129gk104_gr_init_be_0[] = {
 130        { 0x40880c,   1, 0x04, 0x00000000 },
 131        { 0x408850,   1, 0x04, 0x00000004 },
 132        { 0x408910,   9, 0x04, 0x00000000 },
 133        { 0x408950,   1, 0x04, 0x00000000 },
 134        { 0x408954,   1, 0x04, 0x0000ffff },
 135        { 0x408958,   1, 0x04, 0x00000034 },
 136        { 0x408984,   1, 0x04, 0x00000000 },
 137        { 0x408988,   1, 0x04, 0x08040201 },
 138        { 0x40898c,   1, 0x04, 0x80402010 },
 139        {}
 140};
 141
 142const struct gf100_gr_pack
 143gk104_gr_pack_mmio[] = {
 144        { gk104_gr_init_main_0 },
 145        { gf100_gr_init_fe_0 },
 146        { gf100_gr_init_pri_0 },
 147        { gf100_gr_init_rstr2d_0 },
 148        { gf119_gr_init_pd_0 },
 149        { gk104_gr_init_ds_0 },
 150        { gf100_gr_init_scc_0 },
 151        { gk104_gr_init_sked_0 },
 152        { gk104_gr_init_cwd_0 },
 153        { gf119_gr_init_prop_0 },
 154        { gf108_gr_init_gpc_unk_0 },
 155        { gf100_gr_init_setup_0 },
 156        { gf100_gr_init_crstr_0 },
 157        { gf108_gr_init_setup_1 },
 158        { gf100_gr_init_zcull_0 },
 159        { gf119_gr_init_gpm_0 },
 160        { gk104_gr_init_gpc_unk_1 },
 161        { gf100_gr_init_gcc_0 },
 162        { gk104_gr_init_tpccs_0 },
 163        { gf119_gr_init_tex_0 },
 164        { gk104_gr_init_pe_0 },
 165        { gk104_gr_init_l1c_0 },
 166        { gf100_gr_init_mpc_0 },
 167        { gk104_gr_init_sm_0 },
 168        { gf117_gr_init_pes_0 },
 169        { gf117_gr_init_wwdx_0 },
 170        { gf117_gr_init_cbm_0 },
 171        { gk104_gr_init_be_0 },
 172        { gf100_gr_init_fe_1 },
 173        {}
 174};
 175
 176/*******************************************************************************
 177 * PGRAPH engine/subdev functions
 178 ******************************************************************************/
 179
 180int
 181gk104_gr_init(struct gf100_gr *gr)
 182{
 183        struct nvkm_device *device = gr->base.engine.subdev.device;
 184        const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total);
 185        u32 data[TPC_MAX / 8] = {};
 186        u8  tpcnr[GPC_MAX];
 187        int gpc, tpc, rop;
 188        int i;
 189
 190        nvkm_wr32(device, GPC_BCAST(0x0880), 0x00000000);
 191        nvkm_wr32(device, GPC_BCAST(0x08a4), 0x00000000);
 192        nvkm_wr32(device, GPC_BCAST(0x0888), 0x00000000);
 193        nvkm_wr32(device, GPC_BCAST(0x088c), 0x00000000);
 194        nvkm_wr32(device, GPC_BCAST(0x0890), 0x00000000);
 195        nvkm_wr32(device, GPC_BCAST(0x0894), 0x00000000);
 196        nvkm_wr32(device, GPC_BCAST(0x08b4), nvkm_memory_addr(gr->unk4188b4) >> 8);
 197        nvkm_wr32(device, GPC_BCAST(0x08b8), nvkm_memory_addr(gr->unk4188b8) >> 8);
 198
 199        gf100_gr_mmio(gr, gr->func->mmio);
 200
 201        nvkm_wr32(device, GPC_UNIT(0, 0x3018), 0x00000001);
 202
 203        memset(data, 0x00, sizeof(data));
 204        memcpy(tpcnr, gr->tpc_nr, sizeof(gr->tpc_nr));
 205        for (i = 0, gpc = -1; i < gr->tpc_total; i++) {
 206                do {
 207                        gpc = (gpc + 1) % gr->gpc_nr;
 208                } while (!tpcnr[gpc]);
 209                tpc = gr->tpc_nr[gpc] - tpcnr[gpc]--;
 210
 211                data[i / 8] |= tpc << ((i % 8) * 4);
 212        }
 213
 214        nvkm_wr32(device, GPC_BCAST(0x0980), data[0]);
 215        nvkm_wr32(device, GPC_BCAST(0x0984), data[1]);
 216        nvkm_wr32(device, GPC_BCAST(0x0988), data[2]);
 217        nvkm_wr32(device, GPC_BCAST(0x098c), data[3]);
 218
 219        for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
 220                nvkm_wr32(device, GPC_UNIT(gpc, 0x0914),
 221                        gr->magic_not_rop_nr << 8 | gr->tpc_nr[gpc]);
 222                nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 |
 223                        gr->tpc_total);
 224                nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918);
 225        }
 226
 227        nvkm_wr32(device, GPC_BCAST(0x3fd4), magicgpc918);
 228        nvkm_wr32(device, GPC_BCAST(0x08ac), nvkm_rd32(device, 0x100800));
 229
 230        nvkm_wr32(device, 0x400500, 0x00010001);
 231
 232        nvkm_wr32(device, 0x400100, 0xffffffff);
 233        nvkm_wr32(device, 0x40013c, 0xffffffff);
 234
 235        nvkm_wr32(device, 0x409ffc, 0x00000000);
 236        nvkm_wr32(device, 0x409c14, 0x00003e3e);
 237        nvkm_wr32(device, 0x409c24, 0x000f0001);
 238        nvkm_wr32(device, 0x404000, 0xc0000000);
 239        nvkm_wr32(device, 0x404600, 0xc0000000);
 240        nvkm_wr32(device, 0x408030, 0xc0000000);
 241        nvkm_wr32(device, 0x404490, 0xc0000000);
 242        nvkm_wr32(device, 0x406018, 0xc0000000);
 243        nvkm_wr32(device, 0x407020, 0x40000000);
 244        nvkm_wr32(device, 0x405840, 0xc0000000);
 245        nvkm_wr32(device, 0x405844, 0x00ffffff);
 246        nvkm_mask(device, 0x419cc0, 0x00000008, 0x00000008);
 247        nvkm_mask(device, 0x419eb4, 0x00001000, 0x00001000);
 248
 249        for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
 250                nvkm_wr32(device, GPC_UNIT(gpc, 0x3038), 0xc0000000);
 251                nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000);
 252                nvkm_wr32(device, GPC_UNIT(gpc, 0x0900), 0xc0000000);
 253                nvkm_wr32(device, GPC_UNIT(gpc, 0x1028), 0xc0000000);
 254                nvkm_wr32(device, GPC_UNIT(gpc, 0x0824), 0xc0000000);
 255                for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) {
 256                        nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff);
 257                        nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff);
 258                        nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000);
 259                        nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000);
 260                        nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000);
 261                        nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x644), 0x001ffffe);
 262                        nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x64c), 0x0000000f);
 263                }
 264                nvkm_wr32(device, GPC_UNIT(gpc, 0x2c90), 0xffffffff);
 265                nvkm_wr32(device, GPC_UNIT(gpc, 0x2c94), 0xffffffff);
 266        }
 267
 268        for (rop = 0; rop < gr->rop_nr; rop++) {
 269                nvkm_wr32(device, ROP_UNIT(rop, 0x144), 0xc0000000);
 270                nvkm_wr32(device, ROP_UNIT(rop, 0x070), 0xc0000000);
 271                nvkm_wr32(device, ROP_UNIT(rop, 0x204), 0xffffffff);
 272                nvkm_wr32(device, ROP_UNIT(rop, 0x208), 0xffffffff);
 273        }
 274
 275        nvkm_wr32(device, 0x400108, 0xffffffff);
 276        nvkm_wr32(device, 0x400138, 0xffffffff);
 277        nvkm_wr32(device, 0x400118, 0xffffffff);
 278        nvkm_wr32(device, 0x400130, 0xffffffff);
 279        nvkm_wr32(device, 0x40011c, 0xffffffff);
 280        nvkm_wr32(device, 0x400134, 0xffffffff);
 281
 282        nvkm_wr32(device, 0x400054, 0x34ce3464);
 283
 284        gf100_gr_zbc_init(gr);
 285
 286        return gf100_gr_init_ctxctl(gr);
 287}
 288
 289#include "fuc/hubgk104.fuc3.h"
 290
 291static struct gf100_gr_ucode
 292gk104_gr_fecs_ucode = {
 293        .code.data = gk104_grhub_code,
 294        .code.size = sizeof(gk104_grhub_code),
 295        .data.data = gk104_grhub_data,
 296        .data.size = sizeof(gk104_grhub_data),
 297};
 298
 299#include "fuc/gpcgk104.fuc3.h"
 300
 301static struct gf100_gr_ucode
 302gk104_gr_gpccs_ucode = {
 303        .code.data = gk104_grgpc_code,
 304        .code.size = sizeof(gk104_grgpc_code),
 305        .data.data = gk104_grgpc_data,
 306        .data.size = sizeof(gk104_grgpc_data),
 307};
 308
 309static const struct gf100_gr_func
 310gk104_gr = {
 311        .init = gk104_gr_init,
 312        .mmio = gk104_gr_pack_mmio,
 313        .fecs.ucode = &gk104_gr_fecs_ucode,
 314        .gpccs.ucode = &gk104_gr_gpccs_ucode,
 315        .ppc_nr = 1,
 316        .grctx = &gk104_grctx,
 317        .sclass = {
 318                { -1, -1, FERMI_TWOD_A },
 319                { -1, -1, KEPLER_INLINE_TO_MEMORY_A },
 320                { -1, -1, KEPLER_A, &gf100_fermi },
 321                { -1, -1, KEPLER_COMPUTE_A },
 322                {}
 323        }
 324};
 325
 326int
 327gk104_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
 328{
 329        return gf100_gr_new_(&gk104_gr, device, index, pgr);
 330}
 331