LXR linux/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv04.c

   1/*
   2 * Copyright 2012 Red Hat Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Authors: Ben Skeggs
  23 */
  24#include "priv.h"
  25#include "pll.h"
  26
  27#include <subdev/bios.h>
  28#include <subdev/bios/pll.h>
  29#include <subdev/devinit/nv04.h>
  30
  31int
  32nv04_clk_pll_calc(struct nvkm_clk *clock, struct nvbios_pll *info,
  33                  int clk, struct nvkm_pll_vals *pv)
  34{
  35        int N1, M1, N2, M2, P;
  36        int ret = nv04_pll_calc(&clock->subdev, info, clk, &N1, &M1, &N2, &M2, &P);
  37        if (ret) {
  38                pv->refclk = info->refclk;
  39                pv->N1 = N1;
  40                pv->M1 = M1;
  41                pv->N2 = N2;
  42                pv->M2 = M2;
  43                pv->log2P = P;
  44        }
  45        return ret;
  46}
  47
  48int
  49nv04_clk_pll_prog(struct nvkm_clk *clk, u32 reg1, struct nvkm_pll_vals *pv)
  50{
  51        struct nvkm_device *device = clk->subdev.device;
  52        struct nvkm_devinit *devinit = device->devinit;
  53        int cv = device->bios->version.chip;
  54
  55        if (cv == 0x30 || cv == 0x31 || cv == 0x35 || cv == 0x36 ||
  56            cv >= 0x40) {
  57                if (reg1 > 0x405c)
  58                        setPLL_double_highregs(devinit, reg1, pv);
  59                else
  60                        setPLL_double_lowregs(devinit, reg1, pv);
  61        } else
  62                setPLL_single(devinit, reg1, pv);
  63
  64        return 0;
  65}
  66
  67static const struct nvkm_clk_func
  68nv04_clk = {
  69        .domains = {
  70                { nv_clk_src_max }
  71        }
  72};
  73
  74int
  75nv04_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk)
  76{
  77        int ret = nvkm_clk_new_(&nv04_clk, device, index, false, pclk);
  78        if (ret == 0) {
  79                (*pclk)->pll_calc = nv04_clk_pll_calc;
  80                (*pclk)->pll_prog = nv04_clk_pll_prog;
  81        }
  82        return ret;
  83}
  84