1/* 2 * Copyright (C) 2012 Avionic Design GmbH 3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 */ 9 10#ifndef TEGRA_DC_H 11#define TEGRA_DC_H 1 12 13#define DC_CMD_GENERAL_INCR_SYNCPT 0x000 14#define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL 0x001 15#define SYNCPT_CNTRL_NO_STALL (1 << 8) 16#define SYNCPT_CNTRL_SOFT_RESET (1 << 0) 17#define DC_CMD_GENERAL_INCR_SYNCPT_ERROR 0x002 18#define DC_CMD_WIN_A_INCR_SYNCPT 0x008 19#define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL 0x009 20#define DC_CMD_WIN_A_INCR_SYNCPT_ERROR 0x00a 21#define DC_CMD_WIN_B_INCR_SYNCPT 0x010 22#define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL 0x011 23#define DC_CMD_WIN_B_INCR_SYNCPT_ERROR 0x012 24#define DC_CMD_WIN_C_INCR_SYNCPT 0x018 25#define DC_CMD_WIN_C_INCR_SYNCPT_CNTRL 0x019 26#define DC_CMD_WIN_C_INCR_SYNCPT_ERROR 0x01a 27#define DC_CMD_CONT_SYNCPT_VSYNC 0x028 28#define SYNCPT_VSYNC_ENABLE (1 << 8) 29#define DC_CMD_DISPLAY_COMMAND_OPTION0 0x031 30#define DC_CMD_DISPLAY_COMMAND 0x032 31#define DISP_CTRL_MODE_STOP (0 << 5) 32#define DISP_CTRL_MODE_C_DISPLAY (1 << 5) 33#define DISP_CTRL_MODE_NC_DISPLAY (2 << 5) 34#define DISP_CTRL_MODE_MASK (3 << 5) 35#define DC_CMD_SIGNAL_RAISE 0x033 36#define DC_CMD_DISPLAY_POWER_CONTROL 0x036 37#define PW0_ENABLE (1 << 0) 38#define PW1_ENABLE (1 << 2) 39#define PW2_ENABLE (1 << 4) 40#define PW3_ENABLE (1 << 6) 41#define PW4_ENABLE (1 << 8) 42#define PM0_ENABLE (1 << 16) 43#define PM1_ENABLE (1 << 18) 44 45#define DC_CMD_INT_STATUS 0x037 46#define DC_CMD_INT_MASK 0x038 47#define DC_CMD_INT_ENABLE 0x039 48#define DC_CMD_INT_TYPE 0x03a 49#define DC_CMD_INT_POLARITY 0x03b 50#define CTXSW_INT (1 << 0) 51#define FRAME_END_INT (1 << 1) 52#define VBLANK_INT (1 << 2) 53#define WIN_A_UF_INT (1 << 8) 54#define WIN_B_UF_INT (1 << 9) 55#define WIN_C_UF_INT (1 << 10) 56#define WIN_A_OF_INT (1 << 14) 57#define WIN_B_OF_INT (1 << 15) 58#define WIN_C_OF_INT (1 << 16) 59 60#define DC_CMD_SIGNAL_RAISE1 0x03c 61#define DC_CMD_SIGNAL_RAISE2 0x03d 62#define DC_CMD_SIGNAL_RAISE3 0x03e 63 64#define DC_CMD_STATE_ACCESS 0x040 65#define READ_MUX (1 << 0) 66#define WRITE_MUX (1 << 2) 67 68#define DC_CMD_STATE_CONTROL 0x041 69#define GENERAL_ACT_REQ (1 << 0) 70#define WIN_A_ACT_REQ (1 << 1) 71#define WIN_B_ACT_REQ (1 << 2) 72#define WIN_C_ACT_REQ (1 << 3) 73#define CURSOR_ACT_REQ (1 << 7) 74#define GENERAL_UPDATE (1 << 8) 75#define WIN_A_UPDATE (1 << 9) 76#define WIN_B_UPDATE (1 << 10) 77#define WIN_C_UPDATE (1 << 11) 78#define CURSOR_UPDATE (1 << 15) 79#define NC_HOST_TRIG (1 << 24) 80 81#define DC_CMD_DISPLAY_WINDOW_HEADER 0x042 82#define WINDOW_A_SELECT (1 << 4) 83#define WINDOW_B_SELECT (1 << 5) 84#define WINDOW_C_SELECT (1 << 6) 85 86#define DC_CMD_REG_ACT_CONTROL 0x043 87 88#define DC_COM_CRC_CONTROL 0x300 89#define DC_COM_CRC_CONTROL_ALWAYS (1 << 3) 90#define DC_COM_CRC_CONTROL_FULL_FRAME (0 << 2) 91#define DC_COM_CRC_CONTROL_ACTIVE_DATA (1 << 2) 92#define DC_COM_CRC_CONTROL_WAIT (1 << 1) 93#define DC_COM_CRC_CONTROL_ENABLE (1 << 0) 94#define DC_COM_CRC_CHECKSUM 0x301 95#define DC_COM_PIN_OUTPUT_ENABLE(x) (0x302 + (x)) 96#define DC_COM_PIN_OUTPUT_POLARITY(x) (0x306 + (x)) 97#define LVS_OUTPUT_POLARITY_LOW (1 << 28) 98#define LHS_OUTPUT_POLARITY_LOW (1 << 30) 99#define DC_COM_PIN_OUTPUT_DATA(x) (0x30a + (x)) 100#define DC_COM_PIN_INPUT_ENABLE(x) (0x30e + (x)) 101#define DC_COM_PIN_INPUT_DATA(x) (0x312 + (x)) 102#define DC_COM_PIN_OUTPUT_SELECT(x) (0x314 + (x)) 103 104#define DC_COM_PIN_MISC_CONTROL 0x31b 105#define DC_COM_PIN_PM0_CONTROL 0x31c 106#define DC_COM_PIN_PM0_DUTY_CYCLE 0x31d 107#define DC_COM_PIN_PM1_CONTROL 0x31e 108#define DC_COM_PIN_PM1_DUTY_CYCLE 0x31f 109 110#define DC_COM_SPI_CONTROL 0x320 111#define DC_COM_SPI_START_BYTE 0x321 112#define DC_COM_HSPI_WRITE_DATA_AB 0x322 113#define DC_COM_HSPI_WRITE_DATA_CD 0x323 114#define DC_COM_HSPI_CS_DC 0x324 115#define DC_COM_SCRATCH_REGISTER_A 0x325 116#define DC_COM_SCRATCH_REGISTER_B 0x326 117#define DC_COM_GPIO_CTRL 0x327 118#define DC_COM_GPIO_DEBOUNCE_COUNTER 0x328 119#define DC_COM_CRC_CHECKSUM_LATCHED 0x329 120 121#define DC_DISP_DISP_SIGNAL_OPTIONS0 0x400 122#define H_PULSE0_ENABLE (1 << 8) 123#define H_PULSE1_ENABLE (1 << 10) 124#define H_PULSE2_ENABLE (1 << 12) 125 126#define DC_DISP_DISP_SIGNAL_OPTIONS1 0x401 127 128#define DC_DISP_DISP_WIN_OPTIONS 0x402 129#define HDMI_ENABLE (1 << 30) 130#define DSI_ENABLE (1 << 29) 131#define SOR1_TIMING_CYA (1 << 27) 132#define SOR1_ENABLE (1 << 26) 133#define SOR_ENABLE (1 << 25) 134#define CURSOR_ENABLE (1 << 16) 135 136#define DC_DISP_DISP_MEM_HIGH_PRIORITY 0x403 137#define CURSOR_THRESHOLD(x) (((x) & 0x03) << 24) 138#define WINDOW_A_THRESHOLD(x) (((x) & 0x7f) << 16) 139#define WINDOW_B_THRESHOLD(x) (((x) & 0x7f) << 8) 140#define WINDOW_C_THRESHOLD(x) (((x) & 0xff) << 0) 141 142#define DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER 0x404 143#define CURSOR_DELAY(x) (((x) & 0x3f) << 24) 144#define WINDOW_A_DELAY(x) (((x) & 0x3f) << 16) 145#define WINDOW_B_DELAY(x) (((x) & 0x3f) << 8) 146#define WINDOW_C_DELAY(x) (((x) & 0x3f) << 0) 147 148#define DC_DISP_DISP_TIMING_OPTIONS 0x405 149#define VSYNC_H_POSITION(x) ((x) & 0xfff) 150 151#define DC_DISP_REF_TO_SYNC 0x406 152#define DC_DISP_SYNC_WIDTH 0x407 153#define DC_DISP_BACK_PORCH 0x408 154#define DC_DISP_ACTIVE 0x409 155#define DC_DISP_FRONT_PORCH 0x40a 156#define DC_DISP_H_PULSE0_CONTROL 0x40b 157#define DC_DISP_H_PULSE0_POSITION_A 0x40c 158#define DC_DISP_H_PULSE0_POSITION_B 0x40d 159#define DC_DISP_H_PULSE0_POSITION_C 0x40e 160#define DC_DISP_H_PULSE0_POSITION_D 0x40f 161#define DC_DISP_H_PULSE1_CONTROL 0x410 162#define DC_DISP_H_PULSE1_POSITION_A 0x411 163#define DC_DISP_H_PULSE1_POSITION_B 0x412 164#define DC_DISP_H_PULSE1_POSITION_C 0x413 165#define DC_DISP_H_PULSE1_POSITION_D 0x414 166#define DC_DISP_H_PULSE2_CONTROL 0x415 167#define DC_DISP_H_PULSE2_POSITION_A 0x416 168#define DC_DISP_H_PULSE2_POSITION_B 0x417 169#define DC_DISP_H_PULSE2_POSITION_C 0x418 170#define DC_DISP_H_PULSE2_POSITION_D 0x419 171#define DC_DISP_V_PULSE0_CONTROL 0x41a 172#define DC_DISP_V_PULSE0_POSITION_A 0x41b 173#define DC_DISP_V_PULSE0_POSITION_B 0x41c 174#define DC_DISP_V_PULSE0_POSITION_C 0x41d 175#define DC_DISP_V_PULSE1_CONTROL 0x41e 176#define DC_DISP_V_PULSE1_POSITION_A 0x41f 177#define DC_DISP_V_PULSE1_POSITION_B 0x420 178#define DC_DISP_V_PULSE1_POSITION_C 0x421 179#define DC_DISP_V_PULSE2_CONTROL 0x422 180#define DC_DISP_V_PULSE2_POSITION_A 0x423 181#define DC_DISP_V_PULSE3_CONTROL 0x424 182#define DC_DISP_V_PULSE3_POSITION_A 0x425 183#define DC_DISP_M0_CONTROL 0x426 184#define DC_DISP_M1_CONTROL 0x427 185#define DC_DISP_DI_CONTROL 0x428 186#define DC_DISP_PP_CONTROL 0x429 187#define DC_DISP_PP_SELECT_A 0x42a 188#define DC_DISP_PP_SELECT_B 0x42b 189#define DC_DISP_PP_SELECT_C 0x42c 190#define DC_DISP_PP_SELECT_D 0x42d 191 192#define PULSE_MODE_NORMAL (0 << 3) 193#define PULSE_MODE_ONE_CLOCK (1 << 3) 194#define PULSE_POLARITY_HIGH (0 << 4) 195#define PULSE_POLARITY_LOW (1 << 4) 196#define PULSE_QUAL_ALWAYS (0 << 6) 197#define PULSE_QUAL_VACTIVE (2 << 6) 198#define PULSE_QUAL_VACTIVE1 (3 << 6) 199#define PULSE_LAST_START_A (0 << 8) 200#define PULSE_LAST_END_A (1 << 8) 201#define PULSE_LAST_START_B (2 << 8) 202#define PULSE_LAST_END_B (3 << 8) 203#define PULSE_LAST_START_C (4 << 8) 204#define PULSE_LAST_END_C (5 << 8) 205#define PULSE_LAST_START_D (6 << 8) 206#define PULSE_LAST_END_D (7 << 8) 207 208#define PULSE_START(x) (((x) & 0xfff) << 0) 209#define PULSE_END(x) (((x) & 0xfff) << 16) 210 211#define DC_DISP_DISP_CLOCK_CONTROL 0x42e 212#define PIXEL_CLK_DIVIDER_PCD1 (0 << 8) 213#define PIXEL_CLK_DIVIDER_PCD1H (1 << 8) 214#define PIXEL_CLK_DIVIDER_PCD2 (2 << 8) 215#define PIXEL_CLK_DIVIDER_PCD3 (3 << 8) 216#define PIXEL_CLK_DIVIDER_PCD4 (4 << 8) 217#define PIXEL_CLK_DIVIDER_PCD6 (5 << 8) 218#define PIXEL_CLK_DIVIDER_PCD8 (6 << 8) 219#define PIXEL_CLK_DIVIDER_PCD9 (7 << 8) 220#define PIXEL_CLK_DIVIDER_PCD12 (8 << 8) 221#define PIXEL_CLK_DIVIDER_PCD16 (9 << 8) 222#define PIXEL_CLK_DIVIDER_PCD18 (10 << 8) 223#define PIXEL_CLK_DIVIDER_PCD24 (11 << 8) 224#define PIXEL_CLK_DIVIDER_PCD13 (12 << 8) 225#define SHIFT_CLK_DIVIDER(x) ((x) & 0xff) 226 227#define DC_DISP_DISP_INTERFACE_CONTROL 0x42f 228#define DISP_DATA_FORMAT_DF1P1C (0 << 0) 229#define DISP_DATA_FORMAT_DF1P2C24B (1 << 0) 230#define DISP_DATA_FORMAT_DF1P2C18B (2 << 0) 231#define DISP_DATA_FORMAT_DF1P2C16B (3 << 0) 232#define DISP_DATA_FORMAT_DF2S (4 << 0) 233#define DISP_DATA_FORMAT_DF3S (5 << 0) 234#define DISP_DATA_FORMAT_DFSPI (6 << 0) 235#define DISP_DATA_FORMAT_DF1P3C24B (7 << 0) 236#define DISP_DATA_FORMAT_DF1P3C18B (8 << 0) 237#define DISP_ALIGNMENT_MSB (0 << 8) 238#define DISP_ALIGNMENT_LSB (1 << 8) 239#define DISP_ORDER_RED_BLUE (0 << 9) 240#define DISP_ORDER_BLUE_RED (1 << 9) 241 242#define DC_DISP_DISP_COLOR_CONTROL 0x430 243#define BASE_COLOR_SIZE666 (0 << 0) 244#define BASE_COLOR_SIZE111 (1 << 0) 245#define BASE_COLOR_SIZE222 (2 << 0) 246#define BASE_COLOR_SIZE333 (3 << 0) 247#define BASE_COLOR_SIZE444 (4 << 0) 248#define BASE_COLOR_SIZE555 (5 << 0) 249#define BASE_COLOR_SIZE565 (6 << 0) 250#define BASE_COLOR_SIZE332 (7 << 0) 251#define BASE_COLOR_SIZE888 (8 << 0) 252#define DITHER_CONTROL_MASK (3 << 8) 253#define DITHER_CONTROL_DISABLE (0 << 8) 254#define DITHER_CONTROL_ORDERED (2 << 8) 255#define DITHER_CONTROL_ERRDIFF (3 << 8) 256#define BASE_COLOR_SIZE_MASK (0xf << 0) 257#define BASE_COLOR_SIZE_666 (0 << 0) 258#define BASE_COLOR_SIZE_111 (1 << 0) 259#define BASE_COLOR_SIZE_222 (2 << 0) 260#define BASE_COLOR_SIZE_333 (3 << 0) 261#define BASE_COLOR_SIZE_444 (4 << 0) 262#define BASE_COLOR_SIZE_555 (5 << 0) 263#define BASE_COLOR_SIZE_565 (6 << 0) 264#define BASE_COLOR_SIZE_332 (7 << 0) 265#define BASE_COLOR_SIZE_888 (8 << 0) 266 267#define DC_DISP_SHIFT_CLOCK_OPTIONS 0x431 268#define SC1_H_QUALIFIER_NONE (1 << 16) 269#define SC0_H_QUALIFIER_NONE (1 << 0) 270 271#define DC_DISP_DATA_ENABLE_OPTIONS 0x432 272#define DE_SELECT_ACTIVE_BLANK (0 << 0) 273#define DE_SELECT_ACTIVE (1 << 0) 274#define DE_SELECT_ACTIVE_IS (2 << 0) 275#define DE_CONTROL_ONECLK (0 << 2) 276#define DE_CONTROL_NORMAL (1 << 2) 277#define DE_CONTROL_EARLY_EXT (2 << 2) 278#define DE_CONTROL_EARLY (3 << 2) 279#define DE_CONTROL_ACTIVE_BLANK (4 << 2) 280 281#define DC_DISP_SERIAL_INTERFACE_OPTIONS 0x433 282#define DC_DISP_LCD_SPI_OPTIONS 0x434 283#define DC_DISP_BORDER_COLOR 0x435 284#define DC_DISP_COLOR_KEY0_LOWER 0x436 285#define DC_DISP_COLOR_KEY0_UPPER 0x437 286#define DC_DISP_COLOR_KEY1_LOWER 0x438 287#define DC_DISP_COLOR_KEY1_UPPER 0x439 288 289#define DC_DISP_CURSOR_FOREGROUND 0x43c 290#define DC_DISP_CURSOR_BACKGROUND 0x43d 291 292#define DC_DISP_CURSOR_START_ADDR 0x43e 293#define CURSOR_CLIP_DISPLAY (0 << 28) 294#define CURSOR_CLIP_WIN_A (1 << 28) 295#define CURSOR_CLIP_WIN_B (2 << 28) 296#define CURSOR_CLIP_WIN_C (3 << 28) 297#define CURSOR_SIZE_32x32 (0 << 24) 298#define CURSOR_SIZE_64x64 (1 << 24) 299#define CURSOR_SIZE_128x128 (2 << 24) 300#define CURSOR_SIZE_256x256 (3 << 24) 301#define DC_DISP_CURSOR_START_ADDR_NS 0x43f 302 303#define DC_DISP_CURSOR_POSITION 0x440 304#define DC_DISP_CURSOR_POSITION_NS 0x441 305 306#define DC_DISP_INIT_SEQ_CONTROL 0x442 307#define DC_DISP_SPI_INIT_SEQ_DATA_A 0x443 308#define DC_DISP_SPI_INIT_SEQ_DATA_B 0x444 309#define DC_DISP_SPI_INIT_SEQ_DATA_C 0x445 310#define DC_DISP_SPI_INIT_SEQ_DATA_D 0x446 311 312#define DC_DISP_DC_MCCIF_FIFOCTRL 0x480 313#define DC_DISP_MCCIF_DISPLAY0A_HYST 0x481 314#define DC_DISP_MCCIF_DISPLAY0B_HYST 0x482 315#define DC_DISP_MCCIF_DISPLAY1A_HYST 0x483 316#define DC_DISP_MCCIF_DISPLAY1B_HYST 0x484 317 318#define DC_DISP_DAC_CRT_CTRL 0x4c0 319#define DC_DISP_DISP_MISC_CONTROL 0x4c1 320#define DC_DISP_SD_CONTROL 0x4c2 321#define DC_DISP_SD_CSC_COEFF 0x4c3 322#define DC_DISP_SD_LUT(x) (0x4c4 + (x)) 323#define DC_DISP_SD_FLICKER_CONTROL 0x4cd 324#define DC_DISP_DC_PIXEL_COUNT 0x4ce 325#define DC_DISP_SD_HISTOGRAM(x) (0x4cf + (x)) 326#define DC_DISP_SD_BL_PARAMETERS 0x4d7 327#define DC_DISP_SD_BL_TF(x) (0x4d8 + (x)) 328#define DC_DISP_SD_BL_CONTROL 0x4dc 329#define DC_DISP_SD_HW_K_VALUES 0x4dd 330#define DC_DISP_SD_MAN_K_VALUES 0x4de 331 332#define DC_DISP_INTERLACE_CONTROL 0x4e5 333#define INTERLACE_STATUS (1 << 2) 334#define INTERLACE_START (1 << 1) 335#define INTERLACE_ENABLE (1 << 0) 336 337#define DC_DISP_CURSOR_START_ADDR_HI 0x4ec 338#define DC_DISP_BLEND_CURSOR_CONTROL 0x4f1 339#define CURSOR_MODE_LEGACY (0 << 24) 340#define CURSOR_MODE_NORMAL (1 << 24) 341#define CURSOR_DST_BLEND_ZERO (0 << 16) 342#define CURSOR_DST_BLEND_K1 (1 << 16) 343#define CURSOR_DST_BLEND_NEG_K1_TIMES_SRC (2 << 16) 344#define CURSOR_DST_BLEND_MASK (3 << 16) 345#define CURSOR_SRC_BLEND_K1 (0 << 8) 346#define CURSOR_SRC_BLEND_K1_TIMES_SRC (1 << 8) 347#define CURSOR_SRC_BLEND_MASK (3 << 8) 348#define CURSOR_ALPHA 0xff 349 350#define DC_WIN_CSC_YOF 0x611 351#define DC_WIN_CSC_KYRGB 0x612 352#define DC_WIN_CSC_KUR 0x613 353#define DC_WIN_CSC_KVR 0x614 354#define DC_WIN_CSC_KUG 0x615 355#define DC_WIN_CSC_KVG 0x616 356#define DC_WIN_CSC_KUB 0x617 357#define DC_WIN_CSC_KVB 0x618 358 359#define DC_WIN_WIN_OPTIONS 0x700 360#define H_DIRECTION (1 << 0) 361#define V_DIRECTION (1 << 2) 362#define COLOR_EXPAND (1 << 6) 363#define CSC_ENABLE (1 << 18) 364#define WIN_ENABLE (1 << 30) 365 366#define DC_WIN_BYTE_SWAP 0x701 367#define BYTE_SWAP_NOSWAP (0 << 0) 368#define BYTE_SWAP_SWAP2 (1 << 0) 369#define BYTE_SWAP_SWAP4 (2 << 0) 370#define BYTE_SWAP_SWAP4HW (3 << 0) 371 372#define DC_WIN_BUFFER_CONTROL 0x702 373#define BUFFER_CONTROL_HOST (0 << 0) 374#define BUFFER_CONTROL_VI (1 << 0) 375#define BUFFER_CONTROL_EPP (2 << 0) 376#define BUFFER_CONTROL_MPEGE (3 << 0) 377#define BUFFER_CONTROL_SB2D (4 << 0) 378 379#define DC_WIN_COLOR_DEPTH 0x703 380#define WIN_COLOR_DEPTH_P1 0 381#define WIN_COLOR_DEPTH_P2 1 382#define WIN_COLOR_DEPTH_P4 2 383#define WIN_COLOR_DEPTH_P8 3 384#define WIN_COLOR_DEPTH_B4G4R4A4 4 385#define WIN_COLOR_DEPTH_B5G5R5A 5 386#define WIN_COLOR_DEPTH_B5G6R5 6 387#define WIN_COLOR_DEPTH_AB5G5R5 7 388#define WIN_COLOR_DEPTH_B8G8R8A8 12 389#define WIN_COLOR_DEPTH_R8G8B8A8 13 390#define WIN_COLOR_DEPTH_B6x2G6x2R6x2A8 14 391#define WIN_COLOR_DEPTH_R6x2G6x2B6x2A8 15 392#define WIN_COLOR_DEPTH_YCbCr422 16 393#define WIN_COLOR_DEPTH_YUV422 17 394#define WIN_COLOR_DEPTH_YCbCr420P 18 395#define WIN_COLOR_DEPTH_YUV420P 19 396#define WIN_COLOR_DEPTH_YCbCr422P 20 397#define WIN_COLOR_DEPTH_YUV422P 21 398#define WIN_COLOR_DEPTH_YCbCr422R 22 399#define WIN_COLOR_DEPTH_YUV422R 23 400#define WIN_COLOR_DEPTH_YCbCr422RA 24 401#define WIN_COLOR_DEPTH_YUV422RA 25 402 403#define DC_WIN_POSITION 0x704 404#define H_POSITION(x) (((x) & 0x1fff) << 0) 405#define V_POSITION(x) (((x) & 0x1fff) << 16) 406 407#define DC_WIN_SIZE 0x705 408#define H_SIZE(x) (((x) & 0x1fff) << 0) 409#define V_SIZE(x) (((x) & 0x1fff) << 16) 410 411#define DC_WIN_PRESCALED_SIZE 0x706 412#define H_PRESCALED_SIZE(x) (((x) & 0x7fff) << 0) 413#define V_PRESCALED_SIZE(x) (((x) & 0x1fff) << 16) 414 415#define DC_WIN_H_INITIAL_DDA 0x707 416#define DC_WIN_V_INITIAL_DDA 0x708 417#define DC_WIN_DDA_INC 0x709 418#define H_DDA_INC(x) (((x) & 0xffff) << 0) 419#define V_DDA_INC(x) (((x) & 0xffff) << 16) 420 421#define DC_WIN_LINE_STRIDE 0x70a 422#define DC_WIN_BUF_STRIDE 0x70b 423#define DC_WIN_UV_BUF_STRIDE 0x70c 424#define DC_WIN_BUFFER_ADDR_MODE 0x70d 425#define DC_WIN_BUFFER_ADDR_MODE_LINEAR (0 << 0) 426#define DC_WIN_BUFFER_ADDR_MODE_TILE (1 << 0) 427#define DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV (0 << 16) 428#define DC_WIN_BUFFER_ADDR_MODE_TILE_UV (1 << 16) 429#define DC_WIN_DV_CONTROL 0x70e 430 431#define DC_WIN_BLEND_NOKEY 0x70f 432#define DC_WIN_BLEND_1WIN 0x710 433#define DC_WIN_BLEND_2WIN_X 0x711 434#define DC_WIN_BLEND_2WIN_Y 0x712 435#define DC_WIN_BLEND_3WIN_XY 0x713 436 437#define DC_WIN_HP_FETCH_CONTROL 0x714 438 439#define DC_WINBUF_START_ADDR 0x800 440#define DC_WINBUF_START_ADDR_NS 0x801 441#define DC_WINBUF_START_ADDR_U 0x802 442#define DC_WINBUF_START_ADDR_U_NS 0x803 443#define DC_WINBUF_START_ADDR_V 0x804 444#define DC_WINBUF_START_ADDR_V_NS 0x805 445 446#define DC_WINBUF_ADDR_H_OFFSET 0x806 447#define DC_WINBUF_ADDR_H_OFFSET_NS 0x807 448#define DC_WINBUF_ADDR_V_OFFSET 0x808 449#define DC_WINBUF_ADDR_V_OFFSET_NS 0x809 450 451#define DC_WINBUF_UFLOW_STATUS 0x80a 452#define DC_WINBUF_SURFACE_KIND 0x80b 453#define DC_WINBUF_SURFACE_KIND_PITCH (0 << 0) 454#define DC_WINBUF_SURFACE_KIND_TILED (1 << 0) 455#define DC_WINBUF_SURFACE_KIND_BLOCK (2 << 0) 456#define DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(x) (((x) & 0x7) << 4) 457 458#define DC_WINBUF_AD_UFLOW_STATUS 0xbca 459#define DC_WINBUF_BD_UFLOW_STATUS 0xdca 460#define DC_WINBUF_CD_UFLOW_STATUS 0xfca 461 462#endif /* TEGRA_DC_H */ 463