1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18#include <linux/interrupt.h>
19#include <linux/device.h>
20#include <linux/kernel.h>
21#include <linux/sysfs.h>
22#include <linux/list.h>
23#include <linux/i2c.h>
24#include <linux/regulator/consumer.h>
25#include <linux/slab.h>
26#include <linux/err.h>
27#include <linux/module.h>
28
29#include <linux/iio/iio.h>
30#include <linux/iio/sysfs.h>
31#include <linux/iio/events.h>
32#include <linux/iio/buffer.h>
33#include <linux/iio/driver.h>
34#include <linux/iio/kfifo_buf.h>
35#include <linux/iio/trigger_consumer.h>
36#include <linux/iio/triggered_buffer.h>
37
38#define MAX1363_SETUP_BYTE(a) ((a) | 0x80)
39
40
41
42
43
44
45
46#define MAX1363_SETUP_AIN3_IS_AIN3_REF_IS_VDD 0x00
47#define MAX1363_SETUP_AIN3_IS_REF_EXT_TO_REF 0x20
48#define MAX1363_SETUP_AIN3_IS_AIN3_REF_IS_INT 0x40
49#define MAX1363_SETUP_AIN3_IS_REF_REF_IS_INT 0x60
50#define MAX1363_SETUP_POWER_UP_INT_REF 0x10
51#define MAX1363_SETUP_POWER_DOWN_INT_REF 0x00
52
53
54#define MAX1363_SETUP_EXT_CLOCK 0x08
55#define MAX1363_SETUP_INT_CLOCK 0x00
56#define MAX1363_SETUP_UNIPOLAR 0x00
57#define MAX1363_SETUP_BIPOLAR 0x04
58#define MAX1363_SETUP_RESET 0x00
59#define MAX1363_SETUP_NORESET 0x02
60
61
62
63
64
65#define MAX1363_SETUP_MONITOR_SETUP 0x01
66
67
68#define MAX1363_MON_RESET_CHAN(a) (1 << ((a) + 4))
69#define MAX1363_MON_INT_ENABLE 0x01
70
71
72
73#define MAX1363_CONFIG_BYTE(a) ((a))
74
75#define MAX1363_CONFIG_SE 0x01
76#define MAX1363_CONFIG_DE 0x00
77#define MAX1363_CONFIG_SCAN_TO_CS 0x00
78#define MAX1363_CONFIG_SCAN_SINGLE_8 0x20
79#define MAX1363_CONFIG_SCAN_MONITOR_MODE 0x40
80#define MAX1363_CONFIG_SCAN_SINGLE_1 0x60
81
82#define MAX1236_SCAN_MID_TO_CHANNEL 0x40
83
84
85#define MAX1363_CONFIG_EN_MON_MODE_READ 0x18
86
87#define MAX1363_CHANNEL_SEL(a) ((a) << 1)
88
89
90#define MAX1363_CHANNEL_SEL_MASK 0x1E
91#define MAX1363_SCAN_MASK 0x60
92#define MAX1363_SE_DE_MASK 0x01
93
94#define MAX1363_MAX_CHANNELS 25
95
96
97
98
99
100struct max1363_mode {
101 int8_t conf;
102 DECLARE_BITMAP(modemask, MAX1363_MAX_CHANNELS);
103};
104
105
106enum max1363_modes {
107
108 _s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7, _s8, _s9, _s10, _s11,
109
110 d0m1, d2m3, d4m5, d6m7, d8m9, d10m11,
111 d1m0, d3m2, d5m4, d7m6, d9m8, d11m10,
112
113 s0to1, s0to2, s2to3, s0to3, s0to4, s0to5, s0to6,
114 s6to7, s0to7, s6to8, s0to8, s6to9,
115 s0to9, s6to10, s0to10, s6to11, s0to11,
116
117 d0m1to2m3, d0m1to4m5, d0m1to6m7, d6m7to8m9,
118 d0m1to8m9, d6m7to10m11, d0m1to10m11, d1m0to3m2,
119 d1m0to5m4, d1m0to7m6, d7m6to9m8, d1m0to9m8,
120 d7m6to11m10, d1m0to11m10,
121};
122
123
124
125
126
127
128
129
130
131
132
133
134struct max1363_chip_info {
135 const struct iio_info *info;
136 const struct iio_chan_spec *channels;
137 int num_channels;
138 const enum max1363_modes *mode_list;
139 enum max1363_modes default_mode;
140 u16 int_vref_mv;
141 u8 num_modes;
142 u8 bits;
143};
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165struct max1363_state {
166 struct i2c_client *client;
167 u8 setupbyte;
168 u8 configbyte;
169 const struct max1363_chip_info *chip_info;
170 const struct max1363_mode *current_mode;
171 u32 requestedmask;
172 struct regulator *reg;
173
174
175
176 bool monitor_on;
177 unsigned int monitor_speed:3;
178 u8 mask_high;
179 u8 mask_low;
180
181 s16 thresh_high[8];
182 s16 thresh_low[8];
183 struct regulator *vref;
184 u32 vref_uv;
185 int (*send)(const struct i2c_client *client,
186 const char *buf, int count);
187 int (*recv)(const struct i2c_client *client,
188 char *buf, int count);
189};
190
191#define MAX1363_MODE_SINGLE(_num, _mask) { \
192 .conf = MAX1363_CHANNEL_SEL(_num) \
193 | MAX1363_CONFIG_SCAN_SINGLE_1 \
194 | MAX1363_CONFIG_SE, \
195 .modemask[0] = _mask, \
196 }
197
198#define MAX1363_MODE_SCAN_TO_CHANNEL(_num, _mask) { \
199 .conf = MAX1363_CHANNEL_SEL(_num) \
200 | MAX1363_CONFIG_SCAN_TO_CS \
201 | MAX1363_CONFIG_SE, \
202 .modemask[0] = _mask, \
203 }
204
205
206#define MAX1236_MODE_SCAN_MID_TO_CHANNEL(_mid, _num, _mask) { \
207 .conf = MAX1363_CHANNEL_SEL(_num) \
208 | MAX1236_SCAN_MID_TO_CHANNEL \
209 | MAX1363_CONFIG_SE, \
210 .modemask[0] = _mask \
211}
212
213#define MAX1363_MODE_DIFF_SINGLE(_nump, _numm, _mask) { \
214 .conf = MAX1363_CHANNEL_SEL(_nump) \
215 | MAX1363_CONFIG_SCAN_SINGLE_1 \
216 | MAX1363_CONFIG_DE, \
217 .modemask[0] = _mask \
218 }
219
220
221#define MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(_num, _numvals, _mask) { \
222 .conf = MAX1363_CHANNEL_SEL(_num) \
223 | MAX1363_CONFIG_SCAN_TO_CS \
224 | MAX1363_CONFIG_DE, \
225 .modemask[0] = _mask \
226 }
227
228
229#define MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(_num, _numvals, _mask) { \
230 .conf = MAX1363_CHANNEL_SEL(_num) \
231 | MAX1236_SCAN_MID_TO_CHANNEL \
232 | MAX1363_CONFIG_SE, \
233 .modemask[0] = _mask \
234}
235
236static const struct max1363_mode max1363_mode_table[] = {
237
238 MAX1363_MODE_SINGLE(0, 1 << 0),
239 MAX1363_MODE_SINGLE(1, 1 << 1),
240 MAX1363_MODE_SINGLE(2, 1 << 2),
241 MAX1363_MODE_SINGLE(3, 1 << 3),
242 MAX1363_MODE_SINGLE(4, 1 << 4),
243 MAX1363_MODE_SINGLE(5, 1 << 5),
244 MAX1363_MODE_SINGLE(6, 1 << 6),
245 MAX1363_MODE_SINGLE(7, 1 << 7),
246 MAX1363_MODE_SINGLE(8, 1 << 8),
247 MAX1363_MODE_SINGLE(9, 1 << 9),
248 MAX1363_MODE_SINGLE(10, 1 << 10),
249 MAX1363_MODE_SINGLE(11, 1 << 11),
250
251 MAX1363_MODE_DIFF_SINGLE(0, 1, 1 << 12),
252 MAX1363_MODE_DIFF_SINGLE(2, 3, 1 << 13),
253 MAX1363_MODE_DIFF_SINGLE(4, 5, 1 << 14),
254 MAX1363_MODE_DIFF_SINGLE(6, 7, 1 << 15),
255 MAX1363_MODE_DIFF_SINGLE(8, 9, 1 << 16),
256 MAX1363_MODE_DIFF_SINGLE(10, 11, 1 << 17),
257 MAX1363_MODE_DIFF_SINGLE(1, 0, 1 << 18),
258 MAX1363_MODE_DIFF_SINGLE(3, 2, 1 << 19),
259 MAX1363_MODE_DIFF_SINGLE(5, 4, 1 << 20),
260 MAX1363_MODE_DIFF_SINGLE(7, 6, 1 << 21),
261 MAX1363_MODE_DIFF_SINGLE(9, 8, 1 << 22),
262 MAX1363_MODE_DIFF_SINGLE(11, 10, 1 << 23),
263
264
265 MAX1363_MODE_SCAN_TO_CHANNEL(1, 0x003),
266 MAX1363_MODE_SCAN_TO_CHANNEL(2, 0x007),
267 MAX1236_MODE_SCAN_MID_TO_CHANNEL(2, 3, 0x00C),
268 MAX1363_MODE_SCAN_TO_CHANNEL(3, 0x00F),
269 MAX1363_MODE_SCAN_TO_CHANNEL(4, 0x01F),
270 MAX1363_MODE_SCAN_TO_CHANNEL(5, 0x03F),
271 MAX1363_MODE_SCAN_TO_CHANNEL(6, 0x07F),
272 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 7, 0x0C0),
273 MAX1363_MODE_SCAN_TO_CHANNEL(7, 0x0FF),
274 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 8, 0x1C0),
275 MAX1363_MODE_SCAN_TO_CHANNEL(8, 0x1FF),
276 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 9, 0x3C0),
277 MAX1363_MODE_SCAN_TO_CHANNEL(9, 0x3FF),
278 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 10, 0x7C0),
279 MAX1363_MODE_SCAN_TO_CHANNEL(10, 0x7FF),
280 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 11, 0xFC0),
281 MAX1363_MODE_SCAN_TO_CHANNEL(11, 0xFFF),
282
283 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(2, 2, 0x003000),
284 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(4, 3, 0x007000),
285 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(6, 4, 0x00F000),
286 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(8, 2, 0x018000),
287 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(8, 5, 0x01F000),
288 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(10, 3, 0x038000),
289 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(10, 6, 0x3F000),
290 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(3, 2, 0x0C0000),
291 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(5, 3, 0x1C0000),
292 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(7, 4, 0x3C0000),
293 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(9, 2, 0x600000),
294 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(9, 5, 0x7C0000),
295 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(11, 3, 0xE00000),
296 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(11, 6, 0xFC0000),
297};
298
299static const struct max1363_mode
300*max1363_match_mode(const unsigned long *mask,
301 const struct max1363_chip_info *ci)
302{
303 int i;
304 if (mask)
305 for (i = 0; i < ci->num_modes; i++)
306 if (bitmap_subset(mask,
307 max1363_mode_table[ci->mode_list[i]].
308 modemask,
309 MAX1363_MAX_CHANNELS))
310 return &max1363_mode_table[ci->mode_list[i]];
311 return NULL;
312}
313
314static int max1363_smbus_send(const struct i2c_client *client, const char *buf,
315 int count)
316{
317 int i, err;
318
319 for (i = err = 0; err == 0 && i < count; ++i)
320 err = i2c_smbus_write_byte(client, buf[i]);
321
322 return err ? err : count;
323}
324
325static int max1363_smbus_recv(const struct i2c_client *client, char *buf,
326 int count)
327{
328 int i, ret;
329
330 for (i = 0; i < count; ++i) {
331 ret = i2c_smbus_read_byte(client);
332 if (ret < 0)
333 return ret;
334 buf[i] = ret;
335 }
336
337 return count;
338}
339
340static int max1363_write_basic_config(struct max1363_state *st)
341{
342 u8 tx_buf[2] = { st->setupbyte, st->configbyte };
343
344 return st->send(st->client, tx_buf, 2);
345}
346
347static int max1363_set_scan_mode(struct max1363_state *st)
348{
349 st->configbyte &= ~(MAX1363_CHANNEL_SEL_MASK
350 | MAX1363_SCAN_MASK
351 | MAX1363_SE_DE_MASK);
352 st->configbyte |= st->current_mode->conf;
353
354 return max1363_write_basic_config(st);
355}
356
357static int max1363_read_single_chan(struct iio_dev *indio_dev,
358 struct iio_chan_spec const *chan,
359 int *val,
360 long m)
361{
362 int ret = 0;
363 s32 data;
364 u8 rxbuf[2];
365 struct max1363_state *st = iio_priv(indio_dev);
366 struct i2c_client *client = st->client;
367
368 mutex_lock(&indio_dev->mlock);
369
370
371
372
373
374
375
376 if (st->monitor_on || iio_buffer_enabled(indio_dev)) {
377 ret = -EBUSY;
378 goto error_ret;
379 }
380
381
382 if (st->current_mode != &max1363_mode_table[chan->address]) {
383
384 st->current_mode = &max1363_mode_table[chan->address];
385 ret = max1363_set_scan_mode(st);
386 if (ret < 0)
387 goto error_ret;
388 }
389 if (st->chip_info->bits != 8) {
390
391 data = st->recv(client, rxbuf, 2);
392 if (data < 0) {
393 ret = data;
394 goto error_ret;
395 }
396 data = (rxbuf[1] | rxbuf[0] << 8) &
397 ((1 << st->chip_info->bits) - 1);
398 } else {
399
400 data = st->recv(client, rxbuf, 1);
401 if (data < 0) {
402 ret = data;
403 goto error_ret;
404 }
405 data = rxbuf[0];
406 }
407 *val = data;
408error_ret:
409 mutex_unlock(&indio_dev->mlock);
410 return ret;
411
412}
413
414static int max1363_read_raw(struct iio_dev *indio_dev,
415 struct iio_chan_spec const *chan,
416 int *val,
417 int *val2,
418 long m)
419{
420 struct max1363_state *st = iio_priv(indio_dev);
421 int ret;
422
423 switch (m) {
424 case IIO_CHAN_INFO_RAW:
425 ret = max1363_read_single_chan(indio_dev, chan, val, m);
426 if (ret < 0)
427 return ret;
428 return IIO_VAL_INT;
429 case IIO_CHAN_INFO_SCALE:
430 *val = st->vref_uv / 1000;
431 *val2 = st->chip_info->bits;
432 return IIO_VAL_FRACTIONAL_LOG2;
433 default:
434 return -EINVAL;
435 }
436 return 0;
437}
438
439
440static const enum max1363_modes max1363_mode_list[] = {
441 _s0, _s1, _s2, _s3,
442 s0to1, s0to2, s0to3,
443 d0m1, d2m3, d1m0, d3m2,
444 d0m1to2m3, d1m0to3m2,
445};
446
447static const struct iio_event_spec max1363_events[] = {
448 {
449 .type = IIO_EV_TYPE_THRESH,
450 .dir = IIO_EV_DIR_RISING,
451 .mask_separate = BIT(IIO_EV_INFO_VALUE) |
452 BIT(IIO_EV_INFO_ENABLE),
453 }, {
454 .type = IIO_EV_TYPE_THRESH,
455 .dir = IIO_EV_DIR_FALLING,
456 .mask_separate = BIT(IIO_EV_INFO_VALUE) |
457 BIT(IIO_EV_INFO_ENABLE),
458 },
459};
460
461#define MAX1363_CHAN_U(num, addr, si, bits, ev_spec, num_ev_spec) \
462 { \
463 .type = IIO_VOLTAGE, \
464 .indexed = 1, \
465 .channel = num, \
466 .address = addr, \
467 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
468 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
469 .datasheet_name = "AIN"#num, \
470 .scan_type = { \
471 .sign = 'u', \
472 .realbits = bits, \
473 .storagebits = (bits > 8) ? 16 : 8, \
474 .endianness = IIO_BE, \
475 }, \
476 .scan_index = si, \
477 .event_spec = ev_spec, \
478 .num_event_specs = num_ev_spec, \
479 }
480
481
482#define MAX1363_CHAN_B(num, num2, addr, si, bits, ev_spec, num_ev_spec) \
483 { \
484 .type = IIO_VOLTAGE, \
485 .differential = 1, \
486 .indexed = 1, \
487 .channel = num, \
488 .channel2 = num2, \
489 .address = addr, \
490 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
491 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
492 .datasheet_name = "AIN"#num"-AIN"#num2, \
493 .scan_type = { \
494 .sign = 's', \
495 .realbits = bits, \
496 .storagebits = (bits > 8) ? 16 : 8, \
497 .endianness = IIO_BE, \
498 }, \
499 .scan_index = si, \
500 .event_spec = ev_spec, \
501 .num_event_specs = num_ev_spec, \
502 }
503
504#define MAX1363_4X_CHANS(bits, ev_spec, num_ev_spec) { \
505 MAX1363_CHAN_U(0, _s0, 0, bits, ev_spec, num_ev_spec), \
506 MAX1363_CHAN_U(1, _s1, 1, bits, ev_spec, num_ev_spec), \
507 MAX1363_CHAN_U(2, _s2, 2, bits, ev_spec, num_ev_spec), \
508 MAX1363_CHAN_U(3, _s3, 3, bits, ev_spec, num_ev_spec), \
509 MAX1363_CHAN_B(0, 1, d0m1, 4, bits, ev_spec, num_ev_spec), \
510 MAX1363_CHAN_B(2, 3, d2m3, 5, bits, ev_spec, num_ev_spec), \
511 MAX1363_CHAN_B(1, 0, d1m0, 6, bits, ev_spec, num_ev_spec), \
512 MAX1363_CHAN_B(3, 2, d3m2, 7, bits, ev_spec, num_ev_spec), \
513 IIO_CHAN_SOFT_TIMESTAMP(8) \
514 }
515
516static const struct iio_chan_spec max1036_channels[] =
517 MAX1363_4X_CHANS(8, NULL, 0);
518static const struct iio_chan_spec max1136_channels[] =
519 MAX1363_4X_CHANS(10, NULL, 0);
520static const struct iio_chan_spec max1236_channels[] =
521 MAX1363_4X_CHANS(12, NULL, 0);
522static const struct iio_chan_spec max1361_channels[] =
523 MAX1363_4X_CHANS(10, max1363_events, ARRAY_SIZE(max1363_events));
524static const struct iio_chan_spec max1363_channels[] =
525 MAX1363_4X_CHANS(12, max1363_events, ARRAY_SIZE(max1363_events));
526
527
528static const enum max1363_modes max1236_mode_list[] = {
529 _s0, _s1, _s2, _s3,
530 s0to1, s0to2, s0to3,
531 d0m1, d2m3, d1m0, d3m2,
532 d0m1to2m3, d1m0to3m2,
533 s2to3,
534};
535
536
537static const enum max1363_modes max1238_mode_list[] = {
538 _s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7, _s8, _s9, _s10, _s11,
539 s0to1, s0to2, s0to3, s0to4, s0to5, s0to6,
540 s0to7, s0to8, s0to9, s0to10, s0to11,
541 d0m1, d2m3, d4m5, d6m7, d8m9, d10m11,
542 d1m0, d3m2, d5m4, d7m6, d9m8, d11m10,
543 d0m1to2m3, d0m1to4m5, d0m1to6m7, d0m1to8m9, d0m1to10m11,
544 d1m0to3m2, d1m0to5m4, d1m0to7m6, d1m0to9m8, d1m0to11m10,
545 s6to7, s6to8, s6to9, s6to10, s6to11,
546 d6m7to8m9, d6m7to10m11, d7m6to9m8, d7m6to11m10,
547};
548
549#define MAX1363_12X_CHANS(bits) { \
550 MAX1363_CHAN_U(0, _s0, 0, bits, NULL, 0), \
551 MAX1363_CHAN_U(1, _s1, 1, bits, NULL, 0), \
552 MAX1363_CHAN_U(2, _s2, 2, bits, NULL, 0), \
553 MAX1363_CHAN_U(3, _s3, 3, bits, NULL, 0), \
554 MAX1363_CHAN_U(4, _s4, 4, bits, NULL, 0), \
555 MAX1363_CHAN_U(5, _s5, 5, bits, NULL, 0), \
556 MAX1363_CHAN_U(6, _s6, 6, bits, NULL, 0), \
557 MAX1363_CHAN_U(7, _s7, 7, bits, NULL, 0), \
558 MAX1363_CHAN_U(8, _s8, 8, bits, NULL, 0), \
559 MAX1363_CHAN_U(9, _s9, 9, bits, NULL, 0), \
560 MAX1363_CHAN_U(10, _s10, 10, bits, NULL, 0), \
561 MAX1363_CHAN_U(11, _s11, 11, bits, NULL, 0), \
562 MAX1363_CHAN_B(0, 1, d0m1, 12, bits, NULL, 0), \
563 MAX1363_CHAN_B(2, 3, d2m3, 13, bits, NULL, 0), \
564 MAX1363_CHAN_B(4, 5, d4m5, 14, bits, NULL, 0), \
565 MAX1363_CHAN_B(6, 7, d6m7, 15, bits, NULL, 0), \
566 MAX1363_CHAN_B(8, 9, d8m9, 16, bits, NULL, 0), \
567 MAX1363_CHAN_B(10, 11, d10m11, 17, bits, NULL, 0), \
568 MAX1363_CHAN_B(1, 0, d1m0, 18, bits, NULL, 0), \
569 MAX1363_CHAN_B(3, 2, d3m2, 19, bits, NULL, 0), \
570 MAX1363_CHAN_B(5, 4, d5m4, 20, bits, NULL, 0), \
571 MAX1363_CHAN_B(7, 6, d7m6, 21, bits, NULL, 0), \
572 MAX1363_CHAN_B(9, 8, d9m8, 22, bits, NULL, 0), \
573 MAX1363_CHAN_B(11, 10, d11m10, 23, bits, NULL, 0), \
574 IIO_CHAN_SOFT_TIMESTAMP(24) \
575 }
576static const struct iio_chan_spec max1038_channels[] = MAX1363_12X_CHANS(8);
577static const struct iio_chan_spec max1138_channels[] = MAX1363_12X_CHANS(10);
578static const struct iio_chan_spec max1238_channels[] = MAX1363_12X_CHANS(12);
579
580static const enum max1363_modes max11607_mode_list[] = {
581 _s0, _s1, _s2, _s3,
582 s0to1, s0to2, s0to3,
583 s2to3,
584 d0m1, d2m3, d1m0, d3m2,
585 d0m1to2m3, d1m0to3m2,
586};
587
588static const enum max1363_modes max11608_mode_list[] = {
589 _s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7,
590 s0to1, s0to2, s0to3, s0to4, s0to5, s0to6, s0to7,
591 s6to7,
592 d0m1, d2m3, d4m5, d6m7,
593 d1m0, d3m2, d5m4, d7m6,
594 d0m1to2m3, d0m1to4m5, d0m1to6m7,
595 d1m0to3m2, d1m0to5m4, d1m0to7m6,
596};
597
598#define MAX1363_8X_CHANS(bits) { \
599 MAX1363_CHAN_U(0, _s0, 0, bits, NULL, 0), \
600 MAX1363_CHAN_U(1, _s1, 1, bits, NULL, 0), \
601 MAX1363_CHAN_U(2, _s2, 2, bits, NULL, 0), \
602 MAX1363_CHAN_U(3, _s3, 3, bits, NULL, 0), \
603 MAX1363_CHAN_U(4, _s4, 4, bits, NULL, 0), \
604 MAX1363_CHAN_U(5, _s5, 5, bits, NULL, 0), \
605 MAX1363_CHAN_U(6, _s6, 6, bits, NULL, 0), \
606 MAX1363_CHAN_U(7, _s7, 7, bits, NULL, 0), \
607 MAX1363_CHAN_B(0, 1, d0m1, 8, bits, NULL, 0), \
608 MAX1363_CHAN_B(2, 3, d2m3, 9, bits, NULL, 0), \
609 MAX1363_CHAN_B(4, 5, d4m5, 10, bits, NULL, 0), \
610 MAX1363_CHAN_B(6, 7, d6m7, 11, bits, NULL, 0), \
611 MAX1363_CHAN_B(1, 0, d1m0, 12, bits, NULL, 0), \
612 MAX1363_CHAN_B(3, 2, d3m2, 13, bits, NULL, 0), \
613 MAX1363_CHAN_B(5, 4, d5m4, 14, bits, NULL, 0), \
614 MAX1363_CHAN_B(7, 6, d7m6, 15, bits, NULL, 0), \
615 IIO_CHAN_SOFT_TIMESTAMP(16) \
616}
617static const struct iio_chan_spec max11602_channels[] = MAX1363_8X_CHANS(8);
618static const struct iio_chan_spec max11608_channels[] = MAX1363_8X_CHANS(10);
619static const struct iio_chan_spec max11614_channels[] = MAX1363_8X_CHANS(12);
620
621static const enum max1363_modes max11644_mode_list[] = {
622 _s0, _s1, s0to1, d0m1, d1m0,
623};
624
625#define MAX1363_2X_CHANS(bits) { \
626 MAX1363_CHAN_U(0, _s0, 0, bits, NULL, 0), \
627 MAX1363_CHAN_U(1, _s1, 1, bits, NULL, 0), \
628 MAX1363_CHAN_B(0, 1, d0m1, 2, bits, NULL, 0), \
629 MAX1363_CHAN_B(1, 0, d1m0, 3, bits, NULL, 0), \
630 IIO_CHAN_SOFT_TIMESTAMP(4) \
631 }
632
633static const struct iio_chan_spec max11646_channels[] = MAX1363_2X_CHANS(10);
634static const struct iio_chan_spec max11644_channels[] = MAX1363_2X_CHANS(12);
635
636enum { max1361,
637 max1362,
638 max1363,
639 max1364,
640 max1036,
641 max1037,
642 max1038,
643 max1039,
644 max1136,
645 max1137,
646 max1138,
647 max1139,
648 max1236,
649 max1237,
650 max1238,
651 max1239,
652 max11600,
653 max11601,
654 max11602,
655 max11603,
656 max11604,
657 max11605,
658 max11606,
659 max11607,
660 max11608,
661 max11609,
662 max11610,
663 max11611,
664 max11612,
665 max11613,
666 max11614,
667 max11615,
668 max11616,
669 max11617,
670 max11644,
671 max11645,
672 max11646,
673 max11647
674};
675
676static const int max1363_monitor_speeds[] = { 133000, 665000, 33300, 16600,
677 8300, 4200, 2000, 1000 };
678
679static ssize_t max1363_monitor_show_freq(struct device *dev,
680 struct device_attribute *attr,
681 char *buf)
682{
683 struct max1363_state *st = iio_priv(dev_to_iio_dev(dev));
684 return sprintf(buf, "%d\n", max1363_monitor_speeds[st->monitor_speed]);
685}
686
687static ssize_t max1363_monitor_store_freq(struct device *dev,
688 struct device_attribute *attr,
689 const char *buf,
690 size_t len)
691{
692 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
693 struct max1363_state *st = iio_priv(indio_dev);
694 int i, ret;
695 unsigned long val;
696 bool found = false;
697
698 ret = kstrtoul(buf, 10, &val);
699 if (ret)
700 return -EINVAL;
701 for (i = 0; i < ARRAY_SIZE(max1363_monitor_speeds); i++)
702 if (val == max1363_monitor_speeds[i]) {
703 found = true;
704 break;
705 }
706 if (!found)
707 return -EINVAL;
708
709 mutex_lock(&indio_dev->mlock);
710 st->monitor_speed = i;
711 mutex_unlock(&indio_dev->mlock);
712
713 return 0;
714}
715
716static IIO_DEV_ATTR_SAMP_FREQ(S_IRUGO | S_IWUSR,
717 max1363_monitor_show_freq,
718 max1363_monitor_store_freq);
719
720static IIO_CONST_ATTR(sampling_frequency_available,
721 "133000 665000 33300 16600 8300 4200 2000 1000");
722
723static int max1363_read_thresh(struct iio_dev *indio_dev,
724 const struct iio_chan_spec *chan, enum iio_event_type type,
725 enum iio_event_direction dir, enum iio_event_info info, int *val,
726 int *val2)
727{
728 struct max1363_state *st = iio_priv(indio_dev);
729 if (dir == IIO_EV_DIR_FALLING)
730 *val = st->thresh_low[chan->channel];
731 else
732 *val = st->thresh_high[chan->channel];
733 return IIO_VAL_INT;
734}
735
736static int max1363_write_thresh(struct iio_dev *indio_dev,
737 const struct iio_chan_spec *chan, enum iio_event_type type,
738 enum iio_event_direction dir, enum iio_event_info info, int val,
739 int val2)
740{
741 struct max1363_state *st = iio_priv(indio_dev);
742
743 switch (st->chip_info->bits) {
744 case 10:
745 if (val > 0x3FF)
746 return -EINVAL;
747 break;
748 case 12:
749 if (val > 0xFFF)
750 return -EINVAL;
751 break;
752 }
753
754 switch (dir) {
755 case IIO_EV_DIR_FALLING:
756 st->thresh_low[chan->channel] = val;
757 break;
758 case IIO_EV_DIR_RISING:
759 st->thresh_high[chan->channel] = val;
760 break;
761 default:
762 return -EINVAL;
763 }
764
765 return 0;
766}
767
768static const u64 max1363_event_codes[] = {
769 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 0,
770 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
771 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 1,
772 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
773 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 2,
774 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
775 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 3,
776 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
777 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 0,
778 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
779 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 1,
780 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
781 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 2,
782 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
783 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 3,
784 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
785};
786
787static irqreturn_t max1363_event_handler(int irq, void *private)
788{
789 struct iio_dev *indio_dev = private;
790 struct max1363_state *st = iio_priv(indio_dev);
791 s64 timestamp = iio_get_time_ns();
792 unsigned long mask, loc;
793 u8 rx;
794 u8 tx[2] = { st->setupbyte,
795 MAX1363_MON_INT_ENABLE | (st->monitor_speed << 1) | 0xF0 };
796
797 st->recv(st->client, &rx, 1);
798 mask = rx;
799 for_each_set_bit(loc, &mask, 8)
800 iio_push_event(indio_dev, max1363_event_codes[loc], timestamp);
801 st->send(st->client, tx, 2);
802
803 return IRQ_HANDLED;
804}
805
806static int max1363_read_event_config(struct iio_dev *indio_dev,
807 const struct iio_chan_spec *chan, enum iio_event_type type,
808 enum iio_event_direction dir)
809{
810 struct max1363_state *st = iio_priv(indio_dev);
811 int val;
812 int number = chan->channel;
813
814 mutex_lock(&indio_dev->mlock);
815 if (dir == IIO_EV_DIR_FALLING)
816 val = (1 << number) & st->mask_low;
817 else
818 val = (1 << number) & st->mask_high;
819 mutex_unlock(&indio_dev->mlock);
820
821 return val;
822}
823
824static int max1363_monitor_mode_update(struct max1363_state *st, int enabled)
825{
826 u8 *tx_buf;
827 int ret, i = 3, j;
828 unsigned long numelements;
829 int len;
830 const long *modemask;
831
832 if (!enabled) {
833
834 st->setupbyte &= ~MAX1363_SETUP_MONITOR_SETUP;
835 st->configbyte &= ~MAX1363_SCAN_MASK;
836 st->monitor_on = false;
837 return max1363_write_basic_config(st);
838 }
839
840
841 st->setupbyte |= MAX1363_SETUP_MONITOR_SETUP;
842 st->configbyte &= ~(MAX1363_CHANNEL_SEL_MASK
843 | MAX1363_SCAN_MASK
844 | MAX1363_SE_DE_MASK);
845 st->configbyte |= MAX1363_CONFIG_SCAN_MONITOR_MODE;
846 if ((st->mask_low | st->mask_high) & 0x0F) {
847 st->configbyte |= max1363_mode_table[s0to3].conf;
848 modemask = max1363_mode_table[s0to3].modemask;
849 } else if ((st->mask_low | st->mask_high) & 0x30) {
850 st->configbyte |= max1363_mode_table[d0m1to2m3].conf;
851 modemask = max1363_mode_table[d0m1to2m3].modemask;
852 } else {
853 st->configbyte |= max1363_mode_table[d1m0to3m2].conf;
854 modemask = max1363_mode_table[d1m0to3m2].modemask;
855 }
856 numelements = bitmap_weight(modemask, MAX1363_MAX_CHANNELS);
857 len = 3 * numelements + 3;
858 tx_buf = kmalloc(len, GFP_KERNEL);
859 if (!tx_buf) {
860 ret = -ENOMEM;
861 goto error_ret;
862 }
863 tx_buf[0] = st->configbyte;
864 tx_buf[1] = st->setupbyte;
865 tx_buf[2] = (st->monitor_speed << 1);
866
867
868
869
870
871 for (j = 0; j < 8; j++)
872 if (test_bit(j, modemask)) {
873
874 if (st->mask_low & (1 << j)) {
875 tx_buf[i] = (st->thresh_low[j] >> 4) & 0xFF;
876 tx_buf[i + 1] = (st->thresh_low[j] << 4) & 0xF0;
877 } else if (j < 4) {
878 tx_buf[i] = 0;
879 tx_buf[i + 1] = 0;
880 } else {
881 tx_buf[i] = 0x80;
882 tx_buf[i + 1] = 0;
883 }
884 if (st->mask_high & (1 << j)) {
885 tx_buf[i + 1] |=
886 (st->thresh_high[j] >> 8) & 0x0F;
887 tx_buf[i + 2] = st->thresh_high[j] & 0xFF;
888 } else if (j < 4) {
889 tx_buf[i + 1] |= 0x0F;
890 tx_buf[i + 2] = 0xFF;
891 } else {
892 tx_buf[i + 1] |= 0x07;
893 tx_buf[i + 2] = 0xFF;
894 }
895 i += 3;
896 }
897
898
899 ret = st->send(st->client, tx_buf, len);
900 if (ret < 0)
901 goto error_ret;
902 if (ret != len) {
903 ret = -EIO;
904 goto error_ret;
905 }
906
907
908
909
910
911
912
913
914 tx_buf[0] = st->setupbyte;
915 tx_buf[1] = MAX1363_MON_INT_ENABLE | (st->monitor_speed << 1) | 0xF0;
916 ret = st->send(st->client, tx_buf, 2);
917 if (ret < 0)
918 goto error_ret;
919 if (ret != 2) {
920 ret = -EIO;
921 goto error_ret;
922 }
923 ret = 0;
924 st->monitor_on = true;
925error_ret:
926
927 kfree(tx_buf);
928
929 return ret;
930}
931
932
933
934
935
936
937static inline int __max1363_check_event_mask(int thismask, int checkmask)
938{
939 int ret = 0;
940
941 if (thismask < 4) {
942 if (checkmask & ~0x0F) {
943 ret = -EBUSY;
944 goto error_ret;
945 }
946 } else if (thismask < 6) {
947 if (checkmask & ~0x30) {
948 ret = -EBUSY;
949 goto error_ret;
950 }
951 } else if (checkmask & ~0xC0)
952 ret = -EBUSY;
953error_ret:
954 return ret;
955}
956
957static int max1363_write_event_config(struct iio_dev *indio_dev,
958 const struct iio_chan_spec *chan, enum iio_event_type type,
959 enum iio_event_direction dir, int state)
960{
961 int ret = 0;
962 struct max1363_state *st = iio_priv(indio_dev);
963 u16 unifiedmask;
964 int number = chan->channel;
965
966 mutex_lock(&indio_dev->mlock);
967 unifiedmask = st->mask_low | st->mask_high;
968 if (dir == IIO_EV_DIR_FALLING) {
969
970 if (state == 0)
971 st->mask_low &= ~(1 << number);
972 else {
973 ret = __max1363_check_event_mask((1 << number),
974 unifiedmask);
975 if (ret)
976 goto error_ret;
977 st->mask_low |= (1 << number);
978 }
979 } else {
980 if (state == 0)
981 st->mask_high &= ~(1 << number);
982 else {
983 ret = __max1363_check_event_mask((1 << number),
984 unifiedmask);
985 if (ret)
986 goto error_ret;
987 st->mask_high |= (1 << number);
988 }
989 }
990
991 max1363_monitor_mode_update(st, !!(st->mask_high | st->mask_low));
992error_ret:
993 mutex_unlock(&indio_dev->mlock);
994
995 return ret;
996}
997
998
999
1000
1001
1002static struct attribute *max1363_event_attributes[] = {
1003 &iio_dev_attr_sampling_frequency.dev_attr.attr,
1004 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
1005 NULL,
1006};
1007
1008static struct attribute_group max1363_event_attribute_group = {
1009 .attrs = max1363_event_attributes,
1010};
1011
1012static int max1363_update_scan_mode(struct iio_dev *indio_dev,
1013 const unsigned long *scan_mask)
1014{
1015 struct max1363_state *st = iio_priv(indio_dev);
1016
1017
1018
1019
1020
1021 st->current_mode = max1363_match_mode(scan_mask, st->chip_info);
1022 if (!st->current_mode)
1023 return -EINVAL;
1024 max1363_set_scan_mode(st);
1025 return 0;
1026}
1027
1028static const struct iio_info max1238_info = {
1029 .read_raw = &max1363_read_raw,
1030 .driver_module = THIS_MODULE,
1031 .update_scan_mode = &max1363_update_scan_mode,
1032};
1033
1034static const struct iio_info max1363_info = {
1035 .read_event_value = &max1363_read_thresh,
1036 .write_event_value = &max1363_write_thresh,
1037 .read_event_config = &max1363_read_event_config,
1038 .write_event_config = &max1363_write_event_config,
1039 .read_raw = &max1363_read_raw,
1040 .update_scan_mode = &max1363_update_scan_mode,
1041 .driver_module = THIS_MODULE,
1042 .event_attrs = &max1363_event_attribute_group,
1043};
1044
1045
1046static const struct max1363_chip_info max1363_chip_info_tbl[] = {
1047 [max1361] = {
1048 .bits = 10,
1049 .int_vref_mv = 2048,
1050 .mode_list = max1363_mode_list,
1051 .num_modes = ARRAY_SIZE(max1363_mode_list),
1052 .default_mode = s0to3,
1053 .channels = max1361_channels,
1054 .num_channels = ARRAY_SIZE(max1361_channels),
1055 .info = &max1363_info,
1056 },
1057 [max1362] = {
1058 .bits = 10,
1059 .int_vref_mv = 4096,
1060 .mode_list = max1363_mode_list,
1061 .num_modes = ARRAY_SIZE(max1363_mode_list),
1062 .default_mode = s0to3,
1063 .channels = max1361_channels,
1064 .num_channels = ARRAY_SIZE(max1361_channels),
1065 .info = &max1363_info,
1066 },
1067 [max1363] = {
1068 .bits = 12,
1069 .int_vref_mv = 2048,
1070 .mode_list = max1363_mode_list,
1071 .num_modes = ARRAY_SIZE(max1363_mode_list),
1072 .default_mode = s0to3,
1073 .channels = max1363_channels,
1074 .num_channels = ARRAY_SIZE(max1363_channels),
1075 .info = &max1363_info,
1076 },
1077 [max1364] = {
1078 .bits = 12,
1079 .int_vref_mv = 4096,
1080 .mode_list = max1363_mode_list,
1081 .num_modes = ARRAY_SIZE(max1363_mode_list),
1082 .default_mode = s0to3,
1083 .channels = max1363_channels,
1084 .num_channels = ARRAY_SIZE(max1363_channels),
1085 .info = &max1363_info,
1086 },
1087 [max1036] = {
1088 .bits = 8,
1089 .int_vref_mv = 4096,
1090 .mode_list = max1236_mode_list,
1091 .num_modes = ARRAY_SIZE(max1236_mode_list),
1092 .default_mode = s0to3,
1093 .info = &max1238_info,
1094 .channels = max1036_channels,
1095 .num_channels = ARRAY_SIZE(max1036_channels),
1096 },
1097 [max1037] = {
1098 .bits = 8,
1099 .int_vref_mv = 2048,
1100 .mode_list = max1236_mode_list,
1101 .num_modes = ARRAY_SIZE(max1236_mode_list),
1102 .default_mode = s0to3,
1103 .info = &max1238_info,
1104 .channels = max1036_channels,
1105 .num_channels = ARRAY_SIZE(max1036_channels),
1106 },
1107 [max1038] = {
1108 .bits = 8,
1109 .int_vref_mv = 4096,
1110 .mode_list = max1238_mode_list,
1111 .num_modes = ARRAY_SIZE(max1238_mode_list),
1112 .default_mode = s0to11,
1113 .info = &max1238_info,
1114 .channels = max1038_channels,
1115 .num_channels = ARRAY_SIZE(max1038_channels),
1116 },
1117 [max1039] = {
1118 .bits = 8,
1119 .int_vref_mv = 2048,
1120 .mode_list = max1238_mode_list,
1121 .num_modes = ARRAY_SIZE(max1238_mode_list),
1122 .default_mode = s0to11,
1123 .info = &max1238_info,
1124 .channels = max1038_channels,
1125 .num_channels = ARRAY_SIZE(max1038_channels),
1126 },
1127 [max1136] = {
1128 .bits = 10,
1129 .int_vref_mv = 4096,
1130 .mode_list = max1236_mode_list,
1131 .num_modes = ARRAY_SIZE(max1236_mode_list),
1132 .default_mode = s0to3,
1133 .info = &max1238_info,
1134 .channels = max1136_channels,
1135 .num_channels = ARRAY_SIZE(max1136_channels),
1136 },
1137 [max1137] = {
1138 .bits = 10,
1139 .int_vref_mv = 2048,
1140 .mode_list = max1236_mode_list,
1141 .num_modes = ARRAY_SIZE(max1236_mode_list),
1142 .default_mode = s0to3,
1143 .info = &max1238_info,
1144 .channels = max1136_channels,
1145 .num_channels = ARRAY_SIZE(max1136_channels),
1146 },
1147 [max1138] = {
1148 .bits = 10,
1149 .int_vref_mv = 4096,
1150 .mode_list = max1238_mode_list,
1151 .num_modes = ARRAY_SIZE(max1238_mode_list),
1152 .default_mode = s0to11,
1153 .info = &max1238_info,
1154 .channels = max1138_channels,
1155 .num_channels = ARRAY_SIZE(max1138_channels),
1156 },
1157 [max1139] = {
1158 .bits = 10,
1159 .int_vref_mv = 2048,
1160 .mode_list = max1238_mode_list,
1161 .num_modes = ARRAY_SIZE(max1238_mode_list),
1162 .default_mode = s0to11,
1163 .info = &max1238_info,
1164 .channels = max1138_channels,
1165 .num_channels = ARRAY_SIZE(max1138_channels),
1166 },
1167 [max1236] = {
1168 .bits = 12,
1169 .int_vref_mv = 4096,
1170 .mode_list = max1236_mode_list,
1171 .num_modes = ARRAY_SIZE(max1236_mode_list),
1172 .default_mode = s0to3,
1173 .info = &max1238_info,
1174 .channels = max1236_channels,
1175 .num_channels = ARRAY_SIZE(max1236_channels),
1176 },
1177 [max1237] = {
1178 .bits = 12,
1179 .int_vref_mv = 2048,
1180 .mode_list = max1236_mode_list,
1181 .num_modes = ARRAY_SIZE(max1236_mode_list),
1182 .default_mode = s0to3,
1183 .info = &max1238_info,
1184 .channels = max1236_channels,
1185 .num_channels = ARRAY_SIZE(max1236_channels),
1186 },
1187 [max1238] = {
1188 .bits = 12,
1189 .int_vref_mv = 4096,
1190 .mode_list = max1238_mode_list,
1191 .num_modes = ARRAY_SIZE(max1238_mode_list),
1192 .default_mode = s0to11,
1193 .info = &max1238_info,
1194 .channels = max1238_channels,
1195 .num_channels = ARRAY_SIZE(max1238_channels),
1196 },
1197 [max1239] = {
1198 .bits = 12,
1199 .int_vref_mv = 2048,
1200 .mode_list = max1238_mode_list,
1201 .num_modes = ARRAY_SIZE(max1238_mode_list),
1202 .default_mode = s0to11,
1203 .info = &max1238_info,
1204 .channels = max1238_channels,
1205 .num_channels = ARRAY_SIZE(max1238_channels),
1206 },
1207 [max11600] = {
1208 .bits = 8,
1209 .int_vref_mv = 4096,
1210 .mode_list = max11607_mode_list,
1211 .num_modes = ARRAY_SIZE(max11607_mode_list),
1212 .default_mode = s0to3,
1213 .info = &max1238_info,
1214 .channels = max1036_channels,
1215 .num_channels = ARRAY_SIZE(max1036_channels),
1216 },
1217 [max11601] = {
1218 .bits = 8,
1219 .int_vref_mv = 2048,
1220 .mode_list = max11607_mode_list,
1221 .num_modes = ARRAY_SIZE(max11607_mode_list),
1222 .default_mode = s0to3,
1223 .info = &max1238_info,
1224 .channels = max1036_channels,
1225 .num_channels = ARRAY_SIZE(max1036_channels),
1226 },
1227 [max11602] = {
1228 .bits = 8,
1229 .int_vref_mv = 4096,
1230 .mode_list = max11608_mode_list,
1231 .num_modes = ARRAY_SIZE(max11608_mode_list),
1232 .default_mode = s0to7,
1233 .info = &max1238_info,
1234 .channels = max11602_channels,
1235 .num_channels = ARRAY_SIZE(max11602_channels),
1236 },
1237 [max11603] = {
1238 .bits = 8,
1239 .int_vref_mv = 2048,
1240 .mode_list = max11608_mode_list,
1241 .num_modes = ARRAY_SIZE(max11608_mode_list),
1242 .default_mode = s0to7,
1243 .info = &max1238_info,
1244 .channels = max11602_channels,
1245 .num_channels = ARRAY_SIZE(max11602_channels),
1246 },
1247 [max11604] = {
1248 .bits = 8,
1249 .int_vref_mv = 4096,
1250 .mode_list = max1238_mode_list,
1251 .num_modes = ARRAY_SIZE(max1238_mode_list),
1252 .default_mode = s0to11,
1253 .info = &max1238_info,
1254 .channels = max1038_channels,
1255 .num_channels = ARRAY_SIZE(max1038_channels),
1256 },
1257 [max11605] = {
1258 .bits = 8,
1259 .int_vref_mv = 2048,
1260 .mode_list = max1238_mode_list,
1261 .num_modes = ARRAY_SIZE(max1238_mode_list),
1262 .default_mode = s0to11,
1263 .info = &max1238_info,
1264 .channels = max1038_channels,
1265 .num_channels = ARRAY_SIZE(max1038_channels),
1266 },
1267 [max11606] = {
1268 .bits = 10,
1269 .int_vref_mv = 4096,
1270 .mode_list = max11607_mode_list,
1271 .num_modes = ARRAY_SIZE(max11607_mode_list),
1272 .default_mode = s0to3,
1273 .info = &max1238_info,
1274 .channels = max1136_channels,
1275 .num_channels = ARRAY_SIZE(max1136_channels),
1276 },
1277 [max11607] = {
1278 .bits = 10,
1279 .int_vref_mv = 2048,
1280 .mode_list = max11607_mode_list,
1281 .num_modes = ARRAY_SIZE(max11607_mode_list),
1282 .default_mode = s0to3,
1283 .info = &max1238_info,
1284 .channels = max1136_channels,
1285 .num_channels = ARRAY_SIZE(max1136_channels),
1286 },
1287 [max11608] = {
1288 .bits = 10,
1289 .int_vref_mv = 4096,
1290 .mode_list = max11608_mode_list,
1291 .num_modes = ARRAY_SIZE(max11608_mode_list),
1292 .default_mode = s0to7,
1293 .info = &max1238_info,
1294 .channels = max11608_channels,
1295 .num_channels = ARRAY_SIZE(max11608_channels),
1296 },
1297 [max11609] = {
1298 .bits = 10,
1299 .int_vref_mv = 2048,
1300 .mode_list = max11608_mode_list,
1301 .num_modes = ARRAY_SIZE(max11608_mode_list),
1302 .default_mode = s0to7,
1303 .info = &max1238_info,
1304 .channels = max11608_channels,
1305 .num_channels = ARRAY_SIZE(max11608_channels),
1306 },
1307 [max11610] = {
1308 .bits = 10,
1309 .int_vref_mv = 4096,
1310 .mode_list = max1238_mode_list,
1311 .num_modes = ARRAY_SIZE(max1238_mode_list),
1312 .default_mode = s0to11,
1313 .info = &max1238_info,
1314 .channels = max1138_channels,
1315 .num_channels = ARRAY_SIZE(max1138_channels),
1316 },
1317 [max11611] = {
1318 .bits = 10,
1319 .int_vref_mv = 2048,
1320 .mode_list = max1238_mode_list,
1321 .num_modes = ARRAY_SIZE(max1238_mode_list),
1322 .default_mode = s0to11,
1323 .info = &max1238_info,
1324 .channels = max1138_channels,
1325 .num_channels = ARRAY_SIZE(max1138_channels),
1326 },
1327 [max11612] = {
1328 .bits = 12,
1329 .int_vref_mv = 4096,
1330 .mode_list = max11607_mode_list,
1331 .num_modes = ARRAY_SIZE(max11607_mode_list),
1332 .default_mode = s0to3,
1333 .info = &max1238_info,
1334 .channels = max1363_channels,
1335 .num_channels = ARRAY_SIZE(max1363_channels),
1336 },
1337 [max11613] = {
1338 .bits = 12,
1339 .int_vref_mv = 2048,
1340 .mode_list = max11607_mode_list,
1341 .num_modes = ARRAY_SIZE(max11607_mode_list),
1342 .default_mode = s0to3,
1343 .info = &max1238_info,
1344 .channels = max1363_channels,
1345 .num_channels = ARRAY_SIZE(max1363_channels),
1346 },
1347 [max11614] = {
1348 .bits = 12,
1349 .int_vref_mv = 4096,
1350 .mode_list = max11608_mode_list,
1351 .num_modes = ARRAY_SIZE(max11608_mode_list),
1352 .default_mode = s0to7,
1353 .info = &max1238_info,
1354 .channels = max11614_channels,
1355 .num_channels = ARRAY_SIZE(max11614_channels),
1356 },
1357 [max11615] = {
1358 .bits = 12,
1359 .int_vref_mv = 2048,
1360 .mode_list = max11608_mode_list,
1361 .num_modes = ARRAY_SIZE(max11608_mode_list),
1362 .default_mode = s0to7,
1363 .info = &max1238_info,
1364 .channels = max11614_channels,
1365 .num_channels = ARRAY_SIZE(max11614_channels),
1366 },
1367 [max11616] = {
1368 .bits = 12,
1369 .int_vref_mv = 4096,
1370 .mode_list = max1238_mode_list,
1371 .num_modes = ARRAY_SIZE(max1238_mode_list),
1372 .default_mode = s0to11,
1373 .info = &max1238_info,
1374 .channels = max1238_channels,
1375 .num_channels = ARRAY_SIZE(max1238_channels),
1376 },
1377 [max11617] = {
1378 .bits = 12,
1379 .int_vref_mv = 2048,
1380 .mode_list = max1238_mode_list,
1381 .num_modes = ARRAY_SIZE(max1238_mode_list),
1382 .default_mode = s0to11,
1383 .info = &max1238_info,
1384 .channels = max1238_channels,
1385 .num_channels = ARRAY_SIZE(max1238_channels),
1386 },
1387 [max11644] = {
1388 .bits = 12,
1389 .int_vref_mv = 2048,
1390 .mode_list = max11644_mode_list,
1391 .num_modes = ARRAY_SIZE(max11644_mode_list),
1392 .default_mode = s0to1,
1393 .info = &max1238_info,
1394 .channels = max11644_channels,
1395 .num_channels = ARRAY_SIZE(max11644_channels),
1396 },
1397 [max11645] = {
1398 .bits = 12,
1399 .int_vref_mv = 4096,
1400 .mode_list = max11644_mode_list,
1401 .num_modes = ARRAY_SIZE(max11644_mode_list),
1402 .default_mode = s0to1,
1403 .info = &max1238_info,
1404 .channels = max11644_channels,
1405 .num_channels = ARRAY_SIZE(max11644_channels),
1406 },
1407 [max11646] = {
1408 .bits = 10,
1409 .int_vref_mv = 2048,
1410 .mode_list = max11644_mode_list,
1411 .num_modes = ARRAY_SIZE(max11644_mode_list),
1412 .default_mode = s0to1,
1413 .info = &max1238_info,
1414 .channels = max11646_channels,
1415 .num_channels = ARRAY_SIZE(max11646_channels),
1416 },
1417 [max11647] = {
1418 .bits = 10,
1419 .int_vref_mv = 4096,
1420 .mode_list = max11644_mode_list,
1421 .num_modes = ARRAY_SIZE(max11644_mode_list),
1422 .default_mode = s0to1,
1423 .info = &max1238_info,
1424 .channels = max11646_channels,
1425 .num_channels = ARRAY_SIZE(max11646_channels),
1426 },
1427};
1428
1429static int max1363_initial_setup(struct max1363_state *st)
1430{
1431 st->setupbyte = MAX1363_SETUP_INT_CLOCK
1432 | MAX1363_SETUP_UNIPOLAR
1433 | MAX1363_SETUP_NORESET;
1434
1435 if (st->vref)
1436 st->setupbyte |= MAX1363_SETUP_AIN3_IS_REF_EXT_TO_REF;
1437 else
1438 st->setupbyte |= MAX1363_SETUP_POWER_UP_INT_REF
1439 | MAX1363_SETUP_AIN3_IS_AIN3_REF_IS_INT;
1440
1441
1442 st->setupbyte = MAX1363_SETUP_BYTE(st->setupbyte);
1443 st->current_mode = &max1363_mode_table[st->chip_info->default_mode];
1444 st->configbyte = MAX1363_CONFIG_BYTE(st->configbyte);
1445
1446 return max1363_set_scan_mode(st);
1447}
1448
1449static int max1363_alloc_scan_masks(struct iio_dev *indio_dev)
1450{
1451 struct max1363_state *st = iio_priv(indio_dev);
1452 unsigned long *masks;
1453 int i;
1454
1455 masks = devm_kzalloc(&indio_dev->dev,
1456 BITS_TO_LONGS(MAX1363_MAX_CHANNELS) * sizeof(long) *
1457 (st->chip_info->num_modes + 1), GFP_KERNEL);
1458 if (!masks)
1459 return -ENOMEM;
1460
1461 for (i = 0; i < st->chip_info->num_modes; i++)
1462 bitmap_copy(masks + BITS_TO_LONGS(MAX1363_MAX_CHANNELS)*i,
1463 max1363_mode_table[st->chip_info->mode_list[i]]
1464 .modemask, MAX1363_MAX_CHANNELS);
1465
1466 indio_dev->available_scan_masks = masks;
1467
1468 return 0;
1469}
1470
1471static irqreturn_t max1363_trigger_handler(int irq, void *p)
1472{
1473 struct iio_poll_func *pf = p;
1474 struct iio_dev *indio_dev = pf->indio_dev;
1475 struct max1363_state *st = iio_priv(indio_dev);
1476 __u8 *rxbuf;
1477 int b_sent;
1478 size_t d_size;
1479 unsigned long numvals = bitmap_weight(st->current_mode->modemask,
1480 MAX1363_MAX_CHANNELS);
1481
1482
1483 if (st->chip_info->bits != 8)
1484 d_size = numvals*2;
1485 else
1486 d_size = numvals;
1487 if (indio_dev->scan_timestamp) {
1488 d_size += sizeof(s64);
1489 if (d_size % sizeof(s64))
1490 d_size += sizeof(s64) - (d_size % sizeof(s64));
1491 }
1492
1493
1494
1495
1496 if (numvals == 0)
1497 goto done;
1498
1499 rxbuf = kmalloc(d_size, GFP_KERNEL);
1500 if (rxbuf == NULL)
1501 goto done;
1502 if (st->chip_info->bits != 8)
1503 b_sent = st->recv(st->client, rxbuf, numvals * 2);
1504 else
1505 b_sent = st->recv(st->client, rxbuf, numvals);
1506 if (b_sent < 0)
1507 goto done_free;
1508
1509 iio_push_to_buffers_with_timestamp(indio_dev, rxbuf, iio_get_time_ns());
1510
1511done_free:
1512 kfree(rxbuf);
1513done:
1514 iio_trigger_notify_done(indio_dev->trig);
1515
1516 return IRQ_HANDLED;
1517}
1518
1519static int max1363_probe(struct i2c_client *client,
1520 const struct i2c_device_id *id)
1521{
1522 int ret;
1523 struct max1363_state *st;
1524 struct iio_dev *indio_dev;
1525 struct regulator *vref;
1526
1527 indio_dev = devm_iio_device_alloc(&client->dev,
1528 sizeof(struct max1363_state));
1529 if (!indio_dev)
1530 return -ENOMEM;
1531
1532 indio_dev->dev.of_node = client->dev.of_node;
1533 ret = iio_map_array_register(indio_dev, client->dev.platform_data);
1534 if (ret < 0)
1535 return ret;
1536
1537 st = iio_priv(indio_dev);
1538
1539 st->reg = devm_regulator_get(&client->dev, "vcc");
1540 if (IS_ERR(st->reg)) {
1541 ret = PTR_ERR(st->reg);
1542 goto error_unregister_map;
1543 }
1544
1545 ret = regulator_enable(st->reg);
1546 if (ret)
1547 goto error_unregister_map;
1548
1549
1550 i2c_set_clientdata(client, indio_dev);
1551
1552 st->chip_info = &max1363_chip_info_tbl[id->driver_data];
1553 st->client = client;
1554
1555 st->vref_uv = st->chip_info->int_vref_mv * 1000;
1556 vref = devm_regulator_get_optional(&client->dev, "vref");
1557 if (!IS_ERR(vref)) {
1558 int vref_uv;
1559
1560 ret = regulator_enable(vref);
1561 if (ret)
1562 goto error_disable_reg;
1563 st->vref = vref;
1564 vref_uv = regulator_get_voltage(vref);
1565 if (vref_uv <= 0) {
1566 ret = -EINVAL;
1567 goto error_disable_reg;
1568 }
1569 st->vref_uv = vref_uv;
1570 }
1571
1572 if (i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
1573 st->send = i2c_master_send;
1574 st->recv = i2c_master_recv;
1575 } else if (i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE)
1576 && st->chip_info->bits == 8) {
1577 st->send = max1363_smbus_send;
1578 st->recv = max1363_smbus_recv;
1579 } else {
1580 ret = -EOPNOTSUPP;
1581 goto error_disable_reg;
1582 }
1583
1584 ret = max1363_alloc_scan_masks(indio_dev);
1585 if (ret)
1586 goto error_disable_reg;
1587
1588
1589 indio_dev->dev.parent = &client->dev;
1590 indio_dev->name = id->name;
1591 indio_dev->channels = st->chip_info->channels;
1592 indio_dev->num_channels = st->chip_info->num_channels;
1593 indio_dev->info = st->chip_info->info;
1594 indio_dev->modes = INDIO_DIRECT_MODE;
1595 ret = max1363_initial_setup(st);
1596 if (ret < 0)
1597 goto error_disable_reg;
1598
1599 ret = iio_triggered_buffer_setup(indio_dev, NULL,
1600 &max1363_trigger_handler, NULL);
1601 if (ret)
1602 goto error_disable_reg;
1603
1604 if (client->irq) {
1605 ret = devm_request_threaded_irq(&client->dev, st->client->irq,
1606 NULL,
1607 &max1363_event_handler,
1608 IRQF_TRIGGER_RISING | IRQF_ONESHOT,
1609 "max1363_event",
1610 indio_dev);
1611
1612 if (ret)
1613 goto error_uninit_buffer;
1614 }
1615
1616 ret = iio_device_register(indio_dev);
1617 if (ret < 0)
1618 goto error_uninit_buffer;
1619
1620 return 0;
1621
1622error_uninit_buffer:
1623 iio_triggered_buffer_cleanup(indio_dev);
1624error_disable_reg:
1625 if (st->vref)
1626 regulator_disable(st->vref);
1627 regulator_disable(st->reg);
1628error_unregister_map:
1629 iio_map_array_unregister(indio_dev);
1630 return ret;
1631}
1632
1633static int max1363_remove(struct i2c_client *client)
1634{
1635 struct iio_dev *indio_dev = i2c_get_clientdata(client);
1636 struct max1363_state *st = iio_priv(indio_dev);
1637
1638 iio_device_unregister(indio_dev);
1639 iio_triggered_buffer_cleanup(indio_dev);
1640 if (st->vref)
1641 regulator_disable(st->vref);
1642 regulator_disable(st->reg);
1643 iio_map_array_unregister(indio_dev);
1644
1645 return 0;
1646}
1647
1648static const struct i2c_device_id max1363_id[] = {
1649 { "max1361", max1361 },
1650 { "max1362", max1362 },
1651 { "max1363", max1363 },
1652 { "max1364", max1364 },
1653 { "max1036", max1036 },
1654 { "max1037", max1037 },
1655 { "max1038", max1038 },
1656 { "max1039", max1039 },
1657 { "max1136", max1136 },
1658 { "max1137", max1137 },
1659 { "max1138", max1138 },
1660 { "max1139", max1139 },
1661 { "max1236", max1236 },
1662 { "max1237", max1237 },
1663 { "max1238", max1238 },
1664 { "max1239", max1239 },
1665 { "max11600", max11600 },
1666 { "max11601", max11601 },
1667 { "max11602", max11602 },
1668 { "max11603", max11603 },
1669 { "max11604", max11604 },
1670 { "max11605", max11605 },
1671 { "max11606", max11606 },
1672 { "max11607", max11607 },
1673 { "max11608", max11608 },
1674 { "max11609", max11609 },
1675 { "max11610", max11610 },
1676 { "max11611", max11611 },
1677 { "max11612", max11612 },
1678 { "max11613", max11613 },
1679 { "max11614", max11614 },
1680 { "max11615", max11615 },
1681 { "max11616", max11616 },
1682 { "max11617", max11617 },
1683 {}
1684};
1685
1686MODULE_DEVICE_TABLE(i2c, max1363_id);
1687
1688static struct i2c_driver max1363_driver = {
1689 .driver = {
1690 .name = "max1363",
1691 },
1692 .probe = max1363_probe,
1693 .remove = max1363_remove,
1694 .id_table = max1363_id,
1695};
1696module_i2c_driver(max1363_driver);
1697
1698MODULE_AUTHOR("Jonathan Cameron <jic23@kernel.org>");
1699MODULE_DESCRIPTION("Maxim 1363 ADC");
1700MODULE_LICENSE("GPL v2");
1701
