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22#ifndef __XGENE_ENET_MAIN_H__
23#define __XGENE_ENET_MAIN_H__
24
25#include <linux/acpi.h>
26#include <linux/clk.h>
27#include <linux/efi.h>
28#include <linux/io.h>
29#include <linux/of_platform.h>
30#include <linux/of_net.h>
31#include <linux/of_mdio.h>
32#include <linux/module.h>
33#include <net/ip.h>
34#include <linux/prefetch.h>
35#include <linux/if_vlan.h>
36#include <linux/phy.h>
37#include "xgene_enet_hw.h"
38#include "xgene_enet_ring2.h"
39
40#define XGENE_DRV_VERSION "v1.0"
41#define XGENE_ENET_MAX_MTU 1536
42#define SKB_BUFFER_SIZE (XGENE_ENET_MAX_MTU - NET_IP_ALIGN)
43#define BUFLEN_16K (16 * 1024)
44#define NUM_PKT_BUF 64
45#define NUM_BUFPOOL 32
46#define MAX_EXP_BUFFS 256
47#define XGENE_ENET_MSS 1448
48#define XGENE_MIN_ENET_FRAME_SIZE 60
49
50#define START_CPU_BUFNUM_0 0
51#define START_ETH_BUFNUM_0 2
52#define START_BP_BUFNUM_0 0x22
53#define START_RING_NUM_0 8
54#define START_CPU_BUFNUM_1 12
55#define START_ETH_BUFNUM_1 10
56#define START_BP_BUFNUM_1 0x2A
57#define START_RING_NUM_1 264
58
59#define XG_START_CPU_BUFNUM_1 12
60#define XG_START_ETH_BUFNUM_1 2
61#define XG_START_BP_BUFNUM_1 0x22
62#define XG_START_RING_NUM_1 264
63
64#define X2_START_CPU_BUFNUM_0 0
65#define X2_START_ETH_BUFNUM_0 0
66#define X2_START_BP_BUFNUM_0 0x20
67#define X2_START_RING_NUM_0 0
68#define X2_START_CPU_BUFNUM_1 0xc
69#define X2_START_ETH_BUFNUM_1 0
70#define X2_START_BP_BUFNUM_1 0x20
71#define X2_START_RING_NUM_1 256
72
73#define IRQ_ID_SIZE 16
74#define XGENE_MAX_TXC_RINGS 1
75
76#define PHY_POLL_LINK_ON (10 * HZ)
77#define PHY_POLL_LINK_OFF (PHY_POLL_LINK_ON / 5)
78
79enum xgene_enet_id {
80 XGENE_ENET1 = 1,
81 XGENE_ENET2
82};
83
84
85struct xgene_enet_desc_ring {
86 struct net_device *ndev;
87 u16 id;
88 u16 num;
89 u16 head;
90 u16 tail;
91 u16 exp_buf_tail;
92 u16 slots;
93 u16 irq;
94 char irq_name[IRQ_ID_SIZE];
95 u32 size;
96 u32 state[X2_NUM_RING_CONFIG];
97 void __iomem *cmd_base;
98 void __iomem *cmd;
99 dma_addr_t dma;
100 dma_addr_t irq_mbox_dma;
101 void *irq_mbox_addr;
102 u16 dst_ring_num;
103 u8 nbufpool;
104 struct sk_buff *(*rx_skb);
105 struct sk_buff *(*cp_skb);
106 dma_addr_t *frag_dma_addr;
107 enum xgene_enet_ring_cfgsize cfgsize;
108 struct xgene_enet_desc_ring *cp_ring;
109 struct xgene_enet_desc_ring *buf_pool;
110 struct napi_struct napi;
111 union {
112 void *desc_addr;
113 struct xgene_enet_raw_desc *raw_desc;
114 struct xgene_enet_raw_desc16 *raw_desc16;
115 };
116 __le64 *exp_bufs;
117};
118
119struct xgene_mac_ops {
120 void (*init)(struct xgene_enet_pdata *pdata);
121 void (*reset)(struct xgene_enet_pdata *pdata);
122 void (*tx_enable)(struct xgene_enet_pdata *pdata);
123 void (*rx_enable)(struct xgene_enet_pdata *pdata);
124 void (*tx_disable)(struct xgene_enet_pdata *pdata);
125 void (*rx_disable)(struct xgene_enet_pdata *pdata);
126 void (*set_mac_addr)(struct xgene_enet_pdata *pdata);
127 void (*set_mss)(struct xgene_enet_pdata *pdata);
128 void (*link_state)(struct work_struct *work);
129};
130
131struct xgene_port_ops {
132 int (*reset)(struct xgene_enet_pdata *pdata);
133 void (*cle_bypass)(struct xgene_enet_pdata *pdata,
134 u32 dst_ring_num, u16 bufpool_id);
135 void (*shutdown)(struct xgene_enet_pdata *pdata);
136};
137
138struct xgene_ring_ops {
139 u8 num_ring_config;
140 u8 num_ring_id_shift;
141 struct xgene_enet_desc_ring * (*setup)(struct xgene_enet_desc_ring *);
142 void (*clear)(struct xgene_enet_desc_ring *);
143 void (*wr_cmd)(struct xgene_enet_desc_ring *, int);
144 u32 (*len)(struct xgene_enet_desc_ring *);
145};
146
147
148struct xgene_enet_pdata {
149 struct net_device *ndev;
150 struct mii_bus *mdio_bus;
151 struct phy_device *phy_dev;
152 int phy_speed;
153 struct clk *clk;
154 struct platform_device *pdev;
155 enum xgene_enet_id enet_id;
156 struct xgene_enet_desc_ring *tx_ring;
157 struct xgene_enet_desc_ring *rx_ring;
158 u16 tx_level;
159 u16 txc_level;
160 char *dev_name;
161 u32 rx_buff_cnt;
162 u32 tx_qcnt_hi;
163 u32 rx_irq;
164 u32 txc_irq;
165 u8 cq_cnt;
166 void __iomem *eth_csr_addr;
167 void __iomem *eth_ring_if_addr;
168 void __iomem *eth_diag_csr_addr;
169 void __iomem *mcx_mac_addr;
170 void __iomem *mcx_mac_csr_addr;
171 void __iomem *base_addr;
172 void __iomem *ring_csr_addr;
173 void __iomem *ring_cmd_addr;
174 int phy_mode;
175 enum xgene_enet_rm rm;
176 struct rtnl_link_stats64 stats;
177 struct xgene_mac_ops *mac_ops;
178 struct xgene_port_ops *port_ops;
179 struct xgene_ring_ops *ring_ops;
180 struct delayed_work link_work;
181 u32 port_id;
182 u8 cpu_bufnum;
183 u8 eth_bufnum;
184 u8 bp_bufnum;
185 u16 ring_num;
186 u32 mss;
187 u8 tx_delay;
188 u8 rx_delay;
189};
190
191struct xgene_indirect_ctl {
192 void __iomem *addr;
193 void __iomem *ctl;
194 void __iomem *cmd;
195 void __iomem *cmd_done;
196};
197
198
199
200
201static inline u64 xgene_enet_set_field_value(int pos, int len, u64 val)
202{
203 return (val & ((1ULL << len) - 1)) << pos;
204}
205
206#define SET_VAL(field, val) \
207 xgene_enet_set_field_value(field ## _POS, field ## _LEN, val)
208
209#define SET_BIT(field) \
210 xgene_enet_set_field_value(field ## _POS, 1, 1)
211
212
213
214
215static inline u64 xgene_enet_get_field_value(int pos, int len, u64 src)
216{
217 return (src >> pos) & ((1ULL << len) - 1);
218}
219
220#define GET_VAL(field, src) \
221 xgene_enet_get_field_value(field ## _POS, field ## _LEN, src)
222
223#define GET_BIT(field, src) \
224 xgene_enet_get_field_value(field ## _POS, 1, src)
225
226static inline struct device *ndev_to_dev(struct net_device *ndev)
227{
228 return ndev->dev.parent;
229}
230
231void xgene_enet_set_ethtool_ops(struct net_device *netdev);
232
233#endif
234
