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20#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
21
22#include <linux/ethtool.h>
23#include <linux/netdevice.h>
24#include <linux/types.h>
25#include <linux/sched.h>
26#include <linux/crc32.h>
27#include "bnx2x.h"
28#include "bnx2x_cmn.h"
29#include "bnx2x_dump.h"
30#include "bnx2x_init.h"
31
32
33
34
35
36#define MAX_QUEUE_NAME_LEN 4
37static const struct {
38 long offset;
39 int size;
40 char string[ETH_GSTRING_LEN];
41} bnx2x_q_stats_arr[] = {
42 { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" },
43 { Q_STATS_OFFSET32(total_unicast_packets_received_hi),
44 8, "[%s]: rx_ucast_packets" },
45 { Q_STATS_OFFSET32(total_multicast_packets_received_hi),
46 8, "[%s]: rx_mcast_packets" },
47 { Q_STATS_OFFSET32(total_broadcast_packets_received_hi),
48 8, "[%s]: rx_bcast_packets" },
49 { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%s]: rx_discards" },
50 { Q_STATS_OFFSET32(rx_err_discard_pkt),
51 4, "[%s]: rx_phy_ip_err_discards"},
52 { Q_STATS_OFFSET32(rx_skb_alloc_failed),
53 4, "[%s]: rx_skb_alloc_discard" },
54 { Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" },
55
56 { Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%s]: tx_bytes" },
57{ Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi),
58 8, "[%s]: tx_ucast_packets" },
59 { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi),
60 8, "[%s]: tx_mcast_packets" },
61 { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
62 8, "[%s]: tx_bcast_packets" },
63 { Q_STATS_OFFSET32(total_tpa_aggregations_hi),
64 8, "[%s]: tpa_aggregations" },
65 { Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi),
66 8, "[%s]: tpa_aggregated_frames"},
67 { Q_STATS_OFFSET32(total_tpa_bytes_hi), 8, "[%s]: tpa_bytes"},
68 { Q_STATS_OFFSET32(driver_filtered_tx_pkt),
69 4, "[%s]: driver_filtered_tx_pkt" }
70};
71
72#define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr)
73
74static const struct {
75 long offset;
76 int size;
77 u32 flags;
78#define STATS_FLAGS_PORT 1
79#define STATS_FLAGS_FUNC 2
80#define STATS_FLAGS_BOTH (STATS_FLAGS_FUNC | STATS_FLAGS_PORT)
81 char string[ETH_GSTRING_LEN];
82} bnx2x_stats_arr[] = {
83 { STATS_OFFSET32(total_bytes_received_hi),
84 8, STATS_FLAGS_BOTH, "rx_bytes" },
85 { STATS_OFFSET32(error_bytes_received_hi),
86 8, STATS_FLAGS_BOTH, "rx_error_bytes" },
87 { STATS_OFFSET32(total_unicast_packets_received_hi),
88 8, STATS_FLAGS_BOTH, "rx_ucast_packets" },
89 { STATS_OFFSET32(total_multicast_packets_received_hi),
90 8, STATS_FLAGS_BOTH, "rx_mcast_packets" },
91 { STATS_OFFSET32(total_broadcast_packets_received_hi),
92 8, STATS_FLAGS_BOTH, "rx_bcast_packets" },
93 { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
94 8, STATS_FLAGS_PORT, "rx_crc_errors" },
95 { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
96 8, STATS_FLAGS_PORT, "rx_align_errors" },
97 { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
98 8, STATS_FLAGS_PORT, "rx_undersize_packets" },
99 { STATS_OFFSET32(etherstatsoverrsizepkts_hi),
100 8, STATS_FLAGS_PORT, "rx_oversize_packets" },
101{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
102 8, STATS_FLAGS_PORT, "rx_fragments" },
103 { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi),
104 8, STATS_FLAGS_PORT, "rx_jabbers" },
105 { STATS_OFFSET32(no_buff_discard_hi),
106 8, STATS_FLAGS_BOTH, "rx_discards" },
107 { STATS_OFFSET32(mac_filter_discard),
108 4, STATS_FLAGS_PORT, "rx_filtered_packets" },
109 { STATS_OFFSET32(mf_tag_discard),
110 4, STATS_FLAGS_PORT, "rx_mf_tag_discard" },
111 { STATS_OFFSET32(pfc_frames_received_hi),
112 8, STATS_FLAGS_PORT, "pfc_frames_received" },
113 { STATS_OFFSET32(pfc_frames_sent_hi),
114 8, STATS_FLAGS_PORT, "pfc_frames_sent" },
115 { STATS_OFFSET32(brb_drop_hi),
116 8, STATS_FLAGS_PORT, "rx_brb_discard" },
117 { STATS_OFFSET32(brb_truncate_hi),
118 8, STATS_FLAGS_PORT, "rx_brb_truncate" },
119 { STATS_OFFSET32(pause_frames_received_hi),
120 8, STATS_FLAGS_PORT, "rx_pause_frames" },
121 { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
122 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" },
123 { STATS_OFFSET32(nig_timer_max),
124 4, STATS_FLAGS_PORT, "rx_constant_pause_events" },
125{ STATS_OFFSET32(rx_err_discard_pkt),
126 4, STATS_FLAGS_BOTH, "rx_phy_ip_err_discards"},
127 { STATS_OFFSET32(rx_skb_alloc_failed),
128 4, STATS_FLAGS_BOTH, "rx_skb_alloc_discard" },
129 { STATS_OFFSET32(hw_csum_err),
130 4, STATS_FLAGS_BOTH, "rx_csum_offload_errors" },
131
132 { STATS_OFFSET32(total_bytes_transmitted_hi),
133 8, STATS_FLAGS_BOTH, "tx_bytes" },
134 { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi),
135 8, STATS_FLAGS_PORT, "tx_error_bytes" },
136 { STATS_OFFSET32(total_unicast_packets_transmitted_hi),
137 8, STATS_FLAGS_BOTH, "tx_ucast_packets" },
138 { STATS_OFFSET32(total_multicast_packets_transmitted_hi),
139 8, STATS_FLAGS_BOTH, "tx_mcast_packets" },
140 { STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
141 8, STATS_FLAGS_BOTH, "tx_bcast_packets" },
142 { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
143 8, STATS_FLAGS_PORT, "tx_mac_errors" },
144 { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
145 8, STATS_FLAGS_PORT, "tx_carrier_errors" },
146{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
147 8, STATS_FLAGS_PORT, "tx_single_collisions" },
148 { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
149 8, STATS_FLAGS_PORT, "tx_multi_collisions" },
150 { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
151 8, STATS_FLAGS_PORT, "tx_deferred" },
152 { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
153 8, STATS_FLAGS_PORT, "tx_excess_collisions" },
154 { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
155 8, STATS_FLAGS_PORT, "tx_late_collisions" },
156 { STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
157 8, STATS_FLAGS_PORT, "tx_total_collisions" },
158 { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
159 8, STATS_FLAGS_PORT, "tx_64_byte_packets" },
160 { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
161 8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" },
162 { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
163 8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" },
164 { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
165 8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" },
166{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
167 8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" },
168 { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
169 8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" },
170 { STATS_OFFSET32(etherstatspktsover1522octets_hi),
171 8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" },
172 { STATS_OFFSET32(pause_frames_sent_hi),
173 8, STATS_FLAGS_PORT, "tx_pause_frames" },
174 { STATS_OFFSET32(total_tpa_aggregations_hi),
175 8, STATS_FLAGS_FUNC, "tpa_aggregations" },
176 { STATS_OFFSET32(total_tpa_aggregated_frames_hi),
177 8, STATS_FLAGS_FUNC, "tpa_aggregated_frames"},
178 { STATS_OFFSET32(total_tpa_bytes_hi),
179 8, STATS_FLAGS_FUNC, "tpa_bytes"},
180 { STATS_OFFSET32(recoverable_error),
181 4, STATS_FLAGS_FUNC, "recoverable_errors" },
182 { STATS_OFFSET32(unrecoverable_error),
183 4, STATS_FLAGS_FUNC, "unrecoverable_errors" },
184 { STATS_OFFSET32(driver_filtered_tx_pkt),
185 4, STATS_FLAGS_FUNC, "driver_filtered_tx_pkt" },
186 { STATS_OFFSET32(eee_tx_lpi),
187 4, STATS_FLAGS_PORT, "Tx LPI entry count"}
188};
189
190#define BNX2X_NUM_STATS ARRAY_SIZE(bnx2x_stats_arr)
191
192static int bnx2x_get_port_type(struct bnx2x *bp)
193{
194 int port_type;
195 u32 phy_idx = bnx2x_get_cur_phy_idx(bp);
196 switch (bp->link_params.phy[phy_idx].media_type) {
197 case ETH_PHY_SFPP_10G_FIBER:
198 case ETH_PHY_SFP_1G_FIBER:
199 case ETH_PHY_XFP_FIBER:
200 case ETH_PHY_KR:
201 case ETH_PHY_CX4:
202 port_type = PORT_FIBRE;
203 break;
204 case ETH_PHY_DA_TWINAX:
205 port_type = PORT_DA;
206 break;
207 case ETH_PHY_BASE_T:
208 port_type = PORT_TP;
209 break;
210 case ETH_PHY_NOT_PRESENT:
211 port_type = PORT_NONE;
212 break;
213 case ETH_PHY_UNSPECIFIED:
214 default:
215 port_type = PORT_OTHER;
216 break;
217 }
218 return port_type;
219}
220
221static int bnx2x_get_vf_settings(struct net_device *dev,
222 struct ethtool_cmd *cmd)
223{
224 struct bnx2x *bp = netdev_priv(dev);
225
226 if (bp->state == BNX2X_STATE_OPEN) {
227 if (test_bit(BNX2X_LINK_REPORT_FD,
228 &bp->vf_link_vars.link_report_flags))
229 cmd->duplex = DUPLEX_FULL;
230 else
231 cmd->duplex = DUPLEX_HALF;
232
233 ethtool_cmd_speed_set(cmd, bp->vf_link_vars.line_speed);
234 } else {
235 cmd->duplex = DUPLEX_UNKNOWN;
236 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
237 }
238
239 cmd->port = PORT_OTHER;
240 cmd->phy_address = 0;
241 cmd->transceiver = XCVR_INTERNAL;
242 cmd->autoneg = AUTONEG_DISABLE;
243 cmd->maxtxpkt = 0;
244 cmd->maxrxpkt = 0;
245
246 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
247 " supported 0x%x advertising 0x%x speed %u\n"
248 " duplex %d port %d phy_address %d transceiver %d\n"
249 " autoneg %d maxtxpkt %d maxrxpkt %d\n",
250 cmd->cmd, cmd->supported, cmd->advertising,
251 ethtool_cmd_speed(cmd),
252 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
253 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
254
255 return 0;
256}
257
258static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
259{
260 struct bnx2x *bp = netdev_priv(dev);
261 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
262 u32 media_type;
263
264
265 cmd->supported = bp->port.supported[cfg_idx] |
266 (bp->port.supported[cfg_idx ^ 1] &
267 (SUPPORTED_TP | SUPPORTED_FIBRE));
268 cmd->advertising = bp->port.advertising[cfg_idx];
269 media_type = bp->link_params.phy[bnx2x_get_cur_phy_idx(bp)].media_type;
270 if (media_type == ETH_PHY_SFP_1G_FIBER) {
271 cmd->supported &= ~(SUPPORTED_10000baseT_Full);
272 cmd->advertising &= ~(ADVERTISED_10000baseT_Full);
273 }
274
275 if ((bp->state == BNX2X_STATE_OPEN) && bp->link_vars.link_up &&
276 !(bp->flags & MF_FUNC_DIS)) {
277 cmd->duplex = bp->link_vars.duplex;
278
279 if (IS_MF(bp) && !BP_NOMCP(bp))
280 ethtool_cmd_speed_set(cmd, bnx2x_get_mf_speed(bp));
281 else
282 ethtool_cmd_speed_set(cmd, bp->link_vars.line_speed);
283 } else {
284 cmd->duplex = DUPLEX_UNKNOWN;
285 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
286 }
287
288 cmd->port = bnx2x_get_port_type(bp);
289
290 cmd->phy_address = bp->mdio.prtad;
291 cmd->transceiver = XCVR_INTERNAL;
292
293 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG)
294 cmd->autoneg = AUTONEG_ENABLE;
295 else
296 cmd->autoneg = AUTONEG_DISABLE;
297
298
299 if (bp->link_vars.link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
300 u32 status = bp->link_vars.link_status;
301
302 cmd->lp_advertising |= ADVERTISED_Autoneg;
303 if (status & LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE)
304 cmd->lp_advertising |= ADVERTISED_Pause;
305 if (status & LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE)
306 cmd->lp_advertising |= ADVERTISED_Asym_Pause;
307
308 if (status & LINK_STATUS_LINK_PARTNER_10THD_CAPABLE)
309 cmd->lp_advertising |= ADVERTISED_10baseT_Half;
310 if (status & LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE)
311 cmd->lp_advertising |= ADVERTISED_10baseT_Full;
312 if (status & LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE)
313 cmd->lp_advertising |= ADVERTISED_100baseT_Half;
314 if (status & LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE)
315 cmd->lp_advertising |= ADVERTISED_100baseT_Full;
316 if (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE)
317 cmd->lp_advertising |= ADVERTISED_1000baseT_Half;
318 if (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) {
319 if (media_type == ETH_PHY_KR) {
320 cmd->lp_advertising |=
321 ADVERTISED_1000baseKX_Full;
322 } else {
323 cmd->lp_advertising |=
324 ADVERTISED_1000baseT_Full;
325 }
326 }
327 if (status & LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE)
328 cmd->lp_advertising |= ADVERTISED_2500baseX_Full;
329 if (status & LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE) {
330 if (media_type == ETH_PHY_KR) {
331 cmd->lp_advertising |=
332 ADVERTISED_10000baseKR_Full;
333 } else {
334 cmd->lp_advertising |=
335 ADVERTISED_10000baseT_Full;
336 }
337 }
338 if (status & LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE)
339 cmd->lp_advertising |= ADVERTISED_20000baseKR2_Full;
340 }
341
342 cmd->maxtxpkt = 0;
343 cmd->maxrxpkt = 0;
344
345 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
346 " supported 0x%x advertising 0x%x speed %u\n"
347 " duplex %d port %d phy_address %d transceiver %d\n"
348 " autoneg %d maxtxpkt %d maxrxpkt %d\n",
349 cmd->cmd, cmd->supported, cmd->advertising,
350 ethtool_cmd_speed(cmd),
351 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
352 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
353
354 return 0;
355}
356
357static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
358{
359 struct bnx2x *bp = netdev_priv(dev);
360 u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config;
361 u32 speed, phy_idx;
362
363 if (IS_MF_SD(bp))
364 return 0;
365
366 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
367 " supported 0x%x advertising 0x%x speed %u\n"
368 " duplex %d port %d phy_address %d transceiver %d\n"
369 " autoneg %d maxtxpkt %d maxrxpkt %d\n",
370 cmd->cmd, cmd->supported, cmd->advertising,
371 ethtool_cmd_speed(cmd),
372 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
373 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
374
375 speed = ethtool_cmd_speed(cmd);
376
377
378 if (cmd->duplex == DUPLEX_UNKNOWN)
379 cmd->duplex = DUPLEX_FULL;
380
381 if (IS_MF_SI(bp)) {
382 u32 part;
383 u32 line_speed = bp->link_vars.line_speed;
384
385
386 if (!line_speed)
387 line_speed = 10000;
388
389 if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) {
390 DP(BNX2X_MSG_ETHTOOL,
391 "To set speed BC %X or higher is required, please upgrade BC\n",
392 REQ_BC_VER_4_SET_MF_BW);
393 return -EINVAL;
394 }
395
396 part = (speed * 100) / line_speed;
397
398 if (line_speed < speed || !part) {
399 DP(BNX2X_MSG_ETHTOOL,
400 "Speed setting should be in a range from 1%% to 100%% of actual line speed\n");
401 return -EINVAL;
402 }
403
404 if (bp->state != BNX2X_STATE_OPEN)
405
406 bp->pending_max = part;
407 else
408 bnx2x_update_max_mf_config(bp, part);
409
410 return 0;
411 }
412
413 cfg_idx = bnx2x_get_link_cfg_idx(bp);
414 old_multi_phy_config = bp->link_params.multi_phy_config;
415 if (cmd->port != bnx2x_get_port_type(bp)) {
416 switch (cmd->port) {
417 case PORT_TP:
418 if (!(bp->port.supported[0] & SUPPORTED_TP ||
419 bp->port.supported[1] & SUPPORTED_TP)) {
420 DP(BNX2X_MSG_ETHTOOL,
421 "Unsupported port type\n");
422 return -EINVAL;
423 }
424 bp->link_params.multi_phy_config &=
425 ~PORT_HW_CFG_PHY_SELECTION_MASK;
426 if (bp->link_params.multi_phy_config &
427 PORT_HW_CFG_PHY_SWAPPED_ENABLED)
428 bp->link_params.multi_phy_config |=
429 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
430 else
431 bp->link_params.multi_phy_config |=
432 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
433 break;
434 case PORT_FIBRE:
435 case PORT_DA:
436 case PORT_NONE:
437 if (!(bp->port.supported[0] & SUPPORTED_FIBRE ||
438 bp->port.supported[1] & SUPPORTED_FIBRE)) {
439 DP(BNX2X_MSG_ETHTOOL,
440 "Unsupported port type\n");
441 return -EINVAL;
442 }
443 bp->link_params.multi_phy_config &=
444 ~PORT_HW_CFG_PHY_SELECTION_MASK;
445 if (bp->link_params.multi_phy_config &
446 PORT_HW_CFG_PHY_SWAPPED_ENABLED)
447 bp->link_params.multi_phy_config |=
448 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
449 else
450 bp->link_params.multi_phy_config |=
451 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
452 break;
453 default:
454 DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
455 return -EINVAL;
456 }
457 }
458
459 new_multi_phy_config = bp->link_params.multi_phy_config;
460
461 cfg_idx = bnx2x_get_link_cfg_idx(bp);
462
463 bp->link_params.multi_phy_config = old_multi_phy_config;
464 DP(BNX2X_MSG_ETHTOOL, "cfg_idx = %x\n", cfg_idx);
465
466 if (cmd->autoneg == AUTONEG_ENABLE) {
467 u32 an_supported_speed = bp->port.supported[cfg_idx];
468 if (bp->link_params.phy[EXT_PHY1].type ==
469 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
470 an_supported_speed |= (SUPPORTED_100baseT_Half |
471 SUPPORTED_100baseT_Full);
472 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
473 DP(BNX2X_MSG_ETHTOOL, "Autoneg not supported\n");
474 return -EINVAL;
475 }
476
477
478 if (cmd->advertising & ~an_supported_speed) {
479 DP(BNX2X_MSG_ETHTOOL,
480 "Advertisement parameters are not supported\n");
481 return -EINVAL;
482 }
483
484 bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG;
485 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
486 bp->port.advertising[cfg_idx] = (ADVERTISED_Autoneg |
487 cmd->advertising);
488 if (cmd->advertising) {
489
490 bp->link_params.speed_cap_mask[cfg_idx] = 0;
491 if (cmd->advertising & ADVERTISED_10baseT_Half) {
492 bp->link_params.speed_cap_mask[cfg_idx] |=
493 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF;
494 }
495 if (cmd->advertising & ADVERTISED_10baseT_Full)
496 bp->link_params.speed_cap_mask[cfg_idx] |=
497 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL;
498
499 if (cmd->advertising & ADVERTISED_100baseT_Full)
500 bp->link_params.speed_cap_mask[cfg_idx] |=
501 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL;
502
503 if (cmd->advertising & ADVERTISED_100baseT_Half) {
504 bp->link_params.speed_cap_mask[cfg_idx] |=
505 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF;
506 }
507 if (cmd->advertising & ADVERTISED_1000baseT_Half) {
508 bp->link_params.speed_cap_mask[cfg_idx] |=
509 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
510 }
511 if (cmd->advertising & (ADVERTISED_1000baseT_Full |
512 ADVERTISED_1000baseKX_Full))
513 bp->link_params.speed_cap_mask[cfg_idx] |=
514 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
515
516 if (cmd->advertising & (ADVERTISED_10000baseT_Full |
517 ADVERTISED_10000baseKX4_Full |
518 ADVERTISED_10000baseKR_Full))
519 bp->link_params.speed_cap_mask[cfg_idx] |=
520 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G;
521
522 if (cmd->advertising & ADVERTISED_20000baseKR2_Full)
523 bp->link_params.speed_cap_mask[cfg_idx] |=
524 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G;
525 }
526 } else {
527
528 switch (speed) {
529 case SPEED_10:
530 if (cmd->duplex == DUPLEX_FULL) {
531 if (!(bp->port.supported[cfg_idx] &
532 SUPPORTED_10baseT_Full)) {
533 DP(BNX2X_MSG_ETHTOOL,
534 "10M full not supported\n");
535 return -EINVAL;
536 }
537
538 advertising = (ADVERTISED_10baseT_Full |
539 ADVERTISED_TP);
540 } else {
541 if (!(bp->port.supported[cfg_idx] &
542 SUPPORTED_10baseT_Half)) {
543 DP(BNX2X_MSG_ETHTOOL,
544 "10M half not supported\n");
545 return -EINVAL;
546 }
547
548 advertising = (ADVERTISED_10baseT_Half |
549 ADVERTISED_TP);
550 }
551 break;
552
553 case SPEED_100:
554 if (cmd->duplex == DUPLEX_FULL) {
555 if (!(bp->port.supported[cfg_idx] &
556 SUPPORTED_100baseT_Full)) {
557 DP(BNX2X_MSG_ETHTOOL,
558 "100M full not supported\n");
559 return -EINVAL;
560 }
561
562 advertising = (ADVERTISED_100baseT_Full |
563 ADVERTISED_TP);
564 } else {
565 if (!(bp->port.supported[cfg_idx] &
566 SUPPORTED_100baseT_Half)) {
567 DP(BNX2X_MSG_ETHTOOL,
568 "100M half not supported\n");
569 return -EINVAL;
570 }
571
572 advertising = (ADVERTISED_100baseT_Half |
573 ADVERTISED_TP);
574 }
575 break;
576
577 case SPEED_1000:
578 if (cmd->duplex != DUPLEX_FULL) {
579 DP(BNX2X_MSG_ETHTOOL,
580 "1G half not supported\n");
581 return -EINVAL;
582 }
583
584 if (bp->port.supported[cfg_idx] &
585 SUPPORTED_1000baseT_Full) {
586 advertising = (ADVERTISED_1000baseT_Full |
587 ADVERTISED_TP);
588
589 } else if (bp->port.supported[cfg_idx] &
590 SUPPORTED_1000baseKX_Full) {
591 advertising = ADVERTISED_1000baseKX_Full;
592 } else {
593 DP(BNX2X_MSG_ETHTOOL,
594 "1G full not supported\n");
595 return -EINVAL;
596 }
597
598 break;
599
600 case SPEED_2500:
601 if (cmd->duplex != DUPLEX_FULL) {
602 DP(BNX2X_MSG_ETHTOOL,
603 "2.5G half not supported\n");
604 return -EINVAL;
605 }
606
607 if (!(bp->port.supported[cfg_idx]
608 & SUPPORTED_2500baseX_Full)) {
609 DP(BNX2X_MSG_ETHTOOL,
610 "2.5G full not supported\n");
611 return -EINVAL;
612 }
613
614 advertising = (ADVERTISED_2500baseX_Full |
615 ADVERTISED_TP);
616 break;
617
618 case SPEED_10000:
619 if (cmd->duplex != DUPLEX_FULL) {
620 DP(BNX2X_MSG_ETHTOOL,
621 "10G half not supported\n");
622 return -EINVAL;
623 }
624 phy_idx = bnx2x_get_cur_phy_idx(bp);
625 if ((bp->port.supported[cfg_idx] &
626 SUPPORTED_10000baseT_Full) &&
627 (bp->link_params.phy[phy_idx].media_type !=
628 ETH_PHY_SFP_1G_FIBER)) {
629 advertising = (ADVERTISED_10000baseT_Full |
630 ADVERTISED_FIBRE);
631 } else if (bp->port.supported[cfg_idx] &
632 SUPPORTED_10000baseKR_Full) {
633 advertising = (ADVERTISED_10000baseKR_Full |
634 ADVERTISED_FIBRE);
635 } else {
636 DP(BNX2X_MSG_ETHTOOL,
637 "10G full not supported\n");
638 return -EINVAL;
639 }
640
641 break;
642
643 default:
644 DP(BNX2X_MSG_ETHTOOL, "Unsupported speed %u\n", speed);
645 return -EINVAL;
646 }
647
648 bp->link_params.req_line_speed[cfg_idx] = speed;
649 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
650 bp->port.advertising[cfg_idx] = advertising;
651 }
652
653 DP(BNX2X_MSG_ETHTOOL, "req_line_speed %d\n"
654 " req_duplex %d advertising 0x%x\n",
655 bp->link_params.req_line_speed[cfg_idx],
656 bp->link_params.req_duplex[cfg_idx],
657 bp->port.advertising[cfg_idx]);
658
659
660 bp->link_params.multi_phy_config = new_multi_phy_config;
661 if (netif_running(dev)) {
662 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
663 bnx2x_force_link_reset(bp);
664 bnx2x_link_set(bp);
665 }
666
667 return 0;
668}
669
670#define DUMP_ALL_PRESETS 0x1FFF
671#define DUMP_MAX_PRESETS 13
672
673static int __bnx2x_get_preset_regs_len(struct bnx2x *bp, u32 preset)
674{
675 if (CHIP_IS_E1(bp))
676 return dump_num_registers[0][preset-1];
677 else if (CHIP_IS_E1H(bp))
678 return dump_num_registers[1][preset-1];
679 else if (CHIP_IS_E2(bp))
680 return dump_num_registers[2][preset-1];
681 else if (CHIP_IS_E3A0(bp))
682 return dump_num_registers[3][preset-1];
683 else if (CHIP_IS_E3B0(bp))
684 return dump_num_registers[4][preset-1];
685 else
686 return 0;
687}
688
689static int __bnx2x_get_regs_len(struct bnx2x *bp)
690{
691 u32 preset_idx;
692 int regdump_len = 0;
693
694
695 for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++)
696 regdump_len += __bnx2x_get_preset_regs_len(bp, preset_idx);
697
698 return regdump_len;
699}
700
701static int bnx2x_get_regs_len(struct net_device *dev)
702{
703 struct bnx2x *bp = netdev_priv(dev);
704 int regdump_len = 0;
705
706 if (IS_VF(bp))
707 return 0;
708
709 regdump_len = __bnx2x_get_regs_len(bp);
710 regdump_len *= 4;
711 regdump_len += sizeof(struct dump_header);
712
713 return regdump_len;
714}
715
716#define IS_E1_REG(chips) ((chips & DUMP_CHIP_E1) == DUMP_CHIP_E1)
717#define IS_E1H_REG(chips) ((chips & DUMP_CHIP_E1H) == DUMP_CHIP_E1H)
718#define IS_E2_REG(chips) ((chips & DUMP_CHIP_E2) == DUMP_CHIP_E2)
719#define IS_E3A0_REG(chips) ((chips & DUMP_CHIP_E3A0) == DUMP_CHIP_E3A0)
720#define IS_E3B0_REG(chips) ((chips & DUMP_CHIP_E3B0) == DUMP_CHIP_E3B0)
721
722#define IS_REG_IN_PRESET(presets, idx) \
723 ((presets & (1 << (idx-1))) == (1 << (idx-1)))
724
725
726static const u32 *__bnx2x_get_page_addr_ar(struct bnx2x *bp)
727{
728 if (CHIP_IS_E2(bp))
729 return page_vals_e2;
730 else if (CHIP_IS_E3(bp))
731 return page_vals_e3;
732 else
733 return NULL;
734}
735
736static u32 __bnx2x_get_page_reg_num(struct bnx2x *bp)
737{
738 if (CHIP_IS_E2(bp))
739 return PAGE_MODE_VALUES_E2;
740 else if (CHIP_IS_E3(bp))
741 return PAGE_MODE_VALUES_E3;
742 else
743 return 0;
744}
745
746static const u32 *__bnx2x_get_page_write_ar(struct bnx2x *bp)
747{
748 if (CHIP_IS_E2(bp))
749 return page_write_regs_e2;
750 else if (CHIP_IS_E3(bp))
751 return page_write_regs_e3;
752 else
753 return NULL;
754}
755
756static u32 __bnx2x_get_page_write_num(struct bnx2x *bp)
757{
758 if (CHIP_IS_E2(bp))
759 return PAGE_WRITE_REGS_E2;
760 else if (CHIP_IS_E3(bp))
761 return PAGE_WRITE_REGS_E3;
762 else
763 return 0;
764}
765
766static const struct reg_addr *__bnx2x_get_page_read_ar(struct bnx2x *bp)
767{
768 if (CHIP_IS_E2(bp))
769 return page_read_regs_e2;
770 else if (CHIP_IS_E3(bp))
771 return page_read_regs_e3;
772 else
773 return NULL;
774}
775
776static u32 __bnx2x_get_page_read_num(struct bnx2x *bp)
777{
778 if (CHIP_IS_E2(bp))
779 return PAGE_READ_REGS_E2;
780 else if (CHIP_IS_E3(bp))
781 return PAGE_READ_REGS_E3;
782 else
783 return 0;
784}
785
786static bool bnx2x_is_reg_in_chip(struct bnx2x *bp,
787 const struct reg_addr *reg_info)
788{
789 if (CHIP_IS_E1(bp))
790 return IS_E1_REG(reg_info->chips);
791 else if (CHIP_IS_E1H(bp))
792 return IS_E1H_REG(reg_info->chips);
793 else if (CHIP_IS_E2(bp))
794 return IS_E2_REG(reg_info->chips);
795 else if (CHIP_IS_E3A0(bp))
796 return IS_E3A0_REG(reg_info->chips);
797 else if (CHIP_IS_E3B0(bp))
798 return IS_E3B0_REG(reg_info->chips);
799 else
800 return false;
801}
802
803static bool bnx2x_is_wreg_in_chip(struct bnx2x *bp,
804 const struct wreg_addr *wreg_info)
805{
806 if (CHIP_IS_E1(bp))
807 return IS_E1_REG(wreg_info->chips);
808 else if (CHIP_IS_E1H(bp))
809 return IS_E1H_REG(wreg_info->chips);
810 else if (CHIP_IS_E2(bp))
811 return IS_E2_REG(wreg_info->chips);
812 else if (CHIP_IS_E3A0(bp))
813 return IS_E3A0_REG(wreg_info->chips);
814 else if (CHIP_IS_E3B0(bp))
815 return IS_E3B0_REG(wreg_info->chips);
816 else
817 return false;
818}
819
820
821
822
823
824
825
826
827
828
829
830
831static void bnx2x_read_pages_regs(struct bnx2x *bp, u32 *p, u32 preset)
832{
833 u32 i, j, k, n;
834
835
836 const u32 *page_addr = __bnx2x_get_page_addr_ar(bp);
837
838 int num_pages = __bnx2x_get_page_reg_num(bp);
839
840 const u32 *write_addr = __bnx2x_get_page_write_ar(bp);
841
842 int write_num = __bnx2x_get_page_write_num(bp);
843
844 const struct reg_addr *read_addr = __bnx2x_get_page_read_ar(bp);
845
846 int read_num = __bnx2x_get_page_read_num(bp);
847 u32 addr, size;
848
849 for (i = 0; i < num_pages; i++) {
850 for (j = 0; j < write_num; j++) {
851 REG_WR(bp, write_addr[j], page_addr[i]);
852
853 for (k = 0; k < read_num; k++) {
854 if (IS_REG_IN_PRESET(read_addr[k].presets,
855 preset)) {
856 size = read_addr[k].size;
857 for (n = 0; n < size; n++) {
858 addr = read_addr[k].addr + n*4;
859 *p++ = REG_RD(bp, addr);
860 }
861 }
862 }
863 }
864 }
865}
866
867static int __bnx2x_get_preset_regs(struct bnx2x *bp, u32 *p, u32 preset)
868{
869 u32 i, j, addr;
870 const struct wreg_addr *wreg_addr_p = NULL;
871
872 if (CHIP_IS_E1(bp))
873 wreg_addr_p = &wreg_addr_e1;
874 else if (CHIP_IS_E1H(bp))
875 wreg_addr_p = &wreg_addr_e1h;
876 else if (CHIP_IS_E2(bp))
877 wreg_addr_p = &wreg_addr_e2;
878 else if (CHIP_IS_E3A0(bp))
879 wreg_addr_p = &wreg_addr_e3;
880 else if (CHIP_IS_E3B0(bp))
881 wreg_addr_p = &wreg_addr_e3b0;
882
883
884 for (i = 0; i < IDLE_REGS_COUNT; i++) {
885 if (bnx2x_is_reg_in_chip(bp, &idle_reg_addrs[i]) &&
886 IS_REG_IN_PRESET(idle_reg_addrs[i].presets, preset)) {
887 for (j = 0; j < idle_reg_addrs[i].size; j++)
888 *p++ = REG_RD(bp, idle_reg_addrs[i].addr + j*4);
889 }
890 }
891
892
893 for (i = 0; i < REGS_COUNT; i++) {
894 if (bnx2x_is_reg_in_chip(bp, ®_addrs[i]) &&
895 IS_REG_IN_PRESET(reg_addrs[i].presets, preset)) {
896 for (j = 0; j < reg_addrs[i].size; j++)
897 *p++ = REG_RD(bp, reg_addrs[i].addr + j*4);
898 }
899 }
900
901
902 if (bnx2x_is_wreg_in_chip(bp, wreg_addr_p) &&
903 IS_REG_IN_PRESET(wreg_addr_p->presets, preset)) {
904 for (i = 0; i < wreg_addr_p->size; i++) {
905 *p++ = REG_RD(bp, wreg_addr_p->addr + i*4);
906
907
908
909
910 for (j = 0; j < wreg_addr_p->read_regs_count; j++) {
911 addr = *(wreg_addr_p->read_regs);
912 *p++ = REG_RD(bp, addr + j*4);
913 }
914 }
915 }
916
917
918 if (CHIP_IS_E2(bp) || CHIP_IS_E3(bp)) {
919
920 bnx2x_read_pages_regs(bp, p, preset);
921 }
922
923 return 0;
924}
925
926static void __bnx2x_get_regs(struct bnx2x *bp, u32 *p)
927{
928 u32 preset_idx;
929
930
931 for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++) {
932
933 if ((preset_idx == 2) ||
934 (preset_idx == 5) ||
935 (preset_idx == 8) ||
936 (preset_idx == 11))
937 continue;
938 __bnx2x_get_preset_regs(bp, p, preset_idx);
939 p += __bnx2x_get_preset_regs_len(bp, preset_idx);
940 }
941}
942
943static void bnx2x_get_regs(struct net_device *dev,
944 struct ethtool_regs *regs, void *_p)
945{
946 u32 *p = _p;
947 struct bnx2x *bp = netdev_priv(dev);
948 struct dump_header dump_hdr = {0};
949
950 regs->version = 2;
951 memset(p, 0, regs->len);
952
953 if (!netif_running(bp->dev))
954 return;
955
956
957
958
959
960
961 bnx2x_disable_blocks_parity(bp);
962
963 dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1;
964 dump_hdr.preset = DUMP_ALL_PRESETS;
965 dump_hdr.version = BNX2X_DUMP_VERSION;
966
967
968 if (CHIP_IS_E1(bp)) {
969 dump_hdr.dump_meta_data = DUMP_CHIP_E1;
970 } else if (CHIP_IS_E1H(bp)) {
971 dump_hdr.dump_meta_data = DUMP_CHIP_E1H;
972 } else if (CHIP_IS_E2(bp)) {
973 dump_hdr.dump_meta_data = DUMP_CHIP_E2 |
974 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
975 } else if (CHIP_IS_E3A0(bp)) {
976 dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 |
977 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
978 } else if (CHIP_IS_E3B0(bp)) {
979 dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 |
980 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
981 }
982
983 memcpy(p, &dump_hdr, sizeof(struct dump_header));
984 p += dump_hdr.header_size + 1;
985
986
987 __bnx2x_get_regs(bp, p);
988
989
990 bnx2x_clear_blocks_parity(bp);
991 bnx2x_enable_blocks_parity(bp);
992}
993
994static int bnx2x_get_preset_regs_len(struct net_device *dev, u32 preset)
995{
996 struct bnx2x *bp = netdev_priv(dev);
997 int regdump_len = 0;
998
999 regdump_len = __bnx2x_get_preset_regs_len(bp, preset);
1000 regdump_len *= 4;
1001 regdump_len += sizeof(struct dump_header);
1002
1003 return regdump_len;
1004}
1005
1006static int bnx2x_set_dump(struct net_device *dev, struct ethtool_dump *val)
1007{
1008 struct bnx2x *bp = netdev_priv(dev);
1009
1010
1011 if (val->flag < 1 || val->flag > DUMP_MAX_PRESETS)
1012 return -EINVAL;
1013
1014 bp->dump_preset_idx = val->flag;
1015 return 0;
1016}
1017
1018static int bnx2x_get_dump_flag(struct net_device *dev,
1019 struct ethtool_dump *dump)
1020{
1021 struct bnx2x *bp = netdev_priv(dev);
1022
1023 dump->version = BNX2X_DUMP_VERSION;
1024 dump->flag = bp->dump_preset_idx;
1025
1026 dump->len = bnx2x_get_preset_regs_len(dev, bp->dump_preset_idx);
1027 DP(BNX2X_MSG_ETHTOOL, "Get dump preset %d length=%d\n",
1028 bp->dump_preset_idx, dump->len);
1029 return 0;
1030}
1031
1032static int bnx2x_get_dump_data(struct net_device *dev,
1033 struct ethtool_dump *dump,
1034 void *buffer)
1035{
1036 u32 *p = buffer;
1037 struct bnx2x *bp = netdev_priv(dev);
1038 struct dump_header dump_hdr = {0};
1039
1040
1041
1042
1043
1044
1045 bnx2x_disable_blocks_parity(bp);
1046
1047 dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1;
1048 dump_hdr.preset = bp->dump_preset_idx;
1049 dump_hdr.version = BNX2X_DUMP_VERSION;
1050
1051 DP(BNX2X_MSG_ETHTOOL, "Get dump data of preset %d\n", dump_hdr.preset);
1052
1053
1054 if (CHIP_IS_E1(bp)) {
1055 dump_hdr.dump_meta_data = DUMP_CHIP_E1;
1056 } else if (CHIP_IS_E1H(bp)) {
1057 dump_hdr.dump_meta_data = DUMP_CHIP_E1H;
1058 } else if (CHIP_IS_E2(bp)) {
1059 dump_hdr.dump_meta_data = DUMP_CHIP_E2 |
1060 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1061 } else if (CHIP_IS_E3A0(bp)) {
1062 dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 |
1063 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1064 } else if (CHIP_IS_E3B0(bp)) {
1065 dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 |
1066 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1067 }
1068
1069 memcpy(p, &dump_hdr, sizeof(struct dump_header));
1070 p += dump_hdr.header_size + 1;
1071
1072
1073 __bnx2x_get_preset_regs(bp, p, dump_hdr.preset);
1074
1075
1076 bnx2x_clear_blocks_parity(bp);
1077 bnx2x_enable_blocks_parity(bp);
1078
1079 return 0;
1080}
1081
1082static void bnx2x_get_drvinfo(struct net_device *dev,
1083 struct ethtool_drvinfo *info)
1084{
1085 struct bnx2x *bp = netdev_priv(dev);
1086
1087 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
1088 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
1089
1090 bnx2x_fill_fw_str(bp, info->fw_version, sizeof(info->fw_version));
1091
1092 strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info));
1093}
1094
1095static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1096{
1097 struct bnx2x *bp = netdev_priv(dev);
1098
1099 if (bp->flags & NO_WOL_FLAG) {
1100 wol->supported = 0;
1101 wol->wolopts = 0;
1102 } else {
1103 wol->supported = WAKE_MAGIC;
1104 if (bp->wol)
1105 wol->wolopts = WAKE_MAGIC;
1106 else
1107 wol->wolopts = 0;
1108 }
1109 memset(&wol->sopass, 0, sizeof(wol->sopass));
1110}
1111
1112static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1113{
1114 struct bnx2x *bp = netdev_priv(dev);
1115
1116 if (wol->wolopts & ~WAKE_MAGIC) {
1117 DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n");
1118 return -EINVAL;
1119 }
1120
1121 if (wol->wolopts & WAKE_MAGIC) {
1122 if (bp->flags & NO_WOL_FLAG) {
1123 DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n");
1124 return -EINVAL;
1125 }
1126 bp->wol = 1;
1127 } else
1128 bp->wol = 0;
1129
1130 if (SHMEM2_HAS(bp, curr_cfg))
1131 SHMEM2_WR(bp, curr_cfg, CURR_CFG_MET_OS);
1132
1133 return 0;
1134}
1135
1136static u32 bnx2x_get_msglevel(struct net_device *dev)
1137{
1138 struct bnx2x *bp = netdev_priv(dev);
1139
1140 return bp->msg_enable;
1141}
1142
1143static void bnx2x_set_msglevel(struct net_device *dev, u32 level)
1144{
1145 struct bnx2x *bp = netdev_priv(dev);
1146
1147 if (capable(CAP_NET_ADMIN)) {
1148
1149 if (IS_PF(bp) && (level & BNX2X_MSG_MCP))
1150 bnx2x_fw_dump_lvl(bp, KERN_INFO);
1151 bp->msg_enable = level;
1152 }
1153}
1154
1155static int bnx2x_nway_reset(struct net_device *dev)
1156{
1157 struct bnx2x *bp = netdev_priv(dev);
1158
1159 if (!bp->port.pmf)
1160 return 0;
1161
1162 if (netif_running(dev)) {
1163 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1164 bnx2x_force_link_reset(bp);
1165 bnx2x_link_set(bp);
1166 }
1167
1168 return 0;
1169}
1170
1171static u32 bnx2x_get_link(struct net_device *dev)
1172{
1173 struct bnx2x *bp = netdev_priv(dev);
1174
1175 if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN))
1176 return 0;
1177
1178 if (IS_VF(bp))
1179 return !test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
1180 &bp->vf_link_vars.link_report_flags);
1181
1182 return bp->link_vars.link_up;
1183}
1184
1185static int bnx2x_get_eeprom_len(struct net_device *dev)
1186{
1187 struct bnx2x *bp = netdev_priv(dev);
1188
1189 return bp->common.flash_size;
1190}
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205static int bnx2x_acquire_nvram_lock(struct bnx2x *bp)
1206{
1207 int port = BP_PORT(bp);
1208 int count, i;
1209 u32 val;
1210
1211
1212 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
1213
1214
1215 count = BNX2X_NVRAM_TIMEOUT_COUNT;
1216 if (CHIP_REV_IS_SLOW(bp))
1217 count *= 100;
1218
1219
1220 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
1221 (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));
1222
1223 for (i = 0; i < count*10; i++) {
1224 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
1225 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))
1226 break;
1227
1228 udelay(5);
1229 }
1230
1231 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
1232 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1233 "cannot get access to nvram interface\n");
1234 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
1235 return -EBUSY;
1236 }
1237
1238 return 0;
1239}
1240
1241static int bnx2x_release_nvram_lock(struct bnx2x *bp)
1242{
1243 int port = BP_PORT(bp);
1244 int count, i;
1245 u32 val;
1246
1247
1248 count = BNX2X_NVRAM_TIMEOUT_COUNT;
1249 if (CHIP_REV_IS_SLOW(bp))
1250 count *= 100;
1251
1252
1253 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
1254 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));
1255
1256 for (i = 0; i < count*10; i++) {
1257 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
1258 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)))
1259 break;
1260
1261 udelay(5);
1262 }
1263
1264 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
1265 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1266 "cannot free access to nvram interface\n");
1267 return -EBUSY;
1268 }
1269
1270
1271 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
1272 return 0;
1273}
1274
1275static void bnx2x_enable_nvram_access(struct bnx2x *bp)
1276{
1277 u32 val;
1278
1279 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1280
1281
1282 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1283 (val | MCPR_NVM_ACCESS_ENABLE_EN |
1284 MCPR_NVM_ACCESS_ENABLE_WR_EN));
1285}
1286
1287static void bnx2x_disable_nvram_access(struct bnx2x *bp)
1288{
1289 u32 val;
1290
1291 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1292
1293
1294 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1295 (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
1296 MCPR_NVM_ACCESS_ENABLE_WR_EN)));
1297}
1298
1299static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val,
1300 u32 cmd_flags)
1301{
1302 int count, i, rc;
1303 u32 val;
1304
1305
1306 cmd_flags |= MCPR_NVM_COMMAND_DOIT;
1307
1308
1309 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1310
1311
1312 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1313 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1314
1315
1316 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1317
1318
1319 count = BNX2X_NVRAM_TIMEOUT_COUNT;
1320 if (CHIP_REV_IS_SLOW(bp))
1321 count *= 100;
1322
1323
1324 *ret_val = 0;
1325 rc = -EBUSY;
1326 for (i = 0; i < count; i++) {
1327 udelay(5);
1328 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1329
1330 if (val & MCPR_NVM_COMMAND_DONE) {
1331 val = REG_RD(bp, MCP_REG_MCPR_NVM_READ);
1332
1333
1334
1335
1336 *ret_val = cpu_to_be32(val);
1337 rc = 0;
1338 break;
1339 }
1340 }
1341 if (rc == -EBUSY)
1342 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1343 "nvram read timeout expired\n");
1344 return rc;
1345}
1346
1347int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf,
1348 int buf_size)
1349{
1350 int rc;
1351 u32 cmd_flags;
1352 __be32 val;
1353
1354 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1355 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1356 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
1357 offset, buf_size);
1358 return -EINVAL;
1359 }
1360
1361 if (offset + buf_size > bp->common.flash_size) {
1362 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1363 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
1364 offset, buf_size, bp->common.flash_size);
1365 return -EINVAL;
1366 }
1367
1368
1369 rc = bnx2x_acquire_nvram_lock(bp);
1370 if (rc)
1371 return rc;
1372
1373
1374 bnx2x_enable_nvram_access(bp);
1375
1376
1377 cmd_flags = MCPR_NVM_COMMAND_FIRST;
1378 while ((buf_size > sizeof(u32)) && (rc == 0)) {
1379 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1380 memcpy(ret_buf, &val, 4);
1381
1382
1383 offset += sizeof(u32);
1384 ret_buf += sizeof(u32);
1385 buf_size -= sizeof(u32);
1386 cmd_flags = 0;
1387 }
1388
1389 if (rc == 0) {
1390 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1391 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1392 memcpy(ret_buf, &val, 4);
1393 }
1394
1395
1396 bnx2x_disable_nvram_access(bp);
1397 bnx2x_release_nvram_lock(bp);
1398
1399 return rc;
1400}
1401
1402static int bnx2x_nvram_read32(struct bnx2x *bp, u32 offset, u32 *buf,
1403 int buf_size)
1404{
1405 int rc;
1406
1407 rc = bnx2x_nvram_read(bp, offset, (u8 *)buf, buf_size);
1408
1409 if (!rc) {
1410 __be32 *be = (__be32 *)buf;
1411
1412 while ((buf_size -= 4) >= 0)
1413 *buf++ = be32_to_cpu(*be++);
1414 }
1415
1416 return rc;
1417}
1418
1419static bool bnx2x_is_nvm_accessible(struct bnx2x *bp)
1420{
1421 int rc = 1;
1422 u16 pm = 0;
1423 struct net_device *dev = pci_get_drvdata(bp->pdev);
1424
1425 if (bp->pdev->pm_cap)
1426 rc = pci_read_config_word(bp->pdev,
1427 bp->pdev->pm_cap + PCI_PM_CTRL, &pm);
1428
1429 if ((rc && !netif_running(dev)) ||
1430 (!rc && ((pm & PCI_PM_CTRL_STATE_MASK) != (__force u16)PCI_D0)))
1431 return false;
1432
1433 return true;
1434}
1435
1436static int bnx2x_get_eeprom(struct net_device *dev,
1437 struct ethtool_eeprom *eeprom, u8 *eebuf)
1438{
1439 struct bnx2x *bp = netdev_priv(dev);
1440
1441 if (!bnx2x_is_nvm_accessible(bp)) {
1442 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1443 "cannot access eeprom when the interface is down\n");
1444 return -EAGAIN;
1445 }
1446
1447 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
1448 " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
1449 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1450 eeprom->len, eeprom->len);
1451
1452
1453
1454 return bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
1455}
1456
1457static int bnx2x_get_module_eeprom(struct net_device *dev,
1458 struct ethtool_eeprom *ee,
1459 u8 *data)
1460{
1461 struct bnx2x *bp = netdev_priv(dev);
1462 int rc = -EINVAL, phy_idx;
1463 u8 *user_data = data;
1464 unsigned int start_addr = ee->offset, xfer_size = 0;
1465
1466 if (!bnx2x_is_nvm_accessible(bp)) {
1467 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1468 "cannot access eeprom when the interface is down\n");
1469 return -EAGAIN;
1470 }
1471
1472 phy_idx = bnx2x_get_cur_phy_idx(bp);
1473
1474
1475 if (start_addr < ETH_MODULE_SFF_8079_LEN) {
1476
1477 if (start_addr + ee->len > ETH_MODULE_SFF_8079_LEN)
1478 xfer_size = ETH_MODULE_SFF_8079_LEN - start_addr;
1479 else
1480 xfer_size = ee->len;
1481 bnx2x_acquire_phy_lock(bp);
1482 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1483 &bp->link_params,
1484 I2C_DEV_ADDR_A0,
1485 start_addr,
1486 xfer_size,
1487 user_data);
1488 bnx2x_release_phy_lock(bp);
1489 if (rc) {
1490 DP(BNX2X_MSG_ETHTOOL, "Failed reading A0 section\n");
1491
1492 return -EINVAL;
1493 }
1494 user_data += xfer_size;
1495 start_addr += xfer_size;
1496 }
1497
1498
1499 if ((start_addr >= ETH_MODULE_SFF_8079_LEN) &&
1500 (start_addr < ETH_MODULE_SFF_8472_LEN)) {
1501 xfer_size = ee->len - xfer_size;
1502
1503 if (start_addr + xfer_size > ETH_MODULE_SFF_8472_LEN)
1504 xfer_size = ETH_MODULE_SFF_8472_LEN - start_addr;
1505 start_addr -= ETH_MODULE_SFF_8079_LEN;
1506 bnx2x_acquire_phy_lock(bp);
1507 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1508 &bp->link_params,
1509 I2C_DEV_ADDR_A2,
1510 start_addr,
1511 xfer_size,
1512 user_data);
1513 bnx2x_release_phy_lock(bp);
1514 if (rc) {
1515 DP(BNX2X_MSG_ETHTOOL, "Failed reading A2 section\n");
1516 return -EINVAL;
1517 }
1518 }
1519 return rc;
1520}
1521
1522static int bnx2x_get_module_info(struct net_device *dev,
1523 struct ethtool_modinfo *modinfo)
1524{
1525 struct bnx2x *bp = netdev_priv(dev);
1526 int phy_idx, rc;
1527 u8 sff8472_comp, diag_type;
1528
1529 if (!bnx2x_is_nvm_accessible(bp)) {
1530 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1531 "cannot access eeprom when the interface is down\n");
1532 return -EAGAIN;
1533 }
1534 phy_idx = bnx2x_get_cur_phy_idx(bp);
1535 bnx2x_acquire_phy_lock(bp);
1536 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1537 &bp->link_params,
1538 I2C_DEV_ADDR_A0,
1539 SFP_EEPROM_SFF_8472_COMP_ADDR,
1540 SFP_EEPROM_SFF_8472_COMP_SIZE,
1541 &sff8472_comp);
1542 bnx2x_release_phy_lock(bp);
1543 if (rc) {
1544 DP(BNX2X_MSG_ETHTOOL, "Failed reading SFF-8472 comp field\n");
1545 return -EINVAL;
1546 }
1547
1548 bnx2x_acquire_phy_lock(bp);
1549 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1550 &bp->link_params,
1551 I2C_DEV_ADDR_A0,
1552 SFP_EEPROM_DIAG_TYPE_ADDR,
1553 SFP_EEPROM_DIAG_TYPE_SIZE,
1554 &diag_type);
1555 bnx2x_release_phy_lock(bp);
1556 if (rc) {
1557 DP(BNX2X_MSG_ETHTOOL, "Failed reading Diag Type field\n");
1558 return -EINVAL;
1559 }
1560
1561 if (!sff8472_comp ||
1562 (diag_type & SFP_EEPROM_DIAG_ADDR_CHANGE_REQ)) {
1563 modinfo->type = ETH_MODULE_SFF_8079;
1564 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
1565 } else {
1566 modinfo->type = ETH_MODULE_SFF_8472;
1567 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
1568 }
1569 return 0;
1570}
1571
1572static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val,
1573 u32 cmd_flags)
1574{
1575 int count, i, rc;
1576
1577
1578 cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR;
1579
1580
1581 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1582
1583
1584 REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val);
1585
1586
1587 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1588 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1589
1590
1591 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1592
1593
1594 count = BNX2X_NVRAM_TIMEOUT_COUNT;
1595 if (CHIP_REV_IS_SLOW(bp))
1596 count *= 100;
1597
1598
1599 rc = -EBUSY;
1600 for (i = 0; i < count; i++) {
1601 udelay(5);
1602 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1603 if (val & MCPR_NVM_COMMAND_DONE) {
1604 rc = 0;
1605 break;
1606 }
1607 }
1608
1609 if (rc == -EBUSY)
1610 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1611 "nvram write timeout expired\n");
1612 return rc;
1613}
1614
1615#define BYTE_OFFSET(offset) (8 * (offset & 0x03))
1616
1617static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf,
1618 int buf_size)
1619{
1620 int rc;
1621 u32 cmd_flags, align_offset, val;
1622 __be32 val_be;
1623
1624 if (offset + buf_size > bp->common.flash_size) {
1625 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1626 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
1627 offset, buf_size, bp->common.flash_size);
1628 return -EINVAL;
1629 }
1630
1631
1632 rc = bnx2x_acquire_nvram_lock(bp);
1633 if (rc)
1634 return rc;
1635
1636
1637 bnx2x_enable_nvram_access(bp);
1638
1639 cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
1640 align_offset = (offset & ~0x03);
1641 rc = bnx2x_nvram_read_dword(bp, align_offset, &val_be, cmd_flags);
1642
1643 if (rc == 0) {
1644
1645
1646
1647 val = be32_to_cpu(val_be);
1648
1649 val &= ~le32_to_cpu((__force __le32)
1650 (0xff << BYTE_OFFSET(offset)));
1651 val |= le32_to_cpu((__force __le32)
1652 (*data_buf << BYTE_OFFSET(offset)));
1653
1654 rc = bnx2x_nvram_write_dword(bp, align_offset, val,
1655 cmd_flags);
1656 }
1657
1658
1659 bnx2x_disable_nvram_access(bp);
1660 bnx2x_release_nvram_lock(bp);
1661
1662 return rc;
1663}
1664
1665static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf,
1666 int buf_size)
1667{
1668 int rc;
1669 u32 cmd_flags;
1670 u32 val;
1671 u32 written_so_far;
1672
1673 if (buf_size == 1)
1674 return bnx2x_nvram_write1(bp, offset, data_buf, buf_size);
1675
1676 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1677 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1678 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
1679 offset, buf_size);
1680 return -EINVAL;
1681 }
1682
1683 if (offset + buf_size > bp->common.flash_size) {
1684 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1685 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
1686 offset, buf_size, bp->common.flash_size);
1687 return -EINVAL;
1688 }
1689
1690
1691 rc = bnx2x_acquire_nvram_lock(bp);
1692 if (rc)
1693 return rc;
1694
1695
1696 bnx2x_enable_nvram_access(bp);
1697
1698 written_so_far = 0;
1699 cmd_flags = MCPR_NVM_COMMAND_FIRST;
1700 while ((written_so_far < buf_size) && (rc == 0)) {
1701 if (written_so_far == (buf_size - sizeof(u32)))
1702 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1703 else if (((offset + 4) % BNX2X_NVRAM_PAGE_SIZE) == 0)
1704 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1705 else if ((offset % BNX2X_NVRAM_PAGE_SIZE) == 0)
1706 cmd_flags |= MCPR_NVM_COMMAND_FIRST;
1707
1708 memcpy(&val, data_buf, 4);
1709
1710
1711
1712
1713
1714
1715
1716 rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags);
1717
1718
1719 offset += sizeof(u32);
1720 data_buf += sizeof(u32);
1721 written_so_far += sizeof(u32);
1722
1723
1724
1725
1726 if ((cmd_flags & MCPR_NVM_COMMAND_LAST) &&
1727 (written_so_far < buf_size)) {
1728 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1729 "Releasing NVM lock after offset 0x%x\n",
1730 (u32)(offset - sizeof(u32)));
1731 bnx2x_release_nvram_lock(bp);
1732 usleep_range(1000, 2000);
1733 rc = bnx2x_acquire_nvram_lock(bp);
1734 if (rc)
1735 return rc;
1736 }
1737
1738 cmd_flags = 0;
1739 }
1740
1741
1742 bnx2x_disable_nvram_access(bp);
1743 bnx2x_release_nvram_lock(bp);
1744
1745 return rc;
1746}
1747
1748static int bnx2x_set_eeprom(struct net_device *dev,
1749 struct ethtool_eeprom *eeprom, u8 *eebuf)
1750{
1751 struct bnx2x *bp = netdev_priv(dev);
1752 int port = BP_PORT(bp);
1753 int rc = 0;
1754 u32 ext_phy_config;
1755
1756 if (!bnx2x_is_nvm_accessible(bp)) {
1757 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1758 "cannot access eeprom when the interface is down\n");
1759 return -EAGAIN;
1760 }
1761
1762 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
1763 " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
1764 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1765 eeprom->len, eeprom->len);
1766
1767
1768
1769
1770 if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) &&
1771 !bp->port.pmf) {
1772 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1773 "wrong magic or interface is not pmf\n");
1774 return -EINVAL;
1775 }
1776
1777 ext_phy_config =
1778 SHMEM_RD(bp,
1779 dev_info.port_hw_config[port].external_phy_config);
1780
1781 if (eeprom->magic == 0x50485950) {
1782
1783 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1784
1785 bnx2x_acquire_phy_lock(bp);
1786 rc |= bnx2x_link_reset(&bp->link_params,
1787 &bp->link_vars, 0);
1788 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
1789 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101)
1790 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1791 MISC_REGISTERS_GPIO_HIGH, port);
1792 bnx2x_release_phy_lock(bp);
1793 bnx2x_link_report(bp);
1794
1795 } else if (eeprom->magic == 0x50485952) {
1796
1797 if (bp->state == BNX2X_STATE_OPEN) {
1798 bnx2x_acquire_phy_lock(bp);
1799 rc |= bnx2x_link_reset(&bp->link_params,
1800 &bp->link_vars, 1);
1801
1802 rc |= bnx2x_phy_init(&bp->link_params,
1803 &bp->link_vars);
1804 bnx2x_release_phy_lock(bp);
1805 bnx2x_calc_fc_adv(bp);
1806 }
1807 } else if (eeprom->magic == 0x53985943) {
1808
1809 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
1810 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) {
1811
1812
1813 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1814 MISC_REGISTERS_GPIO_LOW, port);
1815
1816 bnx2x_acquire_phy_lock(bp);
1817
1818 bnx2x_sfx7101_sp_sw_reset(bp,
1819 &bp->link_params.phy[EXT_PHY1]);
1820
1821
1822 msleep(500);
1823 bnx2x_ext_phy_hw_reset(bp, port);
1824 msleep(500);
1825 bnx2x_release_phy_lock(bp);
1826 }
1827 } else
1828 rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
1829
1830 return rc;
1831}
1832
1833static int bnx2x_get_coalesce(struct net_device *dev,
1834 struct ethtool_coalesce *coal)
1835{
1836 struct bnx2x *bp = netdev_priv(dev);
1837
1838 memset(coal, 0, sizeof(struct ethtool_coalesce));
1839
1840 coal->rx_coalesce_usecs = bp->rx_ticks;
1841 coal->tx_coalesce_usecs = bp->tx_ticks;
1842
1843 return 0;
1844}
1845
1846static int bnx2x_set_coalesce(struct net_device *dev,
1847 struct ethtool_coalesce *coal)
1848{
1849 struct bnx2x *bp = netdev_priv(dev);
1850
1851 bp->rx_ticks = (u16)coal->rx_coalesce_usecs;
1852 if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT)
1853 bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT;
1854
1855 bp->tx_ticks = (u16)coal->tx_coalesce_usecs;
1856 if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT)
1857 bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT;
1858
1859 if (netif_running(dev))
1860 bnx2x_update_coalesce(bp);
1861
1862 return 0;
1863}
1864
1865static void bnx2x_get_ringparam(struct net_device *dev,
1866 struct ethtool_ringparam *ering)
1867{
1868 struct bnx2x *bp = netdev_priv(dev);
1869
1870 ering->rx_max_pending = MAX_RX_AVAIL;
1871
1872 if (bp->rx_ring_size)
1873 ering->rx_pending = bp->rx_ring_size;
1874 else
1875 ering->rx_pending = MAX_RX_AVAIL;
1876
1877 ering->tx_max_pending = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL;
1878 ering->tx_pending = bp->tx_ring_size;
1879}
1880
1881static int bnx2x_set_ringparam(struct net_device *dev,
1882 struct ethtool_ringparam *ering)
1883{
1884 struct bnx2x *bp = netdev_priv(dev);
1885
1886 DP(BNX2X_MSG_ETHTOOL,
1887 "set ring params command parameters: rx_pending = %d, tx_pending = %d\n",
1888 ering->rx_pending, ering->tx_pending);
1889
1890 if (pci_num_vf(bp->pdev)) {
1891 DP(BNX2X_MSG_IOV,
1892 "VFs are enabled, can not change ring parameters\n");
1893 return -EPERM;
1894 }
1895
1896 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
1897 DP(BNX2X_MSG_ETHTOOL,
1898 "Handling parity error recovery. Try again later\n");
1899 return -EAGAIN;
1900 }
1901
1902 if ((ering->rx_pending > MAX_RX_AVAIL) ||
1903 (ering->rx_pending < (bp->disable_tpa ? MIN_RX_SIZE_NONTPA :
1904 MIN_RX_SIZE_TPA)) ||
1905 (ering->tx_pending > (IS_MF_STORAGE_ONLY(bp) ? 0 : MAX_TX_AVAIL)) ||
1906 (ering->tx_pending <= MAX_SKB_FRAGS + 4)) {
1907 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
1908 return -EINVAL;
1909 }
1910
1911 bp->rx_ring_size = ering->rx_pending;
1912 bp->tx_ring_size = ering->tx_pending;
1913
1914 return bnx2x_reload_if_running(dev);
1915}
1916
1917static void bnx2x_get_pauseparam(struct net_device *dev,
1918 struct ethtool_pauseparam *epause)
1919{
1920 struct bnx2x *bp = netdev_priv(dev);
1921 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
1922 int cfg_reg;
1923
1924 epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] ==
1925 BNX2X_FLOW_CTRL_AUTO);
1926
1927 if (!epause->autoneg)
1928 cfg_reg = bp->link_params.req_flow_ctrl[cfg_idx];
1929 else
1930 cfg_reg = bp->link_params.req_fc_auto_adv;
1931
1932 epause->rx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_RX) ==
1933 BNX2X_FLOW_CTRL_RX);
1934 epause->tx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_TX) ==
1935 BNX2X_FLOW_CTRL_TX);
1936
1937 DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n"
1938 " autoneg %d rx_pause %d tx_pause %d\n",
1939 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1940}
1941
1942static int bnx2x_set_pauseparam(struct net_device *dev,
1943 struct ethtool_pauseparam *epause)
1944{
1945 struct bnx2x *bp = netdev_priv(dev);
1946 u32 cfg_idx = bnx2x_get_link_cfg_idx(bp);
1947 if (IS_MF(bp))
1948 return 0;
1949
1950 DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n"
1951 " autoneg %d rx_pause %d tx_pause %d\n",
1952 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1953
1954 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO;
1955
1956 if (epause->rx_pause)
1957 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX;
1958
1959 if (epause->tx_pause)
1960 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX;
1961
1962 if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO)
1963 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE;
1964
1965 if (epause->autoneg) {
1966 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
1967 DP(BNX2X_MSG_ETHTOOL, "autoneg not supported\n");
1968 return -EINVAL;
1969 }
1970
1971 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) {
1972 bp->link_params.req_flow_ctrl[cfg_idx] =
1973 BNX2X_FLOW_CTRL_AUTO;
1974 }
1975 bp->link_params.req_fc_auto_adv = 0;
1976 if (epause->rx_pause)
1977 bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_RX;
1978
1979 if (epause->tx_pause)
1980 bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_TX;
1981
1982 if (!bp->link_params.req_fc_auto_adv)
1983 bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_NONE;
1984 }
1985
1986 DP(BNX2X_MSG_ETHTOOL,
1987 "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]);
1988
1989 if (netif_running(dev)) {
1990 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1991 bnx2x_force_link_reset(bp);
1992 bnx2x_link_set(bp);
1993 }
1994
1995 return 0;
1996}
1997
1998static const char bnx2x_tests_str_arr[BNX2X_NUM_TESTS_SF][ETH_GSTRING_LEN] = {
1999 "register_test (offline) ",
2000 "memory_test (offline) ",
2001 "int_loopback_test (offline)",
2002 "ext_loopback_test (offline)",
2003 "nvram_test (online) ",
2004 "interrupt_test (online) ",
2005 "link_test (online) "
2006};
2007
2008enum {
2009 BNX2X_PRI_FLAG_ISCSI,
2010 BNX2X_PRI_FLAG_FCOE,
2011 BNX2X_PRI_FLAG_STORAGE,
2012 BNX2X_PRI_FLAG_LEN,
2013};
2014
2015static const char bnx2x_private_arr[BNX2X_PRI_FLAG_LEN][ETH_GSTRING_LEN] = {
2016 "iSCSI offload support",
2017 "FCoE offload support",
2018 "Storage only interface"
2019};
2020
2021static u32 bnx2x_eee_to_adv(u32 eee_adv)
2022{
2023 u32 modes = 0;
2024
2025 if (eee_adv & SHMEM_EEE_100M_ADV)
2026 modes |= ADVERTISED_100baseT_Full;
2027 if (eee_adv & SHMEM_EEE_1G_ADV)
2028 modes |= ADVERTISED_1000baseT_Full;
2029 if (eee_adv & SHMEM_EEE_10G_ADV)
2030 modes |= ADVERTISED_10000baseT_Full;
2031
2032 return modes;
2033}
2034
2035static u32 bnx2x_adv_to_eee(u32 modes, u32 shift)
2036{
2037 u32 eee_adv = 0;
2038 if (modes & ADVERTISED_100baseT_Full)
2039 eee_adv |= SHMEM_EEE_100M_ADV;
2040 if (modes & ADVERTISED_1000baseT_Full)
2041 eee_adv |= SHMEM_EEE_1G_ADV;
2042 if (modes & ADVERTISED_10000baseT_Full)
2043 eee_adv |= SHMEM_EEE_10G_ADV;
2044
2045 return eee_adv << shift;
2046}
2047
2048static int bnx2x_get_eee(struct net_device *dev, struct ethtool_eee *edata)
2049{
2050 struct bnx2x *bp = netdev_priv(dev);
2051 u32 eee_cfg;
2052
2053 if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) {
2054 DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n");
2055 return -EOPNOTSUPP;
2056 }
2057
2058 eee_cfg = bp->link_vars.eee_status;
2059
2060 edata->supported =
2061 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_SUPPORTED_MASK) >>
2062 SHMEM_EEE_SUPPORTED_SHIFT);
2063
2064 edata->advertised =
2065 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_ADV_STATUS_MASK) >>
2066 SHMEM_EEE_ADV_STATUS_SHIFT);
2067 edata->lp_advertised =
2068 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_LP_ADV_STATUS_MASK) >>
2069 SHMEM_EEE_LP_ADV_STATUS_SHIFT);
2070
2071
2072 edata->tx_lpi_timer = (eee_cfg & SHMEM_EEE_TIMER_MASK) << 4;
2073
2074 edata->eee_enabled = (eee_cfg & SHMEM_EEE_REQUESTED_BIT) ? 1 : 0;
2075 edata->eee_active = (eee_cfg & SHMEM_EEE_ACTIVE_BIT) ? 1 : 0;
2076 edata->tx_lpi_enabled = (eee_cfg & SHMEM_EEE_LPI_REQUESTED_BIT) ? 1 : 0;
2077
2078 return 0;
2079}
2080
2081static int bnx2x_set_eee(struct net_device *dev, struct ethtool_eee *edata)
2082{
2083 struct bnx2x *bp = netdev_priv(dev);
2084 u32 eee_cfg;
2085 u32 advertised;
2086
2087 if (IS_MF(bp))
2088 return 0;
2089
2090 if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) {
2091 DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n");
2092 return -EOPNOTSUPP;
2093 }
2094
2095 eee_cfg = bp->link_vars.eee_status;
2096
2097 if (!(eee_cfg & SHMEM_EEE_SUPPORTED_MASK)) {
2098 DP(BNX2X_MSG_ETHTOOL, "Board does not support EEE!\n");
2099 return -EOPNOTSUPP;
2100 }
2101
2102 advertised = bnx2x_adv_to_eee(edata->advertised,
2103 SHMEM_EEE_ADV_STATUS_SHIFT);
2104 if ((advertised != (eee_cfg & SHMEM_EEE_ADV_STATUS_MASK))) {
2105 DP(BNX2X_MSG_ETHTOOL,
2106 "Direct manipulation of EEE advertisement is not supported\n");
2107 return -EINVAL;
2108 }
2109
2110 if (edata->tx_lpi_timer > EEE_MODE_TIMER_MASK) {
2111 DP(BNX2X_MSG_ETHTOOL,
2112 "Maximal Tx Lpi timer supported is %x(u)\n",
2113 EEE_MODE_TIMER_MASK);
2114 return -EINVAL;
2115 }
2116 if (edata->tx_lpi_enabled &&
2117 (edata->tx_lpi_timer < EEE_MODE_NVRAM_AGGRESSIVE_TIME)) {
2118 DP(BNX2X_MSG_ETHTOOL,
2119 "Minimal Tx Lpi timer supported is %d(u)\n",
2120 EEE_MODE_NVRAM_AGGRESSIVE_TIME);
2121 return -EINVAL;
2122 }
2123
2124
2125 if (edata->eee_enabled)
2126 bp->link_params.eee_mode |= EEE_MODE_ADV_LPI;
2127 else
2128 bp->link_params.eee_mode &= ~EEE_MODE_ADV_LPI;
2129
2130 if (edata->tx_lpi_enabled)
2131 bp->link_params.eee_mode |= EEE_MODE_ENABLE_LPI;
2132 else
2133 bp->link_params.eee_mode &= ~EEE_MODE_ENABLE_LPI;
2134
2135 bp->link_params.eee_mode &= ~EEE_MODE_TIMER_MASK;
2136 bp->link_params.eee_mode |= (edata->tx_lpi_timer &
2137 EEE_MODE_TIMER_MASK) |
2138 EEE_MODE_OVERRIDE_NVRAM |
2139 EEE_MODE_OUTPUT_TIME;
2140
2141
2142 if (netif_running(dev)) {
2143 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2144 bnx2x_force_link_reset(bp);
2145 bnx2x_link_set(bp);
2146 }
2147
2148 return 0;
2149}
2150
2151enum {
2152 BNX2X_CHIP_E1_OFST = 0,
2153 BNX2X_CHIP_E1H_OFST,
2154 BNX2X_CHIP_E2_OFST,
2155 BNX2X_CHIP_E3_OFST,
2156 BNX2X_CHIP_E3B0_OFST,
2157 BNX2X_CHIP_MAX_OFST
2158};
2159
2160#define BNX2X_CHIP_MASK_E1 (1 << BNX2X_CHIP_E1_OFST)
2161#define BNX2X_CHIP_MASK_E1H (1 << BNX2X_CHIP_E1H_OFST)
2162#define BNX2X_CHIP_MASK_E2 (1 << BNX2X_CHIP_E2_OFST)
2163#define BNX2X_CHIP_MASK_E3 (1 << BNX2X_CHIP_E3_OFST)
2164#define BNX2X_CHIP_MASK_E3B0 (1 << BNX2X_CHIP_E3B0_OFST)
2165
2166#define BNX2X_CHIP_MASK_ALL ((1 << BNX2X_CHIP_MAX_OFST) - 1)
2167#define BNX2X_CHIP_MASK_E1X (BNX2X_CHIP_MASK_E1 | BNX2X_CHIP_MASK_E1H)
2168
2169static int bnx2x_test_registers(struct bnx2x *bp)
2170{
2171 int idx, i, rc = -ENODEV;
2172 u32 wr_val = 0, hw;
2173 int port = BP_PORT(bp);
2174 static const struct {
2175 u32 hw;
2176 u32 offset0;
2177 u32 offset1;
2178 u32 mask;
2179 } reg_tbl[] = {
2180 { BNX2X_CHIP_MASK_ALL,
2181 BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff },
2182 { BNX2X_CHIP_MASK_ALL,
2183 DORQ_REG_DB_ADDR0, 4, 0xffffffff },
2184 { BNX2X_CHIP_MASK_E1X,
2185 HC_REG_AGG_INT_0, 4, 0x000003ff },
2186 { BNX2X_CHIP_MASK_ALL,
2187 PBF_REG_MAC_IF0_ENABLE, 4, 0x00000001 },
2188 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2 | BNX2X_CHIP_MASK_E3,
2189 PBF_REG_P0_INIT_CRD, 4, 0x000007ff },
2190 { BNX2X_CHIP_MASK_E3B0,
2191 PBF_REG_INIT_CRD_Q0, 4, 0x000007ff },
2192 { BNX2X_CHIP_MASK_ALL,
2193 PRS_REG_CID_PORT_0, 4, 0x00ffffff },
2194 { BNX2X_CHIP_MASK_ALL,
2195 PXP2_REG_PSWRQ_CDU0_L2P, 4, 0x000fffff },
2196 { BNX2X_CHIP_MASK_ALL,
2197 PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
2198 { BNX2X_CHIP_MASK_ALL,
2199 PXP2_REG_PSWRQ_TM0_L2P, 4, 0x000fffff },
2200 { BNX2X_CHIP_MASK_ALL,
2201 PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
2202 { BNX2X_CHIP_MASK_ALL,
2203 PXP2_REG_PSWRQ_TSDM0_L2P, 4, 0x000fffff },
2204 { BNX2X_CHIP_MASK_ALL,
2205 QM_REG_CONNNUM_0, 4, 0x000fffff },
2206 { BNX2X_CHIP_MASK_ALL,
2207 TM_REG_LIN0_MAX_ACTIVE_CID, 4, 0x0003ffff },
2208 { BNX2X_CHIP_MASK_ALL,
2209 SRC_REG_KEYRSS0_0, 40, 0xffffffff },
2210 { BNX2X_CHIP_MASK_ALL,
2211 SRC_REG_KEYRSS0_7, 40, 0xffffffff },
2212 { BNX2X_CHIP_MASK_ALL,
2213 XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 },
2214 { BNX2X_CHIP_MASK_ALL,
2215 XCM_REG_WU_DA_CNT_CMD00, 4, 0x00000003 },
2216 { BNX2X_CHIP_MASK_ALL,
2217 XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 4, 0x000000ff },
2218 { BNX2X_CHIP_MASK_ALL,
2219 NIG_REG_LLH0_T_BIT, 4, 0x00000001 },
2220 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2221 NIG_REG_EMAC0_IN_EN, 4, 0x00000001 },
2222 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2223 NIG_REG_BMAC0_IN_EN, 4, 0x00000001 },
2224 { BNX2X_CHIP_MASK_ALL,
2225 NIG_REG_XCM0_OUT_EN, 4, 0x00000001 },
2226 { BNX2X_CHIP_MASK_ALL,
2227 NIG_REG_BRB0_OUT_EN, 4, 0x00000001 },
2228 { BNX2X_CHIP_MASK_ALL,
2229 NIG_REG_LLH0_XCM_MASK, 4, 0x00000007 },
2230 { BNX2X_CHIP_MASK_ALL,
2231 NIG_REG_LLH0_ACPI_PAT_6_LEN, 68, 0x000000ff },
2232 { BNX2X_CHIP_MASK_ALL,
2233 NIG_REG_LLH0_ACPI_PAT_0_CRC, 68, 0xffffffff },
2234 { BNX2X_CHIP_MASK_ALL,
2235 NIG_REG_LLH0_DEST_MAC_0_0, 160, 0xffffffff },
2236 { BNX2X_CHIP_MASK_ALL,
2237 NIG_REG_LLH0_DEST_IP_0_1, 160, 0xffffffff },
2238 { BNX2X_CHIP_MASK_ALL,
2239 NIG_REG_LLH0_IPV4_IPV6_0, 160, 0x00000001 },
2240 { BNX2X_CHIP_MASK_ALL,
2241 NIG_REG_LLH0_DEST_UDP_0, 160, 0x0000ffff },
2242 { BNX2X_CHIP_MASK_ALL,
2243 NIG_REG_LLH0_DEST_TCP_0, 160, 0x0000ffff },
2244 { BNX2X_CHIP_MASK_ALL,
2245 NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff },
2246 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2247 NIG_REG_XGXS_SERDES0_MODE_SEL, 4, 0x00000001 },
2248 { BNX2X_CHIP_MASK_ALL,
2249 NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001},
2250 { BNX2X_CHIP_MASK_ALL,
2251 NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff },
2252 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2253 NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 },
2254 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2255 NIG_REG_SERDES0_CTRL_PHY_ADDR, 16, 0x0000001f },
2256
2257 { BNX2X_CHIP_MASK_ALL, 0xffffffff, 0, 0x00000000 }
2258 };
2259
2260 if (!bnx2x_is_nvm_accessible(bp)) {
2261 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2262 "cannot access eeprom when the interface is down\n");
2263 return rc;
2264 }
2265
2266 if (CHIP_IS_E1(bp))
2267 hw = BNX2X_CHIP_MASK_E1;
2268 else if (CHIP_IS_E1H(bp))
2269 hw = BNX2X_CHIP_MASK_E1H;
2270 else if (CHIP_IS_E2(bp))
2271 hw = BNX2X_CHIP_MASK_E2;
2272 else if (CHIP_IS_E3B0(bp))
2273 hw = BNX2X_CHIP_MASK_E3B0;
2274 else
2275 hw = BNX2X_CHIP_MASK_E3;
2276
2277
2278
2279
2280 for (idx = 0; idx < 2; idx++) {
2281
2282 switch (idx) {
2283 case 0:
2284 wr_val = 0;
2285 break;
2286 case 1:
2287 wr_val = 0xffffffff;
2288 break;
2289 }
2290
2291 for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) {
2292 u32 offset, mask, save_val, val;
2293 if (!(hw & reg_tbl[i].hw))
2294 continue;
2295
2296 offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1;
2297 mask = reg_tbl[i].mask;
2298
2299 save_val = REG_RD(bp, offset);
2300
2301 REG_WR(bp, offset, wr_val & mask);
2302
2303 val = REG_RD(bp, offset);
2304
2305
2306 REG_WR(bp, offset, save_val);
2307
2308
2309 if ((val & mask) != (wr_val & mask)) {
2310 DP(BNX2X_MSG_ETHTOOL,
2311 "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n",
2312 offset, val, wr_val, mask);
2313 goto test_reg_exit;
2314 }
2315 }
2316 }
2317
2318 rc = 0;
2319
2320test_reg_exit:
2321 return rc;
2322}
2323
2324static int bnx2x_test_memory(struct bnx2x *bp)
2325{
2326 int i, j, rc = -ENODEV;
2327 u32 val, index;
2328 static const struct {
2329 u32 offset;
2330 int size;
2331 } mem_tbl[] = {
2332 { CCM_REG_XX_DESCR_TABLE, CCM_REG_XX_DESCR_TABLE_SIZE },
2333 { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE },
2334 { CFC_REG_LINK_LIST, CFC_REG_LINK_LIST_SIZE },
2335 { DMAE_REG_CMD_MEM, DMAE_REG_CMD_MEM_SIZE },
2336 { TCM_REG_XX_DESCR_TABLE, TCM_REG_XX_DESCR_TABLE_SIZE },
2337 { UCM_REG_XX_DESCR_TABLE, UCM_REG_XX_DESCR_TABLE_SIZE },
2338 { XCM_REG_XX_DESCR_TABLE, XCM_REG_XX_DESCR_TABLE_SIZE },
2339
2340 { 0xffffffff, 0 }
2341 };
2342
2343 static const struct {
2344 char *name;
2345 u32 offset;
2346 u32 hw_mask[BNX2X_CHIP_MAX_OFST];
2347 } prty_tbl[] = {
2348 { "CCM_PRTY_STS", CCM_REG_CCM_PRTY_STS,
2349 {0x3ffc0, 0, 0, 0} },
2350 { "CFC_PRTY_STS", CFC_REG_CFC_PRTY_STS,
2351 {0x2, 0x2, 0, 0} },
2352 { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS,
2353 {0, 0, 0, 0} },
2354 { "TCM_PRTY_STS", TCM_REG_TCM_PRTY_STS,
2355 {0x3ffc0, 0, 0, 0} },
2356 { "UCM_PRTY_STS", UCM_REG_UCM_PRTY_STS,
2357 {0x3ffc0, 0, 0, 0} },
2358 { "XCM_PRTY_STS", XCM_REG_XCM_PRTY_STS,
2359 {0x3ffc1, 0, 0, 0} },
2360
2361 { NULL, 0xffffffff, {0, 0, 0, 0} }
2362 };
2363
2364 if (!bnx2x_is_nvm_accessible(bp)) {
2365 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2366 "cannot access eeprom when the interface is down\n");
2367 return rc;
2368 }
2369
2370 if (CHIP_IS_E1(bp))
2371 index = BNX2X_CHIP_E1_OFST;
2372 else if (CHIP_IS_E1H(bp))
2373 index = BNX2X_CHIP_E1H_OFST;
2374 else if (CHIP_IS_E2(bp))
2375 index = BNX2X_CHIP_E2_OFST;
2376 else
2377 index = BNX2X_CHIP_E3_OFST;
2378
2379
2380 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
2381 val = REG_RD(bp, prty_tbl[i].offset);
2382 if (val & ~(prty_tbl[i].hw_mask[index])) {
2383 DP(BNX2X_MSG_ETHTOOL,
2384 "%s is 0x%x\n", prty_tbl[i].name, val);
2385 goto test_mem_exit;
2386 }
2387 }
2388
2389
2390 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++)
2391 for (j = 0; j < mem_tbl[i].size; j++)
2392 REG_RD(bp, mem_tbl[i].offset + j*4);
2393
2394
2395 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
2396 val = REG_RD(bp, prty_tbl[i].offset);
2397 if (val & ~(prty_tbl[i].hw_mask[index])) {
2398 DP(BNX2X_MSG_ETHTOOL,
2399 "%s is 0x%x\n", prty_tbl[i].name, val);
2400 goto test_mem_exit;
2401 }
2402 }
2403
2404 rc = 0;
2405
2406test_mem_exit:
2407 return rc;
2408}
2409
2410static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes)
2411{
2412 int cnt = 1400;
2413
2414 if (link_up) {
2415 while (bnx2x_link_test(bp, is_serdes) && cnt--)
2416 msleep(20);
2417
2418 if (cnt <= 0 && bnx2x_link_test(bp, is_serdes))
2419 DP(BNX2X_MSG_ETHTOOL, "Timeout waiting for link up\n");
2420
2421 cnt = 1400;
2422 while (!bp->link_vars.link_up && cnt--)
2423 msleep(20);
2424
2425 if (cnt <= 0 && !bp->link_vars.link_up)
2426 DP(BNX2X_MSG_ETHTOOL,
2427 "Timeout waiting for link init\n");
2428 }
2429}
2430
2431static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode)
2432{
2433 unsigned int pkt_size, num_pkts, i;
2434 struct sk_buff *skb;
2435 unsigned char *packet;
2436 struct bnx2x_fastpath *fp_rx = &bp->fp[0];
2437 struct bnx2x_fastpath *fp_tx = &bp->fp[0];
2438 struct bnx2x_fp_txdata *txdata = fp_tx->txdata_ptr[0];
2439 u16 tx_start_idx, tx_idx;
2440 u16 rx_start_idx, rx_idx;
2441 u16 pkt_prod, bd_prod;
2442 struct sw_tx_bd *tx_buf;
2443 struct eth_tx_start_bd *tx_start_bd;
2444 dma_addr_t mapping;
2445 union eth_rx_cqe *cqe;
2446 u8 cqe_fp_flags, cqe_fp_type;
2447 struct sw_rx_bd *rx_buf;
2448 u16 len;
2449 int rc = -ENODEV;
2450 u8 *data;
2451 struct netdev_queue *txq = netdev_get_tx_queue(bp->dev,
2452 txdata->txq_index);
2453
2454
2455 switch (loopback_mode) {
2456 case BNX2X_PHY_LOOPBACK:
2457 if (bp->link_params.loopback_mode != LOOPBACK_XGXS) {
2458 DP(BNX2X_MSG_ETHTOOL, "PHY loopback not supported\n");
2459 return -EINVAL;
2460 }
2461 break;
2462 case BNX2X_MAC_LOOPBACK:
2463 if (CHIP_IS_E3(bp)) {
2464 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
2465 if (bp->port.supported[cfg_idx] &
2466 (SUPPORTED_10000baseT_Full |
2467 SUPPORTED_20000baseMLD2_Full |
2468 SUPPORTED_20000baseKR2_Full))
2469 bp->link_params.loopback_mode = LOOPBACK_XMAC;
2470 else
2471 bp->link_params.loopback_mode = LOOPBACK_UMAC;
2472 } else
2473 bp->link_params.loopback_mode = LOOPBACK_BMAC;
2474
2475 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2476 break;
2477 case BNX2X_EXT_LOOPBACK:
2478 if (bp->link_params.loopback_mode != LOOPBACK_EXT) {
2479 DP(BNX2X_MSG_ETHTOOL,
2480 "Can't configure external loopback\n");
2481 return -EINVAL;
2482 }
2483 break;
2484 default:
2485 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
2486 return -EINVAL;
2487 }
2488
2489
2490 pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ?
2491 bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN);
2492 skb = netdev_alloc_skb(bp->dev, fp_rx->rx_buf_size);
2493 if (!skb) {
2494 DP(BNX2X_MSG_ETHTOOL, "Can't allocate skb\n");
2495 rc = -ENOMEM;
2496 goto test_loopback_exit;
2497 }
2498 packet = skb_put(skb, pkt_size);
2499 memcpy(packet, bp->dev->dev_addr, ETH_ALEN);
2500 eth_zero_addr(packet + ETH_ALEN);
2501 memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN));
2502 for (i = ETH_HLEN; i < pkt_size; i++)
2503 packet[i] = (unsigned char) (i & 0xff);
2504 mapping = dma_map_single(&bp->pdev->dev, skb->data,
2505 skb_headlen(skb), DMA_TO_DEVICE);
2506 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
2507 rc = -ENOMEM;
2508 dev_kfree_skb(skb);
2509 DP(BNX2X_MSG_ETHTOOL, "Unable to map SKB\n");
2510 goto test_loopback_exit;
2511 }
2512
2513
2514 num_pkts = 0;
2515 tx_start_idx = le16_to_cpu(*txdata->tx_cons_sb);
2516 rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
2517
2518 netdev_tx_sent_queue(txq, skb->len);
2519
2520 pkt_prod = txdata->tx_pkt_prod++;
2521 tx_buf = &txdata->tx_buf_ring[TX_BD(pkt_prod)];
2522 tx_buf->first_bd = txdata->tx_bd_prod;
2523 tx_buf->skb = skb;
2524 tx_buf->flags = 0;
2525
2526 bd_prod = TX_BD(txdata->tx_bd_prod);
2527 tx_start_bd = &txdata->tx_desc_ring[bd_prod].start_bd;
2528 tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
2529 tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
2530 tx_start_bd->nbd = cpu_to_le16(2);
2531 tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb));
2532 tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod);
2533 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
2534 SET_FLAG(tx_start_bd->general_data,
2535 ETH_TX_START_BD_HDR_NBDS,
2536 1);
2537 SET_FLAG(tx_start_bd->general_data,
2538 ETH_TX_START_BD_PARSE_NBDS,
2539 0);
2540
2541
2542 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
2543
2544 if (CHIP_IS_E1x(bp)) {
2545 u16 global_data = 0;
2546 struct eth_tx_parse_bd_e1x *pbd_e1x =
2547 &txdata->tx_desc_ring[bd_prod].parse_bd_e1x;
2548 memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
2549 SET_FLAG(global_data,
2550 ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE, UNICAST_ADDRESS);
2551 pbd_e1x->global_data = cpu_to_le16(global_data);
2552 } else {
2553 u32 parsing_data = 0;
2554 struct eth_tx_parse_bd_e2 *pbd_e2 =
2555 &txdata->tx_desc_ring[bd_prod].parse_bd_e2;
2556 memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2));
2557 SET_FLAG(parsing_data,
2558 ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE, UNICAST_ADDRESS);
2559 pbd_e2->parsing_data = cpu_to_le32(parsing_data);
2560 }
2561 wmb();
2562
2563 txdata->tx_db.data.prod += 2;
2564 barrier();
2565 DOORBELL(bp, txdata->cid, txdata->tx_db.raw);
2566
2567 mmiowb();
2568 barrier();
2569
2570 num_pkts++;
2571 txdata->tx_bd_prod += 2;
2572
2573 udelay(100);
2574
2575 tx_idx = le16_to_cpu(*txdata->tx_cons_sb);
2576 if (tx_idx != tx_start_idx + num_pkts)
2577 goto test_loopback_exit;
2578
2579
2580
2581
2582
2583 if (bp->common.int_block == INT_BLOCK_IGU) {
2584
2585
2586
2587
2588 local_bh_disable();
2589 bnx2x_tx_int(bp, txdata);
2590 local_bh_enable();
2591 }
2592
2593 rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
2594 if (rx_idx != rx_start_idx + num_pkts)
2595 goto test_loopback_exit;
2596
2597 cqe = &fp_rx->rx_comp_ring[RCQ_BD(fp_rx->rx_comp_cons)];
2598 cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
2599 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
2600 if (!CQE_TYPE_FAST(cqe_fp_type) || (cqe_fp_flags & ETH_RX_ERROR_FALGS))
2601 goto test_loopback_rx_exit;
2602
2603 len = le16_to_cpu(cqe->fast_path_cqe.pkt_len_or_gro_seg_len);
2604 if (len != pkt_size)
2605 goto test_loopback_rx_exit;
2606
2607 rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)];
2608 dma_sync_single_for_cpu(&bp->pdev->dev,
2609 dma_unmap_addr(rx_buf, mapping),
2610 fp_rx->rx_buf_size, DMA_FROM_DEVICE);
2611 data = rx_buf->data + NET_SKB_PAD + cqe->fast_path_cqe.placement_offset;
2612 for (i = ETH_HLEN; i < pkt_size; i++)
2613 if (*(data + i) != (unsigned char) (i & 0xff))
2614 goto test_loopback_rx_exit;
2615
2616 rc = 0;
2617
2618test_loopback_rx_exit:
2619
2620 fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons);
2621 fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod);
2622 fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons);
2623 fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod);
2624
2625
2626 bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod,
2627 fp_rx->rx_sge_prod);
2628
2629test_loopback_exit:
2630 bp->link_params.loopback_mode = LOOPBACK_NONE;
2631
2632 return rc;
2633}
2634
2635static int bnx2x_test_loopback(struct bnx2x *bp)
2636{
2637 int rc = 0, res;
2638
2639 if (BP_NOMCP(bp))
2640 return rc;
2641
2642 if (!netif_running(bp->dev))
2643 return BNX2X_LOOPBACK_FAILED;
2644
2645 bnx2x_netif_stop(bp, 1);
2646 bnx2x_acquire_phy_lock(bp);
2647
2648 res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK);
2649 if (res) {
2650 DP(BNX2X_MSG_ETHTOOL, " PHY loopback failed (res %d)\n", res);
2651 rc |= BNX2X_PHY_LOOPBACK_FAILED;
2652 }
2653
2654 res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK);
2655 if (res) {
2656 DP(BNX2X_MSG_ETHTOOL, " MAC loopback failed (res %d)\n", res);
2657 rc |= BNX2X_MAC_LOOPBACK_FAILED;
2658 }
2659
2660 bnx2x_release_phy_lock(bp);
2661 bnx2x_netif_start(bp);
2662
2663 return rc;
2664}
2665
2666static int bnx2x_test_ext_loopback(struct bnx2x *bp)
2667{
2668 int rc;
2669 u8 is_serdes =
2670 (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
2671
2672 if (BP_NOMCP(bp))
2673 return -ENODEV;
2674
2675 if (!netif_running(bp->dev))
2676 return BNX2X_EXT_LOOPBACK_FAILED;
2677
2678 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
2679 rc = bnx2x_nic_load(bp, LOAD_LOOPBACK_EXT);
2680 if (rc) {
2681 DP(BNX2X_MSG_ETHTOOL,
2682 "Can't perform self-test, nic_load (for external lb) failed\n");
2683 return -ENODEV;
2684 }
2685 bnx2x_wait_for_link(bp, 1, is_serdes);
2686
2687 bnx2x_netif_stop(bp, 1);
2688
2689 rc = bnx2x_run_loopback(bp, BNX2X_EXT_LOOPBACK);
2690 if (rc)
2691 DP(BNX2X_MSG_ETHTOOL, "EXT loopback failed (res %d)\n", rc);
2692
2693 bnx2x_netif_start(bp);
2694
2695 return rc;
2696}
2697
2698struct code_entry {
2699 u32 sram_start_addr;
2700 u32 code_attribute;
2701#define CODE_IMAGE_TYPE_MASK 0xf0800003
2702#define CODE_IMAGE_VNTAG_PROFILES_DATA 0xd0000003
2703#define CODE_IMAGE_LENGTH_MASK 0x007ffffc
2704#define CODE_IMAGE_TYPE_EXTENDED_DIR 0xe0000000
2705 u32 nvm_start_addr;
2706};
2707
2708#define CODE_ENTRY_MAX 16
2709#define CODE_ENTRY_EXTENDED_DIR_IDX 15
2710#define MAX_IMAGES_IN_EXTENDED_DIR 64
2711#define NVRAM_DIR_OFFSET 0x14
2712
2713#define EXTENDED_DIR_EXISTS(code) \
2714 ((code & CODE_IMAGE_TYPE_MASK) == CODE_IMAGE_TYPE_EXTENDED_DIR && \
2715 (code & CODE_IMAGE_LENGTH_MASK) != 0)
2716
2717#define CRC32_RESIDUAL 0xdebb20e3
2718#define CRC_BUFF_SIZE 256
2719
2720static int bnx2x_nvram_crc(struct bnx2x *bp,
2721 int offset,
2722 int size,
2723 u8 *buff)
2724{
2725 u32 crc = ~0;
2726 int rc = 0, done = 0;
2727
2728 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2729 "NVRAM CRC from 0x%08x to 0x%08x\n", offset, offset + size);
2730
2731 while (done < size) {
2732 int count = min_t(int, size - done, CRC_BUFF_SIZE);
2733
2734 rc = bnx2x_nvram_read(bp, offset + done, buff, count);
2735
2736 if (rc)
2737 return rc;
2738
2739 crc = crc32_le(crc, buff, count);
2740 done += count;
2741 }
2742
2743 if (crc != CRC32_RESIDUAL)
2744 rc = -EINVAL;
2745
2746 return rc;
2747}
2748
2749static int bnx2x_test_nvram_dir(struct bnx2x *bp,
2750 struct code_entry *entry,
2751 u8 *buff)
2752{
2753 size_t size = entry->code_attribute & CODE_IMAGE_LENGTH_MASK;
2754 u32 type = entry->code_attribute & CODE_IMAGE_TYPE_MASK;
2755 int rc;
2756
2757
2758 if (size == 0 || type == CODE_IMAGE_VNTAG_PROFILES_DATA)
2759 return 0;
2760
2761 rc = bnx2x_nvram_crc(bp, entry->nvm_start_addr, size, buff);
2762 if (rc)
2763 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2764 "image %x has failed crc test (rc %d)\n", type, rc);
2765
2766 return rc;
2767}
2768
2769static int bnx2x_test_dir_entry(struct bnx2x *bp, u32 addr, u8 *buff)
2770{
2771 int rc;
2772 struct code_entry entry;
2773
2774 rc = bnx2x_nvram_read32(bp, addr, (u32 *)&entry, sizeof(entry));
2775 if (rc)
2776 return rc;
2777
2778 return bnx2x_test_nvram_dir(bp, &entry, buff);
2779}
2780
2781static int bnx2x_test_nvram_ext_dirs(struct bnx2x *bp, u8 *buff)
2782{
2783 u32 rc, cnt, dir_offset = NVRAM_DIR_OFFSET;
2784 struct code_entry entry;
2785 int i;
2786
2787 rc = bnx2x_nvram_read32(bp,
2788 dir_offset +
2789 sizeof(entry) * CODE_ENTRY_EXTENDED_DIR_IDX,
2790 (u32 *)&entry, sizeof(entry));
2791 if (rc)
2792 return rc;
2793
2794 if (!EXTENDED_DIR_EXISTS(entry.code_attribute))
2795 return 0;
2796
2797 rc = bnx2x_nvram_read32(bp, entry.nvm_start_addr,
2798 &cnt, sizeof(u32));
2799 if (rc)
2800 return rc;
2801
2802 dir_offset = entry.nvm_start_addr + 8;
2803
2804 for (i = 0; i < cnt && i < MAX_IMAGES_IN_EXTENDED_DIR; i++) {
2805 rc = bnx2x_test_dir_entry(bp, dir_offset +
2806 sizeof(struct code_entry) * i,
2807 buff);
2808 if (rc)
2809 return rc;
2810 }
2811
2812 return 0;
2813}
2814
2815static int bnx2x_test_nvram_dirs(struct bnx2x *bp, u8 *buff)
2816{
2817 u32 rc, dir_offset = NVRAM_DIR_OFFSET;
2818 int i;
2819
2820 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "NVRAM DIRS CRC test-set\n");
2821
2822 for (i = 0; i < CODE_ENTRY_EXTENDED_DIR_IDX; i++) {
2823 rc = bnx2x_test_dir_entry(bp, dir_offset +
2824 sizeof(struct code_entry) * i,
2825 buff);
2826 if (rc)
2827 return rc;
2828 }
2829
2830 return bnx2x_test_nvram_ext_dirs(bp, buff);
2831}
2832
2833struct crc_pair {
2834 int offset;
2835 int size;
2836};
2837
2838static int bnx2x_test_nvram_tbl(struct bnx2x *bp,
2839 const struct crc_pair *nvram_tbl, u8 *buf)
2840{
2841 int i;
2842
2843 for (i = 0; nvram_tbl[i].size; i++) {
2844 int rc = bnx2x_nvram_crc(bp, nvram_tbl[i].offset,
2845 nvram_tbl[i].size, buf);
2846 if (rc) {
2847 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2848 "nvram_tbl[%d] has failed crc test (rc %d)\n",
2849 i, rc);
2850 return rc;
2851 }
2852 }
2853
2854 return 0;
2855}
2856
2857static int bnx2x_test_nvram(struct bnx2x *bp)
2858{
2859 const struct crc_pair nvram_tbl[] = {
2860 { 0, 0x14 },
2861 { 0x14, 0xec },
2862 { 0x100, 0x350 },
2863 { 0x450, 0xf0 },
2864 { 0x640, 0x64 },
2865 { 0x708, 0x70 },
2866 { 0, 0 }
2867 };
2868 const struct crc_pair nvram_tbl2[] = {
2869 { 0x7e8, 0x350 },
2870 { 0xb38, 0xf0 },
2871 { 0, 0 }
2872 };
2873
2874 u8 *buf;
2875 int rc;
2876 u32 magic;
2877
2878 if (BP_NOMCP(bp))
2879 return 0;
2880
2881 buf = kmalloc(CRC_BUFF_SIZE, GFP_KERNEL);
2882 if (!buf) {
2883 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "kmalloc failed\n");
2884 rc = -ENOMEM;
2885 goto test_nvram_exit;
2886 }
2887
2888 rc = bnx2x_nvram_read32(bp, 0, &magic, sizeof(magic));
2889 if (rc) {
2890 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2891 "magic value read (rc %d)\n", rc);
2892 goto test_nvram_exit;
2893 }
2894
2895 if (magic != 0x669955aa) {
2896 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2897 "wrong magic value (0x%08x)\n", magic);
2898 rc = -ENODEV;
2899 goto test_nvram_exit;
2900 }
2901
2902 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "Port 0 CRC test-set\n");
2903 rc = bnx2x_test_nvram_tbl(bp, nvram_tbl, buf);
2904 if (rc)
2905 goto test_nvram_exit;
2906
2907 if (!CHIP_IS_E1x(bp) && !CHIP_IS_57811xx(bp)) {
2908 u32 hide = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
2909 SHARED_HW_CFG_HIDE_PORT1;
2910
2911 if (!hide) {
2912 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2913 "Port 1 CRC test-set\n");
2914 rc = bnx2x_test_nvram_tbl(bp, nvram_tbl2, buf);
2915 if (rc)
2916 goto test_nvram_exit;
2917 }
2918 }
2919
2920 rc = bnx2x_test_nvram_dirs(bp, buf);
2921
2922test_nvram_exit:
2923 kfree(buf);
2924 return rc;
2925}
2926
2927
2928static int bnx2x_test_intr(struct bnx2x *bp)
2929{
2930 struct bnx2x_queue_state_params params = {NULL};
2931
2932 if (!netif_running(bp->dev)) {
2933 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2934 "cannot access eeprom when the interface is down\n");
2935 return -ENODEV;
2936 }
2937
2938 params.q_obj = &bp->sp_objs->q_obj;
2939 params.cmd = BNX2X_Q_CMD_EMPTY;
2940
2941 __set_bit(RAMROD_COMP_WAIT, ¶ms.ramrod_flags);
2942
2943 return bnx2x_queue_state_change(bp, ¶ms);
2944}
2945
2946static void bnx2x_self_test(struct net_device *dev,
2947 struct ethtool_test *etest, u64 *buf)
2948{
2949 struct bnx2x *bp = netdev_priv(dev);
2950 u8 is_serdes, link_up;
2951 int rc, cnt = 0;
2952
2953 if (pci_num_vf(bp->pdev)) {
2954 DP(BNX2X_MSG_IOV,
2955 "VFs are enabled, can not perform self test\n");
2956 return;
2957 }
2958
2959 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
2960 netdev_err(bp->dev,
2961 "Handling parity error recovery. Try again later\n");
2962 etest->flags |= ETH_TEST_FL_FAILED;
2963 return;
2964 }
2965
2966 DP(BNX2X_MSG_ETHTOOL,
2967 "Self-test command parameters: offline = %d, external_lb = %d\n",
2968 (etest->flags & ETH_TEST_FL_OFFLINE),
2969 (etest->flags & ETH_TEST_FL_EXTERNAL_LB)>>2);
2970
2971 memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS(bp));
2972
2973 if (bnx2x_test_nvram(bp) != 0) {
2974 if (!IS_MF(bp))
2975 buf[4] = 1;
2976 else
2977 buf[0] = 1;
2978 etest->flags |= ETH_TEST_FL_FAILED;
2979 }
2980
2981 if (!netif_running(dev)) {
2982 DP(BNX2X_MSG_ETHTOOL, "Interface is down\n");
2983 return;
2984 }
2985
2986 is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
2987 link_up = bp->link_vars.link_up;
2988
2989 if ((etest->flags & ETH_TEST_FL_OFFLINE) && !IS_MF(bp)) {
2990 int port = BP_PORT(bp);
2991 u32 val;
2992
2993
2994 val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4);
2995
2996 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0);
2997
2998 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
2999 rc = bnx2x_nic_load(bp, LOAD_DIAG);
3000 if (rc) {
3001 etest->flags |= ETH_TEST_FL_FAILED;
3002 DP(BNX2X_MSG_ETHTOOL,
3003 "Can't perform self-test, nic_load (for offline) failed\n");
3004 return;
3005 }
3006
3007
3008 bnx2x_wait_for_link(bp, 1, is_serdes);
3009
3010 if (bnx2x_test_registers(bp) != 0) {
3011 buf[0] = 1;
3012 etest->flags |= ETH_TEST_FL_FAILED;
3013 }
3014 if (bnx2x_test_memory(bp) != 0) {
3015 buf[1] = 1;
3016 etest->flags |= ETH_TEST_FL_FAILED;
3017 }
3018
3019 buf[2] = bnx2x_test_loopback(bp);
3020 if (buf[2] != 0)
3021 etest->flags |= ETH_TEST_FL_FAILED;
3022
3023 if (etest->flags & ETH_TEST_FL_EXTERNAL_LB) {
3024 buf[3] = bnx2x_test_ext_loopback(bp);
3025 if (buf[3] != 0)
3026 etest->flags |= ETH_TEST_FL_FAILED;
3027 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
3028 }
3029
3030 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
3031
3032
3033 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val);
3034 rc = bnx2x_nic_load(bp, LOAD_NORMAL);
3035 if (rc) {
3036 etest->flags |= ETH_TEST_FL_FAILED;
3037 DP(BNX2X_MSG_ETHTOOL,
3038 "Can't perform self-test, nic_load (for online) failed\n");
3039 return;
3040 }
3041
3042 bnx2x_wait_for_link(bp, link_up, is_serdes);
3043 }
3044
3045 if (bnx2x_test_intr(bp) != 0) {
3046 if (!IS_MF(bp))
3047 buf[5] = 1;
3048 else
3049 buf[1] = 1;
3050 etest->flags |= ETH_TEST_FL_FAILED;
3051 }
3052
3053 if (link_up) {
3054 cnt = 100;
3055 while (bnx2x_link_test(bp, is_serdes) && --cnt)
3056 msleep(20);
3057 }
3058
3059 if (!cnt) {
3060 if (!IS_MF(bp))
3061 buf[6] = 1;
3062 else
3063 buf[2] = 1;
3064 etest->flags |= ETH_TEST_FL_FAILED;
3065 }
3066}
3067
3068#define IS_PORT_STAT(i) \
3069 ((bnx2x_stats_arr[i].flags & STATS_FLAGS_BOTH) == STATS_FLAGS_PORT)
3070#define IS_FUNC_STAT(i) (bnx2x_stats_arr[i].flags & STATS_FLAGS_FUNC)
3071#define HIDE_PORT_STAT(bp) \
3072 ((IS_MF(bp) && !(bp->msg_enable & BNX2X_MSG_STATS)) || \
3073 IS_VF(bp))
3074
3075
3076
3077
3078static int bnx2x_num_stat_queues(struct bnx2x *bp)
3079{
3080 return BNX2X_NUM_ETH_QUEUES(bp);
3081}
3082
3083static int bnx2x_get_sset_count(struct net_device *dev, int stringset)
3084{
3085 struct bnx2x *bp = netdev_priv(dev);
3086 int i, num_strings = 0;
3087
3088 switch (stringset) {
3089 case ETH_SS_STATS:
3090 if (is_multi(bp)) {
3091 num_strings = bnx2x_num_stat_queues(bp) *
3092 BNX2X_NUM_Q_STATS;
3093 } else
3094 num_strings = 0;
3095 if (HIDE_PORT_STAT(bp)) {
3096 for (i = 0; i < BNX2X_NUM_STATS; i++)
3097 if (IS_FUNC_STAT(i))
3098 num_strings++;
3099 } else
3100 num_strings += BNX2X_NUM_STATS;
3101
3102 return num_strings;
3103
3104 case ETH_SS_TEST:
3105 return BNX2X_NUM_TESTS(bp);
3106
3107 case ETH_SS_PRIV_FLAGS:
3108 return BNX2X_PRI_FLAG_LEN;
3109
3110 default:
3111 return -EINVAL;
3112 }
3113}
3114
3115static u32 bnx2x_get_private_flags(struct net_device *dev)
3116{
3117 struct bnx2x *bp = netdev_priv(dev);
3118 u32 flags = 0;
3119
3120 flags |= (!(bp->flags & NO_ISCSI_FLAG) ? 1 : 0) << BNX2X_PRI_FLAG_ISCSI;
3121 flags |= (!(bp->flags & NO_FCOE_FLAG) ? 1 : 0) << BNX2X_PRI_FLAG_FCOE;
3122 flags |= (!!IS_MF_STORAGE_ONLY(bp)) << BNX2X_PRI_FLAG_STORAGE;
3123
3124 return flags;
3125}
3126
3127static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
3128{
3129 struct bnx2x *bp = netdev_priv(dev);
3130 int i, j, k, start;
3131 char queue_name[MAX_QUEUE_NAME_LEN+1];
3132
3133 switch (stringset) {
3134 case ETH_SS_STATS:
3135 k = 0;
3136 if (is_multi(bp)) {
3137 for_each_eth_queue(bp, i) {
3138 memset(queue_name, 0, sizeof(queue_name));
3139 sprintf(queue_name, "%d", i);
3140 for (j = 0; j < BNX2X_NUM_Q_STATS; j++)
3141 snprintf(buf + (k + j)*ETH_GSTRING_LEN,
3142 ETH_GSTRING_LEN,
3143 bnx2x_q_stats_arr[j].string,
3144 queue_name);
3145 k += BNX2X_NUM_Q_STATS;
3146 }
3147 }
3148
3149 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
3150 if (HIDE_PORT_STAT(bp) && IS_PORT_STAT(i))
3151 continue;
3152 strcpy(buf + (k + j)*ETH_GSTRING_LEN,
3153 bnx2x_stats_arr[i].string);
3154 j++;
3155 }
3156
3157 break;
3158
3159 case ETH_SS_TEST:
3160
3161 if (!IS_MF(bp))
3162 start = 0;
3163 else
3164 start = 4;
3165 memcpy(buf, bnx2x_tests_str_arr + start,
3166 ETH_GSTRING_LEN * BNX2X_NUM_TESTS(bp));
3167 break;
3168
3169 case ETH_SS_PRIV_FLAGS:
3170 memcpy(buf, bnx2x_private_arr,
3171 ETH_GSTRING_LEN * BNX2X_PRI_FLAG_LEN);
3172 break;
3173 }
3174}
3175
3176static void bnx2x_get_ethtool_stats(struct net_device *dev,
3177 struct ethtool_stats *stats, u64 *buf)
3178{
3179 struct bnx2x *bp = netdev_priv(dev);
3180 u32 *hw_stats, *offset;
3181 int i, j, k = 0;
3182
3183 if (is_multi(bp)) {
3184 for_each_eth_queue(bp, i) {
3185 hw_stats = (u32 *)&bp->fp_stats[i].eth_q_stats;
3186 for (j = 0; j < BNX2X_NUM_Q_STATS; j++) {
3187 if (bnx2x_q_stats_arr[j].size == 0) {
3188
3189 buf[k + j] = 0;
3190 continue;
3191 }
3192 offset = (hw_stats +
3193 bnx2x_q_stats_arr[j].offset);
3194 if (bnx2x_q_stats_arr[j].size == 4) {
3195
3196 buf[k + j] = (u64) *offset;
3197 continue;
3198 }
3199
3200 buf[k + j] = HILO_U64(*offset, *(offset + 1));
3201 }
3202 k += BNX2X_NUM_Q_STATS;
3203 }
3204 }
3205
3206 hw_stats = (u32 *)&bp->eth_stats;
3207 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
3208 if (HIDE_PORT_STAT(bp) && IS_PORT_STAT(i))
3209 continue;
3210 if (bnx2x_stats_arr[i].size == 0) {
3211
3212 buf[k + j] = 0;
3213 j++;
3214 continue;
3215 }
3216 offset = (hw_stats + bnx2x_stats_arr[i].offset);
3217 if (bnx2x_stats_arr[i].size == 4) {
3218
3219 buf[k + j] = (u64) *offset;
3220 j++;
3221 continue;
3222 }
3223
3224 buf[k + j] = HILO_U64(*offset, *(offset + 1));
3225 j++;
3226 }
3227}
3228
3229static int bnx2x_set_phys_id(struct net_device *dev,
3230 enum ethtool_phys_id_state state)
3231{
3232 struct bnx2x *bp = netdev_priv(dev);
3233
3234 if (!bnx2x_is_nvm_accessible(bp)) {
3235 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
3236 "cannot access eeprom when the interface is down\n");
3237 return -EAGAIN;
3238 }
3239
3240 switch (state) {
3241 case ETHTOOL_ID_ACTIVE:
3242 return 1;
3243
3244 case ETHTOOL_ID_ON:
3245 bnx2x_acquire_phy_lock(bp);
3246 bnx2x_set_led(&bp->link_params, &bp->link_vars,
3247 LED_MODE_ON, SPEED_1000);
3248 bnx2x_release_phy_lock(bp);
3249 break;
3250
3251 case ETHTOOL_ID_OFF:
3252 bnx2x_acquire_phy_lock(bp);
3253 bnx2x_set_led(&bp->link_params, &bp->link_vars,
3254 LED_MODE_FRONT_PANEL_OFF, 0);
3255 bnx2x_release_phy_lock(bp);
3256 break;
3257
3258 case ETHTOOL_ID_INACTIVE:
3259 bnx2x_acquire_phy_lock(bp);
3260 bnx2x_set_led(&bp->link_params, &bp->link_vars,
3261 LED_MODE_OPER,
3262 bp->link_vars.line_speed);
3263 bnx2x_release_phy_lock(bp);
3264 }
3265
3266 return 0;
3267}
3268
3269static int bnx2x_get_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info)
3270{
3271 switch (info->flow_type) {
3272 case TCP_V4_FLOW:
3273 case TCP_V6_FLOW:
3274 info->data = RXH_IP_SRC | RXH_IP_DST |
3275 RXH_L4_B_0_1 | RXH_L4_B_2_3;
3276 break;
3277 case UDP_V4_FLOW:
3278 if (bp->rss_conf_obj.udp_rss_v4)
3279 info->data = RXH_IP_SRC | RXH_IP_DST |
3280 RXH_L4_B_0_1 | RXH_L4_B_2_3;
3281 else
3282 info->data = RXH_IP_SRC | RXH_IP_DST;
3283 break;
3284 case UDP_V6_FLOW:
3285 if (bp->rss_conf_obj.udp_rss_v6)
3286 info->data = RXH_IP_SRC | RXH_IP_DST |
3287 RXH_L4_B_0_1 | RXH_L4_B_2_3;
3288 else
3289 info->data = RXH_IP_SRC | RXH_IP_DST;
3290 break;
3291 case IPV4_FLOW:
3292 case IPV6_FLOW:
3293 info->data = RXH_IP_SRC | RXH_IP_DST;
3294 break;
3295 default:
3296 info->data = 0;
3297 break;
3298 }
3299
3300 return 0;
3301}
3302
3303static int bnx2x_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
3304 u32 *rules __always_unused)
3305{
3306 struct bnx2x *bp = netdev_priv(dev);
3307
3308 switch (info->cmd) {
3309 case ETHTOOL_GRXRINGS:
3310 info->data = BNX2X_NUM_ETH_QUEUES(bp);
3311 return 0;
3312 case ETHTOOL_GRXFH:
3313 return bnx2x_get_rss_flags(bp, info);
3314 default:
3315 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
3316 return -EOPNOTSUPP;
3317 }
3318}
3319
3320static int bnx2x_set_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info)
3321{
3322 int udp_rss_requested;
3323
3324 DP(BNX2X_MSG_ETHTOOL,
3325 "Set rss flags command parameters: flow type = %d, data = %llu\n",
3326 info->flow_type, info->data);
3327
3328 switch (info->flow_type) {
3329 case TCP_V4_FLOW:
3330 case TCP_V6_FLOW:
3331
3332 if (info->data ^ (RXH_IP_SRC | RXH_IP_DST |
3333 RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
3334 DP(BNX2X_MSG_ETHTOOL,
3335 "Command parameters not supported\n");
3336 return -EINVAL;
3337 }
3338 return 0;
3339
3340 case UDP_V4_FLOW:
3341 case UDP_V6_FLOW:
3342
3343 if (info->data == (RXH_IP_SRC | RXH_IP_DST |
3344 RXH_L4_B_0_1 | RXH_L4_B_2_3))
3345 udp_rss_requested = 1;
3346 else if (info->data == (RXH_IP_SRC | RXH_IP_DST))
3347 udp_rss_requested = 0;
3348 else
3349 return -EINVAL;
3350
3351 if (CHIP_IS_E1x(bp) && udp_rss_requested) {
3352 DP(BNX2X_MSG_ETHTOOL,
3353 "57710, 57711 boards don't support RSS according to UDP 4-tuple\n");
3354 return -EINVAL;
3355 }
3356
3357 if ((info->flow_type == UDP_V4_FLOW) &&
3358 (bp->rss_conf_obj.udp_rss_v4 != udp_rss_requested)) {
3359 bp->rss_conf_obj.udp_rss_v4 = udp_rss_requested;
3360 DP(BNX2X_MSG_ETHTOOL,
3361 "rss re-configured, UDP 4-tupple %s\n",
3362 udp_rss_requested ? "enabled" : "disabled");
3363 return bnx2x_rss(bp, &bp->rss_conf_obj, false, true);
3364 } else if ((info->flow_type == UDP_V6_FLOW) &&
3365 (bp->rss_conf_obj.udp_rss_v6 != udp_rss_requested)) {
3366 bp->rss_conf_obj.udp_rss_v6 = udp_rss_requested;
3367 DP(BNX2X_MSG_ETHTOOL,
3368 "rss re-configured, UDP 4-tupple %s\n",
3369 udp_rss_requested ? "enabled" : "disabled");
3370 return bnx2x_rss(bp, &bp->rss_conf_obj, false, true);
3371 }
3372 return 0;
3373
3374 case IPV4_FLOW:
3375 case IPV6_FLOW:
3376
3377 if (info->data ^ (RXH_IP_SRC | RXH_IP_DST)) {
3378 DP(BNX2X_MSG_ETHTOOL,
3379 "Command parameters not supported\n");
3380 return -EINVAL;
3381 }
3382 return 0;
3383
3384 case SCTP_V4_FLOW:
3385 case AH_ESP_V4_FLOW:
3386 case AH_V4_FLOW:
3387 case ESP_V4_FLOW:
3388 case SCTP_V6_FLOW:
3389 case AH_ESP_V6_FLOW:
3390 case AH_V6_FLOW:
3391 case ESP_V6_FLOW:
3392 case IP_USER_FLOW:
3393 case ETHER_FLOW:
3394
3395 if (info->data) {
3396 DP(BNX2X_MSG_ETHTOOL,
3397 "Command parameters not supported\n");
3398 return -EINVAL;
3399 }
3400 return 0;
3401
3402 default:
3403 return -EINVAL;
3404 }
3405}
3406
3407static int bnx2x_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info)
3408{
3409 struct bnx2x *bp = netdev_priv(dev);
3410
3411 switch (info->cmd) {
3412 case ETHTOOL_SRXFH:
3413 return bnx2x_set_rss_flags(bp, info);
3414 default:
3415 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
3416 return -EOPNOTSUPP;
3417 }
3418}
3419
3420static u32 bnx2x_get_rxfh_indir_size(struct net_device *dev)
3421{
3422 return T_ETH_INDIRECTION_TABLE_SIZE;
3423}
3424
3425static int bnx2x_get_rxfh(struct net_device *dev, u32 *indir, u8 *key,
3426 u8 *hfunc)
3427{
3428 struct bnx2x *bp = netdev_priv(dev);
3429 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0};
3430 size_t i;
3431
3432 if (hfunc)
3433 *hfunc = ETH_RSS_HASH_TOP;
3434 if (!indir)
3435 return 0;
3436
3437
3438 bnx2x_get_rss_ind_table(&bp->rss_conf_obj, ind_table);
3439
3440
3441
3442
3443
3444
3445
3446
3447
3448
3449 for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++)
3450 indir[i] = ind_table[i] - bp->fp->cl_id;
3451
3452 return 0;
3453}
3454
3455static int bnx2x_set_rxfh(struct net_device *dev, const u32 *indir,
3456 const u8 *key, const u8 hfunc)
3457{
3458 struct bnx2x *bp = netdev_priv(dev);
3459 size_t i;
3460
3461
3462
3463
3464 if (key ||
3465 (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP))
3466 return -EOPNOTSUPP;
3467
3468 if (!indir)
3469 return 0;
3470
3471 for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) {
3472
3473
3474
3475
3476
3477
3478
3479
3480
3481 bp->rss_conf_obj.ind_table[i] = indir[i] + bp->fp->cl_id;
3482 }
3483
3484 return bnx2x_config_rss_eth(bp, false);
3485}
3486
3487
3488
3489
3490
3491
3492
3493static void bnx2x_get_channels(struct net_device *dev,
3494 struct ethtool_channels *channels)
3495{
3496 struct bnx2x *bp = netdev_priv(dev);
3497
3498 channels->max_combined = BNX2X_MAX_RSS_COUNT(bp);
3499 channels->combined_count = BNX2X_NUM_ETH_QUEUES(bp);
3500}
3501
3502
3503
3504
3505
3506
3507
3508
3509
3510static void bnx2x_change_num_queues(struct bnx2x *bp, int num_rss)
3511{
3512 bnx2x_disable_msi(bp);
3513 bp->num_ethernet_queues = num_rss;
3514 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
3515 BNX2X_DEV_INFO("set number of queues to %d\n", bp->num_queues);
3516 bnx2x_set_int_mode(bp);
3517}
3518
3519
3520
3521
3522
3523
3524
3525static int bnx2x_set_channels(struct net_device *dev,
3526 struct ethtool_channels *channels)
3527{
3528 struct bnx2x *bp = netdev_priv(dev);
3529
3530 DP(BNX2X_MSG_ETHTOOL,
3531 "set-channels command parameters: rx = %d, tx = %d, other = %d, combined = %d\n",
3532 channels->rx_count, channels->tx_count, channels->other_count,
3533 channels->combined_count);
3534
3535 if (pci_num_vf(bp->pdev)) {
3536 DP(BNX2X_MSG_IOV, "VFs are enabled, can not set channels\n");
3537 return -EPERM;
3538 }
3539
3540
3541
3542
3543 if (channels->rx_count || channels->tx_count || channels->other_count
3544 || (channels->combined_count == 0) ||
3545 (channels->combined_count > BNX2X_MAX_RSS_COUNT(bp))) {
3546 DP(BNX2X_MSG_ETHTOOL, "command parameters not supported\n");
3547 return -EINVAL;
3548 }
3549
3550
3551 if (channels->combined_count == BNX2X_NUM_ETH_QUEUES(bp)) {
3552 DP(BNX2X_MSG_ETHTOOL, "No change in active parameters\n");
3553 return 0;
3554 }
3555
3556
3557
3558
3559
3560 if (unlikely(!netif_running(dev))) {
3561 bnx2x_change_num_queues(bp, channels->combined_count);
3562 return 0;
3563 }
3564 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
3565 bnx2x_change_num_queues(bp, channels->combined_count);
3566 return bnx2x_nic_load(bp, LOAD_NORMAL);
3567}
3568
3569static int bnx2x_get_ts_info(struct net_device *dev,
3570 struct ethtool_ts_info *info)
3571{
3572 struct bnx2x *bp = netdev_priv(dev);
3573
3574 if (bp->flags & PTP_SUPPORTED) {
3575 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
3576 SOF_TIMESTAMPING_RX_SOFTWARE |
3577 SOF_TIMESTAMPING_SOFTWARE |
3578 SOF_TIMESTAMPING_TX_HARDWARE |
3579 SOF_TIMESTAMPING_RX_HARDWARE |
3580 SOF_TIMESTAMPING_RAW_HARDWARE;
3581
3582 if (bp->ptp_clock)
3583 info->phc_index = ptp_clock_index(bp->ptp_clock);
3584 else
3585 info->phc_index = -1;
3586
3587 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
3588 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
3589 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
3590 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
3591
3592 info->tx_types = (1 << HWTSTAMP_TX_OFF)|(1 << HWTSTAMP_TX_ON);
3593
3594 return 0;
3595 }
3596
3597 return ethtool_op_get_ts_info(dev, info);
3598}
3599
3600static const struct ethtool_ops bnx2x_ethtool_ops = {
3601 .get_settings = bnx2x_get_settings,
3602 .set_settings = bnx2x_set_settings,
3603 .get_drvinfo = bnx2x_get_drvinfo,
3604 .get_regs_len = bnx2x_get_regs_len,
3605 .get_regs = bnx2x_get_regs,
3606 .get_dump_flag = bnx2x_get_dump_flag,
3607 .get_dump_data = bnx2x_get_dump_data,
3608 .set_dump = bnx2x_set_dump,
3609 .get_wol = bnx2x_get_wol,
3610 .set_wol = bnx2x_set_wol,
3611 .get_msglevel = bnx2x_get_msglevel,
3612 .set_msglevel = bnx2x_set_msglevel,
3613 .nway_reset = bnx2x_nway_reset,
3614 .get_link = bnx2x_get_link,
3615 .get_eeprom_len = bnx2x_get_eeprom_len,
3616 .get_eeprom = bnx2x_get_eeprom,
3617 .set_eeprom = bnx2x_set_eeprom,
3618 .get_coalesce = bnx2x_get_coalesce,
3619 .set_coalesce = bnx2x_set_coalesce,
3620 .get_ringparam = bnx2x_get_ringparam,
3621 .set_ringparam = bnx2x_set_ringparam,
3622 .get_pauseparam = bnx2x_get_pauseparam,
3623 .set_pauseparam = bnx2x_set_pauseparam,
3624 .self_test = bnx2x_self_test,
3625 .get_sset_count = bnx2x_get_sset_count,
3626 .get_priv_flags = bnx2x_get_private_flags,
3627 .get_strings = bnx2x_get_strings,
3628 .set_phys_id = bnx2x_set_phys_id,
3629 .get_ethtool_stats = bnx2x_get_ethtool_stats,
3630 .get_rxnfc = bnx2x_get_rxnfc,
3631 .set_rxnfc = bnx2x_set_rxnfc,
3632 .get_rxfh_indir_size = bnx2x_get_rxfh_indir_size,
3633 .get_rxfh = bnx2x_get_rxfh,
3634 .set_rxfh = bnx2x_set_rxfh,
3635 .get_channels = bnx2x_get_channels,
3636 .set_channels = bnx2x_set_channels,
3637 .get_module_info = bnx2x_get_module_info,
3638 .get_module_eeprom = bnx2x_get_module_eeprom,
3639 .get_eee = bnx2x_get_eee,
3640 .set_eee = bnx2x_set_eee,
3641 .get_ts_info = bnx2x_get_ts_info,
3642};
3643
3644static const struct ethtool_ops bnx2x_vf_ethtool_ops = {
3645 .get_settings = bnx2x_get_vf_settings,
3646 .get_drvinfo = bnx2x_get_drvinfo,
3647 .get_msglevel = bnx2x_get_msglevel,
3648 .set_msglevel = bnx2x_set_msglevel,
3649 .get_link = bnx2x_get_link,
3650 .get_coalesce = bnx2x_get_coalesce,
3651 .get_ringparam = bnx2x_get_ringparam,
3652 .set_ringparam = bnx2x_set_ringparam,
3653 .get_sset_count = bnx2x_get_sset_count,
3654 .get_strings = bnx2x_get_strings,
3655 .get_ethtool_stats = bnx2x_get_ethtool_stats,
3656 .get_rxnfc = bnx2x_get_rxnfc,
3657 .set_rxnfc = bnx2x_set_rxnfc,
3658 .get_rxfh_indir_size = bnx2x_get_rxfh_indir_size,
3659 .get_rxfh = bnx2x_get_rxfh,
3660 .set_rxfh = bnx2x_set_rxfh,
3661 .get_channels = bnx2x_get_channels,
3662 .set_channels = bnx2x_set_channels,
3663};
3664
3665void bnx2x_set_ethtool_ops(struct bnx2x *bp, struct net_device *netdev)
3666{
3667 netdev->ethtool_ops = (IS_PF(bp)) ?
3668 &bnx2x_ethtool_ops : &bnx2x_vf_ethtool_ops;
3669}
3670
