1/******************************************************************************* 2 * 3 * Intel Ethernet Controller XL710 Family Linux Driver 4 * Copyright(c) 2013 - 2014 Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * The full GNU General Public License is included in this distribution in 19 * the file called "COPYING". 20 * 21 * Contact Information: 22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 24 * 25 ******************************************************************************/ 26 27#ifndef _I40E_DCB_H_ 28#define _I40E_DCB_H_ 29 30#include "i40e_type.h" 31 32#define I40E_DCBX_STATUS_NOT_STARTED 0 33#define I40E_DCBX_STATUS_IN_PROGRESS 1 34#define I40E_DCBX_STATUS_DONE 2 35#define I40E_DCBX_STATUS_MULTIPLE_PEERS 3 36#define I40E_DCBX_STATUS_DISABLED 7 37 38#define I40E_TLV_TYPE_END 0 39#define I40E_TLV_TYPE_ORG 127 40 41#define I40E_IEEE_8021QAZ_OUI 0x0080C2 42#define I40E_IEEE_SUBTYPE_ETS_CFG 9 43#define I40E_IEEE_SUBTYPE_ETS_REC 10 44#define I40E_IEEE_SUBTYPE_PFC_CFG 11 45#define I40E_IEEE_SUBTYPE_APP_PRI 12 46 47#define I40E_CEE_DCBX_OUI 0x001b21 48#define I40E_CEE_DCBX_TYPE 2 49 50#define I40E_CEE_SUBTYPE_CTRL 1 51#define I40E_CEE_SUBTYPE_PG_CFG 2 52#define I40E_CEE_SUBTYPE_PFC_CFG 3 53#define I40E_CEE_SUBTYPE_APP_PRI 4 54 55#define I40E_CEE_MAX_FEAT_TYPE 3 56/* Defines for LLDP TLV header */ 57#define I40E_LLDP_TLV_LEN_SHIFT 0 58#define I40E_LLDP_TLV_LEN_MASK (0x01FF << I40E_LLDP_TLV_LEN_SHIFT) 59#define I40E_LLDP_TLV_TYPE_SHIFT 9 60#define I40E_LLDP_TLV_TYPE_MASK (0x7F << I40E_LLDP_TLV_TYPE_SHIFT) 61#define I40E_LLDP_TLV_SUBTYPE_SHIFT 0 62#define I40E_LLDP_TLV_SUBTYPE_MASK (0xFF << I40E_LLDP_TLV_SUBTYPE_SHIFT) 63#define I40E_LLDP_TLV_OUI_SHIFT 8 64#define I40E_LLDP_TLV_OUI_MASK (0xFFFFFF << I40E_LLDP_TLV_OUI_SHIFT) 65 66/* Defines for IEEE ETS TLV */ 67#define I40E_IEEE_ETS_MAXTC_SHIFT 0 68#define I40E_IEEE_ETS_MAXTC_MASK (0x7 << I40E_IEEE_ETS_MAXTC_SHIFT) 69#define I40E_IEEE_ETS_CBS_SHIFT 6 70#define I40E_IEEE_ETS_CBS_MASK BIT(I40E_IEEE_ETS_CBS_SHIFT) 71#define I40E_IEEE_ETS_WILLING_SHIFT 7 72#define I40E_IEEE_ETS_WILLING_MASK BIT(I40E_IEEE_ETS_WILLING_SHIFT) 73#define I40E_IEEE_ETS_PRIO_0_SHIFT 0 74#define I40E_IEEE_ETS_PRIO_0_MASK (0x7 << I40E_IEEE_ETS_PRIO_0_SHIFT) 75#define I40E_IEEE_ETS_PRIO_1_SHIFT 4 76#define I40E_IEEE_ETS_PRIO_1_MASK (0x7 << I40E_IEEE_ETS_PRIO_1_SHIFT) 77#define I40E_CEE_PGID_PRIO_0_SHIFT 0 78#define I40E_CEE_PGID_PRIO_0_MASK (0xF << I40E_CEE_PGID_PRIO_0_SHIFT) 79#define I40E_CEE_PGID_PRIO_1_SHIFT 4 80#define I40E_CEE_PGID_PRIO_1_MASK (0xF << I40E_CEE_PGID_PRIO_1_SHIFT) 81#define I40E_CEE_PGID_STRICT 15 82 83/* Defines for IEEE TSA types */ 84#define I40E_IEEE_TSA_STRICT 0 85#define I40E_IEEE_TSA_ETS 2 86 87/* Defines for IEEE PFC TLV */ 88#define I40E_IEEE_PFC_CAP_SHIFT 0 89#define I40E_IEEE_PFC_CAP_MASK (0xF << I40E_IEEE_PFC_CAP_SHIFT) 90#define I40E_IEEE_PFC_MBC_SHIFT 6 91#define I40E_IEEE_PFC_MBC_MASK BIT(I40E_IEEE_PFC_MBC_SHIFT) 92#define I40E_IEEE_PFC_WILLING_SHIFT 7 93#define I40E_IEEE_PFC_WILLING_MASK BIT(I40E_IEEE_PFC_WILLING_SHIFT) 94 95/* Defines for IEEE APP TLV */ 96#define I40E_IEEE_APP_SEL_SHIFT 0 97#define I40E_IEEE_APP_SEL_MASK (0x7 << I40E_IEEE_APP_SEL_SHIFT) 98#define I40E_IEEE_APP_PRIO_SHIFT 5 99#define I40E_IEEE_APP_PRIO_MASK (0x7 << I40E_IEEE_APP_PRIO_SHIFT) 100 101 102#pragma pack(1) 103 104/* IEEE 802.1AB LLDP Organization specific TLV */ 105struct i40e_lldp_org_tlv { 106 __be16 typelength; 107 __be32 ouisubtype; 108 u8 tlvinfo[1]; 109}; 110 111struct i40e_cee_tlv_hdr { 112 __be16 typelen; 113 u8 operver; 114 u8 maxver; 115}; 116 117struct i40e_cee_ctrl_tlv { 118 struct i40e_cee_tlv_hdr hdr; 119 __be32 seqno; 120 __be32 ackno; 121}; 122 123struct i40e_cee_feat_tlv { 124 struct i40e_cee_tlv_hdr hdr; 125 u8 en_will_err; /* Bits: |En|Will|Err|Reserved(5)| */ 126#define I40E_CEE_FEAT_TLV_ENABLE_MASK 0x80 127#define I40E_CEE_FEAT_TLV_WILLING_MASK 0x40 128#define I40E_CEE_FEAT_TLV_ERR_MASK 0x20 129 u8 subtype; 130 u8 tlvinfo[1]; 131}; 132 133struct i40e_cee_app_prio { 134 __be16 protocol; 135 u8 upper_oui_sel; /* Bits: |Upper OUI(6)|Selector(2)| */ 136#define I40E_CEE_APP_SELECTOR_MASK 0x03 137 __be16 lower_oui; 138 u8 prio_map; 139}; 140#pragma pack() 141 142i40e_status i40e_get_dcbx_status(struct i40e_hw *hw, 143 u16 *status); 144i40e_status i40e_lldp_to_dcb_config(u8 *lldpmib, 145 struct i40e_dcbx_config *dcbcfg); 146i40e_status i40e_aq_get_dcb_config(struct i40e_hw *hw, u8 mib_type, 147 u8 bridgetype, 148 struct i40e_dcbx_config *dcbcfg); 149i40e_status i40e_get_dcb_config(struct i40e_hw *hw); 150i40e_status i40e_init_dcb(struct i40e_hw *hw); 151#endif /* _I40E_DCB_H_ */ 152