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24#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
25
26#include <linux/module.h>
27#include <linux/types.h>
28#include <linux/init.h>
29#include <linux/bitops.h>
30#include <linux/vmalloc.h>
31#include <linux/pagemap.h>
32#include <linux/netdevice.h>
33#include <linux/ipv6.h>
34#include <linux/slab.h>
35#include <net/checksum.h>
36#include <net/ip6_checksum.h>
37#include <linux/net_tstamp.h>
38#include <linux/mii.h>
39#include <linux/ethtool.h>
40#include <linux/if.h>
41#include <linux/if_vlan.h>
42#include <linux/pci.h>
43#include <linux/pci-aspm.h>
44#include <linux/delay.h>
45#include <linux/interrupt.h>
46#include <linux/ip.h>
47#include <linux/tcp.h>
48#include <linux/sctp.h>
49#include <linux/if_ether.h>
50#include <linux/aer.h>
51#include <linux/prefetch.h>
52#include <linux/pm_runtime.h>
53#ifdef CONFIG_IGB_DCA
54#include <linux/dca.h>
55#endif
56#include <linux/i2c.h>
57#include "igb.h"
58
59#define MAJ 5
60#define MIN 3
61#define BUILD 0
62#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
63__stringify(BUILD) "-k"
64char igb_driver_name[] = "igb";
65char igb_driver_version[] = DRV_VERSION;
66static const char igb_driver_string[] =
67 "Intel(R) Gigabit Ethernet Network Driver";
68static const char igb_copyright[] =
69 "Copyright (c) 2007-2014 Intel Corporation.";
70
71static const struct e1000_info *igb_info_tbl[] = {
72 [board_82575] = &e1000_82575_info,
73};
74
75static const struct pci_device_id igb_pci_tbl[] = {
76 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) },
78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 },
85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 },
86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
108 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
109 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
110 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
111
112 {0, }
113};
114
115MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
116
117static int igb_setup_all_tx_resources(struct igb_adapter *);
118static int igb_setup_all_rx_resources(struct igb_adapter *);
119static void igb_free_all_tx_resources(struct igb_adapter *);
120static void igb_free_all_rx_resources(struct igb_adapter *);
121static void igb_setup_mrqc(struct igb_adapter *);
122static int igb_probe(struct pci_dev *, const struct pci_device_id *);
123static void igb_remove(struct pci_dev *pdev);
124static int igb_sw_init(struct igb_adapter *);
125static int igb_open(struct net_device *);
126static int igb_close(struct net_device *);
127static void igb_configure(struct igb_adapter *);
128static void igb_configure_tx(struct igb_adapter *);
129static void igb_configure_rx(struct igb_adapter *);
130static void igb_clean_all_tx_rings(struct igb_adapter *);
131static void igb_clean_all_rx_rings(struct igb_adapter *);
132static void igb_clean_tx_ring(struct igb_ring *);
133static void igb_clean_rx_ring(struct igb_ring *);
134static void igb_set_rx_mode(struct net_device *);
135static void igb_update_phy_info(unsigned long);
136static void igb_watchdog(unsigned long);
137static void igb_watchdog_task(struct work_struct *);
138static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
139static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev,
140 struct rtnl_link_stats64 *stats);
141static int igb_change_mtu(struct net_device *, int);
142static int igb_set_mac(struct net_device *, void *);
143static void igb_set_uta(struct igb_adapter *adapter);
144static irqreturn_t igb_intr(int irq, void *);
145static irqreturn_t igb_intr_msi(int irq, void *);
146static irqreturn_t igb_msix_other(int irq, void *);
147static irqreturn_t igb_msix_ring(int irq, void *);
148#ifdef CONFIG_IGB_DCA
149static void igb_update_dca(struct igb_q_vector *);
150static void igb_setup_dca(struct igb_adapter *);
151#endif
152static int igb_poll(struct napi_struct *, int);
153static bool igb_clean_tx_irq(struct igb_q_vector *);
154static int igb_clean_rx_irq(struct igb_q_vector *, int);
155static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
156static void igb_tx_timeout(struct net_device *);
157static void igb_reset_task(struct work_struct *);
158static void igb_vlan_mode(struct net_device *netdev,
159 netdev_features_t features);
160static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16);
161static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16);
162static void igb_restore_vlan(struct igb_adapter *);
163static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
164static void igb_ping_all_vfs(struct igb_adapter *);
165static void igb_msg_task(struct igb_adapter *);
166static void igb_vmm_control(struct igb_adapter *);
167static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
168static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
169static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
170static int igb_ndo_set_vf_vlan(struct net_device *netdev,
171 int vf, u16 vlan, u8 qos);
172static int igb_ndo_set_vf_bw(struct net_device *, int, int, int);
173static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
174 bool setting);
175static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
176 struct ifla_vf_info *ivi);
177static void igb_check_vf_rate_limit(struct igb_adapter *);
178
179#ifdef CONFIG_PCI_IOV
180static int igb_vf_configure(struct igb_adapter *adapter, int vf);
181static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs);
182static int igb_disable_sriov(struct pci_dev *dev);
183static int igb_pci_disable_sriov(struct pci_dev *dev);
184#endif
185
186#ifdef CONFIG_PM
187#ifdef CONFIG_PM_SLEEP
188static int igb_suspend(struct device *);
189#endif
190static int igb_resume(struct device *);
191static int igb_runtime_suspend(struct device *dev);
192static int igb_runtime_resume(struct device *dev);
193static int igb_runtime_idle(struct device *dev);
194static const struct dev_pm_ops igb_pm_ops = {
195 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume)
196 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume,
197 igb_runtime_idle)
198};
199#endif
200static void igb_shutdown(struct pci_dev *);
201static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs);
202#ifdef CONFIG_IGB_DCA
203static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
204static struct notifier_block dca_notifier = {
205 .notifier_call = igb_notify_dca,
206 .next = NULL,
207 .priority = 0
208};
209#endif
210#ifdef CONFIG_NET_POLL_CONTROLLER
211
212static void igb_netpoll(struct net_device *);
213#endif
214#ifdef CONFIG_PCI_IOV
215static unsigned int max_vfs;
216module_param(max_vfs, uint, 0);
217MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function");
218#endif
219
220static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
221 pci_channel_state_t);
222static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
223static void igb_io_resume(struct pci_dev *);
224
225static const struct pci_error_handlers igb_err_handler = {
226 .error_detected = igb_io_error_detected,
227 .slot_reset = igb_io_slot_reset,
228 .resume = igb_io_resume,
229};
230
231static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
232
233static struct pci_driver igb_driver = {
234 .name = igb_driver_name,
235 .id_table = igb_pci_tbl,
236 .probe = igb_probe,
237 .remove = igb_remove,
238#ifdef CONFIG_PM
239 .driver.pm = &igb_pm_ops,
240#endif
241 .shutdown = igb_shutdown,
242 .sriov_configure = igb_pci_sriov_configure,
243 .err_handler = &igb_err_handler
244};
245
246MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
247MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
248MODULE_LICENSE("GPL");
249MODULE_VERSION(DRV_VERSION);
250
251#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
252static int debug = -1;
253module_param(debug, int, 0);
254MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
255
256struct igb_reg_info {
257 u32 ofs;
258 char *name;
259};
260
261static const struct igb_reg_info igb_reg_info_tbl[] = {
262
263
264 {E1000_CTRL, "CTRL"},
265 {E1000_STATUS, "STATUS"},
266 {E1000_CTRL_EXT, "CTRL_EXT"},
267
268
269 {E1000_ICR, "ICR"},
270
271
272 {E1000_RCTL, "RCTL"},
273 {E1000_RDLEN(0), "RDLEN"},
274 {E1000_RDH(0), "RDH"},
275 {E1000_RDT(0), "RDT"},
276 {E1000_RXDCTL(0), "RXDCTL"},
277 {E1000_RDBAL(0), "RDBAL"},
278 {E1000_RDBAH(0), "RDBAH"},
279
280
281 {E1000_TCTL, "TCTL"},
282 {E1000_TDBAL(0), "TDBAL"},
283 {E1000_TDBAH(0), "TDBAH"},
284 {E1000_TDLEN(0), "TDLEN"},
285 {E1000_TDH(0), "TDH"},
286 {E1000_TDT(0), "TDT"},
287 {E1000_TXDCTL(0), "TXDCTL"},
288 {E1000_TDFH, "TDFH"},
289 {E1000_TDFT, "TDFT"},
290 {E1000_TDFHS, "TDFHS"},
291 {E1000_TDFPC, "TDFPC"},
292
293
294 {}
295};
296
297
298static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
299{
300 int n = 0;
301 char rname[16];
302 u32 regs[8];
303
304 switch (reginfo->ofs) {
305 case E1000_RDLEN(0):
306 for (n = 0; n < 4; n++)
307 regs[n] = rd32(E1000_RDLEN(n));
308 break;
309 case E1000_RDH(0):
310 for (n = 0; n < 4; n++)
311 regs[n] = rd32(E1000_RDH(n));
312 break;
313 case E1000_RDT(0):
314 for (n = 0; n < 4; n++)
315 regs[n] = rd32(E1000_RDT(n));
316 break;
317 case E1000_RXDCTL(0):
318 for (n = 0; n < 4; n++)
319 regs[n] = rd32(E1000_RXDCTL(n));
320 break;
321 case E1000_RDBAL(0):
322 for (n = 0; n < 4; n++)
323 regs[n] = rd32(E1000_RDBAL(n));
324 break;
325 case E1000_RDBAH(0):
326 for (n = 0; n < 4; n++)
327 regs[n] = rd32(E1000_RDBAH(n));
328 break;
329 case E1000_TDBAL(0):
330 for (n = 0; n < 4; n++)
331 regs[n] = rd32(E1000_RDBAL(n));
332 break;
333 case E1000_TDBAH(0):
334 for (n = 0; n < 4; n++)
335 regs[n] = rd32(E1000_TDBAH(n));
336 break;
337 case E1000_TDLEN(0):
338 for (n = 0; n < 4; n++)
339 regs[n] = rd32(E1000_TDLEN(n));
340 break;
341 case E1000_TDH(0):
342 for (n = 0; n < 4; n++)
343 regs[n] = rd32(E1000_TDH(n));
344 break;
345 case E1000_TDT(0):
346 for (n = 0; n < 4; n++)
347 regs[n] = rd32(E1000_TDT(n));
348 break;
349 case E1000_TXDCTL(0):
350 for (n = 0; n < 4; n++)
351 regs[n] = rd32(E1000_TXDCTL(n));
352 break;
353 default:
354 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
355 return;
356 }
357
358 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
359 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
360 regs[2], regs[3]);
361}
362
363
364static void igb_dump(struct igb_adapter *adapter)
365{
366 struct net_device *netdev = adapter->netdev;
367 struct e1000_hw *hw = &adapter->hw;
368 struct igb_reg_info *reginfo;
369 struct igb_ring *tx_ring;
370 union e1000_adv_tx_desc *tx_desc;
371 struct my_u0 { u64 a; u64 b; } *u0;
372 struct igb_ring *rx_ring;
373 union e1000_adv_rx_desc *rx_desc;
374 u32 staterr;
375 u16 i, n;
376
377 if (!netif_msg_hw(adapter))
378 return;
379
380
381 if (netdev) {
382 dev_info(&adapter->pdev->dev, "Net device Info\n");
383 pr_info("Device Name state trans_start last_rx\n");
384 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
385 netdev->state, netdev->trans_start, netdev->last_rx);
386 }
387
388
389 dev_info(&adapter->pdev->dev, "Register Dump\n");
390 pr_info(" Register Name Value\n");
391 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
392 reginfo->name; reginfo++) {
393 igb_regdump(hw, reginfo);
394 }
395
396
397 if (!netdev || !netif_running(netdev))
398 goto exit;
399
400 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
401 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
402 for (n = 0; n < adapter->num_tx_queues; n++) {
403 struct igb_tx_buffer *buffer_info;
404 tx_ring = adapter->tx_ring[n];
405 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
406 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
407 n, tx_ring->next_to_use, tx_ring->next_to_clean,
408 (u64)dma_unmap_addr(buffer_info, dma),
409 dma_unmap_len(buffer_info, len),
410 buffer_info->next_to_watch,
411 (u64)buffer_info->time_stamp);
412 }
413
414
415 if (!netif_msg_tx_done(adapter))
416 goto rx_ring_summary;
417
418 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
419
420
421
422
423
424
425
426
427
428
429
430
431 for (n = 0; n < adapter->num_tx_queues; n++) {
432 tx_ring = adapter->tx_ring[n];
433 pr_info("------------------------------------\n");
434 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
435 pr_info("------------------------------------\n");
436 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] [bi->dma ] leng ntw timestamp bi->skb\n");
437
438 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
439 const char *next_desc;
440 struct igb_tx_buffer *buffer_info;
441 tx_desc = IGB_TX_DESC(tx_ring, i);
442 buffer_info = &tx_ring->tx_buffer_info[i];
443 u0 = (struct my_u0 *)tx_desc;
444 if (i == tx_ring->next_to_use &&
445 i == tx_ring->next_to_clean)
446 next_desc = " NTC/U";
447 else if (i == tx_ring->next_to_use)
448 next_desc = " NTU";
449 else if (i == tx_ring->next_to_clean)
450 next_desc = " NTC";
451 else
452 next_desc = "";
453
454 pr_info("T [0x%03X] %016llX %016llX %016llX %04X %p %016llX %p%s\n",
455 i, le64_to_cpu(u0->a),
456 le64_to_cpu(u0->b),
457 (u64)dma_unmap_addr(buffer_info, dma),
458 dma_unmap_len(buffer_info, len),
459 buffer_info->next_to_watch,
460 (u64)buffer_info->time_stamp,
461 buffer_info->skb, next_desc);
462
463 if (netif_msg_pktdata(adapter) && buffer_info->skb)
464 print_hex_dump(KERN_INFO, "",
465 DUMP_PREFIX_ADDRESS,
466 16, 1, buffer_info->skb->data,
467 dma_unmap_len(buffer_info, len),
468 true);
469 }
470 }
471
472
473rx_ring_summary:
474 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
475 pr_info("Queue [NTU] [NTC]\n");
476 for (n = 0; n < adapter->num_rx_queues; n++) {
477 rx_ring = adapter->rx_ring[n];
478 pr_info(" %5d %5X %5X\n",
479 n, rx_ring->next_to_use, rx_ring->next_to_clean);
480 }
481
482
483 if (!netif_msg_rx_status(adapter))
484 goto exit;
485
486 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509 for (n = 0; n < adapter->num_rx_queues; n++) {
510 rx_ring = adapter->rx_ring[n];
511 pr_info("------------------------------------\n");
512 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
513 pr_info("------------------------------------\n");
514 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] [bi->dma ] [bi->skb] <-- Adv Rx Read format\n");
515 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n");
516
517 for (i = 0; i < rx_ring->count; i++) {
518 const char *next_desc;
519 struct igb_rx_buffer *buffer_info;
520 buffer_info = &rx_ring->rx_buffer_info[i];
521 rx_desc = IGB_RX_DESC(rx_ring, i);
522 u0 = (struct my_u0 *)rx_desc;
523 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
524
525 if (i == rx_ring->next_to_use)
526 next_desc = " NTU";
527 else if (i == rx_ring->next_to_clean)
528 next_desc = " NTC";
529 else
530 next_desc = "";
531
532 if (staterr & E1000_RXD_STAT_DD) {
533
534 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n",
535 "RWB", i,
536 le64_to_cpu(u0->a),
537 le64_to_cpu(u0->b),
538 next_desc);
539 } else {
540 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n",
541 "R ", i,
542 le64_to_cpu(u0->a),
543 le64_to_cpu(u0->b),
544 (u64)buffer_info->dma,
545 next_desc);
546
547 if (netif_msg_pktdata(adapter) &&
548 buffer_info->dma && buffer_info->page) {
549 print_hex_dump(KERN_INFO, "",
550 DUMP_PREFIX_ADDRESS,
551 16, 1,
552 page_address(buffer_info->page) +
553 buffer_info->page_offset,
554 IGB_RX_BUFSZ, true);
555 }
556 }
557 }
558 }
559
560exit:
561 return;
562}
563
564
565
566
567
568
569
570
571static int igb_get_i2c_data(void *data)
572{
573 struct igb_adapter *adapter = (struct igb_adapter *)data;
574 struct e1000_hw *hw = &adapter->hw;
575 s32 i2cctl = rd32(E1000_I2CPARAMS);
576
577 return !!(i2cctl & E1000_I2C_DATA_IN);
578}
579
580
581
582
583
584
585
586
587static void igb_set_i2c_data(void *data, int state)
588{
589 struct igb_adapter *adapter = (struct igb_adapter *)data;
590 struct e1000_hw *hw = &adapter->hw;
591 s32 i2cctl = rd32(E1000_I2CPARAMS);
592
593 if (state)
594 i2cctl |= E1000_I2C_DATA_OUT;
595 else
596 i2cctl &= ~E1000_I2C_DATA_OUT;
597
598 i2cctl &= ~E1000_I2C_DATA_OE_N;
599 i2cctl |= E1000_I2C_CLK_OE_N;
600 wr32(E1000_I2CPARAMS, i2cctl);
601 wrfl();
602
603}
604
605
606
607
608
609
610
611
612static void igb_set_i2c_clk(void *data, int state)
613{
614 struct igb_adapter *adapter = (struct igb_adapter *)data;
615 struct e1000_hw *hw = &adapter->hw;
616 s32 i2cctl = rd32(E1000_I2CPARAMS);
617
618 if (state) {
619 i2cctl |= E1000_I2C_CLK_OUT;
620 i2cctl &= ~E1000_I2C_CLK_OE_N;
621 } else {
622 i2cctl &= ~E1000_I2C_CLK_OUT;
623 i2cctl &= ~E1000_I2C_CLK_OE_N;
624 }
625 wr32(E1000_I2CPARAMS, i2cctl);
626 wrfl();
627}
628
629
630
631
632
633
634
635static int igb_get_i2c_clk(void *data)
636{
637 struct igb_adapter *adapter = (struct igb_adapter *)data;
638 struct e1000_hw *hw = &adapter->hw;
639 s32 i2cctl = rd32(E1000_I2CPARAMS);
640
641 return !!(i2cctl & E1000_I2C_CLK_IN);
642}
643
644static const struct i2c_algo_bit_data igb_i2c_algo = {
645 .setsda = igb_set_i2c_data,
646 .setscl = igb_set_i2c_clk,
647 .getsda = igb_get_i2c_data,
648 .getscl = igb_get_i2c_clk,
649 .udelay = 5,
650 .timeout = 20,
651};
652
653
654
655
656
657
658
659struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
660{
661 struct igb_adapter *adapter = hw->back;
662 return adapter->netdev;
663}
664
665
666
667
668
669
670
671static int __init igb_init_module(void)
672{
673 int ret;
674
675 pr_info("%s - version %s\n",
676 igb_driver_string, igb_driver_version);
677 pr_info("%s\n", igb_copyright);
678
679#ifdef CONFIG_IGB_DCA
680 dca_register_notify(&dca_notifier);
681#endif
682 ret = pci_register_driver(&igb_driver);
683 return ret;
684}
685
686module_init(igb_init_module);
687
688
689
690
691
692
693
694static void __exit igb_exit_module(void)
695{
696#ifdef CONFIG_IGB_DCA
697 dca_unregister_notify(&dca_notifier);
698#endif
699 pci_unregister_driver(&igb_driver);
700}
701
702module_exit(igb_exit_module);
703
704#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
705
706
707
708
709
710
711
712static void igb_cache_ring_register(struct igb_adapter *adapter)
713{
714 int i = 0, j = 0;
715 u32 rbase_offset = adapter->vfs_allocated_count;
716
717 switch (adapter->hw.mac.type) {
718 case e1000_82576:
719
720
721
722
723
724 if (adapter->vfs_allocated_count) {
725 for (; i < adapter->rss_queues; i++)
726 adapter->rx_ring[i]->reg_idx = rbase_offset +
727 Q_IDX_82576(i);
728 }
729
730 case e1000_82575:
731 case e1000_82580:
732 case e1000_i350:
733 case e1000_i354:
734 case e1000_i210:
735 case e1000_i211:
736
737 default:
738 for (; i < adapter->num_rx_queues; i++)
739 adapter->rx_ring[i]->reg_idx = rbase_offset + i;
740 for (; j < adapter->num_tx_queues; j++)
741 adapter->tx_ring[j]->reg_idx = rbase_offset + j;
742 break;
743 }
744}
745
746u32 igb_rd32(struct e1000_hw *hw, u32 reg)
747{
748 struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw);
749 u8 __iomem *hw_addr = ACCESS_ONCE(hw->hw_addr);
750 u32 value = 0;
751
752 if (E1000_REMOVED(hw_addr))
753 return ~value;
754
755 value = readl(&hw_addr[reg]);
756
757
758 if (!(~value) && (!reg || !(~readl(hw_addr)))) {
759 struct net_device *netdev = igb->netdev;
760 hw->hw_addr = NULL;
761 netif_device_detach(netdev);
762 netdev_err(netdev, "PCIe link lost, device now detached\n");
763 }
764
765 return value;
766}
767
768
769
770
771
772
773
774
775
776
777
778
779
780static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
781 int index, int offset)
782{
783 u32 ivar = array_rd32(E1000_IVAR0, index);
784
785
786 ivar &= ~((u32)0xFF << offset);
787
788
789 ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
790
791 array_wr32(E1000_IVAR0, index, ivar);
792}
793
794#define IGB_N0_QUEUE -1
795static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
796{
797 struct igb_adapter *adapter = q_vector->adapter;
798 struct e1000_hw *hw = &adapter->hw;
799 int rx_queue = IGB_N0_QUEUE;
800 int tx_queue = IGB_N0_QUEUE;
801 u32 msixbm = 0;
802
803 if (q_vector->rx.ring)
804 rx_queue = q_vector->rx.ring->reg_idx;
805 if (q_vector->tx.ring)
806 tx_queue = q_vector->tx.ring->reg_idx;
807
808 switch (hw->mac.type) {
809 case e1000_82575:
810
811
812
813
814
815 if (rx_queue > IGB_N0_QUEUE)
816 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
817 if (tx_queue > IGB_N0_QUEUE)
818 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
819 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0)
820 msixbm |= E1000_EIMS_OTHER;
821 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
822 q_vector->eims_value = msixbm;
823 break;
824 case e1000_82576:
825
826
827
828
829
830 if (rx_queue > IGB_N0_QUEUE)
831 igb_write_ivar(hw, msix_vector,
832 rx_queue & 0x7,
833 (rx_queue & 0x8) << 1);
834 if (tx_queue > IGB_N0_QUEUE)
835 igb_write_ivar(hw, msix_vector,
836 tx_queue & 0x7,
837 ((tx_queue & 0x8) << 1) + 8);
838 q_vector->eims_value = 1 << msix_vector;
839 break;
840 case e1000_82580:
841 case e1000_i350:
842 case e1000_i354:
843 case e1000_i210:
844 case e1000_i211:
845
846
847
848
849
850
851 if (rx_queue > IGB_N0_QUEUE)
852 igb_write_ivar(hw, msix_vector,
853 rx_queue >> 1,
854 (rx_queue & 0x1) << 4);
855 if (tx_queue > IGB_N0_QUEUE)
856 igb_write_ivar(hw, msix_vector,
857 tx_queue >> 1,
858 ((tx_queue & 0x1) << 4) + 8);
859 q_vector->eims_value = 1 << msix_vector;
860 break;
861 default:
862 BUG();
863 break;
864 }
865
866
867 adapter->eims_enable_mask |= q_vector->eims_value;
868
869
870 q_vector->set_itr = 1;
871}
872
873
874
875
876
877
878
879
880static void igb_configure_msix(struct igb_adapter *adapter)
881{
882 u32 tmp;
883 int i, vector = 0;
884 struct e1000_hw *hw = &adapter->hw;
885
886 adapter->eims_enable_mask = 0;
887
888
889 switch (hw->mac.type) {
890 case e1000_82575:
891 tmp = rd32(E1000_CTRL_EXT);
892
893 tmp |= E1000_CTRL_EXT_PBA_CLR;
894
895
896 tmp |= E1000_CTRL_EXT_EIAME;
897 tmp |= E1000_CTRL_EXT_IRCA;
898
899 wr32(E1000_CTRL_EXT, tmp);
900
901
902 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER);
903 adapter->eims_other = E1000_EIMS_OTHER;
904
905 break;
906
907 case e1000_82576:
908 case e1000_82580:
909 case e1000_i350:
910 case e1000_i354:
911 case e1000_i210:
912 case e1000_i211:
913
914
915
916 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
917 E1000_GPIE_PBA | E1000_GPIE_EIAME |
918 E1000_GPIE_NSICR);
919
920
921 adapter->eims_other = 1 << vector;
922 tmp = (vector++ | E1000_IVAR_VALID) << 8;
923
924 wr32(E1000_IVAR_MISC, tmp);
925 break;
926 default:
927
928 break;
929 }
930
931 adapter->eims_enable_mask |= adapter->eims_other;
932
933 for (i = 0; i < adapter->num_q_vectors; i++)
934 igb_assign_vector(adapter->q_vector[i], vector++);
935
936 wrfl();
937}
938
939
940
941
942
943
944
945
946static int igb_request_msix(struct igb_adapter *adapter)
947{
948 struct net_device *netdev = adapter->netdev;
949 struct e1000_hw *hw = &adapter->hw;
950 int i, err = 0, vector = 0, free_vector = 0;
951
952 err = request_irq(adapter->msix_entries[vector].vector,
953 igb_msix_other, 0, netdev->name, adapter);
954 if (err)
955 goto err_out;
956
957 for (i = 0; i < adapter->num_q_vectors; i++) {
958 struct igb_q_vector *q_vector = adapter->q_vector[i];
959
960 vector++;
961
962 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector);
963
964 if (q_vector->rx.ring && q_vector->tx.ring)
965 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
966 q_vector->rx.ring->queue_index);
967 else if (q_vector->tx.ring)
968 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
969 q_vector->tx.ring->queue_index);
970 else if (q_vector->rx.ring)
971 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
972 q_vector->rx.ring->queue_index);
973 else
974 sprintf(q_vector->name, "%s-unused", netdev->name);
975
976 err = request_irq(adapter->msix_entries[vector].vector,
977 igb_msix_ring, 0, q_vector->name,
978 q_vector);
979 if (err)
980 goto err_free;
981 }
982
983 igb_configure_msix(adapter);
984 return 0;
985
986err_free:
987
988 free_irq(adapter->msix_entries[free_vector++].vector, adapter);
989
990 vector--;
991 for (i = 0; i < vector; i++) {
992 free_irq(adapter->msix_entries[free_vector++].vector,
993 adapter->q_vector[i]);
994 }
995err_out:
996 return err;
997}
998
999
1000
1001
1002
1003
1004
1005
1006static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx)
1007{
1008 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1009
1010 adapter->q_vector[v_idx] = NULL;
1011
1012
1013
1014
1015 if (q_vector)
1016 kfree_rcu(q_vector, rcu);
1017}
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx)
1028{
1029 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1030
1031
1032
1033
1034 if (!q_vector)
1035 return;
1036
1037 if (q_vector->tx.ring)
1038 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
1039
1040 if (q_vector->rx.ring)
1041 adapter->rx_ring[q_vector->rx.ring->queue_index] = NULL;
1042
1043 netif_napi_del(&q_vector->napi);
1044
1045}
1046
1047static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
1048{
1049 int v_idx = adapter->num_q_vectors;
1050
1051 if (adapter->flags & IGB_FLAG_HAS_MSIX)
1052 pci_disable_msix(adapter->pdev);
1053 else if (adapter->flags & IGB_FLAG_HAS_MSI)
1054 pci_disable_msi(adapter->pdev);
1055
1056 while (v_idx--)
1057 igb_reset_q_vector(adapter, v_idx);
1058}
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068static void igb_free_q_vectors(struct igb_adapter *adapter)
1069{
1070 int v_idx = adapter->num_q_vectors;
1071
1072 adapter->num_tx_queues = 0;
1073 adapter->num_rx_queues = 0;
1074 adapter->num_q_vectors = 0;
1075
1076 while (v_idx--) {
1077 igb_reset_q_vector(adapter, v_idx);
1078 igb_free_q_vector(adapter, v_idx);
1079 }
1080}
1081
1082
1083
1084
1085
1086
1087
1088
1089static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
1090{
1091 igb_free_q_vectors(adapter);
1092 igb_reset_interrupt_capability(adapter);
1093}
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix)
1104{
1105 int err;
1106 int numvecs, i;
1107
1108 if (!msix)
1109 goto msi_only;
1110 adapter->flags |= IGB_FLAG_HAS_MSIX;
1111
1112
1113 adapter->num_rx_queues = adapter->rss_queues;
1114 if (adapter->vfs_allocated_count)
1115 adapter->num_tx_queues = 1;
1116 else
1117 adapter->num_tx_queues = adapter->rss_queues;
1118
1119
1120 numvecs = adapter->num_rx_queues;
1121
1122
1123 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
1124 numvecs += adapter->num_tx_queues;
1125
1126
1127 adapter->num_q_vectors = numvecs;
1128
1129
1130 numvecs++;
1131 for (i = 0; i < numvecs; i++)
1132 adapter->msix_entries[i].entry = i;
1133
1134 err = pci_enable_msix_range(adapter->pdev,
1135 adapter->msix_entries,
1136 numvecs,
1137 numvecs);
1138 if (err > 0)
1139 return;
1140
1141 igb_reset_interrupt_capability(adapter);
1142
1143
1144msi_only:
1145 adapter->flags &= ~IGB_FLAG_HAS_MSIX;
1146#ifdef CONFIG_PCI_IOV
1147
1148 if (adapter->vf_data) {
1149 struct e1000_hw *hw = &adapter->hw;
1150
1151 pci_disable_sriov(adapter->pdev);
1152 msleep(500);
1153
1154 kfree(adapter->vf_data);
1155 adapter->vf_data = NULL;
1156 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
1157 wrfl();
1158 msleep(100);
1159 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1160 }
1161#endif
1162 adapter->vfs_allocated_count = 0;
1163 adapter->rss_queues = 1;
1164 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
1165 adapter->num_rx_queues = 1;
1166 adapter->num_tx_queues = 1;
1167 adapter->num_q_vectors = 1;
1168 if (!pci_enable_msi(adapter->pdev))
1169 adapter->flags |= IGB_FLAG_HAS_MSI;
1170}
1171
1172static void igb_add_ring(struct igb_ring *ring,
1173 struct igb_ring_container *head)
1174{
1175 head->ring = ring;
1176 head->count++;
1177}
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191static int igb_alloc_q_vector(struct igb_adapter *adapter,
1192 int v_count, int v_idx,
1193 int txr_count, int txr_idx,
1194 int rxr_count, int rxr_idx)
1195{
1196 struct igb_q_vector *q_vector;
1197 struct igb_ring *ring;
1198 int ring_count, size;
1199
1200
1201 if (txr_count > 1 || rxr_count > 1)
1202 return -ENOMEM;
1203
1204 ring_count = txr_count + rxr_count;
1205 size = sizeof(struct igb_q_vector) +
1206 (sizeof(struct igb_ring) * ring_count);
1207
1208
1209 q_vector = adapter->q_vector[v_idx];
1210 if (!q_vector) {
1211 q_vector = kzalloc(size, GFP_KERNEL);
1212 } else if (size > ksize(q_vector)) {
1213 kfree_rcu(q_vector, rcu);
1214 q_vector = kzalloc(size, GFP_KERNEL);
1215 } else {
1216 memset(q_vector, 0, size);
1217 }
1218 if (!q_vector)
1219 return -ENOMEM;
1220
1221
1222 netif_napi_add(adapter->netdev, &q_vector->napi,
1223 igb_poll, 64);
1224
1225
1226 adapter->q_vector[v_idx] = q_vector;
1227 q_vector->adapter = adapter;
1228
1229
1230 q_vector->tx.work_limit = adapter->tx_work_limit;
1231
1232
1233 q_vector->itr_register = adapter->hw.hw_addr + E1000_EITR(0);
1234 q_vector->itr_val = IGB_START_ITR;
1235
1236
1237 ring = q_vector->ring;
1238
1239
1240 if (rxr_count) {
1241
1242 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3)
1243 q_vector->itr_val = adapter->rx_itr_setting;
1244 } else {
1245
1246 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3)
1247 q_vector->itr_val = adapter->tx_itr_setting;
1248 }
1249
1250 if (txr_count) {
1251
1252 ring->dev = &adapter->pdev->dev;
1253 ring->netdev = adapter->netdev;
1254
1255
1256 ring->q_vector = q_vector;
1257
1258
1259 igb_add_ring(ring, &q_vector->tx);
1260
1261
1262 if (adapter->hw.mac.type == e1000_82575)
1263 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
1264
1265
1266 ring->count = adapter->tx_ring_count;
1267 ring->queue_index = txr_idx;
1268
1269 u64_stats_init(&ring->tx_syncp);
1270 u64_stats_init(&ring->tx_syncp2);
1271
1272
1273 adapter->tx_ring[txr_idx] = ring;
1274
1275
1276 ring++;
1277 }
1278
1279 if (rxr_count) {
1280
1281 ring->dev = &adapter->pdev->dev;
1282 ring->netdev = adapter->netdev;
1283
1284
1285 ring->q_vector = q_vector;
1286
1287
1288 igb_add_ring(ring, &q_vector->rx);
1289
1290
1291 if (adapter->hw.mac.type >= e1000_82576)
1292 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
1293
1294
1295
1296
1297 if (adapter->hw.mac.type >= e1000_i350)
1298 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
1299
1300
1301 ring->count = adapter->rx_ring_count;
1302 ring->queue_index = rxr_idx;
1303
1304 u64_stats_init(&ring->rx_syncp);
1305
1306
1307 adapter->rx_ring[rxr_idx] = ring;
1308 }
1309
1310 return 0;
1311}
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321static int igb_alloc_q_vectors(struct igb_adapter *adapter)
1322{
1323 int q_vectors = adapter->num_q_vectors;
1324 int rxr_remaining = adapter->num_rx_queues;
1325 int txr_remaining = adapter->num_tx_queues;
1326 int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1327 int err;
1328
1329 if (q_vectors >= (rxr_remaining + txr_remaining)) {
1330 for (; rxr_remaining; v_idx++) {
1331 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1332 0, 0, 1, rxr_idx);
1333
1334 if (err)
1335 goto err_out;
1336
1337
1338 rxr_remaining--;
1339 rxr_idx++;
1340 }
1341 }
1342
1343 for (; v_idx < q_vectors; v_idx++) {
1344 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1345 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
1346
1347 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1348 tqpv, txr_idx, rqpv, rxr_idx);
1349
1350 if (err)
1351 goto err_out;
1352
1353
1354 rxr_remaining -= rqpv;
1355 txr_remaining -= tqpv;
1356 rxr_idx++;
1357 txr_idx++;
1358 }
1359
1360 return 0;
1361
1362err_out:
1363 adapter->num_tx_queues = 0;
1364 adapter->num_rx_queues = 0;
1365 adapter->num_q_vectors = 0;
1366
1367 while (v_idx--)
1368 igb_free_q_vector(adapter, v_idx);
1369
1370 return -ENOMEM;
1371}
1372
1373
1374
1375
1376
1377
1378
1379
1380static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix)
1381{
1382 struct pci_dev *pdev = adapter->pdev;
1383 int err;
1384
1385 igb_set_interrupt_capability(adapter, msix);
1386
1387 err = igb_alloc_q_vectors(adapter);
1388 if (err) {
1389 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1390 goto err_alloc_q_vectors;
1391 }
1392
1393 igb_cache_ring_register(adapter);
1394
1395 return 0;
1396
1397err_alloc_q_vectors:
1398 igb_reset_interrupt_capability(adapter);
1399 return err;
1400}
1401
1402
1403
1404
1405
1406
1407
1408
1409static int igb_request_irq(struct igb_adapter *adapter)
1410{
1411 struct net_device *netdev = adapter->netdev;
1412 struct pci_dev *pdev = adapter->pdev;
1413 int err = 0;
1414
1415 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1416 err = igb_request_msix(adapter);
1417 if (!err)
1418 goto request_done;
1419
1420 igb_free_all_tx_resources(adapter);
1421 igb_free_all_rx_resources(adapter);
1422
1423 igb_clear_interrupt_scheme(adapter);
1424 err = igb_init_interrupt_scheme(adapter, false);
1425 if (err)
1426 goto request_done;
1427
1428 igb_setup_all_tx_resources(adapter);
1429 igb_setup_all_rx_resources(adapter);
1430 igb_configure(adapter);
1431 }
1432
1433 igb_assign_vector(adapter->q_vector[0], 0);
1434
1435 if (adapter->flags & IGB_FLAG_HAS_MSI) {
1436 err = request_irq(pdev->irq, igb_intr_msi, 0,
1437 netdev->name, adapter);
1438 if (!err)
1439 goto request_done;
1440
1441
1442 igb_reset_interrupt_capability(adapter);
1443 adapter->flags &= ~IGB_FLAG_HAS_MSI;
1444 }
1445
1446 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
1447 netdev->name, adapter);
1448
1449 if (err)
1450 dev_err(&pdev->dev, "Error %d getting interrupt\n",
1451 err);
1452
1453request_done:
1454 return err;
1455}
1456
1457static void igb_free_irq(struct igb_adapter *adapter)
1458{
1459 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1460 int vector = 0, i;
1461
1462 free_irq(adapter->msix_entries[vector++].vector, adapter);
1463
1464 for (i = 0; i < adapter->num_q_vectors; i++)
1465 free_irq(adapter->msix_entries[vector++].vector,
1466 adapter->q_vector[i]);
1467 } else {
1468 free_irq(adapter->pdev->irq, adapter);
1469 }
1470}
1471
1472
1473
1474
1475
1476static void igb_irq_disable(struct igb_adapter *adapter)
1477{
1478 struct e1000_hw *hw = &adapter->hw;
1479
1480
1481
1482
1483
1484 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1485 u32 regval = rd32(E1000_EIAM);
1486
1487 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1488 wr32(E1000_EIMC, adapter->eims_enable_mask);
1489 regval = rd32(E1000_EIAC);
1490 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
1491 }
1492
1493 wr32(E1000_IAM, 0);
1494 wr32(E1000_IMC, ~0);
1495 wrfl();
1496 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1497 int i;
1498
1499 for (i = 0; i < adapter->num_q_vectors; i++)
1500 synchronize_irq(adapter->msix_entries[i].vector);
1501 } else {
1502 synchronize_irq(adapter->pdev->irq);
1503 }
1504}
1505
1506
1507
1508
1509
1510static void igb_irq_enable(struct igb_adapter *adapter)
1511{
1512 struct e1000_hw *hw = &adapter->hw;
1513
1514 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1515 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
1516 u32 regval = rd32(E1000_EIAC);
1517
1518 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1519 regval = rd32(E1000_EIAM);
1520 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
1521 wr32(E1000_EIMS, adapter->eims_enable_mask);
1522 if (adapter->vfs_allocated_count) {
1523 wr32(E1000_MBVFIMR, 0xFF);
1524 ims |= E1000_IMS_VMMB;
1525 }
1526 wr32(E1000_IMS, ims);
1527 } else {
1528 wr32(E1000_IMS, IMS_ENABLE_MASK |
1529 E1000_IMS_DRSTA);
1530 wr32(E1000_IAM, IMS_ENABLE_MASK |
1531 E1000_IMS_DRSTA);
1532 }
1533}
1534
1535static void igb_update_mng_vlan(struct igb_adapter *adapter)
1536{
1537 struct e1000_hw *hw = &adapter->hw;
1538 u16 vid = adapter->hw.mng_cookie.vlan_id;
1539 u16 old_vid = adapter->mng_vlan_id;
1540
1541 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1542
1543 igb_vfta_set(hw, vid, true);
1544 adapter->mng_vlan_id = vid;
1545 } else {
1546 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1547 }
1548
1549 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1550 (vid != old_vid) &&
1551 !test_bit(old_vid, adapter->active_vlans)) {
1552
1553 igb_vfta_set(hw, old_vid, false);
1554 }
1555}
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565static void igb_release_hw_control(struct igb_adapter *adapter)
1566{
1567 struct e1000_hw *hw = &adapter->hw;
1568 u32 ctrl_ext;
1569
1570
1571 ctrl_ext = rd32(E1000_CTRL_EXT);
1572 wr32(E1000_CTRL_EXT,
1573 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1574}
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584static void igb_get_hw_control(struct igb_adapter *adapter)
1585{
1586 struct e1000_hw *hw = &adapter->hw;
1587 u32 ctrl_ext;
1588
1589
1590 ctrl_ext = rd32(E1000_CTRL_EXT);
1591 wr32(E1000_CTRL_EXT,
1592 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1593}
1594
1595
1596
1597
1598
1599static void igb_configure(struct igb_adapter *adapter)
1600{
1601 struct net_device *netdev = adapter->netdev;
1602 int i;
1603
1604 igb_get_hw_control(adapter);
1605 igb_set_rx_mode(netdev);
1606
1607 igb_restore_vlan(adapter);
1608
1609 igb_setup_tctl(adapter);
1610 igb_setup_mrqc(adapter);
1611 igb_setup_rctl(adapter);
1612
1613 igb_configure_tx(adapter);
1614 igb_configure_rx(adapter);
1615
1616 igb_rx_fifo_flush_82575(&adapter->hw);
1617
1618
1619
1620
1621
1622 for (i = 0; i < adapter->num_rx_queues; i++) {
1623 struct igb_ring *ring = adapter->rx_ring[i];
1624 igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
1625 }
1626}
1627
1628
1629
1630
1631
1632void igb_power_up_link(struct igb_adapter *adapter)
1633{
1634 igb_reset_phy(&adapter->hw);
1635
1636 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1637 igb_power_up_phy_copper(&adapter->hw);
1638 else
1639 igb_power_up_serdes_link_82575(&adapter->hw);
1640
1641 igb_setup_link(&adapter->hw);
1642}
1643
1644
1645
1646
1647
1648static void igb_power_down_link(struct igb_adapter *adapter)
1649{
1650 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1651 igb_power_down_phy_copper_82575(&adapter->hw);
1652 else
1653 igb_shutdown_serdes_link_82575(&adapter->hw);
1654}
1655
1656
1657
1658
1659
1660static void igb_check_swap_media(struct igb_adapter *adapter)
1661{
1662 struct e1000_hw *hw = &adapter->hw;
1663 u32 ctrl_ext, connsw;
1664 bool swap_now = false;
1665
1666 ctrl_ext = rd32(E1000_CTRL_EXT);
1667 connsw = rd32(E1000_CONNSW);
1668
1669
1670
1671
1672
1673 if ((hw->phy.media_type == e1000_media_type_copper) &&
1674 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) {
1675 swap_now = true;
1676 } else if (!(connsw & E1000_CONNSW_SERDESD)) {
1677
1678 if (adapter->copper_tries < 4) {
1679 adapter->copper_tries++;
1680 connsw |= E1000_CONNSW_AUTOSENSE_CONF;
1681 wr32(E1000_CONNSW, connsw);
1682 return;
1683 } else {
1684 adapter->copper_tries = 0;
1685 if ((connsw & E1000_CONNSW_PHYSD) &&
1686 (!(connsw & E1000_CONNSW_PHY_PDN))) {
1687 swap_now = true;
1688 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF;
1689 wr32(E1000_CONNSW, connsw);
1690 }
1691 }
1692 }
1693
1694 if (!swap_now)
1695 return;
1696
1697 switch (hw->phy.media_type) {
1698 case e1000_media_type_copper:
1699 netdev_info(adapter->netdev,
1700 "MAS: changing media to fiber/serdes\n");
1701 ctrl_ext |=
1702 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1703 adapter->flags |= IGB_FLAG_MEDIA_RESET;
1704 adapter->copper_tries = 0;
1705 break;
1706 case e1000_media_type_internal_serdes:
1707 case e1000_media_type_fiber:
1708 netdev_info(adapter->netdev,
1709 "MAS: changing media to copper\n");
1710 ctrl_ext &=
1711 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1712 adapter->flags |= IGB_FLAG_MEDIA_RESET;
1713 break;
1714 default:
1715
1716 netdev_err(adapter->netdev,
1717 "AMS: Invalid media type found, returning\n");
1718 break;
1719 }
1720 wr32(E1000_CTRL_EXT, ctrl_ext);
1721}
1722
1723
1724
1725
1726
1727int igb_up(struct igb_adapter *adapter)
1728{
1729 struct e1000_hw *hw = &adapter->hw;
1730 int i;
1731
1732
1733 igb_configure(adapter);
1734
1735 clear_bit(__IGB_DOWN, &adapter->state);
1736
1737 for (i = 0; i < adapter->num_q_vectors; i++)
1738 napi_enable(&(adapter->q_vector[i]->napi));
1739
1740 if (adapter->flags & IGB_FLAG_HAS_MSIX)
1741 igb_configure_msix(adapter);
1742 else
1743 igb_assign_vector(adapter->q_vector[0], 0);
1744
1745
1746 rd32(E1000_ICR);
1747 igb_irq_enable(adapter);
1748
1749
1750 if (adapter->vfs_allocated_count) {
1751 u32 reg_data = rd32(E1000_CTRL_EXT);
1752
1753 reg_data |= E1000_CTRL_EXT_PFRSTD;
1754 wr32(E1000_CTRL_EXT, reg_data);
1755 }
1756
1757 netif_tx_start_all_queues(adapter->netdev);
1758
1759
1760 hw->mac.get_link_status = 1;
1761 schedule_work(&adapter->watchdog_task);
1762
1763 if ((adapter->flags & IGB_FLAG_EEE) &&
1764 (!hw->dev_spec._82575.eee_disable))
1765 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T;
1766
1767 return 0;
1768}
1769
1770void igb_down(struct igb_adapter *adapter)
1771{
1772 struct net_device *netdev = adapter->netdev;
1773 struct e1000_hw *hw = &adapter->hw;
1774 u32 tctl, rctl;
1775 int i;
1776
1777
1778
1779
1780 set_bit(__IGB_DOWN, &adapter->state);
1781
1782
1783 rctl = rd32(E1000_RCTL);
1784 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1785
1786
1787 netif_carrier_off(netdev);
1788 netif_tx_stop_all_queues(netdev);
1789
1790
1791 tctl = rd32(E1000_TCTL);
1792 tctl &= ~E1000_TCTL_EN;
1793 wr32(E1000_TCTL, tctl);
1794
1795 wrfl();
1796 usleep_range(10000, 11000);
1797
1798 igb_irq_disable(adapter);
1799
1800 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
1801
1802 for (i = 0; i < adapter->num_q_vectors; i++) {
1803 if (adapter->q_vector[i]) {
1804 napi_synchronize(&adapter->q_vector[i]->napi);
1805 napi_disable(&adapter->q_vector[i]->napi);
1806 }
1807 }
1808
1809 del_timer_sync(&adapter->watchdog_timer);
1810 del_timer_sync(&adapter->phy_info_timer);
1811
1812
1813 spin_lock(&adapter->stats64_lock);
1814 igb_update_stats(adapter, &adapter->stats64);
1815 spin_unlock(&adapter->stats64_lock);
1816
1817 adapter->link_speed = 0;
1818 adapter->link_duplex = 0;
1819
1820 if (!pci_channel_offline(adapter->pdev))
1821 igb_reset(adapter);
1822 igb_clean_all_tx_rings(adapter);
1823 igb_clean_all_rx_rings(adapter);
1824#ifdef CONFIG_IGB_DCA
1825
1826
1827 igb_setup_dca(adapter);
1828#endif
1829}
1830
1831void igb_reinit_locked(struct igb_adapter *adapter)
1832{
1833 WARN_ON(in_interrupt());
1834 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1835 usleep_range(1000, 2000);
1836 igb_down(adapter);
1837 igb_up(adapter);
1838 clear_bit(__IGB_RESETTING, &adapter->state);
1839}
1840
1841
1842
1843
1844
1845static void igb_enable_mas(struct igb_adapter *adapter)
1846{
1847 struct e1000_hw *hw = &adapter->hw;
1848 u32 connsw = rd32(E1000_CONNSW);
1849
1850
1851 if ((hw->phy.media_type == e1000_media_type_copper) &&
1852 (!(connsw & E1000_CONNSW_SERDESD))) {
1853 connsw |= E1000_CONNSW_ENRGSRC;
1854 connsw |= E1000_CONNSW_AUTOSENSE_EN;
1855 wr32(E1000_CONNSW, connsw);
1856 wrfl();
1857 }
1858}
1859
1860void igb_reset(struct igb_adapter *adapter)
1861{
1862 struct pci_dev *pdev = adapter->pdev;
1863 struct e1000_hw *hw = &adapter->hw;
1864 struct e1000_mac_info *mac = &hw->mac;
1865 struct e1000_fc_info *fc = &hw->fc;
1866 u32 pba = 0, tx_space, min_tx_space, min_rx_space, hwm;
1867
1868
1869
1870
1871 switch (mac->type) {
1872 case e1000_i350:
1873 case e1000_i354:
1874 case e1000_82580:
1875 pba = rd32(E1000_RXPBS);
1876 pba = igb_rxpbs_adjust_82580(pba);
1877 break;
1878 case e1000_82576:
1879 pba = rd32(E1000_RXPBS);
1880 pba &= E1000_RXPBS_SIZE_MASK_82576;
1881 break;
1882 case e1000_82575:
1883 case e1000_i210:
1884 case e1000_i211:
1885 default:
1886 pba = E1000_PBA_34K;
1887 break;
1888 }
1889
1890 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1891 (mac->type < e1000_82576)) {
1892
1893 wr32(E1000_PBA, pba);
1894
1895
1896
1897
1898
1899
1900
1901
1902 pba = rd32(E1000_PBA);
1903
1904 tx_space = pba >> 16;
1905
1906 pba &= 0xffff;
1907
1908
1909
1910 min_tx_space = (adapter->max_frame_size +
1911 sizeof(union e1000_adv_tx_desc) -
1912 ETH_FCS_LEN) * 2;
1913 min_tx_space = ALIGN(min_tx_space, 1024);
1914 min_tx_space >>= 10;
1915
1916 min_rx_space = adapter->max_frame_size;
1917 min_rx_space = ALIGN(min_rx_space, 1024);
1918 min_rx_space >>= 10;
1919
1920
1921
1922
1923
1924 if (tx_space < min_tx_space &&
1925 ((min_tx_space - tx_space) < pba)) {
1926 pba = pba - (min_tx_space - tx_space);
1927
1928
1929
1930
1931 if (pba < min_rx_space)
1932 pba = min_rx_space;
1933 }
1934 wr32(E1000_PBA, pba);
1935 }
1936
1937
1938
1939
1940
1941
1942
1943
1944 hwm = min(((pba << 10) * 9 / 10),
1945 ((pba << 10) - 2 * adapter->max_frame_size));
1946
1947 fc->high_water = hwm & 0xFFFFFFF0;
1948 fc->low_water = fc->high_water - 16;
1949 fc->pause_time = 0xFFFF;
1950 fc->send_xon = 1;
1951 fc->current_mode = fc->requested_mode;
1952
1953
1954 if (adapter->vfs_allocated_count) {
1955 int i;
1956
1957 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
1958 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
1959
1960
1961 igb_ping_all_vfs(adapter);
1962
1963
1964 wr32(E1000_VFRE, 0);
1965 wr32(E1000_VFTE, 0);
1966 }
1967
1968
1969 hw->mac.ops.reset_hw(hw);
1970 wr32(E1000_WUC, 0);
1971
1972 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
1973
1974 adapter->ei.get_invariants(hw);
1975 adapter->flags &= ~IGB_FLAG_MEDIA_RESET;
1976 }
1977 if ((mac->type == e1000_82575) &&
1978 (adapter->flags & IGB_FLAG_MAS_ENABLE)) {
1979 igb_enable_mas(adapter);
1980 }
1981 if (hw->mac.ops.init_hw(hw))
1982 dev_err(&pdev->dev, "Hardware Error\n");
1983
1984
1985
1986
1987 if (!hw->mac.autoneg)
1988 igb_force_mac_fc(hw);
1989
1990 igb_init_dmac(adapter, pba);
1991#ifdef CONFIG_IGB_HWMON
1992
1993 if (!test_bit(__IGB_DOWN, &adapter->state)) {
1994 if (mac->type == e1000_i350 && hw->bus.func == 0) {
1995
1996
1997
1998 if (adapter->ets)
1999 mac->ops.init_thermal_sensor_thresh(hw);
2000 }
2001 }
2002#endif
2003
2004 if (hw->phy.media_type == e1000_media_type_copper) {
2005 switch (mac->type) {
2006 case e1000_i350:
2007 case e1000_i210:
2008 case e1000_i211:
2009 igb_set_eee_i350(hw, true, true);
2010 break;
2011 case e1000_i354:
2012 igb_set_eee_i354(hw, true, true);
2013 break;
2014 default:
2015 break;
2016 }
2017 }
2018 if (!netif_running(adapter->netdev))
2019 igb_power_down_link(adapter);
2020
2021 igb_update_mng_vlan(adapter);
2022
2023
2024 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
2025
2026
2027 igb_ptp_reset(adapter);
2028
2029 igb_get_phy_info(hw);
2030}
2031
2032static netdev_features_t igb_fix_features(struct net_device *netdev,
2033 netdev_features_t features)
2034{
2035
2036
2037
2038 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2039 features |= NETIF_F_HW_VLAN_CTAG_TX;
2040 else
2041 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
2042
2043 return features;
2044}
2045
2046static int igb_set_features(struct net_device *netdev,
2047 netdev_features_t features)
2048{
2049 netdev_features_t changed = netdev->features ^ features;
2050 struct igb_adapter *adapter = netdev_priv(netdev);
2051
2052 if (changed & NETIF_F_HW_VLAN_CTAG_RX)
2053 igb_vlan_mode(netdev, features);
2054
2055 if (!(changed & NETIF_F_RXALL))
2056 return 0;
2057
2058 netdev->features = features;
2059
2060 if (netif_running(netdev))
2061 igb_reinit_locked(adapter);
2062 else
2063 igb_reset(adapter);
2064
2065 return 0;
2066}
2067
2068static const struct net_device_ops igb_netdev_ops = {
2069 .ndo_open = igb_open,
2070 .ndo_stop = igb_close,
2071 .ndo_start_xmit = igb_xmit_frame,
2072 .ndo_get_stats64 = igb_get_stats64,
2073 .ndo_set_rx_mode = igb_set_rx_mode,
2074 .ndo_set_mac_address = igb_set_mac,
2075 .ndo_change_mtu = igb_change_mtu,
2076 .ndo_do_ioctl = igb_ioctl,
2077 .ndo_tx_timeout = igb_tx_timeout,
2078 .ndo_validate_addr = eth_validate_addr,
2079 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
2080 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
2081 .ndo_set_vf_mac = igb_ndo_set_vf_mac,
2082 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan,
2083 .ndo_set_vf_rate = igb_ndo_set_vf_bw,
2084 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk,
2085 .ndo_get_vf_config = igb_ndo_get_vf_config,
2086#ifdef CONFIG_NET_POLL_CONTROLLER
2087 .ndo_poll_controller = igb_netpoll,
2088#endif
2089 .ndo_fix_features = igb_fix_features,
2090 .ndo_set_features = igb_set_features,
2091 .ndo_features_check = passthru_features_check,
2092};
2093
2094
2095
2096
2097
2098void igb_set_fw_version(struct igb_adapter *adapter)
2099{
2100 struct e1000_hw *hw = &adapter->hw;
2101 struct e1000_fw_version fw;
2102
2103 igb_get_fw_version(hw, &fw);
2104
2105 switch (hw->mac.type) {
2106 case e1000_i210:
2107 case e1000_i211:
2108 if (!(igb_get_flash_presence_i210(hw))) {
2109 snprintf(adapter->fw_version,
2110 sizeof(adapter->fw_version),
2111 "%2d.%2d-%d",
2112 fw.invm_major, fw.invm_minor,
2113 fw.invm_img_type);
2114 break;
2115 }
2116
2117 default:
2118
2119 if (fw.or_valid) {
2120 snprintf(adapter->fw_version,
2121 sizeof(adapter->fw_version),
2122 "%d.%d, 0x%08x, %d.%d.%d",
2123 fw.eep_major, fw.eep_minor, fw.etrack_id,
2124 fw.or_major, fw.or_build, fw.or_patch);
2125
2126 } else if (fw.etrack_id != 0X0000) {
2127 snprintf(adapter->fw_version,
2128 sizeof(adapter->fw_version),
2129 "%d.%d, 0x%08x",
2130 fw.eep_major, fw.eep_minor, fw.etrack_id);
2131 } else {
2132 snprintf(adapter->fw_version,
2133 sizeof(adapter->fw_version),
2134 "%d.%d.%d",
2135 fw.eep_major, fw.eep_minor, fw.eep_build);
2136 }
2137 break;
2138 }
2139}
2140
2141
2142
2143
2144
2145
2146static void igb_init_mas(struct igb_adapter *adapter)
2147{
2148 struct e1000_hw *hw = &adapter->hw;
2149 u16 eeprom_data;
2150
2151 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data);
2152 switch (hw->bus.func) {
2153 case E1000_FUNC_0:
2154 if (eeprom_data & IGB_MAS_ENABLE_0) {
2155 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2156 netdev_info(adapter->netdev,
2157 "MAS: Enabling Media Autosense for port %d\n",
2158 hw->bus.func);
2159 }
2160 break;
2161 case E1000_FUNC_1:
2162 if (eeprom_data & IGB_MAS_ENABLE_1) {
2163 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2164 netdev_info(adapter->netdev,
2165 "MAS: Enabling Media Autosense for port %d\n",
2166 hw->bus.func);
2167 }
2168 break;
2169 case E1000_FUNC_2:
2170 if (eeprom_data & IGB_MAS_ENABLE_2) {
2171 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2172 netdev_info(adapter->netdev,
2173 "MAS: Enabling Media Autosense for port %d\n",
2174 hw->bus.func);
2175 }
2176 break;
2177 case E1000_FUNC_3:
2178 if (eeprom_data & IGB_MAS_ENABLE_3) {
2179 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2180 netdev_info(adapter->netdev,
2181 "MAS: Enabling Media Autosense for port %d\n",
2182 hw->bus.func);
2183 }
2184 break;
2185 default:
2186
2187 netdev_err(adapter->netdev,
2188 "MAS: Invalid port configuration, returning\n");
2189 break;
2190 }
2191}
2192
2193
2194
2195
2196
2197static s32 igb_init_i2c(struct igb_adapter *adapter)
2198{
2199 s32 status = 0;
2200
2201
2202 if (adapter->hw.mac.type != e1000_i350)
2203 return 0;
2204
2205
2206
2207
2208
2209 adapter->i2c_adap.owner = THIS_MODULE;
2210 adapter->i2c_algo = igb_i2c_algo;
2211 adapter->i2c_algo.data = adapter;
2212 adapter->i2c_adap.algo_data = &adapter->i2c_algo;
2213 adapter->i2c_adap.dev.parent = &adapter->pdev->dev;
2214 strlcpy(adapter->i2c_adap.name, "igb BB",
2215 sizeof(adapter->i2c_adap.name));
2216 status = i2c_bit_add_bus(&adapter->i2c_adap);
2217 return status;
2218}
2219
2220
2221
2222
2223
2224
2225
2226
2227
2228
2229
2230
2231static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2232{
2233 struct net_device *netdev;
2234 struct igb_adapter *adapter;
2235 struct e1000_hw *hw;
2236 u16 eeprom_data = 0;
2237 s32 ret_val;
2238 static int global_quad_port_a;
2239 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
2240 int err, pci_using_dac;
2241 u8 part_str[E1000_PBANUM_LENGTH];
2242
2243
2244
2245
2246 if (pdev->is_virtfn) {
2247 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
2248 pci_name(pdev), pdev->vendor, pdev->device);
2249 return -EINVAL;
2250 }
2251
2252 err = pci_enable_device_mem(pdev);
2253 if (err)
2254 return err;
2255
2256 pci_using_dac = 0;
2257 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
2258 if (!err) {
2259 pci_using_dac = 1;
2260 } else {
2261 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
2262 if (err) {
2263 dev_err(&pdev->dev,
2264 "No usable DMA configuration, aborting\n");
2265 goto err_dma;
2266 }
2267 }
2268
2269 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
2270 IORESOURCE_MEM),
2271 igb_driver_name);
2272 if (err)
2273 goto err_pci_reg;
2274
2275 pci_enable_pcie_error_reporting(pdev);
2276
2277 pci_set_master(pdev);
2278 pci_save_state(pdev);
2279
2280 err = -ENOMEM;
2281 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
2282 IGB_MAX_TX_QUEUES);
2283 if (!netdev)
2284 goto err_alloc_etherdev;
2285
2286 SET_NETDEV_DEV(netdev, &pdev->dev);
2287
2288 pci_set_drvdata(pdev, netdev);
2289 adapter = netdev_priv(netdev);
2290 adapter->netdev = netdev;
2291 adapter->pdev = pdev;
2292 hw = &adapter->hw;
2293 hw->back = adapter;
2294 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
2295
2296 err = -EIO;
2297 hw->hw_addr = pci_iomap(pdev, 0, 0);
2298 if (!hw->hw_addr)
2299 goto err_ioremap;
2300
2301 netdev->netdev_ops = &igb_netdev_ops;
2302 igb_set_ethtool_ops(netdev);
2303 netdev->watchdog_timeo = 5 * HZ;
2304
2305 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
2306
2307 netdev->mem_start = pci_resource_start(pdev, 0);
2308 netdev->mem_end = pci_resource_end(pdev, 0);
2309
2310
2311 hw->vendor_id = pdev->vendor;
2312 hw->device_id = pdev->device;
2313 hw->revision_id = pdev->revision;
2314 hw->subsystem_vendor_id = pdev->subsystem_vendor;
2315 hw->subsystem_device_id = pdev->subsystem_device;
2316
2317
2318 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
2319 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
2320 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
2321
2322 err = ei->get_invariants(hw);
2323 if (err)
2324 goto err_sw_init;
2325
2326
2327 err = igb_sw_init(adapter);
2328 if (err)
2329 goto err_sw_init;
2330
2331 igb_get_bus_info_pcie(hw);
2332
2333 hw->phy.autoneg_wait_to_complete = false;
2334
2335
2336 if (hw->phy.media_type == e1000_media_type_copper) {
2337 hw->phy.mdix = AUTO_ALL_MODES;
2338 hw->phy.disable_polarity_correction = false;
2339 hw->phy.ms_type = e1000_ms_hw_default;
2340 }
2341
2342 if (igb_check_reset_block(hw))
2343 dev_info(&pdev->dev,
2344 "PHY reset is blocked due to SOL/IDER session.\n");
2345
2346
2347
2348
2349
2350 netdev->features |= NETIF_F_SG |
2351 NETIF_F_IP_CSUM |
2352 NETIF_F_IPV6_CSUM |
2353 NETIF_F_TSO |
2354 NETIF_F_TSO6 |
2355 NETIF_F_RXHASH |
2356 NETIF_F_RXCSUM |
2357 NETIF_F_HW_VLAN_CTAG_RX |
2358 NETIF_F_HW_VLAN_CTAG_TX;
2359
2360
2361 netdev->hw_features |= netdev->features;
2362 netdev->hw_features |= NETIF_F_RXALL;
2363
2364
2365 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2366
2367 netdev->vlan_features |= NETIF_F_TSO |
2368 NETIF_F_TSO6 |
2369 NETIF_F_IP_CSUM |
2370 NETIF_F_IPV6_CSUM |
2371 NETIF_F_SG;
2372
2373 netdev->priv_flags |= IFF_SUPP_NOFCS;
2374
2375 if (pci_using_dac) {
2376 netdev->features |= NETIF_F_HIGHDMA;
2377 netdev->vlan_features |= NETIF_F_HIGHDMA;
2378 }
2379
2380 if (hw->mac.type >= e1000_82576) {
2381 netdev->hw_features |= NETIF_F_SCTP_CSUM;
2382 netdev->features |= NETIF_F_SCTP_CSUM;
2383 }
2384
2385 netdev->priv_flags |= IFF_UNICAST_FLT;
2386
2387 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
2388
2389
2390
2391
2392 hw->mac.ops.reset_hw(hw);
2393
2394
2395
2396
2397 switch (hw->mac.type) {
2398 case e1000_i210:
2399 case e1000_i211:
2400 if (igb_get_flash_presence_i210(hw)) {
2401 if (hw->nvm.ops.validate(hw) < 0) {
2402 dev_err(&pdev->dev,
2403 "The NVM Checksum Is Not Valid\n");
2404 err = -EIO;
2405 goto err_eeprom;
2406 }
2407 }
2408 break;
2409 default:
2410 if (hw->nvm.ops.validate(hw) < 0) {
2411 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
2412 err = -EIO;
2413 goto err_eeprom;
2414 }
2415 break;
2416 }
2417
2418
2419 if (hw->mac.ops.read_mac_addr(hw))
2420 dev_err(&pdev->dev, "NVM Read Error\n");
2421
2422 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
2423
2424 if (!is_valid_ether_addr(netdev->dev_addr)) {
2425 dev_err(&pdev->dev, "Invalid MAC Address\n");
2426 err = -EIO;
2427 goto err_eeprom;
2428 }
2429
2430
2431 igb_set_fw_version(adapter);
2432
2433
2434 if (hw->mac.type == e1000_i210) {
2435 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT);
2436 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT);
2437 }
2438
2439 setup_timer(&adapter->watchdog_timer, igb_watchdog,
2440 (unsigned long) adapter);
2441 setup_timer(&adapter->phy_info_timer, igb_update_phy_info,
2442 (unsigned long) adapter);
2443
2444 INIT_WORK(&adapter->reset_task, igb_reset_task);
2445 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
2446
2447
2448 adapter->fc_autoneg = true;
2449 hw->mac.autoneg = true;
2450 hw->phy.autoneg_advertised = 0x2f;
2451
2452 hw->fc.requested_mode = e1000_fc_default;
2453 hw->fc.current_mode = e1000_fc_default;
2454
2455 igb_validate_mdi_setting(hw);
2456
2457
2458 if (hw->bus.func == 0)
2459 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2460
2461
2462 if (hw->mac.type >= e1000_82580)
2463 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2464 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2465 &eeprom_data);
2466 else if (hw->bus.func == 1)
2467 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
2468
2469 if (eeprom_data & IGB_EEPROM_APME)
2470 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2471
2472
2473
2474
2475
2476 switch (pdev->device) {
2477 case E1000_DEV_ID_82575GB_QUAD_COPPER:
2478 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2479 break;
2480 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2481 case E1000_DEV_ID_82576_FIBER:
2482 case E1000_DEV_ID_82576_SERDES:
2483
2484
2485
2486 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
2487 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2488 break;
2489 case E1000_DEV_ID_82576_QUAD_COPPER:
2490 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
2491
2492 if (global_quad_port_a != 0)
2493 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2494 else
2495 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
2496
2497 if (++global_quad_port_a == 4)
2498 global_quad_port_a = 0;
2499 break;
2500 default:
2501
2502 if (!device_can_wakeup(&adapter->pdev->dev))
2503 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2504 }
2505
2506
2507 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED)
2508 adapter->wol |= E1000_WUFC_MAG;
2509
2510
2511 if ((hw->mac.type == e1000_i350) &&
2512 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
2513 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2514 adapter->wol = 0;
2515 }
2516
2517 device_set_wakeup_enable(&adapter->pdev->dev,
2518 adapter->flags & IGB_FLAG_WOL_SUPPORTED);
2519
2520
2521 igb_reset(adapter);
2522
2523
2524 err = igb_init_i2c(adapter);
2525 if (err) {
2526 dev_err(&pdev->dev, "failed to init i2c interface\n");
2527 goto err_eeprom;
2528 }
2529
2530
2531
2532
2533 igb_get_hw_control(adapter);
2534
2535 strcpy(netdev->name, "eth%d");
2536 err = register_netdev(netdev);
2537 if (err)
2538 goto err_register;
2539
2540
2541 netif_carrier_off(netdev);
2542
2543#ifdef CONFIG_IGB_DCA
2544 if (dca_add_requester(&pdev->dev) == 0) {
2545 adapter->flags |= IGB_FLAG_DCA_ENABLED;
2546 dev_info(&pdev->dev, "DCA enabled\n");
2547 igb_setup_dca(adapter);
2548 }
2549
2550#endif
2551#ifdef CONFIG_IGB_HWMON
2552
2553 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) {
2554 u16 ets_word;
2555
2556
2557
2558
2559 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word);
2560 if (ets_word != 0x0000 && ets_word != 0xFFFF)
2561 adapter->ets = true;
2562 else
2563 adapter->ets = false;
2564 if (igb_sysfs_init(adapter))
2565 dev_err(&pdev->dev,
2566 "failed to allocate sysfs resources\n");
2567 } else {
2568 adapter->ets = false;
2569 }
2570#endif
2571
2572 adapter->ei = *ei;
2573 if (hw->dev_spec._82575.mas_capable)
2574 igb_init_mas(adapter);
2575
2576
2577 igb_ptp_init(adapter);
2578
2579 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
2580
2581 if (hw->mac.type != e1000_i354) {
2582 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
2583 netdev->name,
2584 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
2585 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
2586 "unknown"),
2587 ((hw->bus.width == e1000_bus_width_pcie_x4) ?
2588 "Width x4" :
2589 (hw->bus.width == e1000_bus_width_pcie_x2) ?
2590 "Width x2" :
2591 (hw->bus.width == e1000_bus_width_pcie_x1) ?
2592 "Width x1" : "unknown"), netdev->dev_addr);
2593 }
2594
2595 if ((hw->mac.type >= e1000_i210 ||
2596 igb_get_flash_presence_i210(hw))) {
2597 ret_val = igb_read_part_string(hw, part_str,
2598 E1000_PBANUM_LENGTH);
2599 } else {
2600 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND;
2601 }
2602
2603 if (ret_val)
2604 strcpy(part_str, "Unknown");
2605 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
2606 dev_info(&pdev->dev,
2607 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
2608 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" :
2609 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
2610 adapter->num_rx_queues, adapter->num_tx_queues);
2611 if (hw->phy.media_type == e1000_media_type_copper) {
2612 switch (hw->mac.type) {
2613 case e1000_i350:
2614 case e1000_i210:
2615 case e1000_i211:
2616
2617 err = igb_set_eee_i350(hw, true, true);
2618 if ((!err) &&
2619 (!hw->dev_spec._82575.eee_disable)) {
2620 adapter->eee_advert =
2621 MDIO_EEE_100TX | MDIO_EEE_1000T;
2622 adapter->flags |= IGB_FLAG_EEE;
2623 }
2624 break;
2625 case e1000_i354:
2626 if ((rd32(E1000_CTRL_EXT) &
2627 E1000_CTRL_EXT_LINK_MODE_SGMII)) {
2628 err = igb_set_eee_i354(hw, true, true);
2629 if ((!err) &&
2630 (!hw->dev_spec._82575.eee_disable)) {
2631 adapter->eee_advert =
2632 MDIO_EEE_100TX | MDIO_EEE_1000T;
2633 adapter->flags |= IGB_FLAG_EEE;
2634 }
2635 }
2636 break;
2637 default:
2638 break;
2639 }
2640 }
2641 pm_runtime_put_noidle(&pdev->dev);
2642 return 0;
2643
2644err_register:
2645 igb_release_hw_control(adapter);
2646 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap));
2647err_eeprom:
2648 if (!igb_check_reset_block(hw))
2649 igb_reset_phy(hw);
2650
2651 if (hw->flash_address)
2652 iounmap(hw->flash_address);
2653err_sw_init:
2654 kfree(adapter->shadow_vfta);
2655 igb_clear_interrupt_scheme(adapter);
2656#ifdef CONFIG_PCI_IOV
2657 igb_disable_sriov(pdev);
2658#endif
2659 pci_iounmap(pdev, hw->hw_addr);
2660err_ioremap:
2661 free_netdev(netdev);
2662err_alloc_etherdev:
2663 pci_release_selected_regions(pdev,
2664 pci_select_bars(pdev, IORESOURCE_MEM));
2665err_pci_reg:
2666err_dma:
2667 pci_disable_device(pdev);
2668 return err;
2669}
2670
2671#ifdef CONFIG_PCI_IOV
2672static int igb_disable_sriov(struct pci_dev *pdev)
2673{
2674 struct net_device *netdev = pci_get_drvdata(pdev);
2675 struct igb_adapter *adapter = netdev_priv(netdev);
2676 struct e1000_hw *hw = &adapter->hw;
2677
2678
2679 if (adapter->vf_data) {
2680
2681 if (pci_vfs_assigned(pdev)) {
2682 dev_warn(&pdev->dev,
2683 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n");
2684 return -EPERM;
2685 } else {
2686 pci_disable_sriov(pdev);
2687 msleep(500);
2688 }
2689
2690 kfree(adapter->vf_data);
2691 adapter->vf_data = NULL;
2692 adapter->vfs_allocated_count = 0;
2693 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
2694 wrfl();
2695 msleep(100);
2696 dev_info(&pdev->dev, "IOV Disabled\n");
2697
2698
2699 adapter->flags |= IGB_FLAG_DMAC;
2700 }
2701
2702 return 0;
2703}
2704
2705static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs)
2706{
2707 struct net_device *netdev = pci_get_drvdata(pdev);
2708 struct igb_adapter *adapter = netdev_priv(netdev);
2709 int old_vfs = pci_num_vf(pdev);
2710 int err = 0;
2711 int i;
2712
2713 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) {
2714 err = -EPERM;
2715 goto out;
2716 }
2717 if (!num_vfs)
2718 goto out;
2719
2720 if (old_vfs) {
2721 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n",
2722 old_vfs, max_vfs);
2723 adapter->vfs_allocated_count = old_vfs;
2724 } else
2725 adapter->vfs_allocated_count = num_vfs;
2726
2727 adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
2728 sizeof(struct vf_data_storage), GFP_KERNEL);
2729
2730
2731 if (!adapter->vf_data) {
2732 adapter->vfs_allocated_count = 0;
2733 dev_err(&pdev->dev,
2734 "Unable to allocate memory for VF Data Storage\n");
2735 err = -ENOMEM;
2736 goto out;
2737 }
2738
2739
2740 if (!old_vfs) {
2741 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count);
2742 if (err)
2743 goto err_out;
2744 }
2745 dev_info(&pdev->dev, "%d VFs allocated\n",
2746 adapter->vfs_allocated_count);
2747 for (i = 0; i < adapter->vfs_allocated_count; i++)
2748 igb_vf_configure(adapter, i);
2749
2750
2751 adapter->flags &= ~IGB_FLAG_DMAC;
2752 goto out;
2753
2754err_out:
2755 kfree(adapter->vf_data);
2756 adapter->vf_data = NULL;
2757 adapter->vfs_allocated_count = 0;
2758out:
2759 return err;
2760}
2761
2762#endif
2763
2764
2765
2766
2767static void igb_remove_i2c(struct igb_adapter *adapter)
2768{
2769
2770 i2c_del_adapter(&adapter->i2c_adap);
2771}
2772
2773
2774
2775
2776
2777
2778
2779
2780
2781
2782static void igb_remove(struct pci_dev *pdev)
2783{
2784 struct net_device *netdev = pci_get_drvdata(pdev);
2785 struct igb_adapter *adapter = netdev_priv(netdev);
2786 struct e1000_hw *hw = &adapter->hw;
2787
2788 pm_runtime_get_noresume(&pdev->dev);
2789#ifdef CONFIG_IGB_HWMON
2790 igb_sysfs_exit(adapter);
2791#endif
2792 igb_remove_i2c(adapter);
2793 igb_ptp_stop(adapter);
2794
2795
2796
2797 set_bit(__IGB_DOWN, &adapter->state);
2798 del_timer_sync(&adapter->watchdog_timer);
2799 del_timer_sync(&adapter->phy_info_timer);
2800
2801 cancel_work_sync(&adapter->reset_task);
2802 cancel_work_sync(&adapter->watchdog_task);
2803
2804#ifdef CONFIG_IGB_DCA
2805 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
2806 dev_info(&pdev->dev, "DCA disabled\n");
2807 dca_remove_requester(&pdev->dev);
2808 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
2809 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
2810 }
2811#endif
2812
2813
2814
2815
2816 igb_release_hw_control(adapter);
2817
2818#ifdef CONFIG_PCI_IOV
2819 igb_disable_sriov(pdev);
2820#endif
2821
2822 unregister_netdev(netdev);
2823
2824 igb_clear_interrupt_scheme(adapter);
2825
2826 pci_iounmap(pdev, hw->hw_addr);
2827 if (hw->flash_address)
2828 iounmap(hw->flash_address);
2829 pci_release_selected_regions(pdev,
2830 pci_select_bars(pdev, IORESOURCE_MEM));
2831
2832 kfree(adapter->shadow_vfta);
2833 free_netdev(netdev);
2834
2835 pci_disable_pcie_error_reporting(pdev);
2836
2837 pci_disable_device(pdev);
2838}
2839
2840
2841
2842
2843
2844
2845
2846
2847
2848
2849static void igb_probe_vfs(struct igb_adapter *adapter)
2850{
2851#ifdef CONFIG_PCI_IOV
2852 struct pci_dev *pdev = adapter->pdev;
2853 struct e1000_hw *hw = &adapter->hw;
2854
2855
2856 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
2857 return;
2858
2859 pci_sriov_set_totalvfs(pdev, 7);
2860 igb_enable_sriov(pdev, max_vfs);
2861
2862#endif
2863}
2864
2865static void igb_init_queue_configuration(struct igb_adapter *adapter)
2866{
2867 struct e1000_hw *hw = &adapter->hw;
2868 u32 max_rss_queues;
2869
2870
2871 switch (hw->mac.type) {
2872 case e1000_i211:
2873 max_rss_queues = IGB_MAX_RX_QUEUES_I211;
2874 break;
2875 case e1000_82575:
2876 case e1000_i210:
2877 max_rss_queues = IGB_MAX_RX_QUEUES_82575;
2878 break;
2879 case e1000_i350:
2880
2881 if (!!adapter->vfs_allocated_count) {
2882 max_rss_queues = 1;
2883 break;
2884 }
2885
2886 case e1000_82576:
2887 if (!!adapter->vfs_allocated_count) {
2888 max_rss_queues = 2;
2889 break;
2890 }
2891
2892 case e1000_82580:
2893 case e1000_i354:
2894 default:
2895 max_rss_queues = IGB_MAX_RX_QUEUES;
2896 break;
2897 }
2898
2899 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
2900
2901 igb_set_flag_queue_pairs(adapter, max_rss_queues);
2902}
2903
2904void igb_set_flag_queue_pairs(struct igb_adapter *adapter,
2905 const u32 max_rss_queues)
2906{
2907 struct e1000_hw *hw = &adapter->hw;
2908
2909
2910 switch (hw->mac.type) {
2911 case e1000_82575:
2912 case e1000_i211:
2913
2914 break;
2915 case e1000_82576:
2916
2917
2918
2919
2920 if ((adapter->rss_queues > 1) &&
2921 (adapter->vfs_allocated_count > 6))
2922 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2923
2924 case e1000_82580:
2925 case e1000_i350:
2926 case e1000_i354:
2927 case e1000_i210:
2928 default:
2929
2930
2931
2932 if (adapter->rss_queues > (max_rss_queues / 2))
2933 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2934 break;
2935 }
2936}
2937
2938
2939
2940
2941
2942
2943
2944
2945
2946static int igb_sw_init(struct igb_adapter *adapter)
2947{
2948 struct e1000_hw *hw = &adapter->hw;
2949 struct net_device *netdev = adapter->netdev;
2950 struct pci_dev *pdev = adapter->pdev;
2951
2952 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
2953
2954
2955 adapter->tx_ring_count = IGB_DEFAULT_TXD;
2956 adapter->rx_ring_count = IGB_DEFAULT_RXD;
2957
2958
2959 adapter->rx_itr_setting = IGB_DEFAULT_ITR;
2960 adapter->tx_itr_setting = IGB_DEFAULT_ITR;
2961
2962
2963 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
2964
2965 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
2966 VLAN_HLEN;
2967 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
2968
2969 spin_lock_init(&adapter->stats64_lock);
2970#ifdef CONFIG_PCI_IOV
2971 switch (hw->mac.type) {
2972 case e1000_82576:
2973 case e1000_i350:
2974 if (max_vfs > 7) {
2975 dev_warn(&pdev->dev,
2976 "Maximum of 7 VFs per PF, using max\n");
2977 max_vfs = adapter->vfs_allocated_count = 7;
2978 } else
2979 adapter->vfs_allocated_count = max_vfs;
2980 if (adapter->vfs_allocated_count)
2981 dev_warn(&pdev->dev,
2982 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n");
2983 break;
2984 default:
2985 break;
2986 }
2987#endif
2988
2989
2990 adapter->flags |= IGB_FLAG_HAS_MSIX;
2991
2992 igb_probe_vfs(adapter);
2993
2994 igb_init_queue_configuration(adapter);
2995
2996
2997 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32),
2998 GFP_ATOMIC);
2999
3000
3001 if (igb_init_interrupt_scheme(adapter, true)) {
3002 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
3003 return -ENOMEM;
3004 }
3005
3006
3007 igb_irq_disable(adapter);
3008
3009 if (hw->mac.type >= e1000_i350)
3010 adapter->flags &= ~IGB_FLAG_DMAC;
3011
3012 set_bit(__IGB_DOWN, &adapter->state);
3013 return 0;
3014}
3015
3016
3017
3018
3019
3020
3021
3022
3023
3024
3025
3026
3027
3028static int __igb_open(struct net_device *netdev, bool resuming)
3029{
3030 struct igb_adapter *adapter = netdev_priv(netdev);
3031 struct e1000_hw *hw = &adapter->hw;
3032 struct pci_dev *pdev = adapter->pdev;
3033 int err;
3034 int i;
3035
3036
3037 if (test_bit(__IGB_TESTING, &adapter->state)) {
3038 WARN_ON(resuming);
3039 return -EBUSY;
3040 }
3041
3042 if (!resuming)
3043 pm_runtime_get_sync(&pdev->dev);
3044
3045 netif_carrier_off(netdev);
3046
3047
3048 err = igb_setup_all_tx_resources(adapter);
3049 if (err)
3050 goto err_setup_tx;
3051
3052
3053 err = igb_setup_all_rx_resources(adapter);
3054 if (err)
3055 goto err_setup_rx;
3056
3057 igb_power_up_link(adapter);
3058
3059
3060
3061
3062
3063
3064 igb_configure(adapter);
3065
3066 err = igb_request_irq(adapter);
3067 if (err)
3068 goto err_req_irq;
3069
3070
3071 err = netif_set_real_num_tx_queues(adapter->netdev,
3072 adapter->num_tx_queues);
3073 if (err)
3074 goto err_set_queues;
3075
3076 err = netif_set_real_num_rx_queues(adapter->netdev,
3077 adapter->num_rx_queues);
3078 if (err)
3079 goto err_set_queues;
3080
3081
3082 clear_bit(__IGB_DOWN, &adapter->state);
3083
3084 for (i = 0; i < adapter->num_q_vectors; i++)
3085 napi_enable(&(adapter->q_vector[i]->napi));
3086
3087
3088 rd32(E1000_ICR);
3089
3090 igb_irq_enable(adapter);
3091
3092
3093 if (adapter->vfs_allocated_count) {
3094 u32 reg_data = rd32(E1000_CTRL_EXT);
3095
3096 reg_data |= E1000_CTRL_EXT_PFRSTD;
3097 wr32(E1000_CTRL_EXT, reg_data);
3098 }
3099
3100 netif_tx_start_all_queues(netdev);
3101
3102 if (!resuming)
3103 pm_runtime_put(&pdev->dev);
3104
3105
3106 hw->mac.get_link_status = 1;
3107 schedule_work(&adapter->watchdog_task);
3108
3109 return 0;
3110
3111err_set_queues:
3112 igb_free_irq(adapter);
3113err_req_irq:
3114 igb_release_hw_control(adapter);
3115 igb_power_down_link(adapter);
3116 igb_free_all_rx_resources(adapter);
3117err_setup_rx:
3118 igb_free_all_tx_resources(adapter);
3119err_setup_tx:
3120 igb_reset(adapter);
3121 if (!resuming)
3122 pm_runtime_put(&pdev->dev);
3123
3124 return err;
3125}
3126
3127static int igb_open(struct net_device *netdev)
3128{
3129 return __igb_open(netdev, false);
3130}
3131
3132
3133
3134
3135
3136
3137
3138
3139
3140
3141
3142
3143static int __igb_close(struct net_device *netdev, bool suspending)
3144{
3145 struct igb_adapter *adapter = netdev_priv(netdev);
3146 struct pci_dev *pdev = adapter->pdev;
3147
3148 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
3149
3150 if (!suspending)
3151 pm_runtime_get_sync(&pdev->dev);
3152
3153 igb_down(adapter);
3154 igb_free_irq(adapter);
3155
3156 igb_free_all_tx_resources(adapter);
3157 igb_free_all_rx_resources(adapter);
3158
3159 if (!suspending)
3160 pm_runtime_put_sync(&pdev->dev);
3161 return 0;
3162}
3163
3164static int igb_close(struct net_device *netdev)
3165{
3166 return __igb_close(netdev, false);
3167}
3168
3169
3170
3171
3172
3173
3174
3175int igb_setup_tx_resources(struct igb_ring *tx_ring)
3176{
3177 struct device *dev = tx_ring->dev;
3178 int size;
3179
3180 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3181
3182 tx_ring->tx_buffer_info = vzalloc(size);
3183 if (!tx_ring->tx_buffer_info)
3184 goto err;
3185
3186
3187 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
3188 tx_ring->size = ALIGN(tx_ring->size, 4096);
3189
3190 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
3191 &tx_ring->dma, GFP_KERNEL);
3192 if (!tx_ring->desc)
3193 goto err;
3194
3195 tx_ring->next_to_use = 0;
3196 tx_ring->next_to_clean = 0;
3197
3198 return 0;
3199
3200err:
3201 vfree(tx_ring->tx_buffer_info);
3202 tx_ring->tx_buffer_info = NULL;
3203 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
3204 return -ENOMEM;
3205}
3206
3207
3208
3209
3210
3211
3212
3213
3214static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
3215{
3216 struct pci_dev *pdev = adapter->pdev;
3217 int i, err = 0;
3218
3219 for (i = 0; i < adapter->num_tx_queues; i++) {
3220 err = igb_setup_tx_resources(adapter->tx_ring[i]);
3221 if (err) {
3222 dev_err(&pdev->dev,
3223 "Allocation for Tx Queue %u failed\n", i);
3224 for (i--; i >= 0; i--)
3225 igb_free_tx_resources(adapter->tx_ring[i]);
3226 break;
3227 }
3228 }
3229
3230 return err;
3231}
3232
3233
3234
3235
3236
3237void igb_setup_tctl(struct igb_adapter *adapter)
3238{
3239 struct e1000_hw *hw = &adapter->hw;
3240 u32 tctl;
3241
3242
3243 wr32(E1000_TXDCTL(0), 0);
3244
3245
3246 tctl = rd32(E1000_TCTL);
3247 tctl &= ~E1000_TCTL_CT;
3248 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
3249 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
3250
3251 igb_config_collision_dist(hw);
3252
3253
3254 tctl |= E1000_TCTL_EN;
3255
3256 wr32(E1000_TCTL, tctl);
3257}
3258
3259
3260
3261
3262
3263
3264
3265
3266void igb_configure_tx_ring(struct igb_adapter *adapter,
3267 struct igb_ring *ring)
3268{
3269 struct e1000_hw *hw = &adapter->hw;
3270 u32 txdctl = 0;
3271 u64 tdba = ring->dma;
3272 int reg_idx = ring->reg_idx;
3273
3274
3275 wr32(E1000_TXDCTL(reg_idx), 0);
3276 wrfl();
3277 mdelay(10);
3278
3279 wr32(E1000_TDLEN(reg_idx),
3280 ring->count * sizeof(union e1000_adv_tx_desc));
3281 wr32(E1000_TDBAL(reg_idx),
3282 tdba & 0x00000000ffffffffULL);
3283 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
3284
3285 ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
3286 wr32(E1000_TDH(reg_idx), 0);
3287 writel(0, ring->tail);
3288
3289 txdctl |= IGB_TX_PTHRESH;
3290 txdctl |= IGB_TX_HTHRESH << 8;
3291 txdctl |= IGB_TX_WTHRESH << 16;
3292
3293 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
3294 wr32(E1000_TXDCTL(reg_idx), txdctl);
3295}
3296
3297
3298
3299
3300
3301
3302
3303static void igb_configure_tx(struct igb_adapter *adapter)
3304{
3305 int i;
3306
3307 for (i = 0; i < adapter->num_tx_queues; i++)
3308 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
3309}
3310
3311
3312
3313
3314
3315
3316
3317int igb_setup_rx_resources(struct igb_ring *rx_ring)
3318{
3319 struct device *dev = rx_ring->dev;
3320 int size;
3321
3322 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3323
3324 rx_ring->rx_buffer_info = vzalloc(size);
3325 if (!rx_ring->rx_buffer_info)
3326 goto err;
3327
3328
3329 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
3330 rx_ring->size = ALIGN(rx_ring->size, 4096);
3331
3332 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
3333 &rx_ring->dma, GFP_KERNEL);
3334 if (!rx_ring->desc)
3335 goto err;
3336
3337 rx_ring->next_to_alloc = 0;
3338 rx_ring->next_to_clean = 0;
3339 rx_ring->next_to_use = 0;
3340
3341 return 0;
3342
3343err:
3344 vfree(rx_ring->rx_buffer_info);
3345 rx_ring->rx_buffer_info = NULL;
3346 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
3347 return -ENOMEM;
3348}
3349
3350
3351
3352
3353
3354
3355
3356
3357static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
3358{
3359 struct pci_dev *pdev = adapter->pdev;
3360 int i, err = 0;
3361
3362 for (i = 0; i < adapter->num_rx_queues; i++) {
3363 err = igb_setup_rx_resources(adapter->rx_ring[i]);
3364 if (err) {
3365 dev_err(&pdev->dev,
3366 "Allocation for Rx Queue %u failed\n", i);
3367 for (i--; i >= 0; i--)
3368 igb_free_rx_resources(adapter->rx_ring[i]);
3369 break;
3370 }
3371 }
3372
3373 return err;
3374}
3375
3376
3377
3378
3379
3380static void igb_setup_mrqc(struct igb_adapter *adapter)
3381{
3382 struct e1000_hw *hw = &adapter->hw;
3383 u32 mrqc, rxcsum;
3384 u32 j, num_rx_queues;
3385 u32 rss_key[10];
3386
3387 netdev_rss_key_fill(rss_key, sizeof(rss_key));
3388 for (j = 0; j < 10; j++)
3389 wr32(E1000_RSSRK(j), rss_key[j]);
3390
3391 num_rx_queues = adapter->rss_queues;
3392
3393 switch (hw->mac.type) {
3394 case e1000_82576:
3395
3396 if (adapter->vfs_allocated_count)
3397 num_rx_queues = 2;
3398 break;
3399 default:
3400 break;
3401 }
3402
3403 if (adapter->rss_indir_tbl_init != num_rx_queues) {
3404 for (j = 0; j < IGB_RETA_SIZE; j++)
3405 adapter->rss_indir_tbl[j] =
3406 (j * num_rx_queues) / IGB_RETA_SIZE;
3407 adapter->rss_indir_tbl_init = num_rx_queues;
3408 }
3409 igb_write_rss_indir_tbl(adapter);
3410
3411
3412
3413
3414
3415 rxcsum = rd32(E1000_RXCSUM);
3416 rxcsum |= E1000_RXCSUM_PCSD;
3417
3418 if (adapter->hw.mac.type >= e1000_82576)
3419
3420 rxcsum |= E1000_RXCSUM_CRCOFL;
3421
3422
3423 wr32(E1000_RXCSUM, rxcsum);
3424
3425
3426
3427
3428 mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
3429 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3430 E1000_MRQC_RSS_FIELD_IPV6 |
3431 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3432 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
3433
3434 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
3435 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
3436 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
3437 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
3438
3439
3440
3441
3442
3443 if (adapter->vfs_allocated_count) {
3444 if (hw->mac.type > e1000_82575) {
3445
3446 u32 vtctl = rd32(E1000_VT_CTL);
3447
3448 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
3449 E1000_VT_CTL_DISABLE_DEF_POOL);
3450 vtctl |= adapter->vfs_allocated_count <<
3451 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
3452 wr32(E1000_VT_CTL, vtctl);
3453 }
3454 if (adapter->rss_queues > 1)
3455 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
3456 else
3457 mrqc |= E1000_MRQC_ENABLE_VMDQ;
3458 } else {
3459 if (hw->mac.type != e1000_i211)
3460 mrqc |= E1000_MRQC_ENABLE_RSS_4Q;
3461 }
3462 igb_vmm_control(adapter);
3463
3464 wr32(E1000_MRQC, mrqc);
3465}
3466
3467
3468
3469
3470
3471void igb_setup_rctl(struct igb_adapter *adapter)
3472{
3473 struct e1000_hw *hw = &adapter->hw;
3474 u32 rctl;
3475
3476 rctl = rd32(E1000_RCTL);
3477
3478 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3479 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
3480
3481 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
3482 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
3483
3484
3485
3486
3487
3488 rctl |= E1000_RCTL_SECRC;
3489
3490
3491 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
3492
3493
3494 rctl |= E1000_RCTL_LPE;
3495
3496
3497 wr32(E1000_RXDCTL(0), 0);
3498
3499
3500
3501
3502
3503 if (adapter->vfs_allocated_count) {
3504
3505 wr32(E1000_QDE, ALL_QUEUES);
3506 }
3507
3508
3509 if (adapter->netdev->features & NETIF_F_RXALL) {
3510
3511
3512
3513 rctl |= (E1000_RCTL_SBP |
3514 E1000_RCTL_BAM |
3515 E1000_RCTL_PMCF);
3516
3517 rctl &= ~(E1000_RCTL_VFE |
3518 E1000_RCTL_DPF |
3519 E1000_RCTL_CFIEN);
3520
3521
3522
3523 }
3524
3525 wr32(E1000_RCTL, rctl);
3526}
3527
3528static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
3529 int vfn)
3530{
3531 struct e1000_hw *hw = &adapter->hw;
3532 u32 vmolr;
3533
3534
3535
3536
3537 if (vfn < adapter->vfs_allocated_count &&
3538 adapter->vf_data[vfn].vlans_enabled)
3539 size += VLAN_TAG_SIZE;
3540
3541 vmolr = rd32(E1000_VMOLR(vfn));
3542 vmolr &= ~E1000_VMOLR_RLPML_MASK;
3543 vmolr |= size | E1000_VMOLR_LPE;
3544 wr32(E1000_VMOLR(vfn), vmolr);
3545
3546 return 0;
3547}
3548
3549
3550
3551
3552
3553
3554
3555static void igb_rlpml_set(struct igb_adapter *adapter)
3556{
3557 u32 max_frame_size = adapter->max_frame_size;
3558 struct e1000_hw *hw = &adapter->hw;
3559 u16 pf_id = adapter->vfs_allocated_count;
3560
3561 if (pf_id) {
3562 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
3563
3564
3565
3566
3567
3568
3569 max_frame_size = MAX_JUMBO_FRAME_SIZE;
3570 }
3571
3572 wr32(E1000_RLPML, max_frame_size);
3573}
3574
3575static inline void igb_set_vmolr(struct igb_adapter *adapter,
3576 int vfn, bool aupe)
3577{
3578 struct e1000_hw *hw = &adapter->hw;
3579 u32 vmolr;
3580
3581
3582
3583
3584 if (hw->mac.type < e1000_82576)
3585 return;
3586
3587 vmolr = rd32(E1000_VMOLR(vfn));
3588 vmolr |= E1000_VMOLR_STRVLAN;
3589 if (hw->mac.type == e1000_i350) {
3590 u32 dvmolr;
3591
3592 dvmolr = rd32(E1000_DVMOLR(vfn));
3593 dvmolr |= E1000_DVMOLR_STRVLAN;
3594 wr32(E1000_DVMOLR(vfn), dvmolr);
3595 }
3596 if (aupe)
3597 vmolr |= E1000_VMOLR_AUPE;
3598 else
3599 vmolr &= ~(E1000_VMOLR_AUPE);
3600
3601
3602 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
3603
3604 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
3605 vmolr |= E1000_VMOLR_RSSE;
3606
3607
3608
3609 if (vfn <= adapter->vfs_allocated_count)
3610 vmolr |= E1000_VMOLR_BAM;
3611
3612 wr32(E1000_VMOLR(vfn), vmolr);
3613}
3614
3615
3616
3617
3618
3619
3620
3621
3622void igb_configure_rx_ring(struct igb_adapter *adapter,
3623 struct igb_ring *ring)
3624{
3625 struct e1000_hw *hw = &adapter->hw;
3626 u64 rdba = ring->dma;
3627 int reg_idx = ring->reg_idx;
3628 u32 srrctl = 0, rxdctl = 0;
3629
3630
3631 wr32(E1000_RXDCTL(reg_idx), 0);
3632
3633
3634 wr32(E1000_RDBAL(reg_idx),
3635 rdba & 0x00000000ffffffffULL);
3636 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
3637 wr32(E1000_RDLEN(reg_idx),
3638 ring->count * sizeof(union e1000_adv_rx_desc));
3639
3640
3641 ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
3642 wr32(E1000_RDH(reg_idx), 0);
3643 writel(0, ring->tail);
3644
3645
3646 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
3647 srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT;
3648 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
3649 if (hw->mac.type >= e1000_82580)
3650 srrctl |= E1000_SRRCTL_TIMESTAMP;
3651
3652 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
3653 srrctl |= E1000_SRRCTL_DROP_EN;
3654
3655 wr32(E1000_SRRCTL(reg_idx), srrctl);
3656
3657
3658 igb_set_vmolr(adapter, reg_idx & 0x7, true);
3659
3660 rxdctl |= IGB_RX_PTHRESH;
3661 rxdctl |= IGB_RX_HTHRESH << 8;
3662 rxdctl |= IGB_RX_WTHRESH << 16;
3663
3664
3665 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
3666 wr32(E1000_RXDCTL(reg_idx), rxdctl);
3667}
3668
3669
3670
3671
3672
3673
3674
3675static void igb_configure_rx(struct igb_adapter *adapter)
3676{
3677 int i;
3678
3679
3680 igb_set_uta(adapter);
3681
3682
3683 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
3684 adapter->vfs_allocated_count);
3685
3686
3687
3688
3689 for (i = 0; i < adapter->num_rx_queues; i++)
3690 igb_configure_rx_ring(adapter, adapter->rx_ring[i]);
3691}
3692
3693
3694
3695
3696
3697
3698
3699void igb_free_tx_resources(struct igb_ring *tx_ring)
3700{
3701 igb_clean_tx_ring(tx_ring);
3702
3703 vfree(tx_ring->tx_buffer_info);
3704 tx_ring->tx_buffer_info = NULL;
3705
3706
3707 if (!tx_ring->desc)
3708 return;
3709
3710 dma_free_coherent(tx_ring->dev, tx_ring->size,
3711 tx_ring->desc, tx_ring->dma);
3712
3713 tx_ring->desc = NULL;
3714}
3715
3716
3717
3718
3719
3720
3721
3722static void igb_free_all_tx_resources(struct igb_adapter *adapter)
3723{
3724 int i;
3725
3726 for (i = 0; i < adapter->num_tx_queues; i++)
3727 if (adapter->tx_ring[i])
3728 igb_free_tx_resources(adapter->tx_ring[i]);
3729}
3730
3731void igb_unmap_and_free_tx_resource(struct igb_ring *ring,
3732 struct igb_tx_buffer *tx_buffer)
3733{
3734 if (tx_buffer->skb) {
3735 dev_kfree_skb_any(tx_buffer->skb);
3736 if (dma_unmap_len(tx_buffer, len))
3737 dma_unmap_single(ring->dev,
3738 dma_unmap_addr(tx_buffer, dma),
3739 dma_unmap_len(tx_buffer, len),
3740 DMA_TO_DEVICE);
3741 } else if (dma_unmap_len(tx_buffer, len)) {
3742 dma_unmap_page(ring->dev,
3743 dma_unmap_addr(tx_buffer, dma),
3744 dma_unmap_len(tx_buffer, len),
3745 DMA_TO_DEVICE);
3746 }
3747 tx_buffer->next_to_watch = NULL;
3748 tx_buffer->skb = NULL;
3749 dma_unmap_len_set(tx_buffer, len, 0);
3750
3751}
3752
3753
3754
3755
3756
3757static void igb_clean_tx_ring(struct igb_ring *tx_ring)
3758{
3759 struct igb_tx_buffer *buffer_info;
3760 unsigned long size;
3761 u16 i;
3762
3763 if (!tx_ring->tx_buffer_info)
3764 return;
3765
3766
3767 for (i = 0; i < tx_ring->count; i++) {
3768 buffer_info = &tx_ring->tx_buffer_info[i];
3769 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
3770 }
3771
3772 netdev_tx_reset_queue(txring_txq(tx_ring));
3773
3774 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3775 memset(tx_ring->tx_buffer_info, 0, size);
3776
3777
3778 memset(tx_ring->desc, 0, tx_ring->size);
3779
3780 tx_ring->next_to_use = 0;
3781 tx_ring->next_to_clean = 0;
3782}
3783
3784
3785
3786
3787
3788static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
3789{
3790 int i;
3791
3792 for (i = 0; i < adapter->num_tx_queues; i++)
3793 if (adapter->tx_ring[i])
3794 igb_clean_tx_ring(adapter->tx_ring[i]);
3795}
3796
3797
3798
3799
3800
3801
3802
3803void igb_free_rx_resources(struct igb_ring *rx_ring)
3804{
3805 igb_clean_rx_ring(rx_ring);
3806
3807 vfree(rx_ring->rx_buffer_info);
3808 rx_ring->rx_buffer_info = NULL;
3809
3810
3811 if (!rx_ring->desc)
3812 return;
3813
3814 dma_free_coherent(rx_ring->dev, rx_ring->size,
3815 rx_ring->desc, rx_ring->dma);
3816
3817 rx_ring->desc = NULL;
3818}
3819
3820
3821
3822
3823
3824
3825
3826static void igb_free_all_rx_resources(struct igb_adapter *adapter)
3827{
3828 int i;
3829
3830 for (i = 0; i < adapter->num_rx_queues; i++)
3831 if (adapter->rx_ring[i])
3832 igb_free_rx_resources(adapter->rx_ring[i]);
3833}
3834
3835
3836
3837
3838
3839static void igb_clean_rx_ring(struct igb_ring *rx_ring)
3840{
3841 unsigned long size;
3842 u16 i;
3843
3844 if (rx_ring->skb)
3845 dev_kfree_skb(rx_ring->skb);
3846 rx_ring->skb = NULL;
3847
3848 if (!rx_ring->rx_buffer_info)
3849 return;
3850
3851
3852 for (i = 0; i < rx_ring->count; i++) {
3853 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
3854
3855 if (!buffer_info->page)
3856 continue;
3857
3858 dma_unmap_page(rx_ring->dev,
3859 buffer_info->dma,
3860 PAGE_SIZE,
3861 DMA_FROM_DEVICE);
3862 __free_page(buffer_info->page);
3863
3864 buffer_info->page = NULL;
3865 }
3866
3867 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3868 memset(rx_ring->rx_buffer_info, 0, size);
3869
3870
3871 memset(rx_ring->desc, 0, rx_ring->size);
3872
3873 rx_ring->next_to_alloc = 0;
3874 rx_ring->next_to_clean = 0;
3875 rx_ring->next_to_use = 0;
3876}
3877
3878
3879
3880
3881
3882static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
3883{
3884 int i;
3885
3886 for (i = 0; i < adapter->num_rx_queues; i++)
3887 if (adapter->rx_ring[i])
3888 igb_clean_rx_ring(adapter->rx_ring[i]);
3889}
3890
3891
3892
3893
3894
3895
3896
3897
3898static int igb_set_mac(struct net_device *netdev, void *p)
3899{
3900 struct igb_adapter *adapter = netdev_priv(netdev);
3901 struct e1000_hw *hw = &adapter->hw;
3902 struct sockaddr *addr = p;
3903
3904 if (!is_valid_ether_addr(addr->sa_data))
3905 return -EADDRNOTAVAIL;
3906
3907 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
3908 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
3909
3910
3911 igb_rar_set_qsel(adapter, hw->mac.addr, 0,
3912 adapter->vfs_allocated_count);
3913
3914 return 0;
3915}
3916
3917
3918
3919
3920
3921
3922
3923
3924
3925
3926static int igb_write_mc_addr_list(struct net_device *netdev)
3927{
3928 struct igb_adapter *adapter = netdev_priv(netdev);
3929 struct e1000_hw *hw = &adapter->hw;
3930 struct netdev_hw_addr *ha;
3931 u8 *mta_list;
3932 int i;
3933
3934 if (netdev_mc_empty(netdev)) {
3935
3936 igb_update_mc_addr_list(hw, NULL, 0);
3937 igb_restore_vf_multicasts(adapter);
3938 return 0;
3939 }
3940
3941 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
3942 if (!mta_list)
3943 return -ENOMEM;
3944
3945
3946 i = 0;
3947 netdev_for_each_mc_addr(ha, netdev)
3948 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
3949
3950 igb_update_mc_addr_list(hw, mta_list, i);
3951 kfree(mta_list);
3952
3953 return netdev_mc_count(netdev);
3954}
3955
3956
3957
3958
3959
3960
3961
3962
3963
3964
3965static int igb_write_uc_addr_list(struct net_device *netdev)
3966{
3967 struct igb_adapter *adapter = netdev_priv(netdev);
3968 struct e1000_hw *hw = &adapter->hw;
3969 unsigned int vfn = adapter->vfs_allocated_count;
3970 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
3971 int count = 0;
3972
3973
3974 if (netdev_uc_count(netdev) > rar_entries)
3975 return -ENOMEM;
3976
3977 if (!netdev_uc_empty(netdev) && rar_entries) {
3978 struct netdev_hw_addr *ha;
3979
3980 netdev_for_each_uc_addr(ha, netdev) {
3981 if (!rar_entries)
3982 break;
3983 igb_rar_set_qsel(adapter, ha->addr,
3984 rar_entries--,
3985 vfn);
3986 count++;
3987 }
3988 }
3989
3990 for (; rar_entries > 0 ; rar_entries--) {
3991 wr32(E1000_RAH(rar_entries), 0);
3992 wr32(E1000_RAL(rar_entries), 0);
3993 }
3994 wrfl();
3995
3996 return count;
3997}
3998
3999
4000
4001
4002
4003
4004
4005
4006
4007
4008static void igb_set_rx_mode(struct net_device *netdev)
4009{
4010 struct igb_adapter *adapter = netdev_priv(netdev);
4011 struct e1000_hw *hw = &adapter->hw;
4012 unsigned int vfn = adapter->vfs_allocated_count;
4013 u32 rctl, vmolr = 0;
4014 int count;
4015
4016
4017 rctl = rd32(E1000_RCTL);
4018
4019
4020 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);
4021
4022 if (netdev->flags & IFF_PROMISC) {
4023
4024 if (adapter->vfs_allocated_count)
4025 rctl |= E1000_RCTL_VFE;
4026 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
4027 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
4028 } else {
4029 if (netdev->flags & IFF_ALLMULTI) {
4030 rctl |= E1000_RCTL_MPE;
4031 vmolr |= E1000_VMOLR_MPME;
4032 } else {
4033
4034
4035
4036
4037 count = igb_write_mc_addr_list(netdev);
4038 if (count < 0) {
4039 rctl |= E1000_RCTL_MPE;
4040 vmolr |= E1000_VMOLR_MPME;
4041 } else if (count) {
4042 vmolr |= E1000_VMOLR_ROMPE;
4043 }
4044 }
4045
4046
4047
4048
4049 count = igb_write_uc_addr_list(netdev);
4050 if (count < 0) {
4051 rctl |= E1000_RCTL_UPE;
4052 vmolr |= E1000_VMOLR_ROPE;
4053 }
4054 rctl |= E1000_RCTL_VFE;
4055 }
4056 wr32(E1000_RCTL, rctl);
4057
4058
4059
4060
4061
4062
4063 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350))
4064 return;
4065
4066 vmolr |= rd32(E1000_VMOLR(vfn)) &
4067 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
4068 wr32(E1000_VMOLR(vfn), vmolr);
4069 igb_restore_vf_multicasts(adapter);
4070}
4071
4072static void igb_check_wvbr(struct igb_adapter *adapter)
4073{
4074 struct e1000_hw *hw = &adapter->hw;
4075 u32 wvbr = 0;
4076
4077 switch (hw->mac.type) {
4078 case e1000_82576:
4079 case e1000_i350:
4080 wvbr = rd32(E1000_WVBR);
4081 if (!wvbr)
4082 return;
4083 break;
4084 default:
4085 break;
4086 }
4087
4088 adapter->wvbr |= wvbr;
4089}
4090
4091#define IGB_STAGGERED_QUEUE_OFFSET 8
4092
4093static void igb_spoof_check(struct igb_adapter *adapter)
4094{
4095 int j;
4096
4097 if (!adapter->wvbr)
4098 return;
4099
4100 for (j = 0; j < adapter->vfs_allocated_count; j++) {
4101 if (adapter->wvbr & (1 << j) ||
4102 adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) {
4103 dev_warn(&adapter->pdev->dev,
4104 "Spoof event(s) detected on VF %d\n", j);
4105 adapter->wvbr &=
4106 ~((1 << j) |
4107 (1 << (j + IGB_STAGGERED_QUEUE_OFFSET)));
4108 }
4109 }
4110}
4111
4112
4113
4114
4115static void igb_update_phy_info(unsigned long data)
4116{
4117 struct igb_adapter *adapter = (struct igb_adapter *) data;
4118 igb_get_phy_info(&adapter->hw);
4119}
4120
4121
4122
4123
4124
4125bool igb_has_link(struct igb_adapter *adapter)
4126{
4127 struct e1000_hw *hw = &adapter->hw;
4128 bool link_active = false;
4129
4130
4131
4132
4133
4134
4135 switch (hw->phy.media_type) {
4136 case e1000_media_type_copper:
4137 if (!hw->mac.get_link_status)
4138 return true;
4139 case e1000_media_type_internal_serdes:
4140 hw->mac.ops.check_for_link(hw);
4141 link_active = !hw->mac.get_link_status;
4142 break;
4143 default:
4144 case e1000_media_type_unknown:
4145 break;
4146 }
4147
4148 if (((hw->mac.type == e1000_i210) ||
4149 (hw->mac.type == e1000_i211)) &&
4150 (hw->phy.id == I210_I_PHY_ID)) {
4151 if (!netif_carrier_ok(adapter->netdev)) {
4152 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
4153 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) {
4154 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE;
4155 adapter->link_check_timeout = jiffies;
4156 }
4157 }
4158
4159 return link_active;
4160}
4161
4162static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
4163{
4164 bool ret = false;
4165 u32 ctrl_ext, thstat;
4166
4167
4168 if (hw->mac.type == e1000_i350) {
4169 thstat = rd32(E1000_THSTAT);
4170 ctrl_ext = rd32(E1000_CTRL_EXT);
4171
4172 if ((hw->phy.media_type == e1000_media_type_copper) &&
4173 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII))
4174 ret = !!(thstat & event);
4175 }
4176
4177 return ret;
4178}
4179
4180
4181
4182
4183
4184
4185static void igb_check_lvmmc(struct igb_adapter *adapter)
4186{
4187 struct e1000_hw *hw = &adapter->hw;
4188 u32 lvmmc;
4189
4190 lvmmc = rd32(E1000_LVMMC);
4191 if (lvmmc) {
4192 if (unlikely(net_ratelimit())) {
4193 netdev_warn(adapter->netdev,
4194 "malformed Tx packet detected and dropped, LVMMC:0x%08x\n",
4195 lvmmc);
4196 }
4197 }
4198}
4199
4200
4201
4202
4203
4204static void igb_watchdog(unsigned long data)
4205{
4206 struct igb_adapter *adapter = (struct igb_adapter *)data;
4207
4208 schedule_work(&adapter->watchdog_task);
4209}
4210
4211static void igb_watchdog_task(struct work_struct *work)
4212{
4213 struct igb_adapter *adapter = container_of(work,
4214 struct igb_adapter,
4215 watchdog_task);
4216 struct e1000_hw *hw = &adapter->hw;
4217 struct e1000_phy_info *phy = &hw->phy;
4218 struct net_device *netdev = adapter->netdev;
4219 u32 link;
4220 int i;
4221 u32 connsw;
4222
4223 link = igb_has_link(adapter);
4224
4225 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) {
4226 if (time_after(jiffies, (adapter->link_check_timeout + HZ)))
4227 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
4228 else
4229 link = false;
4230 }
4231
4232
4233 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
4234 if (hw->phy.media_type == e1000_media_type_copper) {
4235 connsw = rd32(E1000_CONNSW);
4236 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN))
4237 link = 0;
4238 }
4239 }
4240 if (link) {
4241
4242 if (hw->dev_spec._82575.media_changed) {
4243 hw->dev_spec._82575.media_changed = false;
4244 adapter->flags |= IGB_FLAG_MEDIA_RESET;
4245 igb_reset(adapter);
4246 }
4247
4248 pm_runtime_resume(netdev->dev.parent);
4249
4250 if (!netif_carrier_ok(netdev)) {
4251 u32 ctrl;
4252
4253 hw->mac.ops.get_speed_and_duplex(hw,
4254 &adapter->link_speed,
4255 &adapter->link_duplex);
4256
4257 ctrl = rd32(E1000_CTRL);
4258
4259 netdev_info(netdev,
4260 "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
4261 netdev->name,
4262 adapter->link_speed,
4263 adapter->link_duplex == FULL_DUPLEX ?
4264 "Full" : "Half",
4265 (ctrl & E1000_CTRL_TFCE) &&
4266 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
4267 (ctrl & E1000_CTRL_RFCE) ? "RX" :
4268 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None");
4269
4270
4271 if ((adapter->flags & IGB_FLAG_EEE) &&
4272 (adapter->link_duplex == HALF_DUPLEX)) {
4273 dev_info(&adapter->pdev->dev,
4274 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n");
4275 adapter->hw.dev_spec._82575.eee_disable = true;
4276 adapter->flags &= ~IGB_FLAG_EEE;
4277 }
4278
4279
4280 igb_check_downshift(hw);
4281 if (phy->speed_downgraded)
4282 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n");
4283
4284
4285 if (igb_thermal_sensor_event(hw,
4286 E1000_THSTAT_LINK_THROTTLE))
4287 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n");
4288
4289
4290 adapter->tx_timeout_factor = 1;
4291 switch (adapter->link_speed) {
4292 case SPEED_10:
4293 adapter->tx_timeout_factor = 14;
4294 break;
4295 case SPEED_100:
4296
4297 break;
4298 }
4299
4300 netif_carrier_on(netdev);
4301
4302 igb_ping_all_vfs(adapter);
4303 igb_check_vf_rate_limit(adapter);
4304
4305
4306 if (!test_bit(__IGB_DOWN, &adapter->state))
4307 mod_timer(&adapter->phy_info_timer,
4308 round_jiffies(jiffies + 2 * HZ));
4309 }
4310 } else {
4311 if (netif_carrier_ok(netdev)) {
4312 adapter->link_speed = 0;
4313 adapter->link_duplex = 0;
4314
4315
4316 if (igb_thermal_sensor_event(hw,
4317 E1000_THSTAT_PWR_DOWN)) {
4318 netdev_err(netdev, "The network adapter was stopped because it overheated\n");
4319 }
4320
4321
4322 netdev_info(netdev, "igb: %s NIC Link is Down\n",
4323 netdev->name);
4324 netif_carrier_off(netdev);
4325
4326 igb_ping_all_vfs(adapter);
4327
4328
4329 if (!test_bit(__IGB_DOWN, &adapter->state))
4330 mod_timer(&adapter->phy_info_timer,
4331 round_jiffies(jiffies + 2 * HZ));
4332
4333
4334 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
4335 igb_check_swap_media(adapter);
4336 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
4337 schedule_work(&adapter->reset_task);
4338
4339 return;
4340 }
4341 }
4342 pm_schedule_suspend(netdev->dev.parent,
4343 MSEC_PER_SEC * 5);
4344
4345
4346 } else if (!netif_carrier_ok(netdev) &&
4347 (adapter->flags & IGB_FLAG_MAS_ENABLE)) {
4348 igb_check_swap_media(adapter);
4349 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
4350 schedule_work(&adapter->reset_task);
4351
4352 return;
4353 }
4354 }
4355 }
4356
4357 spin_lock(&adapter->stats64_lock);
4358 igb_update_stats(adapter, &adapter->stats64);
4359 spin_unlock(&adapter->stats64_lock);
4360
4361 for (i = 0; i < adapter->num_tx_queues; i++) {
4362 struct igb_ring *tx_ring = adapter->tx_ring[i];
4363 if (!netif_carrier_ok(netdev)) {
4364
4365
4366
4367
4368
4369 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
4370 adapter->tx_timeout_count++;
4371 schedule_work(&adapter->reset_task);
4372
4373 return;
4374 }
4375 }
4376
4377
4378 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
4379 }
4380
4381
4382 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
4383 u32 eics = 0;
4384
4385 for (i = 0; i < adapter->num_q_vectors; i++)
4386 eics |= adapter->q_vector[i]->eims_value;
4387 wr32(E1000_EICS, eics);
4388 } else {
4389 wr32(E1000_ICS, E1000_ICS_RXDMT0);
4390 }
4391
4392 igb_spoof_check(adapter);
4393 igb_ptp_rx_hang(adapter);
4394
4395
4396 if ((adapter->hw.mac.type == e1000_i350) ||
4397 (adapter->hw.mac.type == e1000_i354))
4398 igb_check_lvmmc(adapter);
4399
4400
4401 if (!test_bit(__IGB_DOWN, &adapter->state)) {
4402 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)
4403 mod_timer(&adapter->watchdog_timer,
4404 round_jiffies(jiffies + HZ));
4405 else
4406 mod_timer(&adapter->watchdog_timer,
4407 round_jiffies(jiffies + 2 * HZ));
4408 }
4409}
4410
4411enum latency_range {
4412 lowest_latency = 0,
4413 low_latency = 1,
4414 bulk_latency = 2,
4415 latency_invalid = 255
4416};
4417
4418
4419
4420
4421
4422
4423
4424
4425
4426
4427
4428
4429
4430
4431
4432
4433static void igb_update_ring_itr(struct igb_q_vector *q_vector)
4434{
4435 int new_val = q_vector->itr_val;
4436 int avg_wire_size = 0;
4437 struct igb_adapter *adapter = q_vector->adapter;
4438 unsigned int packets;
4439
4440
4441
4442
4443 if (adapter->link_speed != SPEED_1000) {
4444 new_val = IGB_4K_ITR;
4445 goto set_itr_val;
4446 }
4447
4448 packets = q_vector->rx.total_packets;
4449 if (packets)
4450 avg_wire_size = q_vector->rx.total_bytes / packets;
4451
4452 packets = q_vector->tx.total_packets;
4453 if (packets)
4454 avg_wire_size = max_t(u32, avg_wire_size,
4455 q_vector->tx.total_bytes / packets);
4456
4457
4458 if (!avg_wire_size)
4459 goto clear_counts;
4460
4461
4462 avg_wire_size += 24;
4463
4464
4465 avg_wire_size = min(avg_wire_size, 3000);
4466
4467
4468 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
4469 new_val = avg_wire_size / 3;
4470 else
4471 new_val = avg_wire_size / 2;
4472
4473
4474 if (new_val < IGB_20K_ITR &&
4475 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4476 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4477 new_val = IGB_20K_ITR;
4478
4479set_itr_val:
4480 if (new_val != q_vector->itr_val) {
4481 q_vector->itr_val = new_val;
4482 q_vector->set_itr = 1;
4483 }
4484clear_counts:
4485 q_vector->rx.total_bytes = 0;
4486 q_vector->rx.total_packets = 0;
4487 q_vector->tx.total_bytes = 0;
4488 q_vector->tx.total_packets = 0;
4489}
4490
4491
4492
4493
4494
4495
4496
4497
4498
4499
4500
4501
4502
4503
4504
4505
4506
4507static void igb_update_itr(struct igb_q_vector *q_vector,
4508 struct igb_ring_container *ring_container)
4509{
4510 unsigned int packets = ring_container->total_packets;
4511 unsigned int bytes = ring_container->total_bytes;
4512 u8 itrval = ring_container->itr;
4513
4514
4515 if (packets == 0)
4516 return;
4517
4518 switch (itrval) {
4519 case lowest_latency:
4520
4521 if (bytes/packets > 8000)
4522 itrval = bulk_latency;
4523 else if ((packets < 5) && (bytes > 512))
4524 itrval = low_latency;
4525 break;
4526 case low_latency:
4527 if (bytes > 10000) {
4528
4529 if (bytes/packets > 8000)
4530 itrval = bulk_latency;
4531 else if ((packets < 10) || ((bytes/packets) > 1200))
4532 itrval = bulk_latency;
4533 else if ((packets > 35))
4534 itrval = lowest_latency;
4535 } else if (bytes/packets > 2000) {
4536 itrval = bulk_latency;
4537 } else if (packets <= 2 && bytes < 512) {
4538 itrval = lowest_latency;
4539 }
4540 break;
4541 case bulk_latency:
4542 if (bytes > 25000) {
4543 if (packets > 35)
4544 itrval = low_latency;
4545 } else if (bytes < 1500) {
4546 itrval = low_latency;
4547 }
4548 break;
4549 }
4550
4551
4552 ring_container->total_bytes = 0;
4553 ring_container->total_packets = 0;
4554
4555
4556 ring_container->itr = itrval;
4557}
4558
4559static void igb_set_itr(struct igb_q_vector *q_vector)
4560{
4561 struct igb_adapter *adapter = q_vector->adapter;
4562 u32 new_itr = q_vector->itr_val;
4563 u8 current_itr = 0;
4564
4565
4566 if (adapter->link_speed != SPEED_1000) {
4567 current_itr = 0;
4568 new_itr = IGB_4K_ITR;
4569 goto set_itr_now;
4570 }
4571
4572 igb_update_itr(q_vector, &q_vector->tx);
4573 igb_update_itr(q_vector, &q_vector->rx);
4574
4575 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
4576
4577
4578 if (current_itr == lowest_latency &&
4579 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4580 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4581 current_itr = low_latency;
4582
4583 switch (current_itr) {
4584
4585 case lowest_latency:
4586 new_itr = IGB_70K_ITR;
4587 break;
4588 case low_latency:
4589 new_itr = IGB_20K_ITR;
4590 break;
4591 case bulk_latency:
4592 new_itr = IGB_4K_ITR;
4593 break;
4594 default:
4595 break;
4596 }
4597
4598set_itr_now:
4599 if (new_itr != q_vector->itr_val) {
4600
4601
4602
4603
4604 new_itr = new_itr > q_vector->itr_val ?
4605 max((new_itr * q_vector->itr_val) /
4606 (new_itr + (q_vector->itr_val >> 2)),
4607 new_itr) : new_itr;
4608
4609
4610
4611
4612
4613
4614 q_vector->itr_val = new_itr;
4615 q_vector->set_itr = 1;
4616 }
4617}
4618
4619static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens,
4620 u32 type_tucmd, u32 mss_l4len_idx)
4621{
4622 struct e1000_adv_tx_context_desc *context_desc;
4623 u16 i = tx_ring->next_to_use;
4624
4625 context_desc = IGB_TX_CTXTDESC(tx_ring, i);
4626
4627 i++;
4628 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
4629
4630
4631 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
4632
4633
4634 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
4635 mss_l4len_idx |= tx_ring->reg_idx << 4;
4636
4637 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4638 context_desc->seqnum_seed = 0;
4639 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
4640 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4641}
4642
4643static int igb_tso(struct igb_ring *tx_ring,
4644 struct igb_tx_buffer *first,
4645 u8 *hdr_len)
4646{
4647 struct sk_buff *skb = first->skb;
4648 u32 vlan_macip_lens, type_tucmd;
4649 u32 mss_l4len_idx, l4len;
4650 int err;
4651
4652 if (skb->ip_summed != CHECKSUM_PARTIAL)
4653 return 0;
4654
4655 if (!skb_is_gso(skb))
4656 return 0;
4657
4658 err = skb_cow_head(skb, 0);
4659 if (err < 0)
4660 return err;
4661
4662
4663 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
4664
4665 if (first->protocol == htons(ETH_P_IP)) {
4666 struct iphdr *iph = ip_hdr(skb);
4667 iph->tot_len = 0;
4668 iph->check = 0;
4669 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4670 iph->daddr, 0,
4671 IPPROTO_TCP,
4672 0);
4673 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4674 first->tx_flags |= IGB_TX_FLAGS_TSO |
4675 IGB_TX_FLAGS_CSUM |
4676 IGB_TX_FLAGS_IPV4;
4677 } else if (skb_is_gso_v6(skb)) {
4678 ipv6_hdr(skb)->payload_len = 0;
4679 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4680 &ipv6_hdr(skb)->daddr,
4681 0, IPPROTO_TCP, 0);
4682 first->tx_flags |= IGB_TX_FLAGS_TSO |
4683 IGB_TX_FLAGS_CSUM;
4684 }
4685
4686
4687 l4len = tcp_hdrlen(skb);
4688 *hdr_len = skb_transport_offset(skb) + l4len;
4689
4690
4691 first->gso_segs = skb_shinfo(skb)->gso_segs;
4692 first->bytecount += (first->gso_segs - 1) * *hdr_len;
4693
4694
4695 mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT;
4696 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
4697
4698
4699 vlan_macip_lens = skb_network_header_len(skb);
4700 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
4701 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
4702
4703 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
4704
4705 return 1;
4706}
4707
4708static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
4709{
4710 struct sk_buff *skb = first->skb;
4711 u32 vlan_macip_lens = 0;
4712 u32 mss_l4len_idx = 0;
4713 u32 type_tucmd = 0;
4714
4715 if (skb->ip_summed != CHECKSUM_PARTIAL) {
4716 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN))
4717 return;
4718 } else {
4719 u8 l4_hdr = 0;
4720
4721 switch (first->protocol) {
4722 case htons(ETH_P_IP):
4723 vlan_macip_lens |= skb_network_header_len(skb);
4724 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4725 l4_hdr = ip_hdr(skb)->protocol;
4726 break;
4727 case htons(ETH_P_IPV6):
4728 vlan_macip_lens |= skb_network_header_len(skb);
4729 l4_hdr = ipv6_hdr(skb)->nexthdr;
4730 break;
4731 default:
4732 if (unlikely(net_ratelimit())) {
4733 dev_warn(tx_ring->dev,
4734 "partial checksum but proto=%x!\n",
4735 first->protocol);
4736 }
4737 break;
4738 }
4739
4740 switch (l4_hdr) {
4741 case IPPROTO_TCP:
4742 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
4743 mss_l4len_idx = tcp_hdrlen(skb) <<
4744 E1000_ADVTXD_L4LEN_SHIFT;
4745 break;
4746 case IPPROTO_SCTP:
4747 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
4748 mss_l4len_idx = sizeof(struct sctphdr) <<
4749 E1000_ADVTXD_L4LEN_SHIFT;
4750 break;
4751 case IPPROTO_UDP:
4752 mss_l4len_idx = sizeof(struct udphdr) <<
4753 E1000_ADVTXD_L4LEN_SHIFT;
4754 break;
4755 default:
4756 if (unlikely(net_ratelimit())) {
4757 dev_warn(tx_ring->dev,
4758 "partial checksum but l4 proto=%x!\n",
4759 l4_hdr);
4760 }
4761 break;
4762 }
4763
4764
4765 first->tx_flags |= IGB_TX_FLAGS_CSUM;
4766 }
4767
4768 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
4769 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
4770
4771 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
4772}
4773
4774#define IGB_SET_FLAG(_input, _flag, _result) \
4775 ((_flag <= _result) ? \
4776 ((u32)(_input & _flag) * (_result / _flag)) : \
4777 ((u32)(_input & _flag) / (_flag / _result)))
4778
4779static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
4780{
4781
4782 u32 cmd_type = E1000_ADVTXD_DTYP_DATA |
4783 E1000_ADVTXD_DCMD_DEXT |
4784 E1000_ADVTXD_DCMD_IFCS;
4785
4786
4787 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN,
4788 (E1000_ADVTXD_DCMD_VLE));
4789
4790
4791 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO,
4792 (E1000_ADVTXD_DCMD_TSE));
4793
4794
4795 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP,
4796 (E1000_ADVTXD_MAC_TSTAMP));
4797
4798
4799 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS);
4800
4801 return cmd_type;
4802}
4803
4804static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
4805 union e1000_adv_tx_desc *tx_desc,
4806 u32 tx_flags, unsigned int paylen)
4807{
4808 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
4809
4810
4811 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
4812 olinfo_status |= tx_ring->reg_idx << 4;
4813
4814
4815 olinfo_status |= IGB_SET_FLAG(tx_flags,
4816 IGB_TX_FLAGS_CSUM,
4817 (E1000_TXD_POPTS_TXSM << 8));
4818
4819
4820 olinfo_status |= IGB_SET_FLAG(tx_flags,
4821 IGB_TX_FLAGS_IPV4,
4822 (E1000_TXD_POPTS_IXSM << 8));
4823
4824 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
4825}
4826
4827static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
4828{
4829 struct net_device *netdev = tx_ring->netdev;
4830
4831 netif_stop_subqueue(netdev, tx_ring->queue_index);
4832
4833
4834
4835
4836
4837 smp_mb();
4838
4839
4840
4841
4842 if (igb_desc_unused(tx_ring) < size)
4843 return -EBUSY;
4844
4845
4846 netif_wake_subqueue(netdev, tx_ring->queue_index);
4847
4848 u64_stats_update_begin(&tx_ring->tx_syncp2);
4849 tx_ring->tx_stats.restart_queue2++;
4850 u64_stats_update_end(&tx_ring->tx_syncp2);
4851
4852 return 0;
4853}
4854
4855static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
4856{
4857 if (igb_desc_unused(tx_ring) >= size)
4858 return 0;
4859 return __igb_maybe_stop_tx(tx_ring, size);
4860}
4861
4862static void igb_tx_map(struct igb_ring *tx_ring,
4863 struct igb_tx_buffer *first,
4864 const u8 hdr_len)
4865{
4866 struct sk_buff *skb = first->skb;
4867 struct igb_tx_buffer *tx_buffer;
4868 union e1000_adv_tx_desc *tx_desc;
4869 struct skb_frag_struct *frag;
4870 dma_addr_t dma;
4871 unsigned int data_len, size;
4872 u32 tx_flags = first->tx_flags;
4873 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags);
4874 u16 i = tx_ring->next_to_use;
4875
4876 tx_desc = IGB_TX_DESC(tx_ring, i);
4877
4878 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);
4879
4880 size = skb_headlen(skb);
4881 data_len = skb->data_len;
4882
4883 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
4884
4885 tx_buffer = first;
4886
4887 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
4888 if (dma_mapping_error(tx_ring->dev, dma))
4889 goto dma_error;
4890
4891
4892 dma_unmap_len_set(tx_buffer, len, size);
4893 dma_unmap_addr_set(tx_buffer, dma, dma);
4894
4895 tx_desc->read.buffer_addr = cpu_to_le64(dma);
4896
4897 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
4898 tx_desc->read.cmd_type_len =
4899 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD);
4900
4901 i++;
4902 tx_desc++;
4903 if (i == tx_ring->count) {
4904 tx_desc = IGB_TX_DESC(tx_ring, 0);
4905 i = 0;
4906 }
4907 tx_desc->read.olinfo_status = 0;
4908
4909 dma += IGB_MAX_DATA_PER_TXD;
4910 size -= IGB_MAX_DATA_PER_TXD;
4911
4912 tx_desc->read.buffer_addr = cpu_to_le64(dma);
4913 }
4914
4915 if (likely(!data_len))
4916 break;
4917
4918 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
4919
4920 i++;
4921 tx_desc++;
4922 if (i == tx_ring->count) {
4923 tx_desc = IGB_TX_DESC(tx_ring, 0);
4924 i = 0;
4925 }
4926 tx_desc->read.olinfo_status = 0;
4927
4928 size = skb_frag_size(frag);
4929 data_len -= size;
4930
4931 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
4932 size, DMA_TO_DEVICE);
4933
4934 tx_buffer = &tx_ring->tx_buffer_info[i];
4935 }
4936
4937
4938 cmd_type |= size | IGB_TXD_DCMD;
4939 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
4940
4941 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
4942
4943
4944 first->time_stamp = jiffies;
4945
4946
4947
4948
4949
4950
4951
4952
4953 wmb();
4954
4955
4956 first->next_to_watch = tx_desc;
4957
4958 i++;
4959 if (i == tx_ring->count)
4960 i = 0;
4961
4962 tx_ring->next_to_use = i;
4963
4964
4965 igb_maybe_stop_tx(tx_ring, DESC_NEEDED);
4966
4967 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) {
4968 writel(i, tx_ring->tail);
4969
4970
4971
4972
4973 mmiowb();
4974 }
4975 return;
4976
4977dma_error:
4978 dev_err(tx_ring->dev, "TX DMA map failed\n");
4979
4980
4981 for (;;) {
4982 tx_buffer = &tx_ring->tx_buffer_info[i];
4983 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer);
4984 if (tx_buffer == first)
4985 break;
4986 if (i == 0)
4987 i = tx_ring->count;
4988 i--;
4989 }
4990
4991 tx_ring->next_to_use = i;
4992}
4993
4994netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
4995 struct igb_ring *tx_ring)
4996{
4997 struct igb_tx_buffer *first;
4998 int tso;
4999 u32 tx_flags = 0;
5000 unsigned short f;
5001 u16 count = TXD_USE_COUNT(skb_headlen(skb));
5002 __be16 protocol = vlan_get_protocol(skb);
5003 u8 hdr_len = 0;
5004
5005
5006
5007
5008
5009
5010
5011 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
5012 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
5013
5014 if (igb_maybe_stop_tx(tx_ring, count + 3)) {
5015
5016 return NETDEV_TX_BUSY;
5017 }
5018
5019
5020 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
5021 first->skb = skb;
5022 first->bytecount = skb->len;
5023 first->gso_segs = 1;
5024
5025 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
5026 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
5027
5028 if (!test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS,
5029 &adapter->state)) {
5030 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
5031 tx_flags |= IGB_TX_FLAGS_TSTAMP;
5032
5033 adapter->ptp_tx_skb = skb_get(skb);
5034 adapter->ptp_tx_start = jiffies;
5035 if (adapter->hw.mac.type == e1000_82576)
5036 schedule_work(&adapter->ptp_tx_work);
5037 }
5038 }
5039
5040 skb_tx_timestamp(skb);
5041
5042 if (skb_vlan_tag_present(skb)) {
5043 tx_flags |= IGB_TX_FLAGS_VLAN;
5044 tx_flags |= (skb_vlan_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
5045 }
5046
5047
5048 first->tx_flags = tx_flags;
5049 first->protocol = protocol;
5050
5051 tso = igb_tso(tx_ring, first, &hdr_len);
5052 if (tso < 0)
5053 goto out_drop;
5054 else if (!tso)
5055 igb_tx_csum(tx_ring, first);
5056
5057 igb_tx_map(tx_ring, first, hdr_len);
5058
5059 return NETDEV_TX_OK;
5060
5061out_drop:
5062 igb_unmap_and_free_tx_resource(tx_ring, first);
5063
5064 return NETDEV_TX_OK;
5065}
5066
5067static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
5068 struct sk_buff *skb)
5069{
5070 unsigned int r_idx = skb->queue_mapping;
5071
5072 if (r_idx >= adapter->num_tx_queues)
5073 r_idx = r_idx % adapter->num_tx_queues;
5074
5075 return adapter->tx_ring[r_idx];
5076}
5077
5078static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
5079 struct net_device *netdev)
5080{
5081 struct igb_adapter *adapter = netdev_priv(netdev);
5082
5083 if (test_bit(__IGB_DOWN, &adapter->state)) {
5084 dev_kfree_skb_any(skb);
5085 return NETDEV_TX_OK;
5086 }
5087
5088 if (skb->len <= 0) {
5089 dev_kfree_skb_any(skb);
5090 return NETDEV_TX_OK;
5091 }
5092
5093
5094
5095
5096 if (skb_put_padto(skb, 17))
5097 return NETDEV_TX_OK;
5098
5099 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
5100}
5101
5102
5103
5104
5105
5106static void igb_tx_timeout(struct net_device *netdev)
5107{
5108 struct igb_adapter *adapter = netdev_priv(netdev);
5109 struct e1000_hw *hw = &adapter->hw;
5110
5111
5112 adapter->tx_timeout_count++;
5113
5114 if (hw->mac.type >= e1000_82580)
5115 hw->dev_spec._82575.global_device_reset = true;
5116
5117 schedule_work(&adapter->reset_task);
5118 wr32(E1000_EICS,
5119 (adapter->eims_enable_mask & ~adapter->eims_other));
5120}
5121
5122static void igb_reset_task(struct work_struct *work)
5123{
5124 struct igb_adapter *adapter;
5125 adapter = container_of(work, struct igb_adapter, reset_task);
5126
5127 igb_dump(adapter);
5128 netdev_err(adapter->netdev, "Reset adapter\n");
5129 igb_reinit_locked(adapter);
5130}
5131
5132
5133
5134
5135
5136
5137static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev,
5138 struct rtnl_link_stats64 *stats)
5139{
5140 struct igb_adapter *adapter = netdev_priv(netdev);
5141
5142 spin_lock(&adapter->stats64_lock);
5143 igb_update_stats(adapter, &adapter->stats64);
5144 memcpy(stats, &adapter->stats64, sizeof(*stats));
5145 spin_unlock(&adapter->stats64_lock);
5146
5147 return stats;
5148}
5149
5150
5151
5152
5153
5154
5155
5156
5157static int igb_change_mtu(struct net_device *netdev, int new_mtu)
5158{
5159 struct igb_adapter *adapter = netdev_priv(netdev);
5160 struct pci_dev *pdev = adapter->pdev;
5161 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
5162
5163 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
5164 dev_err(&pdev->dev, "Invalid MTU setting\n");
5165 return -EINVAL;
5166 }
5167
5168#define MAX_STD_JUMBO_FRAME_SIZE 9238
5169 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
5170 dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
5171 return -EINVAL;
5172 }
5173
5174
5175 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
5176 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN;
5177
5178 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
5179 usleep_range(1000, 2000);
5180
5181
5182 adapter->max_frame_size = max_frame;
5183
5184 if (netif_running(netdev))
5185 igb_down(adapter);
5186
5187 dev_info(&pdev->dev, "changing MTU from %d to %d\n",
5188 netdev->mtu, new_mtu);
5189 netdev->mtu = new_mtu;
5190
5191 if (netif_running(netdev))
5192 igb_up(adapter);
5193 else
5194 igb_reset(adapter);
5195
5196 clear_bit(__IGB_RESETTING, &adapter->state);
5197
5198 return 0;
5199}
5200
5201
5202
5203
5204
5205void igb_update_stats(struct igb_adapter *adapter,
5206 struct rtnl_link_stats64 *net_stats)
5207{
5208 struct e1000_hw *hw = &adapter->hw;
5209 struct pci_dev *pdev = adapter->pdev;
5210 u32 reg, mpc;
5211 int i;
5212 u64 bytes, packets;
5213 unsigned int start;
5214 u64 _bytes, _packets;
5215
5216
5217
5218
5219 if (adapter->link_speed == 0)
5220 return;
5221 if (pci_channel_offline(pdev))
5222 return;
5223
5224 bytes = 0;
5225 packets = 0;
5226
5227 rcu_read_lock();
5228 for (i = 0; i < adapter->num_rx_queues; i++) {
5229 struct igb_ring *ring = adapter->rx_ring[i];
5230 u32 rqdpc = rd32(E1000_RQDPC(i));
5231 if (hw->mac.type >= e1000_i210)
5232 wr32(E1000_RQDPC(i), 0);
5233
5234 if (rqdpc) {
5235 ring->rx_stats.drops += rqdpc;
5236 net_stats->rx_fifo_errors += rqdpc;
5237 }
5238
5239 do {
5240 start = u64_stats_fetch_begin_irq(&ring->rx_syncp);
5241 _bytes = ring->rx_stats.bytes;
5242 _packets = ring->rx_stats.packets;
5243 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start));
5244 bytes += _bytes;
5245 packets += _packets;
5246 }
5247
5248 net_stats->rx_bytes = bytes;
5249 net_stats->rx_packets = packets;
5250
5251 bytes = 0;
5252 packets = 0;
5253 for (i = 0; i < adapter->num_tx_queues; i++) {
5254 struct igb_ring *ring = adapter->tx_ring[i];
5255 do {
5256 start = u64_stats_fetch_begin_irq(&ring->tx_syncp);
5257 _bytes = ring->tx_stats.bytes;
5258 _packets = ring->tx_stats.packets;
5259 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start));
5260 bytes += _bytes;
5261 packets += _packets;
5262 }
5263 net_stats->tx_bytes = bytes;
5264 net_stats->tx_packets = packets;
5265 rcu_read_unlock();
5266
5267
5268 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
5269 adapter->stats.gprc += rd32(E1000_GPRC);
5270 adapter->stats.gorc += rd32(E1000_GORCL);
5271 rd32(E1000_GORCH);
5272 adapter->stats.bprc += rd32(E1000_BPRC);
5273 adapter->stats.mprc += rd32(E1000_MPRC);
5274 adapter->stats.roc += rd32(E1000_ROC);
5275
5276 adapter->stats.prc64 += rd32(E1000_PRC64);
5277 adapter->stats.prc127 += rd32(E1000_PRC127);
5278 adapter->stats.prc255 += rd32(E1000_PRC255);
5279 adapter->stats.prc511 += rd32(E1000_PRC511);
5280 adapter->stats.prc1023 += rd32(E1000_PRC1023);
5281 adapter->stats.prc1522 += rd32(E1000_PRC1522);
5282 adapter->stats.symerrs += rd32(E1000_SYMERRS);
5283 adapter->stats.sec += rd32(E1000_SEC);
5284
5285 mpc = rd32(E1000_MPC);
5286 adapter->stats.mpc += mpc;
5287 net_stats->rx_fifo_errors += mpc;
5288 adapter->stats.scc += rd32(E1000_SCC);
5289 adapter->stats.ecol += rd32(E1000_ECOL);
5290 adapter->stats.mcc += rd32(E1000_MCC);
5291 adapter->stats.latecol += rd32(E1000_LATECOL);
5292 adapter->stats.dc += rd32(E1000_DC);
5293 adapter->stats.rlec += rd32(E1000_RLEC);
5294 adapter->stats.xonrxc += rd32(E1000_XONRXC);
5295 adapter->stats.xontxc += rd32(E1000_XONTXC);
5296 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
5297 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
5298 adapter->stats.fcruc += rd32(E1000_FCRUC);
5299 adapter->stats.gptc += rd32(E1000_GPTC);
5300 adapter->stats.gotc += rd32(E1000_GOTCL);
5301 rd32(E1000_GOTCH);
5302 adapter->stats.rnbc += rd32(E1000_RNBC);
5303 adapter->stats.ruc += rd32(E1000_RUC);
5304 adapter->stats.rfc += rd32(E1000_RFC);
5305 adapter->stats.rjc += rd32(E1000_RJC);
5306 adapter->stats.tor += rd32(E1000_TORH);
5307 adapter->stats.tot += rd32(E1000_TOTH);
5308 adapter->stats.tpr += rd32(E1000_TPR);
5309
5310 adapter->stats.ptc64 += rd32(E1000_PTC64);
5311 adapter->stats.ptc127 += rd32(E1000_PTC127);
5312 adapter->stats.ptc255 += rd32(E1000_PTC255);
5313 adapter->stats.ptc511 += rd32(E1000_PTC511);
5314 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
5315 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
5316
5317 adapter->stats.mptc += rd32(E1000_MPTC);
5318 adapter->stats.bptc += rd32(E1000_BPTC);
5319
5320 adapter->stats.tpt += rd32(E1000_TPT);
5321 adapter->stats.colc += rd32(E1000_COLC);
5322
5323 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
5324
5325 reg = rd32(E1000_CTRL_EXT);
5326 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
5327 adapter->stats.rxerrc += rd32(E1000_RXERRC);
5328
5329
5330 if ((hw->mac.type != e1000_i210) &&
5331 (hw->mac.type != e1000_i211))
5332 adapter->stats.tncrs += rd32(E1000_TNCRS);
5333 }
5334
5335 adapter->stats.tsctc += rd32(E1000_TSCTC);
5336 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
5337
5338 adapter->stats.iac += rd32(E1000_IAC);
5339 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
5340 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
5341 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
5342 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
5343 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
5344 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
5345 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
5346 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
5347
5348
5349 net_stats->multicast = adapter->stats.mprc;
5350 net_stats->collisions = adapter->stats.colc;
5351
5352
5353
5354
5355
5356
5357 net_stats->rx_errors = adapter->stats.rxerrc +
5358 adapter->stats.crcerrs + adapter->stats.algnerrc +
5359 adapter->stats.ruc + adapter->stats.roc +
5360 adapter->stats.cexterr;
5361 net_stats->rx_length_errors = adapter->stats.ruc +
5362 adapter->stats.roc;
5363 net_stats->rx_crc_errors = adapter->stats.crcerrs;
5364 net_stats->rx_frame_errors = adapter->stats.algnerrc;
5365 net_stats->rx_missed_errors = adapter->stats.mpc;
5366
5367
5368 net_stats->tx_errors = adapter->stats.ecol +
5369 adapter->stats.latecol;
5370 net_stats->tx_aborted_errors = adapter->stats.ecol;
5371 net_stats->tx_window_errors = adapter->stats.latecol;
5372 net_stats->tx_carrier_errors = adapter->stats.tncrs;
5373
5374
5375
5376
5377 adapter->stats.mgptc += rd32(E1000_MGTPTC);
5378 adapter->stats.mgprc += rd32(E1000_MGTPRC);
5379 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
5380
5381
5382 reg = rd32(E1000_MANC);
5383 if (reg & E1000_MANC_EN_BMC2OS) {
5384 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
5385 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
5386 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
5387 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
5388 }
5389}
5390
5391static void igb_tsync_interrupt(struct igb_adapter *adapter)
5392{
5393 struct e1000_hw *hw = &adapter->hw;
5394 struct ptp_clock_event event;
5395 struct timespec64 ts;
5396 u32 ack = 0, tsauxc, sec, nsec, tsicr = rd32(E1000_TSICR);
5397
5398 if (tsicr & TSINTR_SYS_WRAP) {
5399 event.type = PTP_CLOCK_PPS;
5400 if (adapter->ptp_caps.pps)
5401 ptp_clock_event(adapter->ptp_clock, &event);
5402 else
5403 dev_err(&adapter->pdev->dev, "unexpected SYS WRAP");
5404 ack |= TSINTR_SYS_WRAP;
5405 }
5406
5407 if (tsicr & E1000_TSICR_TXTS) {
5408
5409 schedule_work(&adapter->ptp_tx_work);
5410 ack |= E1000_TSICR_TXTS;
5411 }
5412
5413 if (tsicr & TSINTR_TT0) {
5414 spin_lock(&adapter->tmreg_lock);
5415 ts = timespec64_add(adapter->perout[0].start,
5416 adapter->perout[0].period);
5417
5418 wr32(E1000_TRGTTIML0, ts.tv_nsec);
5419 wr32(E1000_TRGTTIMH0, (u32)ts.tv_sec);
5420 tsauxc = rd32(E1000_TSAUXC);
5421 tsauxc |= TSAUXC_EN_TT0;
5422 wr32(E1000_TSAUXC, tsauxc);
5423 adapter->perout[0].start = ts;
5424 spin_unlock(&adapter->tmreg_lock);
5425 ack |= TSINTR_TT0;
5426 }
5427
5428 if (tsicr & TSINTR_TT1) {
5429 spin_lock(&adapter->tmreg_lock);
5430 ts = timespec64_add(adapter->perout[1].start,
5431 adapter->perout[1].period);
5432 wr32(E1000_TRGTTIML1, ts.tv_nsec);
5433 wr32(E1000_TRGTTIMH1, (u32)ts.tv_sec);
5434 tsauxc = rd32(E1000_TSAUXC);
5435 tsauxc |= TSAUXC_EN_TT1;
5436 wr32(E1000_TSAUXC, tsauxc);
5437 adapter->perout[1].start = ts;
5438 spin_unlock(&adapter->tmreg_lock);
5439 ack |= TSINTR_TT1;
5440 }
5441
5442 if (tsicr & TSINTR_AUTT0) {
5443 nsec = rd32(E1000_AUXSTMPL0);
5444 sec = rd32(E1000_AUXSTMPH0);
5445 event.type = PTP_CLOCK_EXTTS;
5446 event.index = 0;
5447 event.timestamp = sec * 1000000000ULL + nsec;
5448 ptp_clock_event(adapter->ptp_clock, &event);
5449 ack |= TSINTR_AUTT0;
5450 }
5451
5452 if (tsicr & TSINTR_AUTT1) {
5453 nsec = rd32(E1000_AUXSTMPL1);
5454 sec = rd32(E1000_AUXSTMPH1);
5455 event.type = PTP_CLOCK_EXTTS;
5456 event.index = 1;
5457 event.timestamp = sec * 1000000000ULL + nsec;
5458 ptp_clock_event(adapter->ptp_clock, &event);
5459 ack |= TSINTR_AUTT1;
5460 }
5461
5462
5463 wr32(E1000_TSICR, ack);
5464}
5465
5466static irqreturn_t igb_msix_other(int irq, void *data)
5467{
5468 struct igb_adapter *adapter = data;
5469 struct e1000_hw *hw = &adapter->hw;
5470 u32 icr = rd32(E1000_ICR);
5471
5472
5473 if (icr & E1000_ICR_DRSTA)
5474 schedule_work(&adapter->reset_task);
5475
5476 if (icr & E1000_ICR_DOUTSYNC) {
5477
5478 adapter->stats.doosync++;
5479
5480
5481
5482
5483 igb_check_wvbr(adapter);
5484 }
5485
5486
5487 if (icr & E1000_ICR_VMMB)
5488 igb_msg_task(adapter);
5489
5490 if (icr & E1000_ICR_LSC) {
5491 hw->mac.get_link_status = 1;
5492
5493 if (!test_bit(__IGB_DOWN, &adapter->state))
5494 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5495 }
5496
5497 if (icr & E1000_ICR_TS)
5498 igb_tsync_interrupt(adapter);
5499
5500 wr32(E1000_EIMS, adapter->eims_other);
5501
5502 return IRQ_HANDLED;
5503}
5504
5505static void igb_write_itr(struct igb_q_vector *q_vector)
5506{
5507 struct igb_adapter *adapter = q_vector->adapter;
5508 u32 itr_val = q_vector->itr_val & 0x7FFC;
5509
5510 if (!q_vector->set_itr)
5511 return;
5512
5513 if (!itr_val)
5514 itr_val = 0x4;
5515
5516 if (adapter->hw.mac.type == e1000_82575)
5517 itr_val |= itr_val << 16;
5518 else
5519 itr_val |= E1000_EITR_CNT_IGNR;
5520
5521 writel(itr_val, q_vector->itr_register);
5522 q_vector->set_itr = 0;
5523}
5524
5525static irqreturn_t igb_msix_ring(int irq, void *data)
5526{
5527 struct igb_q_vector *q_vector = data;
5528
5529
5530 igb_write_itr(q_vector);
5531
5532 napi_schedule(&q_vector->napi);
5533
5534 return IRQ_HANDLED;
5535}
5536
5537#ifdef CONFIG_IGB_DCA
5538static void igb_update_tx_dca(struct igb_adapter *adapter,
5539 struct igb_ring *tx_ring,
5540 int cpu)
5541{
5542 struct e1000_hw *hw = &adapter->hw;
5543 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
5544
5545 if (hw->mac.type != e1000_82575)
5546 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT;
5547
5548
5549
5550
5551
5552 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN |
5553 E1000_DCA_TXCTRL_DATA_RRO_EN |
5554 E1000_DCA_TXCTRL_DESC_DCA_EN;
5555
5556 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl);
5557}
5558
5559static void igb_update_rx_dca(struct igb_adapter *adapter,
5560 struct igb_ring *rx_ring,
5561 int cpu)
5562{
5563 struct e1000_hw *hw = &adapter->hw;
5564 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu);
5565
5566 if (hw->mac.type != e1000_82575)
5567 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT;
5568
5569
5570
5571
5572
5573 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN |
5574 E1000_DCA_RXCTRL_DESC_DCA_EN;
5575
5576 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl);
5577}
5578
5579static void igb_update_dca(struct igb_q_vector *q_vector)
5580{
5581 struct igb_adapter *adapter = q_vector->adapter;
5582 int cpu = get_cpu();
5583
5584 if (q_vector->cpu == cpu)
5585 goto out_no_update;
5586
5587 if (q_vector->tx.ring)
5588 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu);
5589
5590 if (q_vector->rx.ring)
5591 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu);
5592
5593 q_vector->cpu = cpu;
5594out_no_update:
5595 put_cpu();
5596}
5597
5598static void igb_setup_dca(struct igb_adapter *adapter)
5599{
5600 struct e1000_hw *hw = &adapter->hw;
5601 int i;
5602
5603 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
5604 return;
5605
5606
5607 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
5608
5609 for (i = 0; i < adapter->num_q_vectors; i++) {
5610 adapter->q_vector[i]->cpu = -1;
5611 igb_update_dca(adapter->q_vector[i]);
5612 }
5613}
5614
5615static int __igb_notify_dca(struct device *dev, void *data)
5616{
5617 struct net_device *netdev = dev_get_drvdata(dev);
5618 struct igb_adapter *adapter = netdev_priv(netdev);
5619 struct pci_dev *pdev = adapter->pdev;
5620 struct e1000_hw *hw = &adapter->hw;
5621 unsigned long event = *(unsigned long *)data;
5622
5623 switch (event) {
5624 case DCA_PROVIDER_ADD:
5625
5626 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
5627 break;
5628 if (dca_add_requester(dev) == 0) {
5629 adapter->flags |= IGB_FLAG_DCA_ENABLED;
5630 dev_info(&pdev->dev, "DCA enabled\n");
5631 igb_setup_dca(adapter);
5632 break;
5633 }
5634
5635 case DCA_PROVIDER_REMOVE:
5636 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
5637
5638
5639
5640 dca_remove_requester(dev);
5641 dev_info(&pdev->dev, "DCA disabled\n");
5642 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
5643 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
5644 }
5645 break;
5646 }
5647
5648 return 0;
5649}
5650
5651static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
5652 void *p)
5653{
5654 int ret_val;
5655
5656 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
5657 __igb_notify_dca);
5658
5659 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5660}
5661#endif
5662
5663#ifdef CONFIG_PCI_IOV
5664static int igb_vf_configure(struct igb_adapter *adapter, int vf)
5665{
5666 unsigned char mac_addr[ETH_ALEN];
5667
5668 eth_zero_addr(mac_addr);
5669 igb_set_vf_mac(adapter, vf, mac_addr);
5670
5671
5672 adapter->vf_data[vf].spoofchk_enabled = true;
5673
5674 return 0;
5675}
5676
5677#endif
5678static void igb_ping_all_vfs(struct igb_adapter *adapter)
5679{
5680 struct e1000_hw *hw = &adapter->hw;
5681 u32 ping;
5682 int i;
5683
5684 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
5685 ping = E1000_PF_CONTROL_MSG;
5686 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
5687 ping |= E1000_VT_MSGTYPE_CTS;
5688 igb_write_mbx(hw, &ping, 1, i);
5689 }
5690}
5691
5692static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5693{
5694 struct e1000_hw *hw = &adapter->hw;
5695 u32 vmolr = rd32(E1000_VMOLR(vf));
5696 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5697
5698 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
5699 IGB_VF_FLAG_MULTI_PROMISC);
5700 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5701
5702 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
5703 vmolr |= E1000_VMOLR_MPME;
5704 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
5705 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
5706 } else {
5707
5708
5709
5710
5711 if (vf_data->num_vf_mc_hashes > 30) {
5712 vmolr |= E1000_VMOLR_MPME;
5713 } else if (vf_data->num_vf_mc_hashes) {
5714 int j;
5715
5716 vmolr |= E1000_VMOLR_ROMPE;
5717 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5718 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5719 }
5720 }
5721
5722 wr32(E1000_VMOLR(vf), vmolr);
5723
5724
5725 if (*msgbuf & E1000_VT_MSGINFO_MASK)
5726 return -EINVAL;
5727
5728 return 0;
5729}
5730
5731static int igb_set_vf_multicasts(struct igb_adapter *adapter,
5732 u32 *msgbuf, u32 vf)
5733{
5734 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5735 u16 *hash_list = (u16 *)&msgbuf[1];
5736 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5737 int i;
5738
5739
5740
5741
5742
5743 vf_data->num_vf_mc_hashes = n;
5744
5745
5746 if (n > 30)
5747 n = 30;
5748
5749
5750 for (i = 0; i < n; i++)
5751 vf_data->vf_mc_hashes[i] = hash_list[i];
5752
5753
5754 igb_set_rx_mode(adapter->netdev);
5755
5756 return 0;
5757}
5758
5759static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
5760{
5761 struct e1000_hw *hw = &adapter->hw;
5762 struct vf_data_storage *vf_data;
5763 int i, j;
5764
5765 for (i = 0; i < adapter->vfs_allocated_count; i++) {
5766 u32 vmolr = rd32(E1000_VMOLR(i));
5767
5768 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5769
5770 vf_data = &adapter->vf_data[i];
5771
5772 if ((vf_data->num_vf_mc_hashes > 30) ||
5773 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
5774 vmolr |= E1000_VMOLR_MPME;
5775 } else if (vf_data->num_vf_mc_hashes) {
5776 vmolr |= E1000_VMOLR_ROMPE;
5777 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5778 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5779 }
5780 wr32(E1000_VMOLR(i), vmolr);
5781 }
5782}
5783
5784static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
5785{
5786 struct e1000_hw *hw = &adapter->hw;
5787 u32 pool_mask, reg, vid;
5788 int i;
5789
5790 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5791
5792
5793 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5794 reg = rd32(E1000_VLVF(i));
5795
5796
5797 reg &= ~pool_mask;
5798
5799
5800 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
5801 (reg & E1000_VLVF_VLANID_ENABLE)) {
5802 reg = 0;
5803 vid = reg & E1000_VLVF_VLANID_MASK;
5804 igb_vfta_set(hw, vid, false);
5805 }
5806
5807 wr32(E1000_VLVF(i), reg);
5808 }
5809
5810 adapter->vf_data[vf].vlans_enabled = 0;
5811}
5812
5813static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
5814{
5815 struct e1000_hw *hw = &adapter->hw;
5816 u32 reg, i;
5817
5818
5819 if (hw->mac.type < e1000_82576)
5820 return -1;
5821
5822
5823 if (!adapter->vfs_allocated_count)
5824 return -1;
5825
5826
5827 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5828 reg = rd32(E1000_VLVF(i));
5829 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5830 vid == (reg & E1000_VLVF_VLANID_MASK))
5831 break;
5832 }
5833
5834 if (add) {
5835 if (i == E1000_VLVF_ARRAY_SIZE) {
5836
5837
5838
5839
5840 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5841 reg = rd32(E1000_VLVF(i));
5842 if (!(reg & E1000_VLVF_VLANID_ENABLE))
5843 break;
5844 }
5845 }
5846 if (i < E1000_VLVF_ARRAY_SIZE) {
5847
5848 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5849
5850
5851 if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
5852
5853 igb_vfta_set(hw, vid, true);
5854 reg |= E1000_VLVF_VLANID_ENABLE;
5855 }
5856 reg &= ~E1000_VLVF_VLANID_MASK;
5857 reg |= vid;
5858 wr32(E1000_VLVF(i), reg);
5859
5860
5861 if (vf >= adapter->vfs_allocated_count)
5862 return 0;
5863
5864 if (!adapter->vf_data[vf].vlans_enabled) {
5865 u32 size;
5866
5867 reg = rd32(E1000_VMOLR(vf));
5868 size = reg & E1000_VMOLR_RLPML_MASK;
5869 size += 4;
5870 reg &= ~E1000_VMOLR_RLPML_MASK;
5871 reg |= size;
5872 wr32(E1000_VMOLR(vf), reg);
5873 }
5874
5875 adapter->vf_data[vf].vlans_enabled++;
5876 }
5877 } else {
5878 if (i < E1000_VLVF_ARRAY_SIZE) {
5879
5880 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
5881
5882 if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
5883 reg = 0;
5884 igb_vfta_set(hw, vid, false);
5885 }
5886 wr32(E1000_VLVF(i), reg);
5887
5888
5889 if (vf >= adapter->vfs_allocated_count)
5890 return 0;
5891
5892 adapter->vf_data[vf].vlans_enabled--;
5893 if (!adapter->vf_data[vf].vlans_enabled) {
5894 u32 size;
5895
5896 reg = rd32(E1000_VMOLR(vf));
5897 size = reg & E1000_VMOLR_RLPML_MASK;
5898 size -= 4;
5899 reg &= ~E1000_VMOLR_RLPML_MASK;
5900 reg |= size;
5901 wr32(E1000_VMOLR(vf), reg);
5902 }
5903 }
5904 }
5905 return 0;
5906}
5907
5908static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
5909{
5910 struct e1000_hw *hw = &adapter->hw;
5911
5912 if (vid)
5913 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
5914 else
5915 wr32(E1000_VMVIR(vf), 0);
5916}
5917
5918static int igb_ndo_set_vf_vlan(struct net_device *netdev,
5919 int vf, u16 vlan, u8 qos)
5920{
5921 int err = 0;
5922 struct igb_adapter *adapter = netdev_priv(netdev);
5923
5924 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
5925 return -EINVAL;
5926 if (vlan || qos) {
5927 err = igb_vlvf_set(adapter, vlan, !!vlan, vf);
5928 if (err)
5929 goto out;
5930 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
5931 igb_set_vmolr(adapter, vf, !vlan);
5932 adapter->vf_data[vf].pf_vlan = vlan;
5933 adapter->vf_data[vf].pf_qos = qos;
5934 dev_info(&adapter->pdev->dev,
5935 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
5936 if (test_bit(__IGB_DOWN, &adapter->state)) {
5937 dev_warn(&adapter->pdev->dev,
5938 "The VF VLAN has been set, but the PF device is not up.\n");
5939 dev_warn(&adapter->pdev->dev,
5940 "Bring the PF device up before attempting to use the VF device.\n");
5941 }
5942 } else {
5943 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan,
5944 false, vf);
5945 igb_set_vmvir(adapter, vlan, vf);
5946 igb_set_vmolr(adapter, vf, true);
5947 adapter->vf_data[vf].pf_vlan = 0;
5948 adapter->vf_data[vf].pf_qos = 0;
5949 }
5950out:
5951 return err;
5952}
5953
5954static int igb_find_vlvf_entry(struct igb_adapter *adapter, int vid)
5955{
5956 struct e1000_hw *hw = &adapter->hw;
5957 int i;
5958 u32 reg;
5959
5960
5961 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5962 reg = rd32(E1000_VLVF(i));
5963 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5964 vid == (reg & E1000_VLVF_VLANID_MASK))
5965 break;
5966 }
5967
5968 if (i >= E1000_VLVF_ARRAY_SIZE)
5969 i = -1;
5970
5971 return i;
5972}
5973
5974static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5975{
5976 struct e1000_hw *hw = &adapter->hw;
5977 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5978 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
5979 int err = 0;
5980
5981
5982
5983
5984 if (add && (adapter->netdev->flags & IFF_PROMISC))
5985 err = igb_vlvf_set(adapter, vid, add,
5986 adapter->vfs_allocated_count);
5987 if (err)
5988 goto out;
5989
5990 err = igb_vlvf_set(adapter, vid, add, vf);
5991
5992 if (err)
5993 goto out;
5994
5995
5996
5997
5998 if (!add && (adapter->netdev->flags & IFF_PROMISC)) {
5999 u32 vlvf, bits;
6000 int regndx = igb_find_vlvf_entry(adapter, vid);
6001
6002 if (regndx < 0)
6003 goto out;
6004
6005
6006
6007 vlvf = bits = rd32(E1000_VLVF(regndx));
6008 bits &= 1 << (E1000_VLVF_POOLSEL_SHIFT +
6009 adapter->vfs_allocated_count);
6010
6011
6012
6013
6014 if ((vlvf & VLAN_VID_MASK) == vid &&
6015 !test_bit(vid, adapter->active_vlans) &&
6016 !bits)
6017 igb_vlvf_set(adapter, vid, add,
6018 adapter->vfs_allocated_count);
6019 }
6020
6021out:
6022 return err;
6023}
6024
6025static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
6026{
6027
6028 adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC;
6029 adapter->vf_data[vf].last_nack = jiffies;
6030
6031
6032 igb_set_vmolr(adapter, vf, true);
6033
6034
6035 igb_clear_vf_vfta(adapter, vf);
6036 if (adapter->vf_data[vf].pf_vlan)
6037 igb_ndo_set_vf_vlan(adapter->netdev, vf,
6038 adapter->vf_data[vf].pf_vlan,
6039 adapter->vf_data[vf].pf_qos);
6040 else
6041 igb_clear_vf_vfta(adapter, vf);
6042
6043
6044 adapter->vf_data[vf].num_vf_mc_hashes = 0;
6045
6046
6047 igb_set_rx_mode(adapter->netdev);
6048}
6049
6050static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
6051{
6052 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
6053
6054
6055 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
6056 eth_zero_addr(vf_mac);
6057
6058
6059 igb_vf_reset(adapter, vf);
6060}
6061
6062static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
6063{
6064 struct e1000_hw *hw = &adapter->hw;
6065 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
6066 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
6067 u32 reg, msgbuf[3];
6068 u8 *addr = (u8 *)(&msgbuf[1]);
6069
6070
6071 igb_vf_reset(adapter, vf);
6072
6073
6074 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
6075
6076
6077 reg = rd32(E1000_VFTE);
6078 wr32(E1000_VFTE, reg | (1 << vf));
6079 reg = rd32(E1000_VFRE);
6080 wr32(E1000_VFRE, reg | (1 << vf));
6081
6082 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
6083
6084
6085 if (!is_zero_ether_addr(vf_mac)) {
6086 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
6087 memcpy(addr, vf_mac, ETH_ALEN);
6088 } else {
6089 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_NACK;
6090 }
6091 igb_write_mbx(hw, msgbuf, 3, vf);
6092}
6093
6094static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
6095{
6096
6097
6098
6099 unsigned char *addr = (char *)&msg[1];
6100 int err = -1;
6101
6102 if (is_valid_ether_addr(addr))
6103 err = igb_set_vf_mac(adapter, vf, addr);
6104
6105 return err;
6106}
6107
6108static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
6109{
6110 struct e1000_hw *hw = &adapter->hw;
6111 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
6112 u32 msg = E1000_VT_MSGTYPE_NACK;
6113
6114
6115 if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
6116 time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
6117 igb_write_mbx(hw, &msg, 1, vf);
6118 vf_data->last_nack = jiffies;
6119 }
6120}
6121
6122static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
6123{
6124 struct pci_dev *pdev = adapter->pdev;
6125 u32 msgbuf[E1000_VFMAILBOX_SIZE];
6126 struct e1000_hw *hw = &adapter->hw;
6127 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
6128 s32 retval;
6129
6130 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
6131
6132 if (retval) {
6133
6134 dev_err(&pdev->dev, "Error receiving message from VF\n");
6135 vf_data->flags &= ~IGB_VF_FLAG_CTS;
6136 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
6137 return;
6138 goto out;
6139 }
6140
6141
6142 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
6143 return;
6144
6145
6146
6147
6148 if (msgbuf[0] == E1000_VF_RESET) {
6149 igb_vf_reset_msg(adapter, vf);
6150 return;
6151 }
6152
6153 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
6154 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
6155 return;
6156 retval = -1;
6157 goto out;
6158 }
6159
6160 switch ((msgbuf[0] & 0xFFFF)) {
6161 case E1000_VF_SET_MAC_ADDR:
6162 retval = -EINVAL;
6163 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC))
6164 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
6165 else
6166 dev_warn(&pdev->dev,
6167 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n",
6168 vf);
6169 break;
6170 case E1000_VF_SET_PROMISC:
6171 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
6172 break;
6173 case E1000_VF_SET_MULTICAST:
6174 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
6175 break;
6176 case E1000_VF_SET_LPE:
6177 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
6178 break;
6179 case E1000_VF_SET_VLAN:
6180 retval = -1;
6181 if (vf_data->pf_vlan)
6182 dev_warn(&pdev->dev,
6183 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n",
6184 vf);
6185 else
6186 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
6187 break;
6188 default:
6189 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
6190 retval = -1;
6191 break;
6192 }
6193
6194 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
6195out:
6196
6197 if (retval)
6198 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
6199 else
6200 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
6201
6202 igb_write_mbx(hw, msgbuf, 1, vf);
6203}
6204
6205static void igb_msg_task(struct igb_adapter *adapter)
6206{
6207 struct e1000_hw *hw = &adapter->hw;
6208 u32 vf;
6209
6210 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
6211
6212 if (!igb_check_for_rst(hw, vf))
6213 igb_vf_reset_event(adapter, vf);
6214
6215
6216 if (!igb_check_for_msg(hw, vf))
6217 igb_rcv_msg_from_vf(adapter, vf);
6218
6219
6220 if (!igb_check_for_ack(hw, vf))
6221 igb_rcv_ack_from_vf(adapter, vf);
6222 }
6223}
6224
6225
6226
6227
6228
6229
6230
6231
6232
6233
6234
6235static void igb_set_uta(struct igb_adapter *adapter)
6236{
6237 struct e1000_hw *hw = &adapter->hw;
6238 int i;
6239
6240
6241 if (hw->mac.type < e1000_82576)
6242 return;
6243
6244
6245 if (!adapter->vfs_allocated_count)
6246 return;
6247
6248 for (i = 0; i < hw->mac.uta_reg_count; i++)
6249 array_wr32(E1000_UTA, i, ~0);
6250}
6251
6252
6253
6254
6255
6256
6257static irqreturn_t igb_intr_msi(int irq, void *data)
6258{
6259 struct igb_adapter *adapter = data;
6260 struct igb_q_vector *q_vector = adapter->q_vector[0];
6261 struct e1000_hw *hw = &adapter->hw;
6262
6263 u32 icr = rd32(E1000_ICR);
6264
6265 igb_write_itr(q_vector);
6266
6267 if (icr & E1000_ICR_DRSTA)
6268 schedule_work(&adapter->reset_task);
6269
6270 if (icr & E1000_ICR_DOUTSYNC) {
6271
6272 adapter->stats.doosync++;
6273 }
6274
6275 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
6276 hw->mac.get_link_status = 1;
6277 if (!test_bit(__IGB_DOWN, &adapter->state))
6278 mod_timer(&adapter->watchdog_timer, jiffies + 1);
6279 }
6280
6281 if (icr & E1000_ICR_TS)
6282 igb_tsync_interrupt(adapter);
6283
6284 napi_schedule(&q_vector->napi);
6285
6286 return IRQ_HANDLED;
6287}
6288
6289
6290
6291
6292
6293
6294static irqreturn_t igb_intr(int irq, void *data)
6295{
6296 struct igb_adapter *adapter = data;
6297 struct igb_q_vector *q_vector = adapter->q_vector[0];
6298 struct e1000_hw *hw = &adapter->hw;
6299
6300
6301
6302 u32 icr = rd32(E1000_ICR);
6303
6304
6305
6306
6307 if (!(icr & E1000_ICR_INT_ASSERTED))
6308 return IRQ_NONE;
6309
6310 igb_write_itr(q_vector);
6311
6312 if (icr & E1000_ICR_DRSTA)
6313 schedule_work(&adapter->reset_task);
6314
6315 if (icr & E1000_ICR_DOUTSYNC) {
6316
6317 adapter->stats.doosync++;
6318 }
6319
6320 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
6321 hw->mac.get_link_status = 1;
6322
6323 if (!test_bit(__IGB_DOWN, &adapter->state))
6324 mod_timer(&adapter->watchdog_timer, jiffies + 1);
6325 }
6326
6327 if (icr & E1000_ICR_TS)
6328 igb_tsync_interrupt(adapter);
6329
6330 napi_schedule(&q_vector->napi);
6331
6332 return IRQ_HANDLED;
6333}
6334
6335static void igb_ring_irq_enable(struct igb_q_vector *q_vector)
6336{
6337 struct igb_adapter *adapter = q_vector->adapter;
6338 struct e1000_hw *hw = &adapter->hw;
6339
6340 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
6341 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
6342 if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
6343 igb_set_itr(q_vector);
6344 else
6345 igb_update_ring_itr(q_vector);
6346 }
6347
6348 if (!test_bit(__IGB_DOWN, &adapter->state)) {
6349 if (adapter->flags & IGB_FLAG_HAS_MSIX)
6350 wr32(E1000_EIMS, q_vector->eims_value);
6351 else
6352 igb_irq_enable(adapter);
6353 }
6354}
6355
6356
6357
6358
6359
6360
6361static int igb_poll(struct napi_struct *napi, int budget)
6362{
6363 struct igb_q_vector *q_vector = container_of(napi,
6364 struct igb_q_vector,
6365 napi);
6366 bool clean_complete = true;
6367 int work_done = 0;
6368
6369#ifdef CONFIG_IGB_DCA
6370 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
6371 igb_update_dca(q_vector);
6372#endif
6373 if (q_vector->tx.ring)
6374 clean_complete = igb_clean_tx_irq(q_vector);
6375
6376 if (q_vector->rx.ring) {
6377 int cleaned = igb_clean_rx_irq(q_vector, budget);
6378
6379 work_done += cleaned;
6380 clean_complete &= (cleaned < budget);
6381 }
6382
6383
6384 if (!clean_complete)
6385 return budget;
6386
6387
6388 napi_complete_done(napi, work_done);
6389 igb_ring_irq_enable(q_vector);
6390
6391 return 0;
6392}
6393
6394
6395
6396
6397
6398
6399
6400static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
6401{
6402 struct igb_adapter *adapter = q_vector->adapter;
6403 struct igb_ring *tx_ring = q_vector->tx.ring;
6404 struct igb_tx_buffer *tx_buffer;
6405 union e1000_adv_tx_desc *tx_desc;
6406 unsigned int total_bytes = 0, total_packets = 0;
6407 unsigned int budget = q_vector->tx.work_limit;
6408 unsigned int i = tx_ring->next_to_clean;
6409
6410 if (test_bit(__IGB_DOWN, &adapter->state))
6411 return true;
6412
6413 tx_buffer = &tx_ring->tx_buffer_info[i];
6414 tx_desc = IGB_TX_DESC(tx_ring, i);
6415 i -= tx_ring->count;
6416
6417 do {
6418 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
6419
6420
6421 if (!eop_desc)
6422 break;
6423
6424
6425 read_barrier_depends();
6426
6427
6428 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
6429 break;
6430
6431
6432 tx_buffer->next_to_watch = NULL;
6433
6434
6435 total_bytes += tx_buffer->bytecount;
6436 total_packets += tx_buffer->gso_segs;
6437
6438
6439 dev_consume_skb_any(tx_buffer->skb);
6440
6441
6442 dma_unmap_single(tx_ring->dev,
6443 dma_unmap_addr(tx_buffer, dma),
6444 dma_unmap_len(tx_buffer, len),
6445 DMA_TO_DEVICE);
6446
6447
6448 tx_buffer->skb = NULL;
6449 dma_unmap_len_set(tx_buffer, len, 0);
6450
6451
6452 while (tx_desc != eop_desc) {
6453 tx_buffer++;
6454 tx_desc++;
6455 i++;
6456 if (unlikely(!i)) {
6457 i -= tx_ring->count;
6458 tx_buffer = tx_ring->tx_buffer_info;
6459 tx_desc = IGB_TX_DESC(tx_ring, 0);
6460 }
6461
6462
6463 if (dma_unmap_len(tx_buffer, len)) {
6464 dma_unmap_page(tx_ring->dev,
6465 dma_unmap_addr(tx_buffer, dma),
6466 dma_unmap_len(tx_buffer, len),
6467 DMA_TO_DEVICE);
6468 dma_unmap_len_set(tx_buffer, len, 0);
6469 }
6470 }
6471
6472
6473 tx_buffer++;
6474 tx_desc++;
6475 i++;
6476 if (unlikely(!i)) {
6477 i -= tx_ring->count;
6478 tx_buffer = tx_ring->tx_buffer_info;
6479 tx_desc = IGB_TX_DESC(tx_ring, 0);
6480 }
6481
6482
6483 prefetch(tx_desc);
6484
6485
6486 budget--;
6487 } while (likely(budget));
6488
6489 netdev_tx_completed_queue(txring_txq(tx_ring),
6490 total_packets, total_bytes);
6491 i += tx_ring->count;
6492 tx_ring->next_to_clean = i;
6493 u64_stats_update_begin(&tx_ring->tx_syncp);
6494 tx_ring->tx_stats.bytes += total_bytes;
6495 tx_ring->tx_stats.packets += total_packets;
6496 u64_stats_update_end(&tx_ring->tx_syncp);
6497 q_vector->tx.total_bytes += total_bytes;
6498 q_vector->tx.total_packets += total_packets;
6499
6500 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
6501 struct e1000_hw *hw = &adapter->hw;
6502
6503
6504
6505
6506 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
6507 if (tx_buffer->next_to_watch &&
6508 time_after(jiffies, tx_buffer->time_stamp +
6509 (adapter->tx_timeout_factor * HZ)) &&
6510 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
6511
6512
6513 dev_err(tx_ring->dev,
6514 "Detected Tx Unit Hang\n"
6515 " Tx Queue <%d>\n"
6516 " TDH <%x>\n"
6517 " TDT <%x>\n"
6518 " next_to_use <%x>\n"
6519 " next_to_clean <%x>\n"
6520 "buffer_info[next_to_clean]\n"
6521 " time_stamp <%lx>\n"
6522 " next_to_watch <%p>\n"
6523 " jiffies <%lx>\n"
6524 " desc.status <%x>\n",
6525 tx_ring->queue_index,
6526 rd32(E1000_TDH(tx_ring->reg_idx)),
6527 readl(tx_ring->tail),
6528 tx_ring->next_to_use,
6529 tx_ring->next_to_clean,
6530 tx_buffer->time_stamp,
6531 tx_buffer->next_to_watch,
6532 jiffies,
6533 tx_buffer->next_to_watch->wb.status);
6534 netif_stop_subqueue(tx_ring->netdev,
6535 tx_ring->queue_index);
6536
6537
6538 return true;
6539 }
6540 }
6541
6542#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
6543 if (unlikely(total_packets &&
6544 netif_carrier_ok(tx_ring->netdev) &&
6545 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) {
6546
6547
6548
6549 smp_mb();
6550 if (__netif_subqueue_stopped(tx_ring->netdev,
6551 tx_ring->queue_index) &&
6552 !(test_bit(__IGB_DOWN, &adapter->state))) {
6553 netif_wake_subqueue(tx_ring->netdev,
6554 tx_ring->queue_index);
6555
6556 u64_stats_update_begin(&tx_ring->tx_syncp);
6557 tx_ring->tx_stats.restart_queue++;
6558 u64_stats_update_end(&tx_ring->tx_syncp);
6559 }
6560 }
6561
6562 return !!budget;
6563}
6564
6565
6566
6567
6568
6569
6570
6571
6572static void igb_reuse_rx_page(struct igb_ring *rx_ring,
6573 struct igb_rx_buffer *old_buff)
6574{
6575 struct igb_rx_buffer *new_buff;
6576 u16 nta = rx_ring->next_to_alloc;
6577
6578 new_buff = &rx_ring->rx_buffer_info[nta];
6579
6580
6581 nta++;
6582 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
6583
6584
6585 *new_buff = *old_buff;
6586
6587
6588 dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma,
6589 old_buff->page_offset,
6590 IGB_RX_BUFSZ,
6591 DMA_FROM_DEVICE);
6592}
6593
6594static inline bool igb_page_is_reserved(struct page *page)
6595{
6596 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page);
6597}
6598
6599static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer,
6600 struct page *page,
6601 unsigned int truesize)
6602{
6603
6604 if (unlikely(igb_page_is_reserved(page)))
6605 return false;
6606
6607#if (PAGE_SIZE < 8192)
6608
6609 if (unlikely(page_count(page) != 1))
6610 return false;
6611
6612
6613 rx_buffer->page_offset ^= IGB_RX_BUFSZ;
6614#else
6615
6616 rx_buffer->page_offset += truesize;
6617
6618 if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ))
6619 return false;
6620#endif
6621
6622
6623
6624
6625 atomic_inc(&page->_count);
6626
6627 return true;
6628}
6629
6630
6631
6632
6633
6634
6635
6636
6637
6638
6639
6640
6641
6642
6643
6644
6645static bool igb_add_rx_frag(struct igb_ring *rx_ring,
6646 struct igb_rx_buffer *rx_buffer,
6647 union e1000_adv_rx_desc *rx_desc,
6648 struct sk_buff *skb)
6649{
6650 struct page *page = rx_buffer->page;
6651 unsigned char *va = page_address(page) + rx_buffer->page_offset;
6652 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
6653#if (PAGE_SIZE < 8192)
6654 unsigned int truesize = IGB_RX_BUFSZ;
6655#else
6656 unsigned int truesize = SKB_DATA_ALIGN(size);
6657#endif
6658 unsigned int pull_len;
6659
6660 if (unlikely(skb_is_nonlinear(skb)))
6661 goto add_tail_frag;
6662
6663 if (unlikely(igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))) {
6664 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6665 va += IGB_TS_HDR_LEN;
6666 size -= IGB_TS_HDR_LEN;
6667 }
6668
6669 if (likely(size <= IGB_RX_HDR_LEN)) {
6670 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
6671
6672
6673 if (likely(!igb_page_is_reserved(page)))
6674 return true;
6675
6676
6677 __free_page(page);
6678 return false;
6679 }
6680
6681
6682
6683
6684 pull_len = eth_get_headlen(va, IGB_RX_HDR_LEN);
6685
6686
6687 memcpy(__skb_put(skb, pull_len), va, ALIGN(pull_len, sizeof(long)));
6688
6689
6690 va += pull_len;
6691 size -= pull_len;
6692
6693add_tail_frag:
6694 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
6695 (unsigned long)va & ~PAGE_MASK, size, truesize);
6696
6697 return igb_can_reuse_rx_page(rx_buffer, page, truesize);
6698}
6699
6700static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring,
6701 union e1000_adv_rx_desc *rx_desc,
6702 struct sk_buff *skb)
6703{
6704 struct igb_rx_buffer *rx_buffer;
6705 struct page *page;
6706
6707 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
6708 page = rx_buffer->page;
6709 prefetchw(page);
6710
6711 if (likely(!skb)) {
6712 void *page_addr = page_address(page) +
6713 rx_buffer->page_offset;
6714
6715
6716 prefetch(page_addr);
6717#if L1_CACHE_BYTES < 128
6718 prefetch(page_addr + L1_CACHE_BYTES);
6719#endif
6720
6721
6722 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IGB_RX_HDR_LEN);
6723 if (unlikely(!skb)) {
6724 rx_ring->rx_stats.alloc_failed++;
6725 return NULL;
6726 }
6727
6728
6729
6730
6731
6732 prefetchw(skb->data);
6733 }
6734
6735
6736 dma_sync_single_range_for_cpu(rx_ring->dev,
6737 rx_buffer->dma,
6738 rx_buffer->page_offset,
6739 IGB_RX_BUFSZ,
6740 DMA_FROM_DEVICE);
6741
6742
6743 if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
6744
6745 igb_reuse_rx_page(rx_ring, rx_buffer);
6746 } else {
6747
6748 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
6749 PAGE_SIZE, DMA_FROM_DEVICE);
6750 }
6751
6752
6753 rx_buffer->page = NULL;
6754
6755 return skb;
6756}
6757
6758static inline void igb_rx_checksum(struct igb_ring *ring,
6759 union e1000_adv_rx_desc *rx_desc,
6760 struct sk_buff *skb)
6761{
6762 skb_checksum_none_assert(skb);
6763
6764
6765 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
6766 return;
6767
6768
6769 if (!(ring->netdev->features & NETIF_F_RXCSUM))
6770 return;
6771
6772
6773 if (igb_test_staterr(rx_desc,
6774 E1000_RXDEXT_STATERR_TCPE |
6775 E1000_RXDEXT_STATERR_IPE)) {
6776
6777
6778
6779
6780 if (!((skb->len == 60) &&
6781 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
6782 u64_stats_update_begin(&ring->rx_syncp);
6783 ring->rx_stats.csum_err++;
6784 u64_stats_update_end(&ring->rx_syncp);
6785 }
6786
6787 return;
6788 }
6789
6790 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
6791 E1000_RXD_STAT_UDPCS))
6792 skb->ip_summed = CHECKSUM_UNNECESSARY;
6793
6794 dev_dbg(ring->dev, "cksum success: bits %08X\n",
6795 le32_to_cpu(rx_desc->wb.upper.status_error));
6796}
6797
6798static inline void igb_rx_hash(struct igb_ring *ring,
6799 union e1000_adv_rx_desc *rx_desc,
6800 struct sk_buff *skb)
6801{
6802 if (ring->netdev->features & NETIF_F_RXHASH)
6803 skb_set_hash(skb,
6804 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
6805 PKT_HASH_TYPE_L3);
6806}
6807
6808
6809
6810
6811
6812
6813
6814
6815
6816
6817
6818
6819static bool igb_is_non_eop(struct igb_ring *rx_ring,
6820 union e1000_adv_rx_desc *rx_desc)
6821{
6822 u32 ntc = rx_ring->next_to_clean + 1;
6823
6824
6825 ntc = (ntc < rx_ring->count) ? ntc : 0;
6826 rx_ring->next_to_clean = ntc;
6827
6828 prefetch(IGB_RX_DESC(rx_ring, ntc));
6829
6830 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)))
6831 return false;
6832
6833 return true;
6834}
6835
6836
6837
6838
6839
6840
6841
6842
6843
6844
6845
6846
6847
6848
6849
6850static bool igb_cleanup_headers(struct igb_ring *rx_ring,
6851 union e1000_adv_rx_desc *rx_desc,
6852 struct sk_buff *skb)
6853{
6854 if (unlikely((igb_test_staterr(rx_desc,
6855 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
6856 struct net_device *netdev = rx_ring->netdev;
6857 if (!(netdev->features & NETIF_F_RXALL)) {
6858 dev_kfree_skb_any(skb);
6859 return true;
6860 }
6861 }
6862
6863
6864 if (eth_skb_pad(skb))
6865 return true;
6866
6867 return false;
6868}
6869
6870
6871
6872
6873
6874
6875
6876
6877
6878
6879
6880static void igb_process_skb_fields(struct igb_ring *rx_ring,
6881 union e1000_adv_rx_desc *rx_desc,
6882 struct sk_buff *skb)
6883{
6884 struct net_device *dev = rx_ring->netdev;
6885
6886 igb_rx_hash(rx_ring, rx_desc, skb);
6887
6888 igb_rx_checksum(rx_ring, rx_desc, skb);
6889
6890 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) &&
6891 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))
6892 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb);
6893
6894 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
6895 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
6896 u16 vid;
6897
6898 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&
6899 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))
6900 vid = be16_to_cpu(rx_desc->wb.upper.vlan);
6901 else
6902 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
6903
6904 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
6905 }
6906
6907 skb_record_rx_queue(skb, rx_ring->queue_index);
6908
6909 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
6910}
6911
6912static int igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget)
6913{
6914 struct igb_ring *rx_ring = q_vector->rx.ring;
6915 struct sk_buff *skb = rx_ring->skb;
6916 unsigned int total_bytes = 0, total_packets = 0;
6917 u16 cleaned_count = igb_desc_unused(rx_ring);
6918
6919 while (likely(total_packets < budget)) {
6920 union e1000_adv_rx_desc *rx_desc;
6921
6922
6923 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
6924 igb_alloc_rx_buffers(rx_ring, cleaned_count);
6925 cleaned_count = 0;
6926 }
6927
6928 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean);
6929
6930 if (!rx_desc->wb.upper.status_error)
6931 break;
6932
6933
6934
6935
6936
6937 dma_rmb();
6938
6939
6940 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb);
6941
6942
6943 if (!skb)
6944 break;
6945
6946 cleaned_count++;
6947
6948
6949 if (igb_is_non_eop(rx_ring, rx_desc))
6950 continue;
6951
6952
6953 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) {
6954 skb = NULL;
6955 continue;
6956 }
6957
6958
6959 total_bytes += skb->len;
6960
6961
6962 igb_process_skb_fields(rx_ring, rx_desc, skb);
6963
6964 napi_gro_receive(&q_vector->napi, skb);
6965
6966
6967 skb = NULL;
6968
6969
6970 total_packets++;
6971 }
6972
6973
6974 rx_ring->skb = skb;
6975
6976 u64_stats_update_begin(&rx_ring->rx_syncp);
6977 rx_ring->rx_stats.packets += total_packets;
6978 rx_ring->rx_stats.bytes += total_bytes;
6979 u64_stats_update_end(&rx_ring->rx_syncp);
6980 q_vector->rx.total_packets += total_packets;
6981 q_vector->rx.total_bytes += total_bytes;
6982
6983 if (cleaned_count)
6984 igb_alloc_rx_buffers(rx_ring, cleaned_count);
6985
6986 return total_packets;
6987}
6988
6989static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
6990 struct igb_rx_buffer *bi)
6991{
6992 struct page *page = bi->page;
6993 dma_addr_t dma;
6994
6995
6996 if (likely(page))
6997 return true;
6998
6999
7000 page = dev_alloc_page();
7001 if (unlikely(!page)) {
7002 rx_ring->rx_stats.alloc_failed++;
7003 return false;
7004 }
7005
7006
7007 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
7008
7009
7010
7011
7012 if (dma_mapping_error(rx_ring->dev, dma)) {
7013 __free_page(page);
7014
7015 rx_ring->rx_stats.alloc_failed++;
7016 return false;
7017 }
7018
7019 bi->dma = dma;
7020 bi->page = page;
7021 bi->page_offset = 0;
7022
7023 return true;
7024}
7025
7026
7027
7028
7029
7030void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
7031{
7032 union e1000_adv_rx_desc *rx_desc;
7033 struct igb_rx_buffer *bi;
7034 u16 i = rx_ring->next_to_use;
7035
7036
7037 if (!cleaned_count)
7038 return;
7039
7040 rx_desc = IGB_RX_DESC(rx_ring, i);
7041 bi = &rx_ring->rx_buffer_info[i];
7042 i -= rx_ring->count;
7043
7044 do {
7045 if (!igb_alloc_mapped_page(rx_ring, bi))
7046 break;
7047
7048
7049
7050
7051 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
7052
7053 rx_desc++;
7054 bi++;
7055 i++;
7056 if (unlikely(!i)) {
7057 rx_desc = IGB_RX_DESC(rx_ring, 0);
7058 bi = rx_ring->rx_buffer_info;
7059 i -= rx_ring->count;
7060 }
7061
7062
7063 rx_desc->wb.upper.status_error = 0;
7064
7065 cleaned_count--;
7066 } while (cleaned_count);
7067
7068 i += rx_ring->count;
7069
7070 if (rx_ring->next_to_use != i) {
7071
7072 rx_ring->next_to_use = i;
7073
7074
7075 rx_ring->next_to_alloc = i;
7076
7077
7078
7079
7080
7081
7082 wmb();
7083 writel(i, rx_ring->tail);
7084 }
7085}
7086
7087
7088
7089
7090
7091
7092
7093static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
7094{
7095 struct igb_adapter *adapter = netdev_priv(netdev);
7096 struct mii_ioctl_data *data = if_mii(ifr);
7097
7098 if (adapter->hw.phy.media_type != e1000_media_type_copper)
7099 return -EOPNOTSUPP;
7100
7101 switch (cmd) {
7102 case SIOCGMIIPHY:
7103 data->phy_id = adapter->hw.phy.addr;
7104 break;
7105 case SIOCGMIIREG:
7106 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
7107 &data->val_out))
7108 return -EIO;
7109 break;
7110 case SIOCSMIIREG:
7111 default:
7112 return -EOPNOTSUPP;
7113 }
7114 return 0;
7115}
7116
7117
7118
7119
7120
7121
7122
7123static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
7124{
7125 switch (cmd) {
7126 case SIOCGMIIPHY:
7127 case SIOCGMIIREG:
7128 case SIOCSMIIREG:
7129 return igb_mii_ioctl(netdev, ifr, cmd);
7130 case SIOCGHWTSTAMP:
7131 return igb_ptp_get_ts_config(netdev, ifr);
7132 case SIOCSHWTSTAMP:
7133 return igb_ptp_set_ts_config(netdev, ifr);
7134 default:
7135 return -EOPNOTSUPP;
7136 }
7137}
7138
7139void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
7140{
7141 struct igb_adapter *adapter = hw->back;
7142
7143 pci_read_config_word(adapter->pdev, reg, value);
7144}
7145
7146void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
7147{
7148 struct igb_adapter *adapter = hw->back;
7149
7150 pci_write_config_word(adapter->pdev, reg, *value);
7151}
7152
7153s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
7154{
7155 struct igb_adapter *adapter = hw->back;
7156
7157 if (pcie_capability_read_word(adapter->pdev, reg, value))
7158 return -E1000_ERR_CONFIG;
7159
7160 return 0;
7161}
7162
7163s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
7164{
7165 struct igb_adapter *adapter = hw->back;
7166
7167 if (pcie_capability_write_word(adapter->pdev, reg, *value))
7168 return -E1000_ERR_CONFIG;
7169
7170 return 0;
7171}
7172
7173static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features)
7174{
7175 struct igb_adapter *adapter = netdev_priv(netdev);
7176 struct e1000_hw *hw = &adapter->hw;
7177 u32 ctrl, rctl;
7178 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
7179
7180 if (enable) {
7181
7182 ctrl = rd32(E1000_CTRL);
7183 ctrl |= E1000_CTRL_VME;
7184 wr32(E1000_CTRL, ctrl);
7185
7186
7187 rctl = rd32(E1000_RCTL);
7188 rctl &= ~E1000_RCTL_CFIEN;
7189 wr32(E1000_RCTL, rctl);
7190 } else {
7191
7192 ctrl = rd32(E1000_CTRL);
7193 ctrl &= ~E1000_CTRL_VME;
7194 wr32(E1000_CTRL, ctrl);
7195 }
7196
7197 igb_rlpml_set(adapter);
7198}
7199
7200static int igb_vlan_rx_add_vid(struct net_device *netdev,
7201 __be16 proto, u16 vid)
7202{
7203 struct igb_adapter *adapter = netdev_priv(netdev);
7204 struct e1000_hw *hw = &adapter->hw;
7205 int pf_id = adapter->vfs_allocated_count;
7206
7207
7208 igb_vlvf_set(adapter, vid, true, pf_id);
7209
7210
7211 igb_vfta_set(hw, vid, true);
7212
7213 set_bit(vid, adapter->active_vlans);
7214
7215 return 0;
7216}
7217
7218static int igb_vlan_rx_kill_vid(struct net_device *netdev,
7219 __be16 proto, u16 vid)
7220{
7221 struct igb_adapter *adapter = netdev_priv(netdev);
7222 struct e1000_hw *hw = &adapter->hw;
7223 int pf_id = adapter->vfs_allocated_count;
7224 s32 err;
7225
7226
7227 err = igb_vlvf_set(adapter, vid, false, pf_id);
7228
7229
7230 if (err)
7231 igb_vfta_set(hw, vid, false);
7232
7233 clear_bit(vid, adapter->active_vlans);
7234
7235 return 0;
7236}
7237
7238static void igb_restore_vlan(struct igb_adapter *adapter)
7239{
7240 u16 vid;
7241
7242 igb_vlan_mode(adapter->netdev, adapter->netdev->features);
7243
7244 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
7245 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
7246}
7247
7248int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
7249{
7250 struct pci_dev *pdev = adapter->pdev;
7251 struct e1000_mac_info *mac = &adapter->hw.mac;
7252
7253 mac->autoneg = 0;
7254
7255
7256
7257
7258 if ((spd & 1) || (dplx & ~1))
7259 goto err_inval;
7260
7261
7262
7263
7264 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
7265 switch (spd + dplx) {
7266 case SPEED_10 + DUPLEX_HALF:
7267 case SPEED_10 + DUPLEX_FULL:
7268 case SPEED_100 + DUPLEX_HALF:
7269 goto err_inval;
7270 default:
7271 break;
7272 }
7273 }
7274
7275 switch (spd + dplx) {
7276 case SPEED_10 + DUPLEX_HALF:
7277 mac->forced_speed_duplex = ADVERTISE_10_HALF;
7278 break;
7279 case SPEED_10 + DUPLEX_FULL:
7280 mac->forced_speed_duplex = ADVERTISE_10_FULL;
7281 break;
7282 case SPEED_100 + DUPLEX_HALF:
7283 mac->forced_speed_duplex = ADVERTISE_100_HALF;
7284 break;
7285 case SPEED_100 + DUPLEX_FULL:
7286 mac->forced_speed_duplex = ADVERTISE_100_FULL;
7287 break;
7288 case SPEED_1000 + DUPLEX_FULL:
7289 mac->autoneg = 1;
7290 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
7291 break;
7292 case SPEED_1000 + DUPLEX_HALF:
7293 default:
7294 goto err_inval;
7295 }
7296
7297
7298 adapter->hw.phy.mdix = AUTO_ALL_MODES;
7299
7300 return 0;
7301
7302err_inval:
7303 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
7304 return -EINVAL;
7305}
7306
7307static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake,
7308 bool runtime)
7309{
7310 struct net_device *netdev = pci_get_drvdata(pdev);
7311 struct igb_adapter *adapter = netdev_priv(netdev);
7312 struct e1000_hw *hw = &adapter->hw;
7313 u32 ctrl, rctl, status;
7314 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
7315#ifdef CONFIG_PM
7316 int retval = 0;
7317#endif
7318
7319 netif_device_detach(netdev);
7320
7321 if (netif_running(netdev))
7322 __igb_close(netdev, true);
7323
7324 igb_clear_interrupt_scheme(adapter);
7325
7326#ifdef CONFIG_PM
7327 retval = pci_save_state(pdev);
7328 if (retval)
7329 return retval;
7330#endif
7331
7332 status = rd32(E1000_STATUS);
7333 if (status & E1000_STATUS_LU)
7334 wufc &= ~E1000_WUFC_LNKC;
7335
7336 if (wufc) {
7337 igb_setup_rctl(adapter);
7338 igb_set_rx_mode(netdev);
7339
7340
7341 if (wufc & E1000_WUFC_MC) {
7342 rctl = rd32(E1000_RCTL);
7343 rctl |= E1000_RCTL_MPE;
7344 wr32(E1000_RCTL, rctl);
7345 }
7346
7347 ctrl = rd32(E1000_CTRL);
7348
7349 #define E1000_CTRL_ADVD3WUC 0x00100000
7350
7351 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
7352 ctrl |= E1000_CTRL_ADVD3WUC;
7353 wr32(E1000_CTRL, ctrl);
7354
7355
7356 igb_disable_pcie_master(hw);
7357
7358 wr32(E1000_WUC, E1000_WUC_PME_EN);
7359 wr32(E1000_WUFC, wufc);
7360 } else {
7361 wr32(E1000_WUC, 0);
7362 wr32(E1000_WUFC, 0);
7363 }
7364
7365 *enable_wake = wufc || adapter->en_mng_pt;
7366 if (!*enable_wake)
7367 igb_power_down_link(adapter);
7368 else
7369 igb_power_up_link(adapter);
7370
7371
7372
7373
7374 igb_release_hw_control(adapter);
7375
7376 pci_disable_device(pdev);
7377
7378 return 0;
7379}
7380
7381#ifdef CONFIG_PM
7382#ifdef CONFIG_PM_SLEEP
7383static int igb_suspend(struct device *dev)
7384{
7385 int retval;
7386 bool wake;
7387 struct pci_dev *pdev = to_pci_dev(dev);
7388
7389 retval = __igb_shutdown(pdev, &wake, 0);
7390 if (retval)
7391 return retval;
7392
7393 if (wake) {
7394 pci_prepare_to_sleep(pdev);
7395 } else {
7396 pci_wake_from_d3(pdev, false);
7397 pci_set_power_state(pdev, PCI_D3hot);
7398 }
7399
7400 return 0;
7401}
7402#endif
7403
7404static int igb_resume(struct device *dev)
7405{
7406 struct pci_dev *pdev = to_pci_dev(dev);
7407 struct net_device *netdev = pci_get_drvdata(pdev);
7408 struct igb_adapter *adapter = netdev_priv(netdev);
7409 struct e1000_hw *hw = &adapter->hw;
7410 u32 err;
7411
7412 pci_set_power_state(pdev, PCI_D0);
7413 pci_restore_state(pdev);
7414 pci_save_state(pdev);
7415
7416 if (!pci_device_is_present(pdev))
7417 return -ENODEV;
7418 err = pci_enable_device_mem(pdev);
7419 if (err) {
7420 dev_err(&pdev->dev,
7421 "igb: Cannot enable PCI device from suspend\n");
7422 return err;
7423 }
7424 pci_set_master(pdev);
7425
7426 pci_enable_wake(pdev, PCI_D3hot, 0);
7427 pci_enable_wake(pdev, PCI_D3cold, 0);
7428
7429 if (igb_init_interrupt_scheme(adapter, true)) {
7430 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7431 rtnl_unlock();
7432 return -ENOMEM;
7433 }
7434
7435 igb_reset(adapter);
7436
7437
7438
7439
7440 igb_get_hw_control(adapter);
7441
7442 wr32(E1000_WUS, ~0);
7443
7444 if (netdev->flags & IFF_UP) {
7445 rtnl_lock();
7446 err = __igb_open(netdev, true);
7447 rtnl_unlock();
7448 if (err)
7449 return err;
7450 }
7451
7452 netif_device_attach(netdev);
7453 return 0;
7454}
7455
7456static int igb_runtime_idle(struct device *dev)
7457{
7458 struct pci_dev *pdev = to_pci_dev(dev);
7459 struct net_device *netdev = pci_get_drvdata(pdev);
7460 struct igb_adapter *adapter = netdev_priv(netdev);
7461
7462 if (!igb_has_link(adapter))
7463 pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
7464
7465 return -EBUSY;
7466}
7467
7468static int igb_runtime_suspend(struct device *dev)
7469{
7470 struct pci_dev *pdev = to_pci_dev(dev);
7471 int retval;
7472 bool wake;
7473
7474 retval = __igb_shutdown(pdev, &wake, 1);
7475 if (retval)
7476 return retval;
7477
7478 if (wake) {
7479 pci_prepare_to_sleep(pdev);
7480 } else {
7481 pci_wake_from_d3(pdev, false);
7482 pci_set_power_state(pdev, PCI_D3hot);
7483 }
7484
7485 return 0;
7486}
7487
7488static int igb_runtime_resume(struct device *dev)
7489{
7490 return igb_resume(dev);
7491}
7492#endif
7493
7494static void igb_shutdown(struct pci_dev *pdev)
7495{
7496 bool wake;
7497
7498 __igb_shutdown(pdev, &wake, 0);
7499
7500 if (system_state == SYSTEM_POWER_OFF) {
7501 pci_wake_from_d3(pdev, wake);
7502 pci_set_power_state(pdev, PCI_D3hot);
7503 }
7504}
7505
7506#ifdef CONFIG_PCI_IOV
7507static int igb_sriov_reinit(struct pci_dev *dev)
7508{
7509 struct net_device *netdev = pci_get_drvdata(dev);
7510 struct igb_adapter *adapter = netdev_priv(netdev);
7511 struct pci_dev *pdev = adapter->pdev;
7512
7513 rtnl_lock();
7514
7515 if (netif_running(netdev))
7516 igb_close(netdev);
7517 else
7518 igb_reset(adapter);
7519
7520 igb_clear_interrupt_scheme(adapter);
7521
7522 igb_init_queue_configuration(adapter);
7523
7524 if (igb_init_interrupt_scheme(adapter, true)) {
7525 rtnl_unlock();
7526 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7527 return -ENOMEM;
7528 }
7529
7530 if (netif_running(netdev))
7531 igb_open(netdev);
7532
7533 rtnl_unlock();
7534
7535 return 0;
7536}
7537
7538static int igb_pci_disable_sriov(struct pci_dev *dev)
7539{
7540 int err = igb_disable_sriov(dev);
7541
7542 if (!err)
7543 err = igb_sriov_reinit(dev);
7544
7545 return err;
7546}
7547
7548static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs)
7549{
7550 int err = igb_enable_sriov(dev, num_vfs);
7551
7552 if (err)
7553 goto out;
7554
7555 err = igb_sriov_reinit(dev);
7556 if (!err)
7557 return num_vfs;
7558
7559out:
7560 return err;
7561}
7562
7563#endif
7564static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs)
7565{
7566#ifdef CONFIG_PCI_IOV
7567 if (num_vfs == 0)
7568 return igb_pci_disable_sriov(dev);
7569 else
7570 return igb_pci_enable_sriov(dev, num_vfs);
7571#endif
7572 return 0;
7573}
7574
7575#ifdef CONFIG_NET_POLL_CONTROLLER
7576
7577
7578
7579
7580static void igb_netpoll(struct net_device *netdev)
7581{
7582 struct igb_adapter *adapter = netdev_priv(netdev);
7583 struct e1000_hw *hw = &adapter->hw;
7584 struct igb_q_vector *q_vector;
7585 int i;
7586
7587 for (i = 0; i < adapter->num_q_vectors; i++) {
7588 q_vector = adapter->q_vector[i];
7589 if (adapter->flags & IGB_FLAG_HAS_MSIX)
7590 wr32(E1000_EIMC, q_vector->eims_value);
7591 else
7592 igb_irq_disable(adapter);
7593 napi_schedule(&q_vector->napi);
7594 }
7595}
7596#endif
7597
7598
7599
7600
7601
7602
7603
7604
7605
7606static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
7607 pci_channel_state_t state)
7608{
7609 struct net_device *netdev = pci_get_drvdata(pdev);
7610 struct igb_adapter *adapter = netdev_priv(netdev);
7611
7612 netif_device_detach(netdev);
7613
7614 if (state == pci_channel_io_perm_failure)
7615 return PCI_ERS_RESULT_DISCONNECT;
7616
7617 if (netif_running(netdev))
7618 igb_down(adapter);
7619 pci_disable_device(pdev);
7620
7621
7622 return PCI_ERS_RESULT_NEED_RESET;
7623}
7624
7625
7626
7627
7628
7629
7630
7631
7632static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
7633{
7634 struct net_device *netdev = pci_get_drvdata(pdev);
7635 struct igb_adapter *adapter = netdev_priv(netdev);
7636 struct e1000_hw *hw = &adapter->hw;
7637 pci_ers_result_t result;
7638 int err;
7639
7640 if (pci_enable_device_mem(pdev)) {
7641 dev_err(&pdev->dev,
7642 "Cannot re-enable PCI device after reset.\n");
7643 result = PCI_ERS_RESULT_DISCONNECT;
7644 } else {
7645 pci_set_master(pdev);
7646 pci_restore_state(pdev);
7647 pci_save_state(pdev);
7648
7649 pci_enable_wake(pdev, PCI_D3hot, 0);
7650 pci_enable_wake(pdev, PCI_D3cold, 0);
7651
7652 igb_reset(adapter);
7653 wr32(E1000_WUS, ~0);
7654 result = PCI_ERS_RESULT_RECOVERED;
7655 }
7656
7657 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7658 if (err) {
7659 dev_err(&pdev->dev,
7660 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
7661 err);
7662
7663 }
7664
7665 return result;
7666}
7667
7668
7669
7670
7671
7672
7673
7674
7675
7676static void igb_io_resume(struct pci_dev *pdev)
7677{
7678 struct net_device *netdev = pci_get_drvdata(pdev);
7679 struct igb_adapter *adapter = netdev_priv(netdev);
7680
7681 if (netif_running(netdev)) {
7682 if (igb_up(adapter)) {
7683 dev_err(&pdev->dev, "igb_up failed after reset\n");
7684 return;
7685 }
7686 }
7687
7688 netif_device_attach(netdev);
7689
7690
7691
7692
7693 igb_get_hw_control(adapter);
7694}
7695
7696static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
7697 u8 qsel)
7698{
7699 u32 rar_low, rar_high;
7700 struct e1000_hw *hw = &adapter->hw;
7701
7702
7703
7704
7705 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
7706 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
7707 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
7708
7709
7710 rar_high |= E1000_RAH_AV;
7711
7712 if (hw->mac.type == e1000_82575)
7713 rar_high |= E1000_RAH_POOL_1 * qsel;
7714 else
7715 rar_high |= E1000_RAH_POOL_1 << qsel;
7716
7717 wr32(E1000_RAL(index), rar_low);
7718 wrfl();
7719 wr32(E1000_RAH(index), rar_high);
7720 wrfl();
7721}
7722
7723static int igb_set_vf_mac(struct igb_adapter *adapter,
7724 int vf, unsigned char *mac_addr)
7725{
7726 struct e1000_hw *hw = &adapter->hw;
7727
7728
7729
7730 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
7731
7732 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
7733
7734 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
7735
7736 return 0;
7737}
7738
7739static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
7740{
7741 struct igb_adapter *adapter = netdev_priv(netdev);
7742 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
7743 return -EINVAL;
7744 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
7745 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
7746 dev_info(&adapter->pdev->dev,
7747 "Reload the VF driver to make this change effective.");
7748 if (test_bit(__IGB_DOWN, &adapter->state)) {
7749 dev_warn(&adapter->pdev->dev,
7750 "The VF MAC address has been set, but the PF device is not up.\n");
7751 dev_warn(&adapter->pdev->dev,
7752 "Bring the PF device up before attempting to use the VF device.\n");
7753 }
7754 return igb_set_vf_mac(adapter, vf, mac);
7755}
7756
7757static int igb_link_mbps(int internal_link_speed)
7758{
7759 switch (internal_link_speed) {
7760 case SPEED_100:
7761 return 100;
7762 case SPEED_1000:
7763 return 1000;
7764 default:
7765 return 0;
7766 }
7767}
7768
7769static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
7770 int link_speed)
7771{
7772 int rf_dec, rf_int;
7773 u32 bcnrc_val;
7774
7775 if (tx_rate != 0) {
7776
7777 rf_int = link_speed / tx_rate;
7778 rf_dec = (link_speed - (rf_int * tx_rate));
7779 rf_dec = (rf_dec * (1 << E1000_RTTBCNRC_RF_INT_SHIFT)) /
7780 tx_rate;
7781
7782 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
7783 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) &
7784 E1000_RTTBCNRC_RF_INT_MASK);
7785 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
7786 } else {
7787 bcnrc_val = 0;
7788 }
7789
7790 wr32(E1000_RTTDQSEL, vf);
7791
7792
7793
7794 wr32(E1000_RTTBCNRM, 0x14);
7795 wr32(E1000_RTTBCNRC, bcnrc_val);
7796}
7797
7798static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
7799{
7800 int actual_link_speed, i;
7801 bool reset_rate = false;
7802
7803
7804 if ((adapter->vf_rate_link_speed == 0) ||
7805 (adapter->hw.mac.type != e1000_82576))
7806 return;
7807
7808 actual_link_speed = igb_link_mbps(adapter->link_speed);
7809 if (actual_link_speed != adapter->vf_rate_link_speed) {
7810 reset_rate = true;
7811 adapter->vf_rate_link_speed = 0;
7812 dev_info(&adapter->pdev->dev,
7813 "Link speed has been changed. VF Transmit rate is disabled\n");
7814 }
7815
7816 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7817 if (reset_rate)
7818 adapter->vf_data[i].tx_rate = 0;
7819
7820 igb_set_vf_rate_limit(&adapter->hw, i,
7821 adapter->vf_data[i].tx_rate,
7822 actual_link_speed);
7823 }
7824}
7825
7826static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf,
7827 int min_tx_rate, int max_tx_rate)
7828{
7829 struct igb_adapter *adapter = netdev_priv(netdev);
7830 struct e1000_hw *hw = &adapter->hw;
7831 int actual_link_speed;
7832
7833 if (hw->mac.type != e1000_82576)
7834 return -EOPNOTSUPP;
7835
7836 if (min_tx_rate)
7837 return -EINVAL;
7838
7839 actual_link_speed = igb_link_mbps(adapter->link_speed);
7840 if ((vf >= adapter->vfs_allocated_count) ||
7841 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
7842 (max_tx_rate < 0) ||
7843 (max_tx_rate > actual_link_speed))
7844 return -EINVAL;
7845
7846 adapter->vf_rate_link_speed = actual_link_speed;
7847 adapter->vf_data[vf].tx_rate = (u16)max_tx_rate;
7848 igb_set_vf_rate_limit(hw, vf, max_tx_rate, actual_link_speed);
7849
7850 return 0;
7851}
7852
7853static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
7854 bool setting)
7855{
7856 struct igb_adapter *adapter = netdev_priv(netdev);
7857 struct e1000_hw *hw = &adapter->hw;
7858 u32 reg_val, reg_offset;
7859
7860 if (!adapter->vfs_allocated_count)
7861 return -EOPNOTSUPP;
7862
7863 if (vf >= adapter->vfs_allocated_count)
7864 return -EINVAL;
7865
7866 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC;
7867 reg_val = rd32(reg_offset);
7868 if (setting)
7869 reg_val |= ((1 << vf) |
7870 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7871 else
7872 reg_val &= ~((1 << vf) |
7873 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7874 wr32(reg_offset, reg_val);
7875
7876 adapter->vf_data[vf].spoofchk_enabled = setting;
7877 return 0;
7878}
7879
7880static int igb_ndo_get_vf_config(struct net_device *netdev,
7881 int vf, struct ifla_vf_info *ivi)
7882{
7883 struct igb_adapter *adapter = netdev_priv(netdev);
7884 if (vf >= adapter->vfs_allocated_count)
7885 return -EINVAL;
7886 ivi->vf = vf;
7887 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
7888 ivi->max_tx_rate = adapter->vf_data[vf].tx_rate;
7889 ivi->min_tx_rate = 0;
7890 ivi->vlan = adapter->vf_data[vf].pf_vlan;
7891 ivi->qos = adapter->vf_data[vf].pf_qos;
7892 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled;
7893 return 0;
7894}
7895
7896static void igb_vmm_control(struct igb_adapter *adapter)
7897{
7898 struct e1000_hw *hw = &adapter->hw;
7899 u32 reg;
7900
7901 switch (hw->mac.type) {
7902 case e1000_82575:
7903 case e1000_i210:
7904 case e1000_i211:
7905 case e1000_i354:
7906 default:
7907
7908 return;
7909 case e1000_82576:
7910
7911 reg = rd32(E1000_DTXCTL);
7912 reg |= E1000_DTXCTL_VLAN_ADDED;
7913 wr32(E1000_DTXCTL, reg);
7914
7915 case e1000_82580:
7916
7917 reg = rd32(E1000_RPLOLR);
7918 reg |= E1000_RPLOLR_STRVLAN;
7919 wr32(E1000_RPLOLR, reg);
7920
7921 case e1000_i350:
7922
7923 break;
7924 }
7925
7926 if (adapter->vfs_allocated_count) {
7927 igb_vmdq_set_loopback_pf(hw, true);
7928 igb_vmdq_set_replication_pf(hw, true);
7929 igb_vmdq_set_anti_spoofing_pf(hw, true,
7930 adapter->vfs_allocated_count);
7931 } else {
7932 igb_vmdq_set_loopback_pf(hw, false);
7933 igb_vmdq_set_replication_pf(hw, false);
7934 }
7935}
7936
7937static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
7938{
7939 struct e1000_hw *hw = &adapter->hw;
7940 u32 dmac_thr;
7941 u16 hwm;
7942
7943 if (hw->mac.type > e1000_82580) {
7944 if (adapter->flags & IGB_FLAG_DMAC) {
7945 u32 reg;
7946
7947
7948 wr32(E1000_DMCTXTH, 0);
7949
7950
7951
7952
7953
7954 hwm = 64 * pba - adapter->max_frame_size / 16;
7955 if (hwm < 64 * (pba - 6))
7956 hwm = 64 * (pba - 6);
7957 reg = rd32(E1000_FCRTC);
7958 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
7959 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
7960 & E1000_FCRTC_RTH_COAL_MASK);
7961 wr32(E1000_FCRTC, reg);
7962
7963
7964
7965
7966 dmac_thr = pba - adapter->max_frame_size / 512;
7967 if (dmac_thr < pba - 10)
7968 dmac_thr = pba - 10;
7969 reg = rd32(E1000_DMACR);
7970 reg &= ~E1000_DMACR_DMACTHR_MASK;
7971 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT)
7972 & E1000_DMACR_DMACTHR_MASK);
7973
7974
7975 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
7976
7977
7978 reg |= (1000 >> 5);
7979
7980
7981 if (hw->mac.type != e1000_i354)
7982 reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
7983
7984 wr32(E1000_DMACR, reg);
7985
7986
7987
7988
7989 wr32(E1000_DMCRTRH, 0);
7990
7991 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4);
7992
7993 wr32(E1000_DMCTLX, reg);
7994
7995
7996
7997
7998 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
7999 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
8000
8001
8002
8003
8004 reg = rd32(E1000_PCIEMISC);
8005 reg &= ~E1000_PCIEMISC_LX_DECISION;
8006 wr32(E1000_PCIEMISC, reg);
8007 }
8008 } else if (hw->mac.type == e1000_82580) {
8009 u32 reg = rd32(E1000_PCIEMISC);
8010
8011 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION);
8012 wr32(E1000_DMACR, 0);
8013 }
8014}
8015
8016
8017
8018
8019
8020
8021
8022
8023
8024
8025
8026s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
8027 u8 dev_addr, u8 *data)
8028{
8029 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
8030 struct i2c_client *this_client = adapter->i2c_client;
8031 s32 status;
8032 u16 swfw_mask = 0;
8033
8034 if (!this_client)
8035 return E1000_ERR_I2C;
8036
8037 swfw_mask = E1000_SWFW_PHY0_SM;
8038
8039 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
8040 return E1000_ERR_SWFW_SYNC;
8041
8042 status = i2c_smbus_read_byte_data(this_client, byte_offset);
8043 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
8044
8045 if (status < 0)
8046 return E1000_ERR_I2C;
8047 else {
8048 *data = status;
8049 return 0;
8050 }
8051}
8052
8053
8054
8055
8056
8057
8058
8059
8060
8061
8062
8063s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
8064 u8 dev_addr, u8 data)
8065{
8066 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
8067 struct i2c_client *this_client = adapter->i2c_client;
8068 s32 status;
8069 u16 swfw_mask = E1000_SWFW_PHY0_SM;
8070
8071 if (!this_client)
8072 return E1000_ERR_I2C;
8073
8074 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
8075 return E1000_ERR_SWFW_SYNC;
8076 status = i2c_smbus_write_byte_data(this_client, byte_offset, data);
8077 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
8078
8079 if (status)
8080 return E1000_ERR_I2C;
8081 else
8082 return 0;
8083
8084}
8085
8086int igb_reinit_queues(struct igb_adapter *adapter)
8087{
8088 struct net_device *netdev = adapter->netdev;
8089 struct pci_dev *pdev = adapter->pdev;
8090 int err = 0;
8091
8092 if (netif_running(netdev))
8093 igb_close(netdev);
8094
8095 igb_reset_interrupt_capability(adapter);
8096
8097 if (igb_init_interrupt_scheme(adapter, true)) {
8098 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
8099 return -ENOMEM;
8100 }
8101
8102 if (netif_running(netdev))
8103 err = igb_open(netdev);
8104
8105 return err;
8106}
8107
8108
