LXR linux/drivers/net/ethernet/smsc/smc911x.h

   1/*------------------------------------------------------------------------
   2 . smc911x.h - macros for SMSC's LAN911{5,6,7,8} single-chip Ethernet device.
   3 .
   4 . Copyright (C) 2005 Sensoria Corp.
   5 . Derived from the unified SMC91x driver by Nicolas Pitre
   6 .
   7 . This program is free software; you can redistribute it and/or modify
   8 . it under the terms of the GNU General Public License as published by
   9 . the Free Software Foundation; either version 2 of the License, or
  10 . (at your option) any later version.
  11 .
  12 . This program is distributed in the hope that it will be useful,
  13 . but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 . GNU General Public License for more details.
  16 .
  17 . You should have received a copy of the GNU General Public License
  18 . along with this program; if not, see <http://www.gnu.org/licenses/>.
  19 .
  20 . Information contained in this file was obtained from the LAN9118
  21 . manual from SMC.  To get a copy, if you really want one, you can find
  22 . information under www.smsc.com.
  23 .
  24 . Authors
  25 .       Dustin McIntire                 <dustin@sensoria.com>
  26 .
  27 ---------------------------------------------------------------------------*/
  28#ifndef _SMC911X_H_
  29#define _SMC911X_H_
  30
  31#include <linux/smc911x.h>
  32/*
  33 * Use the DMA feature on PXA chips
  34 */
  35#ifdef CONFIG_ARCH_PXA
  36  #define SMC_USE_PXA_DMA       1
  37  #define SMC_USE_16BIT         0
  38  #define SMC_USE_32BIT         1
  39  #define SMC_IRQ_SENSE         IRQF_TRIGGER_FALLING
  40#elif defined(CONFIG_SH_MAGIC_PANEL_R2)
  41  #define SMC_USE_16BIT         0
  42  #define SMC_USE_32BIT         1
  43  #define SMC_IRQ_SENSE         IRQF_TRIGGER_LOW
  44#elif defined(CONFIG_ARCH_OMAP3)
  45  #define SMC_USE_16BIT         0
  46  #define SMC_USE_32BIT         1
  47  #define SMC_IRQ_SENSE         IRQF_TRIGGER_LOW
  48  #define SMC_MEM_RESERVED      1
  49#elif defined(CONFIG_ARCH_OMAP2)
  50  #define SMC_USE_16BIT         0
  51  #define SMC_USE_32BIT         1
  52  #define SMC_IRQ_SENSE         IRQF_TRIGGER_LOW
  53  #define SMC_MEM_RESERVED      1
  54#else
  55/*
  56 * Default configuration
  57 */
  58
  59#define SMC_DYNAMIC_BUS_CONFIG
  60#endif
  61
  62#ifdef SMC_USE_PXA_DMA
  63#define SMC_USE_DMA
  64#endif
  65
  66/* store this information for the driver.. */
  67struct smc911x_local {
  68        /*
  69         * If I have to wait until the DMA is finished and ready to reload a
  70         * packet, I will store the skbuff here. Then, the DMA will send it
  71         * out and free it.
  72         */
  73        struct sk_buff *pending_tx_skb;
  74
  75        /* version/revision of the SMC911x chip */
  76        u16 version;
  77        u16 revision;
  78
  79        /* FIFO sizes */
  80        int tx_fifo_kb;
  81        int tx_fifo_size;
  82        int rx_fifo_size;
  83        int afc_cfg;
  84
  85        /* Contains the current active receive/phy mode */
  86        int ctl_rfduplx;
  87        int ctl_rspeed;
  88
  89        u32 msg_enable;
  90        u32 phy_type;
  91        struct mii_if_info mii;
  92
  93        /* work queue */
  94        struct work_struct phy_configure;
  95
  96        int tx_throttle;
  97        spinlock_t lock;
  98
  99        struct net_device *netdev;
 100
 101#ifdef SMC_USE_DMA
 102        /* DMA needs the physical address of the chip */
 103        u_long physaddr;
 104        int rxdma;
 105        int txdma;
 106        int rxdma_active;
 107        int txdma_active;
 108        struct sk_buff *current_rx_skb;
 109        struct sk_buff *current_tx_skb;
 110        struct device *dev;
 111#endif
 112        void __iomem *base;
 113#ifdef SMC_DYNAMIC_BUS_CONFIG
 114        struct smc911x_platdata cfg;
 115#endif
 116};
 117
 118/*
 119 * Define the bus width specific IO macros
 120 */
 121
 122#ifdef SMC_DYNAMIC_BUS_CONFIG
 123static inline unsigned int SMC_inl(struct smc911x_local *lp, int reg)
 124{
 125        void __iomem *ioaddr = lp->base + reg;
 126
 127        if (lp->cfg.flags & SMC911X_USE_32BIT)
 128                return readl(ioaddr);
 129
 130        if (lp->cfg.flags & SMC911X_USE_16BIT)
 131                return readw(ioaddr) | (readw(ioaddr + 2) << 16);
 132
 133        BUG();
 134}
 135
 136static inline void SMC_outl(unsigned int value, struct smc911x_local *lp,
 137                            int reg)
 138{
 139        void __iomem *ioaddr = lp->base + reg;
 140
 141        if (lp->cfg.flags & SMC911X_USE_32BIT) {
 142                writel(value, ioaddr);
 143                return;
 144        }
 145
 146        if (lp->cfg.flags & SMC911X_USE_16BIT) {
 147                writew(value & 0xffff, ioaddr);
 148                writew(value >> 16, ioaddr + 2);
 149                return;
 150        }
 151
 152        BUG();
 153}
 154
 155static inline void SMC_insl(struct smc911x_local *lp, int reg,
 156                              void *addr, unsigned int count)
 157{
 158        void __iomem *ioaddr = lp->base + reg;
 159
 160        if (lp->cfg.flags & SMC911X_USE_32BIT) {
 161                ioread32_rep(ioaddr, addr, count);
 162                return;
 163        }
 164
 165        if (lp->cfg.flags & SMC911X_USE_16BIT) {
 166                ioread16_rep(ioaddr, addr, count * 2);
 167                return;
 168        }
 169
 170        BUG();
 171}
 172
 173static inline void SMC_outsl(struct smc911x_local *lp, int reg,
 174                             void *addr, unsigned int count)
 175{
 176        void __iomem *ioaddr = lp->base + reg;
 177
 178        if (lp->cfg.flags & SMC911X_USE_32BIT) {
 179                iowrite32_rep(ioaddr, addr, count);
 180                return;
 181        }
 182
 183        if (lp->cfg.flags & SMC911X_USE_16BIT) {
 184                iowrite16_rep(ioaddr, addr, count * 2);
 185                return;
 186        }
 187
 188        BUG();
 189}
 190#else
 191#if     SMC_USE_16BIT
 192#define SMC_inl(lp, r)           ((readw((lp)->base + (r)) & 0xFFFF) + (readw((lp)->base + (r) + 2) << 16))
 193#define SMC_outl(v, lp, r)                       \
 194        do{                                      \
 195                 writew(v & 0xFFFF, (lp)->base + (r));   \
 196                 writew(v >> 16, (lp)->base + (r) + 2); \
 197         } while (0)
 198#define SMC_insl(lp, r, p, l)    ioread16_rep((short*)((lp)->base + (r)), p, l*2)
 199#define SMC_outsl(lp, r, p, l)   iowrite16_rep((short*)((lp)->base + (r)), p, l*2)
 200
 201#elif   SMC_USE_32BIT
 202#define SMC_inl(lp, r)           readl((lp)->base + (r))
 203#define SMC_outl(v, lp, r)       writel(v, (lp)->base + (r))
 204#define SMC_insl(lp, r, p, l)    ioread32_rep((int*)((lp)->base + (r)), p, l)
 205#define SMC_outsl(lp, r, p, l)   iowrite32_rep((int*)((lp)->base + (r)), p, l)
 206
 207#endif /* SMC_USE_16BIT */
 208#endif /* SMC_DYNAMIC_BUS_CONFIG */
 209
 210
 211#ifdef SMC_USE_PXA_DMA
 212
 213#include <mach/dma.h>
 214
 215/*
 216 * Define the request and free functions
 217 * These are unfortunately architecture specific as no generic allocation
 218 * mechanism exits
 219 */
 220#define SMC_DMA_REQUEST(dev, handler) \
 221         pxa_request_dma(dev->name, DMA_PRIO_LOW, handler, dev)
 222
 223#define SMC_DMA_FREE(dev, dma) \
 224         pxa_free_dma(dma)
 225
 226#define SMC_DMA_ACK_IRQ(dev, dma)                                       \
 227{                                                                       \
 228        if (DCSR(dma) & DCSR_BUSERR) {                                  \
 229                netdev_err(dev, "DMA %d bus error!\n", dma);            \
 230        }                                                               \
 231        DCSR(dma) = DCSR_STARTINTR|DCSR_ENDINTR|DCSR_BUSERR;            \
 232}
 233
 234/*
 235 * Use a DMA for RX and TX packets.
 236 */
 237#include <linux/dma-mapping.h>
 238
 239static dma_addr_t rx_dmabuf, tx_dmabuf;
 240static int rx_dmalen, tx_dmalen;
 241
 242#ifdef SMC_insl
 243#undef SMC_insl
 244#define SMC_insl(lp, r, p, l) \
 245        smc_pxa_dma_insl(lp, lp->physaddr, r, lp->rxdma, p, l)
 246
 247static inline void
 248smc_pxa_dma_insl(struct smc911x_local *lp, u_long physaddr,
 249                int reg, int dma, u_char *buf, int len)
 250{
 251        /* 64 bit alignment is required for memory to memory DMA */
 252        if ((long)buf & 4) {
 253                *((u32 *)buf) = SMC_inl(lp, reg);
 254                buf += 4;
 255                len--;
 256        }
 257
 258        len *= 4;
 259        rx_dmabuf = dma_map_single(lp->dev, buf, len, DMA_FROM_DEVICE);
 260        rx_dmalen = len;
 261        DCSR(dma) = DCSR_NODESC;
 262        DTADR(dma) = rx_dmabuf;
 263        DSADR(dma) = physaddr + reg;
 264        DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
 265                DCMD_WIDTH4 | DCMD_ENDIRQEN | (DCMD_LENGTH & rx_dmalen));
 266        DCSR(dma) = DCSR_NODESC | DCSR_RUN;
 267}
 268#endif
 269
 270#ifdef SMC_outsl
 271#undef SMC_outsl
 272#define SMC_outsl(lp, r, p, l) \
 273         smc_pxa_dma_outsl(lp, lp->physaddr, r, lp->txdma, p, l)
 274
 275static inline void
 276smc_pxa_dma_outsl(struct smc911x_local *lp, u_long physaddr,
 277                int reg, int dma, u_char *buf, int len)
 278{
 279        /* 64 bit alignment is required for memory to memory DMA */
 280        if ((long)buf & 4) {
 281                SMC_outl(*((u32 *)buf), lp, reg);
 282                buf += 4;
 283                len--;
 284        }
 285
 286        len *= 4;
 287        tx_dmabuf = dma_map_single(lp->dev, buf, len, DMA_TO_DEVICE);
 288        tx_dmalen = len;
 289        DCSR(dma) = DCSR_NODESC;
 290        DSADR(dma) = tx_dmabuf;
 291        DTADR(dma) = physaddr + reg;
 292        DCMD(dma) = (DCMD_INCSRCADDR | DCMD_BURST32 |
 293                DCMD_WIDTH4 | DCMD_ENDIRQEN | (DCMD_LENGTH & tx_dmalen));
 294        DCSR(dma) = DCSR_NODESC | DCSR_RUN;
 295}
 296#endif
 297#endif   /* SMC_USE_PXA_DMA */
 298
 299
 300/* Chip Parameters and Register Definitions */
 301
 302#define SMC911X_TX_FIFO_LOW_THRESHOLD   (1536*2)
 303
 304#define SMC911X_IO_EXTENT        0x100
 305
 306#define SMC911X_EEPROM_LEN       7
 307
 308/* Below are the register offsets and bit definitions
 309 * of the Lan911x memory space
 310 */
 311#define RX_DATA_FIFO             (0x00)
 312
 313#define TX_DATA_FIFO             (0x20)
 314#define TX_CMD_A_INT_ON_COMP_           (0x80000000)
 315#define TX_CMD_A_INT_BUF_END_ALGN_      (0x03000000)
 316#define TX_CMD_A_INT_4_BYTE_ALGN_       (0x00000000)
 317#define TX_CMD_A_INT_16_BYTE_ALGN_      (0x01000000)
 318#define TX_CMD_A_INT_32_BYTE_ALGN_      (0x02000000)
 319#define TX_CMD_A_INT_DATA_OFFSET_       (0x001F0000)
 320#define TX_CMD_A_INT_FIRST_SEG_         (0x00002000)
 321#define TX_CMD_A_INT_LAST_SEG_          (0x00001000)
 322#define TX_CMD_A_BUF_SIZE_              (0x000007FF)
 323#define TX_CMD_B_PKT_TAG_               (0xFFFF0000)
 324#define TX_CMD_B_ADD_CRC_DISABLE_       (0x00002000)
 325#define TX_CMD_B_DISABLE_PADDING_       (0x00001000)
 326#define TX_CMD_B_PKT_BYTE_LENGTH_       (0x000007FF)
 327
 328#define RX_STATUS_FIFO          (0x40)
 329#define RX_STS_PKT_LEN_                 (0x3FFF0000)
 330#define RX_STS_ES_                      (0x00008000)
 331#define RX_STS_BCST_                    (0x00002000)
 332#define RX_STS_LEN_ERR_                 (0x00001000)
 333#define RX_STS_RUNT_ERR_                (0x00000800)
 334#define RX_STS_MCAST_                   (0x00000400)
 335#define RX_STS_TOO_LONG_                (0x00000080)
 336#define RX_STS_COLL_                    (0x00000040)
 337#define RX_STS_ETH_TYPE_                (0x00000020)
 338#define RX_STS_WDOG_TMT_                (0x00000010)
 339#define RX_STS_MII_ERR_                 (0x00000008)
 340#define RX_STS_DRIBBLING_               (0x00000004)
 341#define RX_STS_CRC_ERR_                 (0x00000002)
 342#define RX_STATUS_FIFO_PEEK     (0x44)
 343#define TX_STATUS_FIFO          (0x48)
 344#define TX_STS_TAG_                     (0xFFFF0000)
 345#define TX_STS_ES_                      (0x00008000)
 346#define TX_STS_LOC_                     (0x00000800)
 347#define TX_STS_NO_CARR_                 (0x00000400)
 348#define TX_STS_LATE_COLL_               (0x00000200)
 349#define TX_STS_MANY_COLL_               (0x00000100)
 350#define TX_STS_COLL_CNT_                (0x00000078)
 351#define TX_STS_MANY_DEFER_              (0x00000004)
 352#define TX_STS_UNDERRUN_                (0x00000002)
 353#define TX_STS_DEFERRED_                (0x00000001)
 354#define TX_STATUS_FIFO_PEEK     (0x4C)
 355#define ID_REV                  (0x50)
 356#define ID_REV_CHIP_ID_                 (0xFFFF0000)  /* RO */
 357#define ID_REV_REV_ID_                  (0x0000FFFF)  /* RO */
 358
 359#define INT_CFG                 (0x54)
 360#define INT_CFG_INT_DEAS_               (0xFF000000)  /* R/W */
 361#define INT_CFG_INT_DEAS_CLR_           (0x00004000)
 362#define INT_CFG_INT_DEAS_STS_           (0x00002000)
 363#define INT_CFG_IRQ_INT_                (0x00001000)  /* RO */
 364#define INT_CFG_IRQ_EN_                 (0x00000100)  /* R/W */
 365#define INT_CFG_IRQ_POL_                (0x00000010)  /* R/W Not Affected by SW Reset */
 366#define INT_CFG_IRQ_TYPE_               (0x00000001)  /* R/W Not Affected by SW Reset */
 367
 368#define INT_STS                 (0x58)
 369#define INT_STS_SW_INT_                 (0x80000000)  /* R/WC */
 370#define INT_STS_TXSTOP_INT_             (0x02000000)  /* R/WC */
 371#define INT_STS_RXSTOP_INT_             (0x01000000)  /* R/WC */
 372#define INT_STS_RXDFH_INT_              (0x00800000)  /* R/WC */
 373#define INT_STS_RXDF_INT_               (0x00400000)  /* R/WC */
 374#define INT_STS_TX_IOC_                 (0x00200000)  /* R/WC */
 375#define INT_STS_RXD_INT_                (0x00100000)  /* R/WC */
 376#define INT_STS_GPT_INT_                (0x00080000)  /* R/WC */
 377#define INT_STS_PHY_INT_                (0x00040000)  /* RO */
 378#define INT_STS_PME_INT_                (0x00020000)  /* R/WC */
 379#define INT_STS_TXSO_                   (0x00010000)  /* R/WC */
 380#define INT_STS_RWT_                    (0x00008000)  /* R/WC */
 381#define INT_STS_RXE_                    (0x00004000)  /* R/WC */
 382#define INT_STS_TXE_                    (0x00002000)  /* R/WC */
 383//#define       INT_STS_ERX_            (0x00001000)  /* R/WC */
 384#define INT_STS_TDFU_                   (0x00000800)  /* R/WC */
 385#define INT_STS_TDFO_                   (0x00000400)  /* R/WC */
 386#define INT_STS_TDFA_                   (0x00000200)  /* R/WC */
 387#define INT_STS_TSFF_                   (0x00000100)  /* R/WC */
 388#define INT_STS_TSFL_                   (0x00000080)  /* R/WC */
 389//#define       INT_STS_RXDF_           (0x00000040)  /* R/WC */
 390#define INT_STS_RDFO_                   (0x00000040)  /* R/WC */
 391#define INT_STS_RDFL_                   (0x00000020)  /* R/WC */
 392#define INT_STS_RSFF_                   (0x00000010)  /* R/WC */
 393#define INT_STS_RSFL_                   (0x00000008)  /* R/WC */
 394#define INT_STS_GPIO2_INT_              (0x00000004)  /* R/WC */
 395#define INT_STS_GPIO1_INT_              (0x00000002)  /* R/WC */
 396#define INT_STS_GPIO0_INT_              (0x00000001)  /* R/WC */
 397
 398#define INT_EN                  (0x5C)
 399#define INT_EN_SW_INT_EN_               (0x80000000)  /* R/W */
 400#define INT_EN_TXSTOP_INT_EN_           (0x02000000)  /* R/W */
 401#define INT_EN_RXSTOP_INT_EN_           (0x01000000)  /* R/W */
 402#define INT_EN_RXDFH_INT_EN_            (0x00800000)  /* R/W */
 403//#define       INT_EN_RXDF_INT_EN_             (0x00400000)  /* R/W */
 404#define INT_EN_TIOC_INT_EN_             (0x00200000)  /* R/W */
 405#define INT_EN_RXD_INT_EN_              (0x00100000)  /* R/W */
 406#define INT_EN_GPT_INT_EN_              (0x00080000)  /* R/W */
 407#define INT_EN_PHY_INT_EN_              (0x00040000)  /* R/W */
 408#define INT_EN_PME_INT_EN_              (0x00020000)  /* R/W */
 409#define INT_EN_TXSO_EN_                 (0x00010000)  /* R/W */
 410#define INT_EN_RWT_EN_                  (0x00008000)  /* R/W */
 411#define INT_EN_RXE_EN_                  (0x00004000)  /* R/W */
 412#define INT_EN_TXE_EN_                  (0x00002000)  /* R/W */
 413//#define       INT_EN_ERX_EN_                  (0x00001000)  /* R/W */
 414#define INT_EN_TDFU_EN_                 (0x00000800)  /* R/W */
 415#define INT_EN_TDFO_EN_                 (0x00000400)  /* R/W */
 416#define INT_EN_TDFA_EN_                 (0x00000200)  /* R/W */
 417#define INT_EN_TSFF_EN_                 (0x00000100)  /* R/W */
 418#define INT_EN_TSFL_EN_                 (0x00000080)  /* R/W */
 419//#define       INT_EN_RXDF_EN_                 (0x00000040)  /* R/W */
 420#define INT_EN_RDFO_EN_                 (0x00000040)  /* R/W */
 421#define INT_EN_RDFL_EN_                 (0x00000020)  /* R/W */
 422#define INT_EN_RSFF_EN_                 (0x00000010)  /* R/W */
 423#define INT_EN_RSFL_EN_                 (0x00000008)  /* R/W */
 424#define INT_EN_GPIO2_INT_               (0x00000004)  /* R/W */
 425#define INT_EN_GPIO1_INT_               (0x00000002)  /* R/W */
 426#define INT_EN_GPIO0_INT_               (0x00000001)  /* R/W */
 427
 428#define BYTE_TEST               (0x64)
 429#define FIFO_INT                (0x68)
 430#define FIFO_INT_TX_AVAIL_LEVEL_        (0xFF000000)  /* R/W */
 431#define FIFO_INT_TX_STS_LEVEL_          (0x00FF0000)  /* R/W */
 432#define FIFO_INT_RX_AVAIL_LEVEL_        (0x0000FF00)  /* R/W */
 433#define FIFO_INT_RX_STS_LEVEL_          (0x000000FF)  /* R/W */
 434
 435#define RX_CFG                  (0x6C)
 436#define RX_CFG_RX_END_ALGN_             (0xC0000000)  /* R/W */
 437#define         RX_CFG_RX_END_ALGN4_            (0x00000000)  /* R/W */
 438#define         RX_CFG_RX_END_ALGN16_           (0x40000000)  /* R/W */
 439#define         RX_CFG_RX_END_ALGN32_           (0x80000000)  /* R/W */
 440#define RX_CFG_RX_DMA_CNT_              (0x0FFF0000)  /* R/W */
 441#define RX_CFG_RX_DUMP_                 (0x00008000)  /* R/W */
 442#define RX_CFG_RXDOFF_                  (0x00001F00)  /* R/W */
 443//#define       RX_CFG_RXBAD_                   (0x00000001)  /* R/W */
 444
 445#define TX_CFG                  (0x70)
 446//#define       TX_CFG_TX_DMA_LVL_              (0xE0000000)     /* R/W */
 447//#define       TX_CFG_TX_DMA_CNT_              (0x0FFF0000)     /* R/W Self Clearing */
 448#define TX_CFG_TXS_DUMP_                (0x00008000)  /* Self Clearing */
 449#define TX_CFG_TXD_DUMP_                (0x00004000)  /* Self Clearing */
 450#define TX_CFG_TXSAO_                   (0x00000004)  /* R/W */
 451#define TX_CFG_TX_ON_                   (0x00000002)  /* R/W */
 452#define TX_CFG_STOP_TX_                 (0x00000001)  /* Self Clearing */
 453
 454#define HW_CFG                  (0x74)
 455#define HW_CFG_TTM_                     (0x00200000)  /* R/W */
 456#define HW_CFG_SF_                      (0x00100000)  /* R/W */
 457#define HW_CFG_TX_FIF_SZ_               (0x000F0000)  /* R/W */
 458#define HW_CFG_TR_                      (0x00003000)  /* R/W */
 459#define HW_CFG_PHY_CLK_SEL_             (0x00000060)  /* R/W */
 460#define          HW_CFG_PHY_CLK_SEL_INT_PHY_    (0x00000000) /* R/W */
 461#define          HW_CFG_PHY_CLK_SEL_EXT_PHY_    (0x00000020) /* R/W */
 462#define          HW_CFG_PHY_CLK_SEL_CLK_DIS_    (0x00000040) /* R/W */
 463#define HW_CFG_SMI_SEL_                 (0x00000010)  /* R/W */
 464#define HW_CFG_EXT_PHY_DET_             (0x00000008)  /* RO */
 465#define HW_CFG_EXT_PHY_EN_              (0x00000004)  /* R/W */
 466#define HW_CFG_32_16_BIT_MODE_          (0x00000004)  /* RO */
 467#define HW_CFG_SRST_TO_                 (0x00000002)  /* RO */
 468#define HW_CFG_SRST_                    (0x00000001)  /* Self Clearing */
 469
 470#define RX_DP_CTRL              (0x78)
 471#define RX_DP_CTRL_RX_FFWD_             (0x80000000)  /* R/W */
 472#define RX_DP_CTRL_FFWD_BUSY_           (0x80000000)  /* RO */
 473
 474#define RX_FIFO_INF             (0x7C)
 475#define  RX_FIFO_INF_RXSUSED_           (0x00FF0000)  /* RO */
 476#define  RX_FIFO_INF_RXDUSED_           (0x0000FFFF)  /* RO */
 477
 478#define TX_FIFO_INF             (0x80)
 479#define TX_FIFO_INF_TSUSED_             (0x00FF0000)  /* RO */
 480#define TX_FIFO_INF_TDFREE_             (0x0000FFFF)  /* RO */
 481
 482#define PMT_CTRL                (0x84)
 483#define PMT_CTRL_PM_MODE_               (0x00003000)  /* Self Clearing */
 484#define PMT_CTRL_PHY_RST_               (0x00000400)  /* Self Clearing */
 485#define PMT_CTRL_WOL_EN_                (0x00000200)  /* R/W */
 486#define PMT_CTRL_ED_EN_                 (0x00000100)  /* R/W */
 487#define PMT_CTRL_PME_TYPE_              (0x00000040)  /* R/W Not Affected by SW Reset */
 488#define PMT_CTRL_WUPS_                  (0x00000030)  /* R/WC */
 489#define         PMT_CTRL_WUPS_NOWAKE_           (0x00000000)  /* R/WC */
 490#define         PMT_CTRL_WUPS_ED_               (0x00000010)  /* R/WC */
 491#define         PMT_CTRL_WUPS_WOL_              (0x00000020)  /* R/WC */
 492#define         PMT_CTRL_WUPS_MULTI_            (0x00000030)  /* R/WC */
 493#define PMT_CTRL_PME_IND_               (0x00000008)  /* R/W */
 494#define PMT_CTRL_PME_POL_               (0x00000004)  /* R/W */
 495#define PMT_CTRL_PME_EN_                (0x00000002)  /* R/W Not Affected by SW Reset */
 496#define PMT_CTRL_READY_                 (0x00000001)  /* RO */
 497
 498#define GPIO_CFG                (0x88)
 499#define GPIO_CFG_LED3_EN_               (0x40000000)  /* R/W */
 500#define GPIO_CFG_LED2_EN_               (0x20000000)  /* R/W */
 501#define GPIO_CFG_LED1_EN_               (0x10000000)  /* R/W */
 502#define GPIO_CFG_GPIO2_INT_POL_         (0x04000000)  /* R/W */
 503#define GPIO_CFG_GPIO1_INT_POL_         (0x02000000)  /* R/W */
 504#define GPIO_CFG_GPIO0_INT_POL_         (0x01000000)  /* R/W */
 505#define GPIO_CFG_EEPR_EN_               (0x00700000)  /* R/W */
 506#define GPIO_CFG_GPIOBUF2_              (0x00040000)  /* R/W */
 507#define GPIO_CFG_GPIOBUF1_              (0x00020000)  /* R/W */
 508#define GPIO_CFG_GPIOBUF0_              (0x00010000)  /* R/W */
 509#define GPIO_CFG_GPIODIR2_              (0x00000400)  /* R/W */
 510#define GPIO_CFG_GPIODIR1_              (0x00000200)  /* R/W */
 511#define GPIO_CFG_GPIODIR0_              (0x00000100)  /* R/W */
 512#define GPIO_CFG_GPIOD4_                (0x00000010)  /* R/W */
 513#define GPIO_CFG_GPIOD3_                (0x00000008)  /* R/W */
 514#define GPIO_CFG_GPIOD2_                (0x00000004)  /* R/W */
 515#define GPIO_CFG_GPIOD1_                (0x00000002)  /* R/W */
 516#define GPIO_CFG_GPIOD0_                (0x00000001)  /* R/W */
 517
 518#define GPT_CFG                 (0x8C)
 519#define GPT_CFG_TIMER_EN_               (0x20000000)  /* R/W */
 520#define GPT_CFG_GPT_LOAD_               (0x0000FFFF)  /* R/W */
 521
 522#define GPT_CNT                 (0x90)
 523#define GPT_CNT_GPT_CNT_                (0x0000FFFF)  /* RO */
 524
 525#define ENDIAN                  (0x98)
 526#define FREE_RUN                (0x9C)
 527#define RX_DROP                 (0xA0)
 528#define MAC_CSR_CMD             (0xA4)
 529#define  MAC_CSR_CMD_CSR_BUSY_          (0x80000000)  /* Self Clearing */
 530#define  MAC_CSR_CMD_R_NOT_W_           (0x40000000)  /* R/W */
 531#define  MAC_CSR_CMD_CSR_ADDR_          (0x000000FF)  /* R/W */
 532
 533#define MAC_CSR_DATA            (0xA8)
 534#define AFC_CFG                 (0xAC)
 535#define         AFC_CFG_AFC_HI_                 (0x00FF0000)  /* R/W */
 536#define         AFC_CFG_AFC_LO_                 (0x0000FF00)  /* R/W */
 537#define         AFC_CFG_BACK_DUR_               (0x000000F0)  /* R/W */
 538#define         AFC_CFG_FCMULT_                 (0x00000008)  /* R/W */
 539#define         AFC_CFG_FCBRD_                  (0x00000004)  /* R/W */
 540#define         AFC_CFG_FCADD_                  (0x00000002)  /* R/W */
 541#define         AFC_CFG_FCANY_                  (0x00000001)  /* R/W */
 542
 543#define E2P_CMD                 (0xB0)
 544#define E2P_CMD_EPC_BUSY_               (0x80000000)  /* Self Clearing */
 545#define E2P_CMD_EPC_CMD_                        (0x70000000)  /* R/W */
 546#define         E2P_CMD_EPC_CMD_READ_           (0x00000000)  /* R/W */
 547#define         E2P_CMD_EPC_CMD_EWDS_           (0x10000000)  /* R/W */
 548#define         E2P_CMD_EPC_CMD_EWEN_           (0x20000000)  /* R/W */
 549#define         E2P_CMD_EPC_CMD_WRITE_          (0x30000000)  /* R/W */
 550#define         E2P_CMD_EPC_CMD_WRAL_           (0x40000000)  /* R/W */
 551#define         E2P_CMD_EPC_CMD_ERASE_          (0x50000000)  /* R/W */
 552#define         E2P_CMD_EPC_CMD_ERAL_           (0x60000000)  /* R/W */
 553#define         E2P_CMD_EPC_CMD_RELOAD_         (0x70000000)  /* R/W */
 554#define E2P_CMD_EPC_TIMEOUT_            (0x00000200)  /* RO */
 555#define E2P_CMD_MAC_ADDR_LOADED_        (0x00000100)  /* RO */
 556#define E2P_CMD_EPC_ADDR_               (0x000000FF)  /* R/W */
 557
 558#define E2P_DATA                (0xB4)
 559#define E2P_DATA_EEPROM_DATA_           (0x000000FF)  /* R/W */
 560/* end of LAN register offsets and bit definitions */
 561
 562/*
 563 ****************************************************************************
 564 ****************************************************************************
 565 * MAC Control and Status Register (Indirect Address)
 566 * Offset (through the MAC_CSR CMD and DATA port)
 567 ****************************************************************************
 568 ****************************************************************************
 569 *
 570 */
 571#define MAC_CR                  (0x01)  /* R/W */
 572
 573/* MAC_CR - MAC Control Register */
 574#define MAC_CR_RXALL_                   (0x80000000)
 575// TODO: delete this bit? It is not described in the data sheet.
 576#define MAC_CR_HBDIS_                   (0x10000000)
 577#define MAC_CR_RCVOWN_                  (0x00800000)
 578#define MAC_CR_LOOPBK_                  (0x00200000)
 579#define MAC_CR_FDPX_                    (0x00100000)
 580#define MAC_CR_MCPAS_                   (0x00080000)
 581#define MAC_CR_PRMS_                    (0x00040000)
 582#define MAC_CR_INVFILT_                 (0x00020000)
 583#define MAC_CR_PASSBAD_                 (0x00010000)
 584#define MAC_CR_HFILT_                   (0x00008000)
 585#define MAC_CR_HPFILT_                  (0x00002000)
 586#define MAC_CR_LCOLL_                   (0x00001000)
 587#define MAC_CR_BCAST_                   (0x00000800)
 588#define MAC_CR_DISRTY_                  (0x00000400)
 589#define MAC_CR_PADSTR_                  (0x00000100)
 590#define MAC_CR_BOLMT_MASK_              (0x000000C0)
 591#define MAC_CR_DFCHK_                   (0x00000020)
 592#define MAC_CR_TXEN_                    (0x00000008)
 593#define MAC_CR_RXEN_                    (0x00000004)
 594
 595#define ADDRH                   (0x02)    /* R/W mask 0x0000FFFFUL */
 596#define ADDRL                   (0x03)    /* R/W mask 0xFFFFFFFFUL */
 597#define HASHH                   (0x04)    /* R/W */
 598#define HASHL                   (0x05)    /* R/W */
 599
 600#define MII_ACC                 (0x06)    /* R/W */
 601#define MII_ACC_PHY_ADDR_               (0x0000F800)
 602#define MII_ACC_MIIRINDA_               (0x000007C0)
 603#define MII_ACC_MII_WRITE_              (0x00000002)
 604#define MII_ACC_MII_BUSY_               (0x00000001)
 605
 606#define MII_DATA                (0x07)    /* R/W mask 0x0000FFFFUL */
 607
 608#define FLOW                    (0x08)    /* R/W */
 609#define FLOW_FCPT_                      (0xFFFF0000)
 610#define FLOW_FCPASS_                    (0x00000004)
 611#define FLOW_FCEN_                      (0x00000002)
 612#define FLOW_FCBSY_                     (0x00000001)
 613
 614#define VLAN1                   (0x09)    /* R/W mask 0x0000FFFFUL */
 615#define VLAN1_VTI1_                     (0x0000ffff)
 616
 617#define VLAN2                   (0x0A)    /* R/W mask 0x0000FFFFUL */
 618#define VLAN2_VTI2_                     (0x0000ffff)
 619
 620#define WUFF                    (0x0B)    /* WO */
 621
 622#define WUCSR                   (0x0C)    /* R/W */
 623#define WUCSR_GUE_                      (0x00000200)
 624#define WUCSR_WUFR_                     (0x00000040)
 625#define WUCSR_MPR_                      (0x00000020)
 626#define WUCSR_WAKE_EN_                  (0x00000004)
 627#define WUCSR_MPEN_                     (0x00000002)
 628
 629/*
 630 ****************************************************************************
 631 * Chip Specific MII Defines
 632 ****************************************************************************
 633 *
 634 * Phy register offsets and bit definitions
 635 *
 636 */
 637
 638#define PHY_MODE_CTRL_STS       ((u32)17)       /* Mode Control/Status Register */
 639//#define MODE_CTRL_STS_FASTRIP_          ((u16)0x4000)
 640#define MODE_CTRL_STS_EDPWRDOWN_         ((u16)0x2000)
 641//#define MODE_CTRL_STS_LOWSQEN_           ((u16)0x0800)
 642//#define MODE_CTRL_STS_MDPREBP_           ((u16)0x0400)
 643//#define MODE_CTRL_STS_FARLOOPBACK_  ((u16)0x0200)
 644//#define MODE_CTRL_STS_FASTEST_           ((u16)0x0100)
 645//#define MODE_CTRL_STS_REFCLKEN_          ((u16)0x0010)
 646//#define MODE_CTRL_STS_PHYADBP_           ((u16)0x0008)
 647//#define MODE_CTRL_STS_FORCE_G_LINK_ ((u16)0x0004)
 648#define MODE_CTRL_STS_ENERGYON_         ((u16)0x0002)
 649
 650#define PHY_INT_SRC                     ((u32)29)
 651#define PHY_INT_SRC_ENERGY_ON_                  ((u16)0x0080)
 652#define PHY_INT_SRC_ANEG_COMP_                  ((u16)0x0040)
 653#define PHY_INT_SRC_REMOTE_FAULT_               ((u16)0x0020)
 654#define PHY_INT_SRC_LINK_DOWN_                  ((u16)0x0010)
 655#define PHY_INT_SRC_ANEG_LP_ACK_                ((u16)0x0008)
 656#define PHY_INT_SRC_PAR_DET_FAULT_              ((u16)0x0004)
 657#define PHY_INT_SRC_ANEG_PGRX_                  ((u16)0x0002)
 658
 659#define PHY_INT_MASK                    ((u32)30)
 660#define PHY_INT_MASK_ENERGY_ON_                 ((u16)0x0080)
 661#define PHY_INT_MASK_ANEG_COMP_                 ((u16)0x0040)
 662#define PHY_INT_MASK_REMOTE_FAULT_              ((u16)0x0020)
 663#define PHY_INT_MASK_LINK_DOWN_                 ((u16)0x0010)
 664#define PHY_INT_MASK_ANEG_LP_ACK_               ((u16)0x0008)
 665#define PHY_INT_MASK_PAR_DET_FAULT_             ((u16)0x0004)
 666#define PHY_INT_MASK_ANEG_PGRX_                 ((u16)0x0002)
 667
 668#define PHY_SPECIAL                     ((u32)31)
 669#define PHY_SPECIAL_ANEG_DONE_                  ((u16)0x1000)
 670#define PHY_SPECIAL_RES_                        ((u16)0x0040)
 671#define PHY_SPECIAL_RES_MASK_                   ((u16)0x0FE1)
 672#define PHY_SPECIAL_SPD_                        ((u16)0x001C)
 673#define PHY_SPECIAL_SPD_10HALF_                 ((u16)0x0004)
 674#define PHY_SPECIAL_SPD_10FULL_                 ((u16)0x0014)
 675#define PHY_SPECIAL_SPD_100HALF_                ((u16)0x0008)
 676#define PHY_SPECIAL_SPD_100FULL_                ((u16)0x0018)
 677
 678#define LAN911X_INTERNAL_PHY_ID         (0x0007C000)
 679
 680/* Chip ID values */
 681#define CHIP_9115       0x0115
 682#define CHIP_9116       0x0116
 683#define CHIP_9117       0x0117
 684#define CHIP_9118       0x0118
 685#define CHIP_9211       0x9211
 686#define CHIP_9215       0x115A
 687#define CHIP_9217       0x117A
 688#define CHIP_9218       0x118A
 689
 690struct chip_id {
 691        u16 id;
 692        char *name;
 693};
 694
 695static const struct chip_id chip_ids[] =  {
 696        { CHIP_9115, "LAN9115" },
 697        { CHIP_9116, "LAN9116" },
 698        { CHIP_9117, "LAN9117" },
 699        { CHIP_9118, "LAN9118" },
 700        { CHIP_9211, "LAN9211" },
 701        { CHIP_9215, "LAN9215" },
 702        { CHIP_9217, "LAN9217" },
 703        { CHIP_9218, "LAN9218" },
 704        { 0, NULL },
 705};
 706
 707#define IS_REV_A(x)     ((x & 0xFFFF)==0)
 708
 709/*
 710 * Macros to abstract register access according to the data bus
 711 * capabilities.  Please use those and not the in/out primitives.
 712 */
 713/* FIFO read/write macros */
 714#define SMC_PUSH_DATA(lp, p, l) SMC_outsl( lp, TX_DATA_FIFO, p, (l) >> 2 )
 715#define SMC_PULL_DATA(lp, p, l) SMC_insl ( lp, RX_DATA_FIFO, p, (l) >> 2 )
 716#define SMC_SET_TX_FIFO(lp, x)  SMC_outl( x, lp, TX_DATA_FIFO )
 717#define SMC_GET_RX_FIFO(lp)     SMC_inl( lp, RX_DATA_FIFO )
 718
 719
 720/* I/O mapped register read/write macros */
 721#define SMC_GET_TX_STS_FIFO(lp)         SMC_inl( lp, TX_STATUS_FIFO )
 722#define SMC_GET_RX_STS_FIFO(lp)         SMC_inl( lp, RX_STATUS_FIFO )
 723#define SMC_GET_RX_STS_FIFO_PEEK(lp)    SMC_inl( lp, RX_STATUS_FIFO_PEEK )
 724#define SMC_GET_PN(lp)                  (SMC_inl( lp, ID_REV ) >> 16)
 725#define SMC_GET_REV(lp)                 (SMC_inl( lp, ID_REV ) & 0xFFFF)
 726#define SMC_GET_IRQ_CFG(lp)             SMC_inl( lp, INT_CFG )
 727#define SMC_SET_IRQ_CFG(lp, x)          SMC_outl( x, lp, INT_CFG )
 728#define SMC_GET_INT(lp)                 SMC_inl( lp, INT_STS )
 729#define SMC_ACK_INT(lp, x)                      SMC_outl( x, lp, INT_STS )
 730#define SMC_GET_INT_EN(lp)              SMC_inl( lp, INT_EN )
 731#define SMC_SET_INT_EN(lp, x)           SMC_outl( x, lp, INT_EN )
 732#define SMC_GET_BYTE_TEST(lp)           SMC_inl( lp, BYTE_TEST )
 733#define SMC_SET_BYTE_TEST(lp, x)                SMC_outl( x, lp, BYTE_TEST )
 734#define SMC_GET_FIFO_INT(lp)            SMC_inl( lp, FIFO_INT )
 735#define SMC_SET_FIFO_INT(lp, x)         SMC_outl( x, lp, FIFO_INT )
 736#define SMC_SET_FIFO_TDA(lp, x)                                 \
 737        do {                                                    \
 738                unsigned long __flags;                          \
 739                int __mask;                                     \
 740                local_irq_save(__flags);                        \
 741                __mask = SMC_GET_FIFO_INT((lp)) & ~(0xFF<<24);  \
 742                SMC_SET_FIFO_INT( (lp), __mask | (x)<<24 );     \
 743                local_irq_restore(__flags);                     \
 744        } while (0)
 745#define SMC_SET_FIFO_TSL(lp, x)                                 \
 746        do {                                                    \
 747                unsigned long __flags;                          \
 748                int __mask;                                     \
 749                local_irq_save(__flags);                        \
 750                __mask = SMC_GET_FIFO_INT((lp)) & ~(0xFF<<16);  \
 751                SMC_SET_FIFO_INT( (lp), __mask | (((x) & 0xFF)<<16));   \
 752                local_irq_restore(__flags);                     \
 753        } while (0)
 754#define SMC_SET_FIFO_RSA(lp, x)                                 \
 755        do {                                                    \
 756                unsigned long __flags;                          \
 757                int __mask;                                     \
 758                local_irq_save(__flags);                        \
 759                __mask = SMC_GET_FIFO_INT((lp)) & ~(0xFF<<8);   \
 760                SMC_SET_FIFO_INT( (lp), __mask | (((x) & 0xFF)<<8));    \
 761                local_irq_restore(__flags);                     \
 762        } while (0)
 763#define SMC_SET_FIFO_RSL(lp, x)                                 \
 764        do {                                                    \
 765                unsigned long __flags;                          \
 766                int __mask;                                     \
 767                local_irq_save(__flags);                        \
 768                __mask = SMC_GET_FIFO_INT((lp)) & ~0xFF;        \
 769                SMC_SET_FIFO_INT( (lp),__mask | ((x) & 0xFF));  \
 770                local_irq_restore(__flags);                     \
 771        } while (0)
 772#define SMC_GET_RX_CFG(lp)              SMC_inl( lp, RX_CFG )
 773#define SMC_SET_RX_CFG(lp, x)           SMC_outl( x, lp, RX_CFG )
 774#define SMC_GET_TX_CFG(lp)              SMC_inl( lp, TX_CFG )
 775#define SMC_SET_TX_CFG(lp, x)           SMC_outl( x, lp, TX_CFG )
 776#define SMC_GET_HW_CFG(lp)              SMC_inl( lp, HW_CFG )
 777#define SMC_SET_HW_CFG(lp, x)           SMC_outl( x, lp, HW_CFG )
 778#define SMC_GET_RX_DP_CTRL(lp)          SMC_inl( lp, RX_DP_CTRL )
 779#define SMC_SET_RX_DP_CTRL(lp, x)               SMC_outl( x, lp, RX_DP_CTRL )
 780#define SMC_GET_PMT_CTRL(lp)            SMC_inl( lp, PMT_CTRL )
 781#define SMC_SET_PMT_CTRL(lp, x)         SMC_outl( x, lp, PMT_CTRL )
 782#define SMC_GET_GPIO_CFG(lp)            SMC_inl( lp, GPIO_CFG )
 783#define SMC_SET_GPIO_CFG(lp, x)         SMC_outl( x, lp, GPIO_CFG )
 784#define SMC_GET_RX_FIFO_INF(lp)         SMC_inl( lp, RX_FIFO_INF )
 785#define SMC_SET_RX_FIFO_INF(lp, x)              SMC_outl( x, lp, RX_FIFO_INF )
 786#define SMC_GET_TX_FIFO_INF(lp)         SMC_inl( lp, TX_FIFO_INF )
 787#define SMC_SET_TX_FIFO_INF(lp, x)              SMC_outl( x, lp, TX_FIFO_INF )
 788#define SMC_GET_GPT_CFG(lp)             SMC_inl( lp, GPT_CFG )
 789#define SMC_SET_GPT_CFG(lp, x)          SMC_outl( x, lp, GPT_CFG )
 790#define SMC_GET_RX_DROP(lp)             SMC_inl( lp, RX_DROP )
 791#define SMC_SET_RX_DROP(lp, x)          SMC_outl( x, lp, RX_DROP )
 792#define SMC_GET_MAC_CMD(lp)             SMC_inl( lp, MAC_CSR_CMD )
 793#define SMC_SET_MAC_CMD(lp, x)          SMC_outl( x, lp, MAC_CSR_CMD )
 794#define SMC_GET_MAC_DATA(lp)            SMC_inl( lp, MAC_CSR_DATA )
 795#define SMC_SET_MAC_DATA(lp, x)         SMC_outl( x, lp, MAC_CSR_DATA )
 796#define SMC_GET_AFC_CFG(lp)             SMC_inl( lp, AFC_CFG )
 797#define SMC_SET_AFC_CFG(lp, x)          SMC_outl( x, lp, AFC_CFG )
 798#define SMC_GET_E2P_CMD(lp)             SMC_inl( lp, E2P_CMD )
 799#define SMC_SET_E2P_CMD(lp, x)          SMC_outl( x, lp, E2P_CMD )
 800#define SMC_GET_E2P_DATA(lp)            SMC_inl( lp, E2P_DATA )
 801#define SMC_SET_E2P_DATA(lp, x)         SMC_outl( x, lp, E2P_DATA )
 802
 803/* MAC register read/write macros */
 804#define SMC_GET_MAC_CSR(lp,a,v)                                         \
 805        do {                                                            \
 806                while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_);  \
 807                SMC_SET_MAC_CMD((lp),MAC_CSR_CMD_CSR_BUSY_ |            \
 808                        MAC_CSR_CMD_R_NOT_W_ | (a) );                   \
 809                while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_);  \
 810                v = SMC_GET_MAC_DATA((lp));                             \
 811        } while (0)
 812#define SMC_SET_MAC_CSR(lp,a,v)                                         \
 813        do {                                                            \
 814                while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_);  \
 815                SMC_SET_MAC_DATA((lp), v);                              \
 816                SMC_SET_MAC_CMD((lp), MAC_CSR_CMD_CSR_BUSY_ | (a) );    \
 817                while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_);  \
 818        } while (0)
 819#define SMC_GET_MAC_CR(lp, x)   SMC_GET_MAC_CSR( (lp), MAC_CR, x )
 820#define SMC_SET_MAC_CR(lp, x)   SMC_SET_MAC_CSR( (lp), MAC_CR, x )
 821#define SMC_GET_ADDRH(lp, x)    SMC_GET_MAC_CSR( (lp), ADDRH, x )
 822#define SMC_SET_ADDRH(lp, x)    SMC_SET_MAC_CSR( (lp), ADDRH, x )
 823#define SMC_GET_ADDRL(lp, x)    SMC_GET_MAC_CSR( (lp), ADDRL, x )
 824#define SMC_SET_ADDRL(lp, x)    SMC_SET_MAC_CSR( (lp), ADDRL, x )
 825#define SMC_GET_HASHH(lp, x)    SMC_GET_MAC_CSR( (lp), HASHH, x )
 826#define SMC_SET_HASHH(lp, x)    SMC_SET_MAC_CSR( (lp), HASHH, x )
 827#define SMC_GET_HASHL(lp, x)    SMC_GET_MAC_CSR( (lp), HASHL, x )
 828#define SMC_SET_HASHL(lp, x)    SMC_SET_MAC_CSR( (lp), HASHL, x )
 829#define SMC_GET_MII_ACC(lp, x)  SMC_GET_MAC_CSR( (lp), MII_ACC, x )
 830#define SMC_SET_MII_ACC(lp, x)  SMC_SET_MAC_CSR( (lp), MII_ACC, x )
 831#define SMC_GET_MII_DATA(lp, x) SMC_GET_MAC_CSR( (lp), MII_DATA, x )
 832#define SMC_SET_MII_DATA(lp, x) SMC_SET_MAC_CSR( (lp), MII_DATA, x )
 833#define SMC_GET_FLOW(lp, x)             SMC_GET_MAC_CSR( (lp), FLOW, x )
 834#define SMC_SET_FLOW(lp, x)             SMC_SET_MAC_CSR( (lp), FLOW, x )
 835#define SMC_GET_VLAN1(lp, x)    SMC_GET_MAC_CSR( (lp), VLAN1, x )
 836#define SMC_SET_VLAN1(lp, x)    SMC_SET_MAC_CSR( (lp), VLAN1, x )
 837#define SMC_GET_VLAN2(lp, x)    SMC_GET_MAC_CSR( (lp), VLAN2, x )
 838#define SMC_SET_VLAN2(lp, x)    SMC_SET_MAC_CSR( (lp), VLAN2, x )
 839#define SMC_SET_WUFF(lp, x)             SMC_SET_MAC_CSR( (lp), WUFF, x )
 840#define SMC_GET_WUCSR(lp, x)    SMC_GET_MAC_CSR( (lp), WUCSR, x )
 841#define SMC_SET_WUCSR(lp, x)    SMC_SET_MAC_CSR( (lp), WUCSR, x )
 842
 843/* PHY register read/write macros */
 844#define SMC_GET_MII(lp,a,phy,v)                                 \
 845        do {                                                    \
 846                u32 __v;                                        \
 847                do {                                            \
 848                        SMC_GET_MII_ACC((lp), __v);                     \
 849                } while ( __v & MII_ACC_MII_BUSY_ );            \
 850                SMC_SET_MII_ACC( (lp), ((phy)<<11) | ((a)<<6) | \
 851                        MII_ACC_MII_BUSY_);                     \
 852                do {                                            \
 853                        SMC_GET_MII_ACC( (lp), __v);                    \
 854                } while ( __v & MII_ACC_MII_BUSY_ );            \
 855                SMC_GET_MII_DATA((lp), v);                              \
 856        } while (0)
 857#define SMC_SET_MII(lp,a,phy,v)                                 \
 858        do {                                                    \
 859                u32 __v;                                        \
 860                do {                                            \
 861                        SMC_GET_MII_ACC((lp), __v);                     \
 862                } while ( __v & MII_ACC_MII_BUSY_ );            \
 863                SMC_SET_MII_DATA((lp), v);                              \
 864                SMC_SET_MII_ACC( (lp), ((phy)<<11) | ((a)<<6) | \
 865                        MII_ACC_MII_BUSY_        |              \
 866                        MII_ACC_MII_WRITE_  );                  \
 867                do {                                            \
 868                        SMC_GET_MII_ACC((lp), __v);                     \
 869                } while ( __v & MII_ACC_MII_BUSY_ );            \
 870        } while (0)
 871#define SMC_GET_PHY_BMCR(lp,phy,x)              SMC_GET_MII( (lp), MII_BMCR, phy, x )
 872#define SMC_SET_PHY_BMCR(lp,phy,x)              SMC_SET_MII( (lp), MII_BMCR, phy, x )
 873#define SMC_GET_PHY_BMSR(lp,phy,x)              SMC_GET_MII( (lp), MII_BMSR, phy, x )
 874#define SMC_GET_PHY_ID1(lp,phy,x)               SMC_GET_MII( (lp), MII_PHYSID1, phy, x )
 875#define SMC_GET_PHY_ID2(lp,phy,x)               SMC_GET_MII( (lp), MII_PHYSID2, phy, x )
 876#define SMC_GET_PHY_MII_ADV(lp,phy,x)   SMC_GET_MII( (lp), MII_ADVERTISE, phy, x )
 877#define SMC_SET_PHY_MII_ADV(lp,phy,x)   SMC_SET_MII( (lp), MII_ADVERTISE, phy, x )
 878#define SMC_GET_PHY_MII_LPA(lp,phy,x)   SMC_GET_MII( (lp), MII_LPA, phy, x )
 879#define SMC_SET_PHY_MII_LPA(lp,phy,x)   SMC_SET_MII( (lp), MII_LPA, phy, x )
 880#define SMC_GET_PHY_CTRL_STS(lp,phy,x)  SMC_GET_MII( (lp), PHY_MODE_CTRL_STS, phy, x )
 881#define SMC_SET_PHY_CTRL_STS(lp,phy,x)  SMC_SET_MII( (lp), PHY_MODE_CTRL_STS, phy, x )
 882#define SMC_GET_PHY_INT_SRC(lp,phy,x)   SMC_GET_MII( (lp), PHY_INT_SRC, phy, x )
 883#define SMC_SET_PHY_INT_SRC(lp,phy,x)   SMC_SET_MII( (lp), PHY_INT_SRC, phy, x )
 884#define SMC_GET_PHY_INT_MASK(lp,phy,x)  SMC_GET_MII( (lp), PHY_INT_MASK, phy, x )
 885#define SMC_SET_PHY_INT_MASK(lp,phy,x)  SMC_SET_MII( (lp), PHY_INT_MASK, phy, x )
 886#define SMC_GET_PHY_SPECIAL(lp,phy,x)   SMC_GET_MII( (lp), PHY_SPECIAL, phy, x )
 887
 888
 889
 890/* Misc read/write macros */
 891
 892#ifndef SMC_GET_MAC_ADDR
 893#define SMC_GET_MAC_ADDR(lp, addr)                              \
 894        do {                                                    \
 895                unsigned int __v;                               \
 896                                                                \
 897                SMC_GET_MAC_CSR((lp), ADDRL, __v);                      \
 898                addr[0] = __v; addr[1] = __v >> 8;              \
 899                addr[2] = __v >> 16; addr[3] = __v >> 24;       \
 900                SMC_GET_MAC_CSR((lp), ADDRH, __v);                      \
 901                addr[4] = __v; addr[5] = __v >> 8;              \
 902        } while (0)
 903#endif
 904
 905#define SMC_SET_MAC_ADDR(lp, addr)                              \
 906        do {                                                    \
 907                 SMC_SET_MAC_CSR((lp), ADDRL,                           \
 908                                 addr[0] |                      \
 909                                (addr[1] << 8) |                \
 910                                (addr[2] << 16) |               \
 911                                (addr[3] << 24));               \
 912                 SMC_SET_MAC_CSR((lp), ADDRH, addr[4]|(addr[5] << 8));\
 913        } while (0)
 914
 915
 916#define SMC_WRITE_EEPROM_CMD(lp, cmd, addr)                             \
 917        do {                                                            \
 918                while (SMC_GET_E2P_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_);  \
 919                SMC_SET_MAC_CMD((lp), MAC_CSR_CMD_R_NOT_W_ | a );               \
 920                while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_);  \
 921        } while (0)
 922
 923#endif   /* _SMC911X_H_ */
 924