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44
45#include <linux/module.h>
46#include <linux/types.h>
47#include <linux/bitops.h>
48#include <linux/init.h>
49#include <linux/dma-mapping.h>
50#include <linux/mm.h>
51#include <linux/errno.h>
52#include <linux/ioport.h>
53#include <linux/pci.h>
54#include <linux/kernel.h>
55#include <linux/netdevice.h>
56#include <linux/etherdevice.h>
57#include <linux/skbuff.h>
58#include <linux/delay.h>
59#include <linux/timer.h>
60#include <linux/slab.h>
61#include <linux/interrupt.h>
62#include <linux/string.h>
63#include <linux/wait.h>
64#include <linux/io.h>
65#include <linux/if.h>
66#include <linux/uaccess.h>
67#include <linux/proc_fs.h>
68#include <linux/of_address.h>
69#include <linux/of_device.h>
70#include <linux/of_irq.h>
71#include <linux/inetdevice.h>
72#include <linux/platform_device.h>
73#include <linux/reboot.h>
74#include <linux/ethtool.h>
75#include <linux/mii.h>
76#include <linux/in.h>
77#include <linux/if_arp.h>
78#include <linux/if_vlan.h>
79#include <linux/ip.h>
80#include <linux/tcp.h>
81#include <linux/udp.h>
82#include <linux/crc-ccitt.h>
83#include <linux/crc32.h>
84
85#include "via-velocity.h"
86
87enum velocity_bus_type {
88 BUS_PCI,
89 BUS_PLATFORM,
90};
91
92static int velocity_nics;
93static int msglevel = MSG_LEVEL_INFO;
94
95static void velocity_set_power_state(struct velocity_info *vptr, char state)
96{
97 void *addr = vptr->mac_regs;
98
99 if (vptr->pdev)
100 pci_set_power_state(vptr->pdev, state);
101 else
102 writeb(state, addr + 0x154);
103}
104
105
106
107
108
109
110
111
112
113static void mac_get_cam_mask(struct mac_regs __iomem *regs, u8 *mask)
114{
115 int i;
116
117
118 BYTE_REG_BITS_SET(CAMCR_PS_CAM_MASK, CAMCR_PS1 | CAMCR_PS0, ®s->CAMCR);
119
120 writeb(0, ®s->CAMADDR);
121
122
123 for (i = 0; i < 8; i++)
124 *mask++ = readb(&(regs->MARCAM[i]));
125
126
127 writeb(0, ®s->CAMADDR);
128
129
130 BYTE_REG_BITS_SET(CAMCR_PS_MAR, CAMCR_PS1 | CAMCR_PS0, ®s->CAMCR);
131}
132
133
134
135
136
137
138
139
140static void mac_set_cam_mask(struct mac_regs __iomem *regs, u8 *mask)
141{
142 int i;
143
144 BYTE_REG_BITS_SET(CAMCR_PS_CAM_MASK, CAMCR_PS1 | CAMCR_PS0, ®s->CAMCR);
145
146 writeb(CAMADDR_CAMEN, ®s->CAMADDR);
147
148 for (i = 0; i < 8; i++)
149 writeb(*mask++, &(regs->MARCAM[i]));
150
151
152 writeb(0, ®s->CAMADDR);
153
154
155 BYTE_REG_BITS_SET(CAMCR_PS_MAR, CAMCR_PS1 | CAMCR_PS0, ®s->CAMCR);
156}
157
158static void mac_set_vlan_cam_mask(struct mac_regs __iomem *regs, u8 *mask)
159{
160 int i;
161
162 BYTE_REG_BITS_SET(CAMCR_PS_CAM_MASK, CAMCR_PS1 | CAMCR_PS0, ®s->CAMCR);
163
164 writeb(CAMADDR_CAMEN | CAMADDR_VCAMSL, ®s->CAMADDR);
165
166 for (i = 0; i < 8; i++)
167 writeb(*mask++, &(regs->MARCAM[i]));
168
169
170 writeb(0, ®s->CAMADDR);
171
172
173 BYTE_REG_BITS_SET(CAMCR_PS_MAR, CAMCR_PS1 | CAMCR_PS0, ®s->CAMCR);
174}
175
176
177
178
179
180
181
182
183
184static void mac_set_cam(struct mac_regs __iomem *regs, int idx, const u8 *addr)
185{
186 int i;
187
188
189 BYTE_REG_BITS_SET(CAMCR_PS_CAM_DATA, CAMCR_PS1 | CAMCR_PS0, ®s->CAMCR);
190
191 idx &= (64 - 1);
192
193 writeb(CAMADDR_CAMEN | idx, ®s->CAMADDR);
194
195 for (i = 0; i < 6; i++)
196 writeb(*addr++, &(regs->MARCAM[i]));
197
198 BYTE_REG_BITS_ON(CAMCR_CAMWR, ®s->CAMCR);
199
200 udelay(10);
201
202 writeb(0, ®s->CAMADDR);
203
204
205 BYTE_REG_BITS_SET(CAMCR_PS_MAR, CAMCR_PS1 | CAMCR_PS0, ®s->CAMCR);
206}
207
208static void mac_set_vlan_cam(struct mac_regs __iomem *regs, int idx,
209 const u8 *addr)
210{
211
212
213 BYTE_REG_BITS_SET(CAMCR_PS_CAM_DATA, CAMCR_PS1 | CAMCR_PS0, ®s->CAMCR);
214
215 idx &= (64 - 1);
216
217 writeb(CAMADDR_CAMEN | CAMADDR_VCAMSL | idx, ®s->CAMADDR);
218 writew(*((u16 *) addr), ®s->MARCAM[0]);
219
220 BYTE_REG_BITS_ON(CAMCR_CAMWR, ®s->CAMCR);
221
222 udelay(10);
223
224 writeb(0, ®s->CAMADDR);
225
226
227 BYTE_REG_BITS_SET(CAMCR_PS_MAR, CAMCR_PS1 | CAMCR_PS0, ®s->CAMCR);
228}
229
230
231
232
233
234
235
236
237
238
239static void mac_wol_reset(struct mac_regs __iomem *regs)
240{
241
242
243 BYTE_REG_BITS_OFF(STICKHW_SWPTAG, ®s->STICKHW);
244
245 BYTE_REG_BITS_OFF((STICKHW_DS1 | STICKHW_DS0), ®s->STICKHW);
246
247 BYTE_REG_BITS_OFF(CHIPGCR_FCGMII, ®s->CHIPGCR);
248 BYTE_REG_BITS_OFF(CHIPGCR_FCMODE, ®s->CHIPGCR);
249
250 writeb(WOLCFG_PMEOVR, ®s->WOLCFGClr);
251
252 writew(0xFFFF, ®s->WOLCRClr);
253
254 writew(0xFFFF, ®s->WOLSRClr);
255}
256
257static const struct ethtool_ops velocity_ethtool_ops;
258
259
260
261
262
263MODULE_AUTHOR("VIA Networking Technologies, Inc.");
264MODULE_LICENSE("GPL");
265MODULE_DESCRIPTION("VIA Networking Velocity Family Gigabit Ethernet Adapter Driver");
266
267#define VELOCITY_PARAM(N, D) \
268 static int N[MAX_UNITS] = OPTION_DEFAULT;\
269 module_param_array(N, int, NULL, 0); \
270 MODULE_PARM_DESC(N, D);
271
272#define RX_DESC_MIN 64
273#define RX_DESC_MAX 255
274#define RX_DESC_DEF 64
275VELOCITY_PARAM(RxDescriptors, "Number of receive descriptors");
276
277#define TX_DESC_MIN 16
278#define TX_DESC_MAX 256
279#define TX_DESC_DEF 64
280VELOCITY_PARAM(TxDescriptors, "Number of transmit descriptors");
281
282#define RX_THRESH_MIN 0
283#define RX_THRESH_MAX 3
284#define RX_THRESH_DEF 0
285
286
287
288
289
290
291VELOCITY_PARAM(rx_thresh, "Receive fifo threshold");
292
293#define DMA_LENGTH_MIN 0
294#define DMA_LENGTH_MAX 7
295#define DMA_LENGTH_DEF 6
296
297
298
299
300
301
302
303
304
305
306
307VELOCITY_PARAM(DMA_length, "DMA length");
308
309#define IP_ALIG_DEF 0
310
311
312
313
314
315
316VELOCITY_PARAM(IP_byte_align, "Enable IP header dword aligned");
317
318#define FLOW_CNTL_DEF 1
319#define FLOW_CNTL_MIN 1
320#define FLOW_CNTL_MAX 5
321
322
323
324
325
326
327
328
329VELOCITY_PARAM(flow_control, "Enable flow control ability");
330
331#define MED_LNK_DEF 0
332#define MED_LNK_MIN 0
333#define MED_LNK_MAX 5
334
335
336
337
338
339
340
341
342
343
344
345
346VELOCITY_PARAM(speed_duplex, "Setting the speed and duplex mode");
347
348#define WOL_OPT_DEF 0
349#define WOL_OPT_MIN 0
350#define WOL_OPT_MAX 7
351
352
353
354
355
356
357
358VELOCITY_PARAM(wol_opts, "Wake On Lan options");
359
360static int rx_copybreak = 200;
361module_param(rx_copybreak, int, 0644);
362MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
363
364
365
366
367static struct velocity_info_tbl chip_info_table[] = {
368 {CHIP_TYPE_VT6110, "VIA Networking Velocity Family Gigabit Ethernet Adapter", 1, 0x00FFFFFFUL},
369 { }
370};
371
372
373
374
375
376
377static const struct pci_device_id velocity_pci_id_table[] = {
378 { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_612X) },
379 { }
380};
381
382MODULE_DEVICE_TABLE(pci, velocity_pci_id_table);
383
384
385
386
387
388static const struct of_device_id velocity_of_ids[] = {
389 { .compatible = "via,velocity-vt6110", .data = &chip_info_table[0] },
390 { },
391};
392MODULE_DEVICE_TABLE(of, velocity_of_ids);
393
394
395
396
397
398
399
400
401static const char *get_chip_name(enum chip_type chip_id)
402{
403 int i;
404 for (i = 0; chip_info_table[i].name != NULL; i++)
405 if (chip_info_table[i].chip_id == chip_id)
406 break;
407 return chip_info_table[i].name;
408}
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424static void velocity_set_int_opt(int *opt, int val, int min, int max, int def,
425 char *name, const char *devname)
426{
427 if (val == -1)
428 *opt = def;
429 else if (val < min || val > max) {
430 VELOCITY_PRT(MSG_LEVEL_INFO, KERN_NOTICE "%s: the value of parameter %s is invalid, the valid range is (%d-%d)\n",
431 devname, name, min, max);
432 *opt = def;
433 } else {
434 VELOCITY_PRT(MSG_LEVEL_INFO, KERN_INFO "%s: set value of parameter %s to %d\n",
435 devname, name, val);
436 *opt = val;
437 }
438}
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453static void velocity_set_bool_opt(u32 *opt, int val, int def, u32 flag,
454 char *name, const char *devname)
455{
456 (*opt) &= (~flag);
457 if (val == -1)
458 *opt |= (def ? flag : 0);
459 else if (val < 0 || val > 1) {
460 printk(KERN_NOTICE "%s: the value of parameter %s is invalid, the valid range is (0-1)\n",
461 devname, name);
462 *opt |= (def ? flag : 0);
463 } else {
464 printk(KERN_INFO "%s: set parameter %s to %s\n",
465 devname, name, val ? "TRUE" : "FALSE");
466 *opt |= (val ? flag : 0);
467 }
468}
469
470
471
472
473
474
475
476
477
478
479static void velocity_get_options(struct velocity_opt *opts, int index,
480 const char *devname)
481{
482
483 velocity_set_int_opt(&opts->rx_thresh, rx_thresh[index], RX_THRESH_MIN, RX_THRESH_MAX, RX_THRESH_DEF, "rx_thresh", devname);
484 velocity_set_int_opt(&opts->DMA_length, DMA_length[index], DMA_LENGTH_MIN, DMA_LENGTH_MAX, DMA_LENGTH_DEF, "DMA_length", devname);
485 velocity_set_int_opt(&opts->numrx, RxDescriptors[index], RX_DESC_MIN, RX_DESC_MAX, RX_DESC_DEF, "RxDescriptors", devname);
486 velocity_set_int_opt(&opts->numtx, TxDescriptors[index], TX_DESC_MIN, TX_DESC_MAX, TX_DESC_DEF, "TxDescriptors", devname);
487
488 velocity_set_int_opt(&opts->flow_cntl, flow_control[index], FLOW_CNTL_MIN, FLOW_CNTL_MAX, FLOW_CNTL_DEF, "flow_control", devname);
489 velocity_set_bool_opt(&opts->flags, IP_byte_align[index], IP_ALIG_DEF, VELOCITY_FLAGS_IP_ALIGN, "IP_byte_align", devname);
490 velocity_set_int_opt((int *) &opts->spd_dpx, speed_duplex[index], MED_LNK_MIN, MED_LNK_MAX, MED_LNK_DEF, "Media link mode", devname);
491 velocity_set_int_opt(&opts->wol_opts, wol_opts[index], WOL_OPT_MIN, WOL_OPT_MAX, WOL_OPT_DEF, "Wake On Lan options", devname);
492 opts->numrx = (opts->numrx & ~3);
493}
494
495
496
497
498
499
500
501
502static void velocity_init_cam_filter(struct velocity_info *vptr)
503{
504 struct mac_regs __iomem *regs = vptr->mac_regs;
505 unsigned int vid, i = 0;
506
507
508 WORD_REG_BITS_SET(MCFG_PQEN, MCFG_RTGOPT, ®s->MCFG);
509 WORD_REG_BITS_ON(MCFG_VIDFR, ®s->MCFG);
510
511
512 memset(vptr->vCAMmask, 0, sizeof(u8) * 8);
513 memset(vptr->mCAMmask, 0, sizeof(u8) * 8);
514 mac_set_vlan_cam_mask(regs, vptr->vCAMmask);
515 mac_set_cam_mask(regs, vptr->mCAMmask);
516
517
518 for_each_set_bit(vid, vptr->active_vlans, VLAN_N_VID) {
519 mac_set_vlan_cam(regs, i, (u8 *) &vid);
520 vptr->vCAMmask[i / 8] |= 0x1 << (i % 8);
521 if (++i >= VCAM_SIZE)
522 break;
523 }
524 mac_set_vlan_cam_mask(regs, vptr->vCAMmask);
525}
526
527static int velocity_vlan_rx_add_vid(struct net_device *dev,
528 __be16 proto, u16 vid)
529{
530 struct velocity_info *vptr = netdev_priv(dev);
531
532 spin_lock_irq(&vptr->lock);
533 set_bit(vid, vptr->active_vlans);
534 velocity_init_cam_filter(vptr);
535 spin_unlock_irq(&vptr->lock);
536 return 0;
537}
538
539static int velocity_vlan_rx_kill_vid(struct net_device *dev,
540 __be16 proto, u16 vid)
541{
542 struct velocity_info *vptr = netdev_priv(dev);
543
544 spin_lock_irq(&vptr->lock);
545 clear_bit(vid, vptr->active_vlans);
546 velocity_init_cam_filter(vptr);
547 spin_unlock_irq(&vptr->lock);
548 return 0;
549}
550
551static void velocity_init_rx_ring_indexes(struct velocity_info *vptr)
552{
553 vptr->rx.dirty = vptr->rx.filled = vptr->rx.curr = 0;
554}
555
556
557
558
559
560
561
562
563static void velocity_rx_reset(struct velocity_info *vptr)
564{
565
566 struct mac_regs __iomem *regs = vptr->mac_regs;
567 int i;
568
569 velocity_init_rx_ring_indexes(vptr);
570
571
572
573
574 for (i = 0; i < vptr->options.numrx; ++i)
575 vptr->rx.ring[i].rdesc0.len |= OWNED_BY_NIC;
576
577 writew(vptr->options.numrx, ®s->RBRDU);
578 writel(vptr->rx.pool_dma, ®s->RDBaseLo);
579 writew(0, ®s->RDIdx);
580 writew(vptr->options.numrx - 1, ®s->RDCSize);
581}
582
583
584
585
586
587
588
589
590
591static u32 velocity_get_opt_media_mode(struct velocity_info *vptr)
592{
593 u32 status = 0;
594
595 switch (vptr->options.spd_dpx) {
596 case SPD_DPX_AUTO:
597 status = VELOCITY_AUTONEG_ENABLE;
598 break;
599 case SPD_DPX_100_FULL:
600 status = VELOCITY_SPEED_100 | VELOCITY_DUPLEX_FULL;
601 break;
602 case SPD_DPX_10_FULL:
603 status = VELOCITY_SPEED_10 | VELOCITY_DUPLEX_FULL;
604 break;
605 case SPD_DPX_100_HALF:
606 status = VELOCITY_SPEED_100;
607 break;
608 case SPD_DPX_10_HALF:
609 status = VELOCITY_SPEED_10;
610 break;
611 case SPD_DPX_1000_FULL:
612 status = VELOCITY_SPEED_1000 | VELOCITY_DUPLEX_FULL;
613 break;
614 }
615 vptr->mii_status = status;
616 return status;
617}
618
619
620
621
622
623
624
625static void safe_disable_mii_autopoll(struct mac_regs __iomem *regs)
626{
627 u16 ww;
628
629
630 writeb(0, ®s->MIICR);
631 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
632 udelay(1);
633 if (BYTE_REG_BITS_IS_ON(MIISR_MIDLE, ®s->MIISR))
634 break;
635 }
636}
637
638
639
640
641
642
643
644
645static void enable_mii_autopoll(struct mac_regs __iomem *regs)
646{
647 int ii;
648
649 writeb(0, &(regs->MIICR));
650 writeb(MIIADR_SWMPL, ®s->MIIADR);
651
652 for (ii = 0; ii < W_MAX_TIMEOUT; ii++) {
653 udelay(1);
654 if (BYTE_REG_BITS_IS_ON(MIISR_MIDLE, ®s->MIISR))
655 break;
656 }
657
658 writeb(MIICR_MAUTO, ®s->MIICR);
659
660 for (ii = 0; ii < W_MAX_TIMEOUT; ii++) {
661 udelay(1);
662 if (!BYTE_REG_BITS_IS_ON(MIISR_MIDLE, ®s->MIISR))
663 break;
664 }
665
666}
667
668
669
670
671
672
673
674
675
676
677static int velocity_mii_read(struct mac_regs __iomem *regs, u8 index, u16 *data)
678{
679 u16 ww;
680
681
682
683
684 safe_disable_mii_autopoll(regs);
685
686 writeb(index, ®s->MIIADR);
687
688 BYTE_REG_BITS_ON(MIICR_RCMD, ®s->MIICR);
689
690 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
691 if (!(readb(®s->MIICR) & MIICR_RCMD))
692 break;
693 }
694
695 *data = readw(®s->MIIDATA);
696
697 enable_mii_autopoll(regs);
698 if (ww == W_MAX_TIMEOUT)
699 return -ETIMEDOUT;
700 return 0;
701}
702
703
704
705
706
707
708
709
710static u32 mii_check_media_mode(struct mac_regs __iomem *regs)
711{
712 u32 status = 0;
713 u16 ANAR;
714
715 if (!MII_REG_BITS_IS_ON(BMSR_LSTATUS, MII_BMSR, regs))
716 status |= VELOCITY_LINK_FAIL;
717
718 if (MII_REG_BITS_IS_ON(ADVERTISE_1000FULL, MII_CTRL1000, regs))
719 status |= VELOCITY_SPEED_1000 | VELOCITY_DUPLEX_FULL;
720 else if (MII_REG_BITS_IS_ON(ADVERTISE_1000HALF, MII_CTRL1000, regs))
721 status |= (VELOCITY_SPEED_1000);
722 else {
723 velocity_mii_read(regs, MII_ADVERTISE, &ANAR);
724 if (ANAR & ADVERTISE_100FULL)
725 status |= (VELOCITY_SPEED_100 | VELOCITY_DUPLEX_FULL);
726 else if (ANAR & ADVERTISE_100HALF)
727 status |= VELOCITY_SPEED_100;
728 else if (ANAR & ADVERTISE_10FULL)
729 status |= (VELOCITY_SPEED_10 | VELOCITY_DUPLEX_FULL);
730 else
731 status |= (VELOCITY_SPEED_10);
732 }
733
734 if (MII_REG_BITS_IS_ON(BMCR_ANENABLE, MII_BMCR, regs)) {
735 velocity_mii_read(regs, MII_ADVERTISE, &ANAR);
736 if ((ANAR & (ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10FULL | ADVERTISE_10HALF))
737 == (ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10FULL | ADVERTISE_10HALF)) {
738 if (MII_REG_BITS_IS_ON(ADVERTISE_1000HALF | ADVERTISE_1000FULL, MII_CTRL1000, regs))
739 status |= VELOCITY_AUTONEG_ENABLE;
740 }
741 }
742
743 return status;
744}
745
746
747
748
749
750
751
752
753
754
755static int velocity_mii_write(struct mac_regs __iomem *regs, u8 mii_addr, u16 data)
756{
757 u16 ww;
758
759
760
761
762 safe_disable_mii_autopoll(regs);
763
764
765 writeb(mii_addr, ®s->MIIADR);
766
767 writew(data, ®s->MIIDATA);
768
769
770 BYTE_REG_BITS_ON(MIICR_WCMD, ®s->MIICR);
771
772
773 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
774 udelay(5);
775 if (!(readb(®s->MIICR) & MIICR_WCMD))
776 break;
777 }
778 enable_mii_autopoll(regs);
779
780 if (ww == W_MAX_TIMEOUT)
781 return -ETIMEDOUT;
782 return 0;
783}
784
785
786
787
788
789
790
791
792static void set_mii_flow_control(struct velocity_info *vptr)
793{
794
795 switch (vptr->options.flow_cntl) {
796 case FLOW_CNTL_TX:
797 MII_REG_BITS_OFF(ADVERTISE_PAUSE_CAP, MII_ADVERTISE, vptr->mac_regs);
798 MII_REG_BITS_ON(ADVERTISE_PAUSE_ASYM, MII_ADVERTISE, vptr->mac_regs);
799 break;
800
801 case FLOW_CNTL_RX:
802 MII_REG_BITS_ON(ADVERTISE_PAUSE_CAP, MII_ADVERTISE, vptr->mac_regs);
803 MII_REG_BITS_ON(ADVERTISE_PAUSE_ASYM, MII_ADVERTISE, vptr->mac_regs);
804 break;
805
806 case FLOW_CNTL_TX_RX:
807 MII_REG_BITS_ON(ADVERTISE_PAUSE_CAP, MII_ADVERTISE, vptr->mac_regs);
808 MII_REG_BITS_OFF(ADVERTISE_PAUSE_ASYM, MII_ADVERTISE, vptr->mac_regs);
809 break;
810
811 case FLOW_CNTL_DISABLE:
812 MII_REG_BITS_OFF(ADVERTISE_PAUSE_CAP, MII_ADVERTISE, vptr->mac_regs);
813 MII_REG_BITS_OFF(ADVERTISE_PAUSE_ASYM, MII_ADVERTISE, vptr->mac_regs);
814 break;
815 default:
816 break;
817 }
818}
819
820
821
822
823
824
825
826static void mii_set_auto_on(struct velocity_info *vptr)
827{
828 if (MII_REG_BITS_IS_ON(BMCR_ANENABLE, MII_BMCR, vptr->mac_regs))
829 MII_REG_BITS_ON(BMCR_ANRESTART, MII_BMCR, vptr->mac_regs);
830 else
831 MII_REG_BITS_ON(BMCR_ANENABLE, MII_BMCR, vptr->mac_regs);
832}
833
834static u32 check_connection_type(struct mac_regs __iomem *regs)
835{
836 u32 status = 0;
837 u8 PHYSR0;
838 u16 ANAR;
839 PHYSR0 = readb(®s->PHYSR0);
840
841
842
843
844
845
846 if (PHYSR0 & PHYSR0_FDPX)
847 status |= VELOCITY_DUPLEX_FULL;
848
849 if (PHYSR0 & PHYSR0_SPDG)
850 status |= VELOCITY_SPEED_1000;
851 else if (PHYSR0 & PHYSR0_SPD10)
852 status |= VELOCITY_SPEED_10;
853 else
854 status |= VELOCITY_SPEED_100;
855
856 if (MII_REG_BITS_IS_ON(BMCR_ANENABLE, MII_BMCR, regs)) {
857 velocity_mii_read(regs, MII_ADVERTISE, &ANAR);
858 if ((ANAR & (ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10FULL | ADVERTISE_10HALF))
859 == (ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10FULL | ADVERTISE_10HALF)) {
860 if (MII_REG_BITS_IS_ON(ADVERTISE_1000HALF | ADVERTISE_1000FULL, MII_CTRL1000, regs))
861 status |= VELOCITY_AUTONEG_ENABLE;
862 }
863 }
864
865 return status;
866}
867
868
869
870
871
872
873
874
875
876static int velocity_set_media_mode(struct velocity_info *vptr, u32 mii_status)
877{
878 u32 curr_status;
879 struct mac_regs __iomem *regs = vptr->mac_regs;
880
881 vptr->mii_status = mii_check_media_mode(vptr->mac_regs);
882 curr_status = vptr->mii_status & (~VELOCITY_LINK_FAIL);
883
884
885 set_mii_flow_control(vptr);
886
887
888
889
890
891
892
893
894
895
896
897
898 if (PHYID_GET_PHY_ID(vptr->phy_id) == PHYID_CICADA_CS8201)
899 MII_REG_BITS_ON(AUXCR_MDPPS, MII_NCONFIG, vptr->mac_regs);
900
901
902
903
904 if (mii_status & VELOCITY_AUTONEG_ENABLE) {
905 VELOCITY_PRT(MSG_LEVEL_INFO, "Velocity is AUTO mode\n");
906
907 BYTE_REG_BITS_OFF(CHIPGCR_FCMODE, ®s->CHIPGCR);
908
909 MII_REG_BITS_ON(ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10FULL | ADVERTISE_10HALF, MII_ADVERTISE, vptr->mac_regs);
910 MII_REG_BITS_ON(ADVERTISE_1000FULL | ADVERTISE_1000HALF, MII_CTRL1000, vptr->mac_regs);
911 MII_REG_BITS_ON(BMCR_SPEED1000, MII_BMCR, vptr->mac_regs);
912
913
914 mii_set_auto_on(vptr);
915 } else {
916 u16 CTRL1000;
917 u16 ANAR;
918 u8 CHIPGCR;
919
920
921
922
923
924
925
926
927
928 BYTE_REG_BITS_ON(CHIPGCR_FCMODE, ®s->CHIPGCR);
929
930 CHIPGCR = readb(®s->CHIPGCR);
931
932 if (mii_status & VELOCITY_SPEED_1000)
933 CHIPGCR |= CHIPGCR_FCGMII;
934 else
935 CHIPGCR &= ~CHIPGCR_FCGMII;
936
937 if (mii_status & VELOCITY_DUPLEX_FULL) {
938 CHIPGCR |= CHIPGCR_FCFDX;
939 writeb(CHIPGCR, ®s->CHIPGCR);
940 VELOCITY_PRT(MSG_LEVEL_INFO, "set Velocity to forced full mode\n");
941 if (vptr->rev_id < REV_ID_VT3216_A0)
942 BYTE_REG_BITS_OFF(TCR_TB2BDIS, ®s->TCR);
943 } else {
944 CHIPGCR &= ~CHIPGCR_FCFDX;
945 VELOCITY_PRT(MSG_LEVEL_INFO, "set Velocity to forced half mode\n");
946 writeb(CHIPGCR, ®s->CHIPGCR);
947 if (vptr->rev_id < REV_ID_VT3216_A0)
948 BYTE_REG_BITS_ON(TCR_TB2BDIS, ®s->TCR);
949 }
950
951 velocity_mii_read(vptr->mac_regs, MII_CTRL1000, &CTRL1000);
952 CTRL1000 &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
953 if ((mii_status & VELOCITY_SPEED_1000) &&
954 (mii_status & VELOCITY_DUPLEX_FULL)) {
955 CTRL1000 |= ADVERTISE_1000FULL;
956 }
957 velocity_mii_write(vptr->mac_regs, MII_CTRL1000, CTRL1000);
958
959 if (!(mii_status & VELOCITY_DUPLEX_FULL) && (mii_status & VELOCITY_SPEED_10))
960 BYTE_REG_BITS_OFF(TESTCFG_HBDIS, ®s->TESTCFG);
961 else
962 BYTE_REG_BITS_ON(TESTCFG_HBDIS, ®s->TESTCFG);
963
964
965 velocity_mii_read(vptr->mac_regs, MII_ADVERTISE, &ANAR);
966 ANAR &= (~(ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10FULL | ADVERTISE_10HALF));
967 if (mii_status & VELOCITY_SPEED_100) {
968 if (mii_status & VELOCITY_DUPLEX_FULL)
969 ANAR |= ADVERTISE_100FULL;
970 else
971 ANAR |= ADVERTISE_100HALF;
972 } else if (mii_status & VELOCITY_SPEED_10) {
973 if (mii_status & VELOCITY_DUPLEX_FULL)
974 ANAR |= ADVERTISE_10FULL;
975 else
976 ANAR |= ADVERTISE_10HALF;
977 }
978 velocity_mii_write(vptr->mac_regs, MII_ADVERTISE, ANAR);
979
980 mii_set_auto_on(vptr);
981
982 }
983
984
985 return VELOCITY_LINK_CHANGE;
986}
987
988
989
990
991
992
993
994
995
996static void velocity_print_link_status(struct velocity_info *vptr)
997{
998
999 if (vptr->mii_status & VELOCITY_LINK_FAIL) {
1000 VELOCITY_PRT(MSG_LEVEL_INFO, KERN_NOTICE "%s: failed to detect cable link\n", vptr->netdev->name);
1001 } else if (vptr->options.spd_dpx == SPD_DPX_AUTO) {
1002 VELOCITY_PRT(MSG_LEVEL_INFO, KERN_NOTICE "%s: Link auto-negotiation", vptr->netdev->name);
1003
1004 if (vptr->mii_status & VELOCITY_SPEED_1000)
1005 VELOCITY_PRT(MSG_LEVEL_INFO, " speed 1000M bps");
1006 else if (vptr->mii_status & VELOCITY_SPEED_100)
1007 VELOCITY_PRT(MSG_LEVEL_INFO, " speed 100M bps");
1008 else
1009 VELOCITY_PRT(MSG_LEVEL_INFO, " speed 10M bps");
1010
1011 if (vptr->mii_status & VELOCITY_DUPLEX_FULL)
1012 VELOCITY_PRT(MSG_LEVEL_INFO, " full duplex\n");
1013 else
1014 VELOCITY_PRT(MSG_LEVEL_INFO, " half duplex\n");
1015 } else {
1016 VELOCITY_PRT(MSG_LEVEL_INFO, KERN_NOTICE "%s: Link forced", vptr->netdev->name);
1017 switch (vptr->options.spd_dpx) {
1018 case SPD_DPX_1000_FULL:
1019 VELOCITY_PRT(MSG_LEVEL_INFO, " speed 1000M bps full duplex\n");
1020 break;
1021 case SPD_DPX_100_HALF:
1022 VELOCITY_PRT(MSG_LEVEL_INFO, " speed 100M bps half duplex\n");
1023 break;
1024 case SPD_DPX_100_FULL:
1025 VELOCITY_PRT(MSG_LEVEL_INFO, " speed 100M bps full duplex\n");
1026 break;
1027 case SPD_DPX_10_HALF:
1028 VELOCITY_PRT(MSG_LEVEL_INFO, " speed 10M bps half duplex\n");
1029 break;
1030 case SPD_DPX_10_FULL:
1031 VELOCITY_PRT(MSG_LEVEL_INFO, " speed 10M bps full duplex\n");
1032 break;
1033 default:
1034 break;
1035 }
1036 }
1037}
1038
1039
1040
1041
1042
1043
1044
1045
1046static void enable_flow_control_ability(struct velocity_info *vptr)
1047{
1048
1049 struct mac_regs __iomem *regs = vptr->mac_regs;
1050
1051 switch (vptr->options.flow_cntl) {
1052
1053 case FLOW_CNTL_DEFAULT:
1054 if (BYTE_REG_BITS_IS_ON(PHYSR0_RXFLC, ®s->PHYSR0))
1055 writel(CR0_FDXRFCEN, ®s->CR0Set);
1056 else
1057 writel(CR0_FDXRFCEN, ®s->CR0Clr);
1058
1059 if (BYTE_REG_BITS_IS_ON(PHYSR0_TXFLC, ®s->PHYSR0))
1060 writel(CR0_FDXTFCEN, ®s->CR0Set);
1061 else
1062 writel(CR0_FDXTFCEN, ®s->CR0Clr);
1063 break;
1064
1065 case FLOW_CNTL_TX:
1066 writel(CR0_FDXTFCEN, ®s->CR0Set);
1067 writel(CR0_FDXRFCEN, ®s->CR0Clr);
1068 break;
1069
1070 case FLOW_CNTL_RX:
1071 writel(CR0_FDXRFCEN, ®s->CR0Set);
1072 writel(CR0_FDXTFCEN, ®s->CR0Clr);
1073 break;
1074
1075 case FLOW_CNTL_TX_RX:
1076 writel(CR0_FDXTFCEN, ®s->CR0Set);
1077 writel(CR0_FDXRFCEN, ®s->CR0Set);
1078 break;
1079
1080 case FLOW_CNTL_DISABLE:
1081 writel(CR0_FDXRFCEN, ®s->CR0Clr);
1082 writel(CR0_FDXTFCEN, ®s->CR0Clr);
1083 break;
1084
1085 default:
1086 break;
1087 }
1088
1089}
1090
1091
1092
1093
1094
1095
1096
1097
1098static int velocity_soft_reset(struct velocity_info *vptr)
1099{
1100 struct mac_regs __iomem *regs = vptr->mac_regs;
1101 int i = 0;
1102
1103 writel(CR0_SFRST, ®s->CR0Set);
1104
1105 for (i = 0; i < W_MAX_TIMEOUT; i++) {
1106 udelay(5);
1107 if (!DWORD_REG_BITS_IS_ON(CR0_SFRST, ®s->CR0Set))
1108 break;
1109 }
1110
1111 if (i == W_MAX_TIMEOUT) {
1112 writel(CR0_FORSRST, ®s->CR0Set);
1113
1114
1115 mdelay(2);
1116 }
1117 return 0;
1118}
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128static void velocity_set_multi(struct net_device *dev)
1129{
1130 struct velocity_info *vptr = netdev_priv(dev);
1131 struct mac_regs __iomem *regs = vptr->mac_regs;
1132 u8 rx_mode;
1133 int i;
1134 struct netdev_hw_addr *ha;
1135
1136 if (dev->flags & IFF_PROMISC) {
1137 writel(0xffffffff, ®s->MARCAM[0]);
1138 writel(0xffffffff, ®s->MARCAM[4]);
1139 rx_mode = (RCR_AM | RCR_AB | RCR_PROM);
1140 } else if ((netdev_mc_count(dev) > vptr->multicast_limit) ||
1141 (dev->flags & IFF_ALLMULTI)) {
1142 writel(0xffffffff, ®s->MARCAM[0]);
1143 writel(0xffffffff, ®s->MARCAM[4]);
1144 rx_mode = (RCR_AM | RCR_AB);
1145 } else {
1146 int offset = MCAM_SIZE - vptr->multicast_limit;
1147 mac_get_cam_mask(regs, vptr->mCAMmask);
1148
1149 i = 0;
1150 netdev_for_each_mc_addr(ha, dev) {
1151 mac_set_cam(regs, i + offset, ha->addr);
1152 vptr->mCAMmask[(offset + i) / 8] |= 1 << ((offset + i) & 7);
1153 i++;
1154 }
1155
1156 mac_set_cam_mask(regs, vptr->mCAMmask);
1157 rx_mode = RCR_AM | RCR_AB | RCR_AP;
1158 }
1159 if (dev->mtu > 1500)
1160 rx_mode |= RCR_AL;
1161
1162 BYTE_REG_BITS_ON(rx_mode, ®s->RCR);
1163
1164}
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177static void mii_init(struct velocity_info *vptr, u32 mii_status)
1178{
1179 u16 BMCR;
1180
1181 switch (PHYID_GET_PHY_ID(vptr->phy_id)) {
1182 case PHYID_ICPLUS_IP101A:
1183 MII_REG_BITS_ON((ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP),
1184 MII_ADVERTISE, vptr->mac_regs);
1185 if (vptr->mii_status & VELOCITY_DUPLEX_FULL)
1186 MII_REG_BITS_ON(TCSR_ECHODIS, MII_SREVISION,
1187 vptr->mac_regs);
1188 else
1189 MII_REG_BITS_OFF(TCSR_ECHODIS, MII_SREVISION,
1190 vptr->mac_regs);
1191 MII_REG_BITS_ON(PLED_LALBE, MII_TPISTATUS, vptr->mac_regs);
1192 break;
1193 case PHYID_CICADA_CS8201:
1194
1195
1196
1197 MII_REG_BITS_OFF((ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP), MII_ADVERTISE, vptr->mac_regs);
1198
1199
1200
1201
1202
1203 if (vptr->mii_status & VELOCITY_DUPLEX_FULL)
1204 MII_REG_BITS_ON(TCSR_ECHODIS, MII_SREVISION, vptr->mac_regs);
1205 else
1206 MII_REG_BITS_OFF(TCSR_ECHODIS, MII_SREVISION, vptr->mac_regs);
1207
1208
1209
1210 MII_REG_BITS_ON(PLED_LALBE, MII_TPISTATUS, vptr->mac_regs);
1211 break;
1212 case PHYID_VT3216_32BIT:
1213 case PHYID_VT3216_64BIT:
1214
1215
1216
1217 MII_REG_BITS_ON((ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP), MII_ADVERTISE, vptr->mac_regs);
1218
1219
1220
1221
1222
1223 if (vptr->mii_status & VELOCITY_DUPLEX_FULL)
1224 MII_REG_BITS_ON(TCSR_ECHODIS, MII_SREVISION, vptr->mac_regs);
1225 else
1226 MII_REG_BITS_OFF(TCSR_ECHODIS, MII_SREVISION, vptr->mac_regs);
1227 break;
1228
1229 case PHYID_MARVELL_1000:
1230 case PHYID_MARVELL_1000S:
1231
1232
1233
1234 MII_REG_BITS_ON(PSCR_ACRSTX, MII_REG_PSCR, vptr->mac_regs);
1235
1236
1237
1238 MII_REG_BITS_ON((ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP), MII_ADVERTISE, vptr->mac_regs);
1239 break;
1240 default:
1241 ;
1242 }
1243 velocity_mii_read(vptr->mac_regs, MII_BMCR, &BMCR);
1244 if (BMCR & BMCR_ISOLATE) {
1245 BMCR &= ~BMCR_ISOLATE;
1246 velocity_mii_write(vptr->mac_regs, MII_BMCR, BMCR);
1247 }
1248}
1249
1250
1251
1252
1253
1254
1255
1256static void setup_queue_timers(struct velocity_info *vptr)
1257{
1258
1259 if (vptr->rev_id >= REV_ID_VT3216_A0) {
1260 u8 txqueue_timer = 0;
1261 u8 rxqueue_timer = 0;
1262
1263 if (vptr->mii_status & (VELOCITY_SPEED_1000 |
1264 VELOCITY_SPEED_100)) {
1265 txqueue_timer = vptr->options.txqueue_timer;
1266 rxqueue_timer = vptr->options.rxqueue_timer;
1267 }
1268
1269 writeb(txqueue_timer, &vptr->mac_regs->TQETMR);
1270 writeb(rxqueue_timer, &vptr->mac_regs->RQETMR);
1271 }
1272}
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282static void setup_adaptive_interrupts(struct velocity_info *vptr)
1283{
1284 struct mac_regs __iomem *regs = vptr->mac_regs;
1285 u16 tx_intsup = vptr->options.tx_intsup;
1286 u16 rx_intsup = vptr->options.rx_intsup;
1287
1288
1289 vptr->int_mask = INT_MASK_DEF;
1290
1291
1292 writeb(CAMCR_PS0, ®s->CAMCR);
1293 if (tx_intsup != 0) {
1294 vptr->int_mask &= ~(ISR_PTXI | ISR_PTX0I | ISR_PTX1I |
1295 ISR_PTX2I | ISR_PTX3I);
1296 writew(tx_intsup, ®s->ISRCTL);
1297 } else
1298 writew(ISRCTL_TSUPDIS, ®s->ISRCTL);
1299
1300
1301 writeb(CAMCR_PS1, ®s->CAMCR);
1302 if (rx_intsup != 0) {
1303 vptr->int_mask &= ~ISR_PRXI;
1304 writew(rx_intsup, ®s->ISRCTL);
1305 } else
1306 writew(ISRCTL_RSUPDIS, ®s->ISRCTL);
1307
1308
1309 writeb(0, ®s->CAMCR);
1310}
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320static void velocity_init_registers(struct velocity_info *vptr,
1321 enum velocity_init_type type)
1322{
1323 struct mac_regs __iomem *regs = vptr->mac_regs;
1324 struct net_device *netdev = vptr->netdev;
1325 int i, mii_status;
1326
1327 mac_wol_reset(regs);
1328
1329 switch (type) {
1330 case VELOCITY_INIT_RESET:
1331 case VELOCITY_INIT_WOL:
1332
1333 netif_stop_queue(netdev);
1334
1335
1336
1337
1338 velocity_rx_reset(vptr);
1339 mac_rx_queue_run(regs);
1340 mac_rx_queue_wake(regs);
1341
1342 mii_status = velocity_get_opt_media_mode(vptr);
1343 if (velocity_set_media_mode(vptr, mii_status) != VELOCITY_LINK_CHANGE) {
1344 velocity_print_link_status(vptr);
1345 if (!(vptr->mii_status & VELOCITY_LINK_FAIL))
1346 netif_wake_queue(netdev);
1347 }
1348
1349 enable_flow_control_ability(vptr);
1350
1351 mac_clear_isr(regs);
1352 writel(CR0_STOP, ®s->CR0Clr);
1353 writel((CR0_DPOLL | CR0_TXON | CR0_RXON | CR0_STRT),
1354 ®s->CR0Set);
1355
1356 break;
1357
1358 case VELOCITY_INIT_COLD:
1359 default:
1360
1361
1362
1363 velocity_soft_reset(vptr);
1364 mdelay(5);
1365
1366 if (!vptr->no_eeprom) {
1367 mac_eeprom_reload(regs);
1368 for (i = 0; i < 6; i++)
1369 writeb(netdev->dev_addr[i], regs->PAR + i);
1370 }
1371
1372
1373
1374
1375 BYTE_REG_BITS_OFF(CFGA_PACPI, &(regs->CFGA));
1376 mac_set_rx_thresh(regs, vptr->options.rx_thresh);
1377 mac_set_dma_length(regs, vptr->options.DMA_length);
1378
1379 writeb(WOLCFG_SAM | WOLCFG_SAB, ®s->WOLCFGSet);
1380
1381
1382
1383 BYTE_REG_BITS_SET(CFGB_OFSET, (CFGB_CRANDOM | CFGB_CAP | CFGB_MBA | CFGB_BAKOPT), ®s->CFGB);
1384
1385
1386
1387
1388 velocity_init_cam_filter(vptr);
1389
1390
1391
1392
1393 velocity_set_multi(netdev);
1394
1395
1396
1397
1398 enable_mii_autopoll(regs);
1399
1400 setup_adaptive_interrupts(vptr);
1401
1402 writel(vptr->rx.pool_dma, ®s->RDBaseLo);
1403 writew(vptr->options.numrx - 1, ®s->RDCSize);
1404 mac_rx_queue_run(regs);
1405 mac_rx_queue_wake(regs);
1406
1407 writew(vptr->options.numtx - 1, ®s->TDCSize);
1408
1409 for (i = 0; i < vptr->tx.numq; i++) {
1410 writel(vptr->tx.pool_dma[i], ®s->TDBaseLo[i]);
1411 mac_tx_queue_run(regs, i);
1412 }
1413
1414 init_flow_control_register(vptr);
1415
1416 writel(CR0_STOP, ®s->CR0Clr);
1417 writel((CR0_DPOLL | CR0_TXON | CR0_RXON | CR0_STRT), ®s->CR0Set);
1418
1419 mii_status = velocity_get_opt_media_mode(vptr);
1420 netif_stop_queue(netdev);
1421
1422 mii_init(vptr, mii_status);
1423
1424 if (velocity_set_media_mode(vptr, mii_status) != VELOCITY_LINK_CHANGE) {
1425 velocity_print_link_status(vptr);
1426 if (!(vptr->mii_status & VELOCITY_LINK_FAIL))
1427 netif_wake_queue(netdev);
1428 }
1429
1430 enable_flow_control_ability(vptr);
1431 mac_hw_mibs_init(regs);
1432 mac_write_int_mask(vptr->int_mask, regs);
1433 mac_clear_isr(regs);
1434
1435 }
1436}
1437
1438static void velocity_give_many_rx_descs(struct velocity_info *vptr)
1439{
1440 struct mac_regs __iomem *regs = vptr->mac_regs;
1441 int avail, dirty, unusable;
1442
1443
1444
1445
1446
1447 if (vptr->rx.filled < 4)
1448 return;
1449
1450 wmb();
1451
1452 unusable = vptr->rx.filled & 0x0003;
1453 dirty = vptr->rx.dirty - unusable;
1454 for (avail = vptr->rx.filled & 0xfffc; avail; avail--) {
1455 dirty = (dirty > 0) ? dirty - 1 : vptr->options.numrx - 1;
1456 vptr->rx.ring[dirty].rdesc0.len |= OWNED_BY_NIC;
1457 }
1458
1459 writew(vptr->rx.filled & 0xfffc, ®s->RBRDU);
1460 vptr->rx.filled = unusable;
1461}
1462
1463
1464
1465
1466
1467
1468
1469
1470static int velocity_init_dma_rings(struct velocity_info *vptr)
1471{
1472 struct velocity_opt *opt = &vptr->options;
1473 const unsigned int rx_ring_size = opt->numrx * sizeof(struct rx_desc);
1474 const unsigned int tx_ring_size = opt->numtx * sizeof(struct tx_desc);
1475 dma_addr_t pool_dma;
1476 void *pool;
1477 unsigned int i;
1478
1479
1480
1481
1482
1483
1484
1485 pool = dma_alloc_coherent(vptr->dev, tx_ring_size * vptr->tx.numq +
1486 rx_ring_size, &pool_dma, GFP_ATOMIC);
1487 if (!pool) {
1488 dev_err(vptr->dev, "%s : DMA memory allocation failed.\n",
1489 vptr->netdev->name);
1490 return -ENOMEM;
1491 }
1492
1493 vptr->rx.ring = pool;
1494 vptr->rx.pool_dma = pool_dma;
1495
1496 pool += rx_ring_size;
1497 pool_dma += rx_ring_size;
1498
1499 for (i = 0; i < vptr->tx.numq; i++) {
1500 vptr->tx.rings[i] = pool;
1501 vptr->tx.pool_dma[i] = pool_dma;
1502 pool += tx_ring_size;
1503 pool_dma += tx_ring_size;
1504 }
1505
1506 return 0;
1507}
1508
1509static void velocity_set_rxbufsize(struct velocity_info *vptr, int mtu)
1510{
1511 vptr->rx.buf_sz = (mtu <= ETH_DATA_LEN) ? PKT_BUF_SZ : mtu + 32;
1512}
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524static int velocity_alloc_rx_buf(struct velocity_info *vptr, int idx)
1525{
1526 struct rx_desc *rd = &(vptr->rx.ring[idx]);
1527 struct velocity_rd_info *rd_info = &(vptr->rx.info[idx]);
1528
1529 rd_info->skb = netdev_alloc_skb(vptr->netdev, vptr->rx.buf_sz + 64);
1530 if (rd_info->skb == NULL)
1531 return -ENOMEM;
1532
1533
1534
1535
1536
1537 skb_reserve(rd_info->skb,
1538 64 - ((unsigned long) rd_info->skb->data & 63));
1539 rd_info->skb_dma = dma_map_single(vptr->dev, rd_info->skb->data,
1540 vptr->rx.buf_sz, DMA_FROM_DEVICE);
1541
1542
1543
1544
1545
1546 *((u32 *) & (rd->rdesc0)) = 0;
1547 rd->size = cpu_to_le16(vptr->rx.buf_sz) | RX_INTEN;
1548 rd->pa_low = cpu_to_le32(rd_info->skb_dma);
1549 rd->pa_high = 0;
1550 return 0;
1551}
1552
1553
1554static int velocity_rx_refill(struct velocity_info *vptr)
1555{
1556 int dirty = vptr->rx.dirty, done = 0;
1557
1558 do {
1559 struct rx_desc *rd = vptr->rx.ring + dirty;
1560
1561
1562 if (rd->rdesc0.len & OWNED_BY_NIC)
1563 break;
1564
1565 if (!vptr->rx.info[dirty].skb) {
1566 if (velocity_alloc_rx_buf(vptr, dirty) < 0)
1567 break;
1568 }
1569 done++;
1570 dirty = (dirty < vptr->options.numrx - 1) ? dirty + 1 : 0;
1571 } while (dirty != vptr->rx.curr);
1572
1573 if (done) {
1574 vptr->rx.dirty = dirty;
1575 vptr->rx.filled += done;
1576 }
1577
1578 return done;
1579}
1580
1581
1582
1583
1584
1585
1586
1587
1588static void velocity_free_rd_ring(struct velocity_info *vptr)
1589{
1590 int i;
1591
1592 if (vptr->rx.info == NULL)
1593 return;
1594
1595 for (i = 0; i < vptr->options.numrx; i++) {
1596 struct velocity_rd_info *rd_info = &(vptr->rx.info[i]);
1597 struct rx_desc *rd = vptr->rx.ring + i;
1598
1599 memset(rd, 0, sizeof(*rd));
1600
1601 if (!rd_info->skb)
1602 continue;
1603 dma_unmap_single(vptr->dev, rd_info->skb_dma, vptr->rx.buf_sz,
1604 DMA_FROM_DEVICE);
1605 rd_info->skb_dma = 0;
1606
1607 dev_kfree_skb(rd_info->skb);
1608 rd_info->skb = NULL;
1609 }
1610
1611 kfree(vptr->rx.info);
1612 vptr->rx.info = NULL;
1613}
1614
1615
1616
1617
1618
1619
1620
1621
1622static int velocity_init_rd_ring(struct velocity_info *vptr)
1623{
1624 int ret = -ENOMEM;
1625
1626 vptr->rx.info = kcalloc(vptr->options.numrx,
1627 sizeof(struct velocity_rd_info), GFP_KERNEL);
1628 if (!vptr->rx.info)
1629 goto out;
1630
1631 velocity_init_rx_ring_indexes(vptr);
1632
1633 if (velocity_rx_refill(vptr) != vptr->options.numrx) {
1634 VELOCITY_PRT(MSG_LEVEL_ERR, KERN_ERR
1635 "%s: failed to allocate RX buffer.\n", vptr->netdev->name);
1636 velocity_free_rd_ring(vptr);
1637 goto out;
1638 }
1639
1640 ret = 0;
1641out:
1642 return ret;
1643}
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653static int velocity_init_td_ring(struct velocity_info *vptr)
1654{
1655 int j;
1656
1657
1658 for (j = 0; j < vptr->tx.numq; j++) {
1659
1660 vptr->tx.infos[j] = kcalloc(vptr->options.numtx,
1661 sizeof(struct velocity_td_info),
1662 GFP_KERNEL);
1663 if (!vptr->tx.infos[j]) {
1664 while (--j >= 0)
1665 kfree(vptr->tx.infos[j]);
1666 return -ENOMEM;
1667 }
1668
1669 vptr->tx.tail[j] = vptr->tx.curr[j] = vptr->tx.used[j] = 0;
1670 }
1671 return 0;
1672}
1673
1674
1675
1676
1677
1678
1679
1680static void velocity_free_dma_rings(struct velocity_info *vptr)
1681{
1682 const int size = vptr->options.numrx * sizeof(struct rx_desc) +
1683 vptr->options.numtx * sizeof(struct tx_desc) * vptr->tx.numq;
1684
1685 dma_free_coherent(vptr->dev, size, vptr->rx.ring, vptr->rx.pool_dma);
1686}
1687
1688static int velocity_init_rings(struct velocity_info *vptr, int mtu)
1689{
1690 int ret;
1691
1692 velocity_set_rxbufsize(vptr, mtu);
1693
1694 ret = velocity_init_dma_rings(vptr);
1695 if (ret < 0)
1696 goto out;
1697
1698 ret = velocity_init_rd_ring(vptr);
1699 if (ret < 0)
1700 goto err_free_dma_rings_0;
1701
1702 ret = velocity_init_td_ring(vptr);
1703 if (ret < 0)
1704 goto err_free_rd_ring_1;
1705out:
1706 return ret;
1707
1708err_free_rd_ring_1:
1709 velocity_free_rd_ring(vptr);
1710err_free_dma_rings_0:
1711 velocity_free_dma_rings(vptr);
1712 goto out;
1713}
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723static void velocity_free_tx_buf(struct velocity_info *vptr,
1724 struct velocity_td_info *tdinfo, struct tx_desc *td)
1725{
1726 struct sk_buff *skb = tdinfo->skb;
1727
1728
1729
1730
1731 if (tdinfo->skb_dma) {
1732 int i;
1733
1734 for (i = 0; i < tdinfo->nskb_dma; i++) {
1735 size_t pktlen = max_t(size_t, skb->len, ETH_ZLEN);
1736
1737
1738 if (skb_shinfo(skb)->nr_frags > 0)
1739 pktlen = max_t(size_t, pktlen,
1740 td->td_buf[i].size & ~TD_QUEUE);
1741
1742 dma_unmap_single(vptr->dev, tdinfo->skb_dma[i],
1743 le16_to_cpu(pktlen), DMA_TO_DEVICE);
1744 }
1745 }
1746 dev_kfree_skb_irq(skb);
1747 tdinfo->skb = NULL;
1748}
1749
1750
1751
1752
1753static void velocity_free_td_ring_entry(struct velocity_info *vptr,
1754 int q, int n)
1755{
1756 struct velocity_td_info *td_info = &(vptr->tx.infos[q][n]);
1757 int i;
1758
1759 if (td_info == NULL)
1760 return;
1761
1762 if (td_info->skb) {
1763 for (i = 0; i < td_info->nskb_dma; i++) {
1764 if (td_info->skb_dma[i]) {
1765 dma_unmap_single(vptr->dev, td_info->skb_dma[i],
1766 td_info->skb->len, DMA_TO_DEVICE);
1767 td_info->skb_dma[i] = 0;
1768 }
1769 }
1770 dev_kfree_skb(td_info->skb);
1771 td_info->skb = NULL;
1772 }
1773}
1774
1775
1776
1777
1778
1779
1780
1781
1782static void velocity_free_td_ring(struct velocity_info *vptr)
1783{
1784 int i, j;
1785
1786 for (j = 0; j < vptr->tx.numq; j++) {
1787 if (vptr->tx.infos[j] == NULL)
1788 continue;
1789 for (i = 0; i < vptr->options.numtx; i++)
1790 velocity_free_td_ring_entry(vptr, j, i);
1791
1792 kfree(vptr->tx.infos[j]);
1793 vptr->tx.infos[j] = NULL;
1794 }
1795}
1796
1797static void velocity_free_rings(struct velocity_info *vptr)
1798{
1799 velocity_free_td_ring(vptr);
1800 velocity_free_rd_ring(vptr);
1801 velocity_free_dma_rings(vptr);
1802}
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815static void velocity_error(struct velocity_info *vptr, int status)
1816{
1817
1818 if (status & ISR_TXSTLI) {
1819 struct mac_regs __iomem *regs = vptr->mac_regs;
1820
1821 printk(KERN_ERR "TD structure error TDindex=%hx\n", readw(®s->TDIdx[0]));
1822 BYTE_REG_BITS_ON(TXESR_TDSTR, ®s->TXESR);
1823 writew(TRDCSR_RUN, ®s->TDCSRClr);
1824 netif_stop_queue(vptr->netdev);
1825
1826
1827
1828 }
1829
1830 if (status & ISR_SRCI) {
1831 struct mac_regs __iomem *regs = vptr->mac_regs;
1832 int linked;
1833
1834 if (vptr->options.spd_dpx == SPD_DPX_AUTO) {
1835 vptr->mii_status = check_connection_type(regs);
1836
1837
1838
1839
1840
1841
1842 if (vptr->rev_id < REV_ID_VT3216_A0) {
1843 if (vptr->mii_status & VELOCITY_DUPLEX_FULL)
1844 BYTE_REG_BITS_ON(TCR_TB2BDIS, ®s->TCR);
1845 else
1846 BYTE_REG_BITS_OFF(TCR_TB2BDIS, ®s->TCR);
1847 }
1848
1849
1850
1851 if (!(vptr->mii_status & VELOCITY_DUPLEX_FULL) && (vptr->mii_status & VELOCITY_SPEED_10))
1852 BYTE_REG_BITS_OFF(TESTCFG_HBDIS, ®s->TESTCFG);
1853 else
1854 BYTE_REG_BITS_ON(TESTCFG_HBDIS, ®s->TESTCFG);
1855
1856 setup_queue_timers(vptr);
1857 }
1858
1859
1860
1861 linked = readb(®s->PHYSR0) & PHYSR0_LINKGD;
1862
1863 if (linked) {
1864 vptr->mii_status &= ~VELOCITY_LINK_FAIL;
1865 netif_carrier_on(vptr->netdev);
1866 } else {
1867 vptr->mii_status |= VELOCITY_LINK_FAIL;
1868 netif_carrier_off(vptr->netdev);
1869 }
1870
1871 velocity_print_link_status(vptr);
1872 enable_flow_control_ability(vptr);
1873
1874
1875
1876
1877
1878
1879 enable_mii_autopoll(regs);
1880
1881 if (vptr->mii_status & VELOCITY_LINK_FAIL)
1882 netif_stop_queue(vptr->netdev);
1883 else
1884 netif_wake_queue(vptr->netdev);
1885
1886 }
1887 if (status & ISR_MIBFI)
1888 velocity_update_hw_mibs(vptr);
1889 if (status & ISR_LSTEI)
1890 mac_rx_queue_wake(vptr->mac_regs);
1891}
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901static int velocity_tx_srv(struct velocity_info *vptr)
1902{
1903 struct tx_desc *td;
1904 int qnum;
1905 int full = 0;
1906 int idx;
1907 int works = 0;
1908 struct velocity_td_info *tdinfo;
1909 struct net_device_stats *stats = &vptr->netdev->stats;
1910
1911 for (qnum = 0; qnum < vptr->tx.numq; qnum++) {
1912 for (idx = vptr->tx.tail[qnum]; vptr->tx.used[qnum] > 0;
1913 idx = (idx + 1) % vptr->options.numtx) {
1914
1915
1916
1917
1918 td = &(vptr->tx.rings[qnum][idx]);
1919 tdinfo = &(vptr->tx.infos[qnum][idx]);
1920
1921 if (td->tdesc0.len & OWNED_BY_NIC)
1922 break;
1923
1924 if ((works++ > 15))
1925 break;
1926
1927 if (td->tdesc0.TSR & TSR0_TERR) {
1928 stats->tx_errors++;
1929 stats->tx_dropped++;
1930 if (td->tdesc0.TSR & TSR0_CDH)
1931 stats->tx_heartbeat_errors++;
1932 if (td->tdesc0.TSR & TSR0_CRS)
1933 stats->tx_carrier_errors++;
1934 if (td->tdesc0.TSR & TSR0_ABT)
1935 stats->tx_aborted_errors++;
1936 if (td->tdesc0.TSR & TSR0_OWC)
1937 stats->tx_window_errors++;
1938 } else {
1939 stats->tx_packets++;
1940 stats->tx_bytes += tdinfo->skb->len;
1941 }
1942 velocity_free_tx_buf(vptr, tdinfo, td);
1943 vptr->tx.used[qnum]--;
1944 }
1945 vptr->tx.tail[qnum] = idx;
1946
1947 if (AVAIL_TD(vptr, qnum) < 1)
1948 full = 1;
1949 }
1950
1951
1952
1953
1954 if (netif_queue_stopped(vptr->netdev) && (full == 0) &&
1955 (!(vptr->mii_status & VELOCITY_LINK_FAIL))) {
1956 netif_wake_queue(vptr->netdev);
1957 }
1958 return works;
1959}
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969static inline void velocity_rx_csum(struct rx_desc *rd, struct sk_buff *skb)
1970{
1971 skb_checksum_none_assert(skb);
1972
1973 if (rd->rdesc1.CSM & CSM_IPKT) {
1974 if (rd->rdesc1.CSM & CSM_IPOK) {
1975 if ((rd->rdesc1.CSM & CSM_TCPKT) ||
1976 (rd->rdesc1.CSM & CSM_UDPKT)) {
1977 if (!(rd->rdesc1.CSM & CSM_TUPOK))
1978 return;
1979 }
1980 skb->ip_summed = CHECKSUM_UNNECESSARY;
1981 }
1982 }
1983}
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997static int velocity_rx_copy(struct sk_buff **rx_skb, int pkt_size,
1998 struct velocity_info *vptr)
1999{
2000 int ret = -1;
2001 if (pkt_size < rx_copybreak) {
2002 struct sk_buff *new_skb;
2003
2004 new_skb = netdev_alloc_skb_ip_align(vptr->netdev, pkt_size);
2005 if (new_skb) {
2006 new_skb->ip_summed = rx_skb[0]->ip_summed;
2007 skb_copy_from_linear_data(*rx_skb, new_skb->data, pkt_size);
2008 *rx_skb = new_skb;
2009 ret = 0;
2010 }
2011
2012 }
2013 return ret;
2014}
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
2025static inline void velocity_iph_realign(struct velocity_info *vptr,
2026 struct sk_buff *skb, int pkt_size)
2027{
2028 if (vptr->flags & VELOCITY_FLAGS_IP_ALIGN) {
2029 memmove(skb->data + 2, skb->data, pkt_size);
2030 skb_reserve(skb, 2);
2031 }
2032}
2033
2034
2035
2036
2037
2038
2039
2040
2041
2042static int velocity_receive_frame(struct velocity_info *vptr, int idx)
2043{
2044 struct net_device_stats *stats = &vptr->netdev->stats;
2045 struct velocity_rd_info *rd_info = &(vptr->rx.info[idx]);
2046 struct rx_desc *rd = &(vptr->rx.ring[idx]);
2047 int pkt_len = le16_to_cpu(rd->rdesc0.len) & 0x3fff;
2048 struct sk_buff *skb;
2049
2050 if (unlikely(rd->rdesc0.RSR & (RSR_STP | RSR_EDP | RSR_RL))) {
2051 if (rd->rdesc0.RSR & (RSR_STP | RSR_EDP))
2052 VELOCITY_PRT(MSG_LEVEL_VERBOSE, KERN_ERR " %s : the received frame spans multiple RDs.\n", vptr->netdev->name);
2053 stats->rx_length_errors++;
2054 return -EINVAL;
2055 }
2056
2057 if (rd->rdesc0.RSR & RSR_MAR)
2058 stats->multicast++;
2059
2060 skb = rd_info->skb;
2061
2062 dma_sync_single_for_cpu(vptr->dev, rd_info->skb_dma,
2063 vptr->rx.buf_sz, DMA_FROM_DEVICE);
2064
2065 velocity_rx_csum(rd, skb);
2066
2067 if (velocity_rx_copy(&skb, pkt_len, vptr) < 0) {
2068 velocity_iph_realign(vptr, skb, pkt_len);
2069 rd_info->skb = NULL;
2070 dma_unmap_single(vptr->dev, rd_info->skb_dma, vptr->rx.buf_sz,
2071 DMA_FROM_DEVICE);
2072 } else {
2073 dma_sync_single_for_device(vptr->dev, rd_info->skb_dma,
2074 vptr->rx.buf_sz, DMA_FROM_DEVICE);
2075 }
2076
2077 skb_put(skb, pkt_len - 4);
2078 skb->protocol = eth_type_trans(skb, vptr->netdev);
2079
2080 if (rd->rdesc0.RSR & RSR_DETAG) {
2081 u16 vid = swab16(le16_to_cpu(rd->rdesc1.PQTAG));
2082
2083 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
2084 }
2085 netif_receive_skb(skb);
2086
2087 stats->rx_bytes += pkt_len;
2088 stats->rx_packets++;
2089
2090 return 0;
2091}
2092
2093
2094
2095
2096
2097
2098
2099
2100
2101static int velocity_rx_srv(struct velocity_info *vptr, int budget_left)
2102{
2103 struct net_device_stats *stats = &vptr->netdev->stats;
2104 int rd_curr = vptr->rx.curr;
2105 int works = 0;
2106
2107 while (works < budget_left) {
2108 struct rx_desc *rd = vptr->rx.ring + rd_curr;
2109
2110 if (!vptr->rx.info[rd_curr].skb)
2111 break;
2112
2113 if (rd->rdesc0.len & OWNED_BY_NIC)
2114 break;
2115
2116 rmb();
2117
2118
2119
2120
2121 if (rd->rdesc0.RSR & (RSR_RXOK | RSR_CE | RSR_RL)) {
2122 if (velocity_receive_frame(vptr, rd_curr) < 0)
2123 stats->rx_dropped++;
2124 } else {
2125 if (rd->rdesc0.RSR & RSR_CRC)
2126 stats->rx_crc_errors++;
2127 if (rd->rdesc0.RSR & RSR_FAE)
2128 stats->rx_frame_errors++;
2129
2130 stats->rx_dropped++;
2131 }
2132
2133 rd->size |= RX_INTEN;
2134
2135 rd_curr++;
2136 if (rd_curr >= vptr->options.numrx)
2137 rd_curr = 0;
2138 works++;
2139 }
2140
2141 vptr->rx.curr = rd_curr;
2142
2143 if ((works > 0) && (velocity_rx_refill(vptr) > 0))
2144 velocity_give_many_rx_descs(vptr);
2145
2146 VAR_USED(stats);
2147 return works;
2148}
2149
2150static int velocity_poll(struct napi_struct *napi, int budget)
2151{
2152 struct velocity_info *vptr = container_of(napi,
2153 struct velocity_info, napi);
2154 unsigned int rx_done;
2155 unsigned long flags;
2156
2157
2158
2159
2160
2161 rx_done = velocity_rx_srv(vptr, budget);
2162 spin_lock_irqsave(&vptr->lock, flags);
2163 velocity_tx_srv(vptr);
2164
2165 if (rx_done < budget) {
2166 napi_complete(napi);
2167 mac_enable_int(vptr->mac_regs);
2168 }
2169 spin_unlock_irqrestore(&vptr->lock, flags);
2170
2171 return rx_done;
2172}
2173
2174
2175
2176
2177
2178
2179
2180
2181
2182
2183
2184static irqreturn_t velocity_intr(int irq, void *dev_instance)
2185{
2186 struct net_device *dev = dev_instance;
2187 struct velocity_info *vptr = netdev_priv(dev);
2188 u32 isr_status;
2189
2190 spin_lock(&vptr->lock);
2191 isr_status = mac_read_isr(vptr->mac_regs);
2192
2193
2194 if (isr_status == 0) {
2195 spin_unlock(&vptr->lock);
2196 return IRQ_NONE;
2197 }
2198
2199
2200 mac_write_isr(vptr->mac_regs, isr_status);
2201
2202 if (likely(napi_schedule_prep(&vptr->napi))) {
2203 mac_disable_int(vptr->mac_regs);
2204 __napi_schedule(&vptr->napi);
2205 }
2206
2207 if (isr_status & (~(ISR_PRXI | ISR_PPRXI | ISR_PTXI | ISR_PPTXI)))
2208 velocity_error(vptr, isr_status);
2209
2210 spin_unlock(&vptr->lock);
2211
2212 return IRQ_HANDLED;
2213}
2214
2215
2216
2217
2218
2219
2220
2221
2222
2223
2224
2225static int velocity_open(struct net_device *dev)
2226{
2227 struct velocity_info *vptr = netdev_priv(dev);
2228 int ret;
2229
2230 ret = velocity_init_rings(vptr, dev->mtu);
2231 if (ret < 0)
2232 goto out;
2233
2234
2235 velocity_set_power_state(vptr, PCI_D0);
2236
2237 velocity_init_registers(vptr, VELOCITY_INIT_COLD);
2238
2239 ret = request_irq(dev->irq, velocity_intr, IRQF_SHARED,
2240 dev->name, dev);
2241 if (ret < 0) {
2242
2243 velocity_set_power_state(vptr, PCI_D3hot);
2244 velocity_free_rings(vptr);
2245 goto out;
2246 }
2247
2248 velocity_give_many_rx_descs(vptr);
2249
2250 mac_enable_int(vptr->mac_regs);
2251 netif_start_queue(dev);
2252 napi_enable(&vptr->napi);
2253 vptr->flags |= VELOCITY_FLAGS_OPENED;
2254out:
2255 return ret;
2256}
2257
2258
2259
2260
2261
2262
2263
2264
2265static void velocity_shutdown(struct velocity_info *vptr)
2266{
2267 struct mac_regs __iomem *regs = vptr->mac_regs;
2268 mac_disable_int(regs);
2269 writel(CR0_STOP, ®s->CR0Set);
2270 writew(0xFFFF, ®s->TDCSRClr);
2271 writeb(0xFF, ®s->RDCSRClr);
2272 safe_disable_mii_autopoll(regs);
2273 mac_clear_isr(regs);
2274}
2275
2276
2277
2278
2279
2280
2281
2282
2283
2284
2285static int velocity_change_mtu(struct net_device *dev, int new_mtu)
2286{
2287 struct velocity_info *vptr = netdev_priv(dev);
2288 int ret = 0;
2289
2290 if ((new_mtu < VELOCITY_MIN_MTU) || new_mtu > (VELOCITY_MAX_MTU)) {
2291 VELOCITY_PRT(MSG_LEVEL_ERR, KERN_NOTICE "%s: Invalid MTU.\n",
2292 vptr->netdev->name);
2293 ret = -EINVAL;
2294 goto out_0;
2295 }
2296
2297 if (!netif_running(dev)) {
2298 dev->mtu = new_mtu;
2299 goto out_0;
2300 }
2301
2302 if (dev->mtu != new_mtu) {
2303 struct velocity_info *tmp_vptr;
2304 unsigned long flags;
2305 struct rx_info rx;
2306 struct tx_info tx;
2307
2308 tmp_vptr = kzalloc(sizeof(*tmp_vptr), GFP_KERNEL);
2309 if (!tmp_vptr) {
2310 ret = -ENOMEM;
2311 goto out_0;
2312 }
2313
2314 tmp_vptr->netdev = dev;
2315 tmp_vptr->pdev = vptr->pdev;
2316 tmp_vptr->dev = vptr->dev;
2317 tmp_vptr->options = vptr->options;
2318 tmp_vptr->tx.numq = vptr->tx.numq;
2319
2320 ret = velocity_init_rings(tmp_vptr, new_mtu);
2321 if (ret < 0)
2322 goto out_free_tmp_vptr_1;
2323
2324 napi_disable(&vptr->napi);
2325
2326 spin_lock_irqsave(&vptr->lock, flags);
2327
2328 netif_stop_queue(dev);
2329 velocity_shutdown(vptr);
2330
2331 rx = vptr->rx;
2332 tx = vptr->tx;
2333
2334 vptr->rx = tmp_vptr->rx;
2335 vptr->tx = tmp_vptr->tx;
2336
2337 tmp_vptr->rx = rx;
2338 tmp_vptr->tx = tx;
2339
2340 dev->mtu = new_mtu;
2341
2342 velocity_init_registers(vptr, VELOCITY_INIT_COLD);
2343
2344 velocity_give_many_rx_descs(vptr);
2345
2346 napi_enable(&vptr->napi);
2347
2348 mac_enable_int(vptr->mac_regs);
2349 netif_start_queue(dev);
2350
2351 spin_unlock_irqrestore(&vptr->lock, flags);
2352
2353 velocity_free_rings(tmp_vptr);
2354
2355out_free_tmp_vptr_1:
2356 kfree(tmp_vptr);
2357 }
2358out_0:
2359 return ret;
2360}
2361
2362#ifdef CONFIG_NET_POLL_CONTROLLER
2363
2364
2365
2366
2367
2368
2369
2370
2371static void velocity_poll_controller(struct net_device *dev)
2372{
2373 disable_irq(dev->irq);
2374 velocity_intr(dev->irq, dev);
2375 enable_irq(dev->irq);
2376}
2377#endif
2378
2379
2380
2381
2382
2383
2384
2385
2386
2387
2388
2389static int velocity_mii_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2390{
2391 struct velocity_info *vptr = netdev_priv(dev);
2392 struct mac_regs __iomem *regs = vptr->mac_regs;
2393 unsigned long flags;
2394 struct mii_ioctl_data *miidata = if_mii(ifr);
2395 int err;
2396
2397 switch (cmd) {
2398 case SIOCGMIIPHY:
2399 miidata->phy_id = readb(®s->MIIADR) & 0x1f;
2400 break;
2401 case SIOCGMIIREG:
2402 if (velocity_mii_read(vptr->mac_regs, miidata->reg_num & 0x1f, &(miidata->val_out)) < 0)
2403 return -ETIMEDOUT;
2404 break;
2405 case SIOCSMIIREG:
2406 spin_lock_irqsave(&vptr->lock, flags);
2407 err = velocity_mii_write(vptr->mac_regs, miidata->reg_num & 0x1f, miidata->val_in);
2408 spin_unlock_irqrestore(&vptr->lock, flags);
2409 check_connection_type(vptr->mac_regs);
2410 if (err)
2411 return err;
2412 break;
2413 default:
2414 return -EOPNOTSUPP;
2415 }
2416 return 0;
2417}
2418
2419
2420
2421
2422
2423
2424
2425
2426
2427
2428static int velocity_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2429{
2430 struct velocity_info *vptr = netdev_priv(dev);
2431 int ret;
2432
2433
2434
2435
2436 if (!netif_running(dev))
2437 velocity_set_power_state(vptr, PCI_D0);
2438
2439 switch (cmd) {
2440 case SIOCGMIIPHY:
2441 case SIOCGMIIREG:
2442 case SIOCSMIIREG:
2443 ret = velocity_mii_ioctl(dev, rq, cmd);
2444 break;
2445
2446 default:
2447 ret = -EOPNOTSUPP;
2448 }
2449 if (!netif_running(dev))
2450 velocity_set_power_state(vptr, PCI_D3hot);
2451
2452
2453 return ret;
2454}
2455
2456
2457
2458
2459
2460
2461
2462
2463
2464
2465
2466static struct net_device_stats *velocity_get_stats(struct net_device *dev)
2467{
2468 struct velocity_info *vptr = netdev_priv(dev);
2469
2470
2471 if (!netif_running(dev))
2472 return &dev->stats;
2473
2474 spin_lock_irq(&vptr->lock);
2475 velocity_update_hw_mibs(vptr);
2476 spin_unlock_irq(&vptr->lock);
2477
2478 dev->stats.rx_packets = vptr->mib_counter[HW_MIB_ifRxAllPkts];
2479 dev->stats.rx_errors = vptr->mib_counter[HW_MIB_ifRxErrorPkts];
2480 dev->stats.rx_length_errors = vptr->mib_counter[HW_MIB_ifInRangeLengthErrors];
2481
2482
2483 dev->stats.collisions = vptr->mib_counter[HW_MIB_ifTxEtherCollisions];
2484
2485
2486
2487 dev->stats.rx_crc_errors = vptr->mib_counter[HW_MIB_ifRxPktCRCE];
2488
2489
2490
2491
2492
2493
2494
2495 return &dev->stats;
2496}
2497
2498
2499
2500
2501
2502
2503
2504
2505static int velocity_close(struct net_device *dev)
2506{
2507 struct velocity_info *vptr = netdev_priv(dev);
2508
2509 napi_disable(&vptr->napi);
2510 netif_stop_queue(dev);
2511 velocity_shutdown(vptr);
2512
2513 if (vptr->flags & VELOCITY_FLAGS_WOL_ENABLED)
2514 velocity_get_ip(vptr);
2515
2516 free_irq(dev->irq, dev);
2517
2518 velocity_free_rings(vptr);
2519
2520 vptr->flags &= (~VELOCITY_FLAGS_OPENED);
2521 return 0;
2522}
2523
2524
2525
2526
2527
2528
2529
2530
2531
2532static netdev_tx_t velocity_xmit(struct sk_buff *skb,
2533 struct net_device *dev)
2534{
2535 struct velocity_info *vptr = netdev_priv(dev);
2536 int qnum = 0;
2537 struct tx_desc *td_ptr;
2538 struct velocity_td_info *tdinfo;
2539 unsigned long flags;
2540 int pktlen;
2541 int index, prev;
2542 int i = 0;
2543
2544 if (skb_padto(skb, ETH_ZLEN))
2545 goto out;
2546
2547
2548
2549 if (skb_shinfo(skb)->nr_frags > 6 && __skb_linearize(skb)) {
2550 dev_kfree_skb_any(skb);
2551 return NETDEV_TX_OK;
2552 }
2553
2554 pktlen = skb_shinfo(skb)->nr_frags == 0 ?
2555 max_t(unsigned int, skb->len, ETH_ZLEN) :
2556 skb_headlen(skb);
2557
2558 spin_lock_irqsave(&vptr->lock, flags);
2559
2560 index = vptr->tx.curr[qnum];
2561 td_ptr = &(vptr->tx.rings[qnum][index]);
2562 tdinfo = &(vptr->tx.infos[qnum][index]);
2563
2564 td_ptr->tdesc1.TCR = TCR0_TIC;
2565 td_ptr->td_buf[0].size &= ~TD_QUEUE;
2566
2567
2568
2569
2570
2571 tdinfo->skb = skb;
2572 tdinfo->skb_dma[0] = dma_map_single(vptr->dev, skb->data, pktlen,
2573 DMA_TO_DEVICE);
2574 td_ptr->tdesc0.len = cpu_to_le16(pktlen);
2575 td_ptr->td_buf[0].pa_low = cpu_to_le32(tdinfo->skb_dma[0]);
2576 td_ptr->td_buf[0].pa_high = 0;
2577 td_ptr->td_buf[0].size = cpu_to_le16(pktlen);
2578
2579
2580 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2581 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2582
2583 tdinfo->skb_dma[i + 1] = skb_frag_dma_map(vptr->dev,
2584 frag, 0,
2585 skb_frag_size(frag),
2586 DMA_TO_DEVICE);
2587
2588 td_ptr->td_buf[i + 1].pa_low = cpu_to_le32(tdinfo->skb_dma[i + 1]);
2589 td_ptr->td_buf[i + 1].pa_high = 0;
2590 td_ptr->td_buf[i + 1].size = cpu_to_le16(skb_frag_size(frag));
2591 }
2592 tdinfo->nskb_dma = i + 1;
2593
2594 td_ptr->tdesc1.cmd = TCPLS_NORMAL + (tdinfo->nskb_dma + 1) * 16;
2595
2596 if (skb_vlan_tag_present(skb)) {
2597 td_ptr->tdesc1.vlan = cpu_to_le16(skb_vlan_tag_get(skb));
2598 td_ptr->tdesc1.TCR |= TCR0_VETAG;
2599 }
2600
2601
2602
2603
2604 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2605 const struct iphdr *ip = ip_hdr(skb);
2606 if (ip->protocol == IPPROTO_TCP)
2607 td_ptr->tdesc1.TCR |= TCR0_TCPCK;
2608 else if (ip->protocol == IPPROTO_UDP)
2609 td_ptr->tdesc1.TCR |= (TCR0_UDPCK);
2610 td_ptr->tdesc1.TCR |= TCR0_IPCK;
2611 }
2612
2613 prev = index - 1;
2614 if (prev < 0)
2615 prev = vptr->options.numtx - 1;
2616 td_ptr->tdesc0.len |= OWNED_BY_NIC;
2617 vptr->tx.used[qnum]++;
2618 vptr->tx.curr[qnum] = (index + 1) % vptr->options.numtx;
2619
2620 if (AVAIL_TD(vptr, qnum) < 1)
2621 netif_stop_queue(dev);
2622
2623 td_ptr = &(vptr->tx.rings[qnum][prev]);
2624 td_ptr->td_buf[0].size |= TD_QUEUE;
2625 mac_tx_queue_wake(vptr->mac_regs, qnum);
2626
2627 spin_unlock_irqrestore(&vptr->lock, flags);
2628out:
2629 return NETDEV_TX_OK;
2630}
2631
2632static const struct net_device_ops velocity_netdev_ops = {
2633 .ndo_open = velocity_open,
2634 .ndo_stop = velocity_close,
2635 .ndo_start_xmit = velocity_xmit,
2636 .ndo_get_stats = velocity_get_stats,
2637 .ndo_validate_addr = eth_validate_addr,
2638 .ndo_set_mac_address = eth_mac_addr,
2639 .ndo_set_rx_mode = velocity_set_multi,
2640 .ndo_change_mtu = velocity_change_mtu,
2641 .ndo_do_ioctl = velocity_ioctl,
2642 .ndo_vlan_rx_add_vid = velocity_vlan_rx_add_vid,
2643 .ndo_vlan_rx_kill_vid = velocity_vlan_rx_kill_vid,
2644#ifdef CONFIG_NET_POLL_CONTROLLER
2645 .ndo_poll_controller = velocity_poll_controller,
2646#endif
2647};
2648
2649
2650
2651
2652
2653
2654
2655
2656
2657
2658static void velocity_init_info(struct velocity_info *vptr,
2659 const struct velocity_info_tbl *info)
2660{
2661 vptr->chip_id = info->chip_id;
2662 vptr->tx.numq = info->txqueue;
2663 vptr->multicast_limit = MCAM_SIZE;
2664 spin_lock_init(&vptr->lock);
2665}
2666
2667
2668
2669
2670
2671
2672
2673
2674
2675static int velocity_get_pci_info(struct velocity_info *vptr)
2676{
2677 struct pci_dev *pdev = vptr->pdev;
2678
2679 pci_set_master(pdev);
2680
2681 vptr->ioaddr = pci_resource_start(pdev, 0);
2682 vptr->memaddr = pci_resource_start(pdev, 1);
2683
2684 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_IO)) {
2685 dev_err(&pdev->dev,
2686 "region #0 is not an I/O resource, aborting.\n");
2687 return -EINVAL;
2688 }
2689
2690 if ((pci_resource_flags(pdev, 1) & IORESOURCE_IO)) {
2691 dev_err(&pdev->dev,
2692 "region #1 is an I/O resource, aborting.\n");
2693 return -EINVAL;
2694 }
2695
2696 if (pci_resource_len(pdev, 1) < VELOCITY_IO_SIZE) {
2697 dev_err(&pdev->dev, "region #1 is too small.\n");
2698 return -EINVAL;
2699 }
2700
2701 return 0;
2702}
2703
2704
2705
2706
2707
2708
2709
2710
2711static int velocity_get_platform_info(struct velocity_info *vptr)
2712{
2713 struct resource res;
2714 int ret;
2715
2716 if (of_get_property(vptr->dev->of_node, "no-eeprom", NULL))
2717 vptr->no_eeprom = 1;
2718
2719 ret = of_address_to_resource(vptr->dev->of_node, 0, &res);
2720 if (ret) {
2721 dev_err(vptr->dev, "unable to find memory address\n");
2722 return ret;
2723 }
2724
2725 vptr->memaddr = res.start;
2726
2727 if (resource_size(&res) < VELOCITY_IO_SIZE) {
2728 dev_err(vptr->dev, "memory region is too small.\n");
2729 return -EINVAL;
2730 }
2731
2732 return 0;
2733}
2734
2735
2736
2737
2738
2739
2740
2741
2742static void velocity_print_info(struct velocity_info *vptr)
2743{
2744 struct net_device *dev = vptr->netdev;
2745
2746 printk(KERN_INFO "%s: %s\n", dev->name, get_chip_name(vptr->chip_id));
2747 printk(KERN_INFO "%s: Ethernet Address: %pM\n",
2748 dev->name, dev->dev_addr);
2749}
2750
2751static u32 velocity_get_link(struct net_device *dev)
2752{
2753 struct velocity_info *vptr = netdev_priv(dev);
2754 struct mac_regs __iomem *regs = vptr->mac_regs;
2755 return BYTE_REG_BITS_IS_ON(PHYSR0_LINKGD, ®s->PHYSR0) ? 1 : 0;
2756}
2757
2758
2759
2760
2761
2762
2763
2764
2765
2766
2767static int velocity_probe(struct device *dev, int irq,
2768 const struct velocity_info_tbl *info,
2769 enum velocity_bus_type bustype)
2770{
2771 static int first = 1;
2772 struct net_device *netdev;
2773 int i;
2774 const char *drv_string;
2775 struct velocity_info *vptr;
2776 struct mac_regs __iomem *regs;
2777 int ret = -ENOMEM;
2778
2779
2780
2781
2782 if (velocity_nics >= MAX_UNITS) {
2783 dev_notice(dev, "already found %d NICs.\n", velocity_nics);
2784 return -ENODEV;
2785 }
2786
2787 netdev = alloc_etherdev(sizeof(struct velocity_info));
2788 if (!netdev)
2789 goto out;
2790
2791
2792
2793 SET_NETDEV_DEV(netdev, dev);
2794 vptr = netdev_priv(netdev);
2795
2796 if (first) {
2797 printk(KERN_INFO "%s Ver. %s\n",
2798 VELOCITY_FULL_DRV_NAM, VELOCITY_VERSION);
2799 printk(KERN_INFO "Copyright (c) 2002, 2003 VIA Networking Technologies, Inc.\n");
2800 printk(KERN_INFO "Copyright (c) 2004 Red Hat Inc.\n");
2801 first = 0;
2802 }
2803
2804 netdev->irq = irq;
2805 vptr->netdev = netdev;
2806 vptr->dev = dev;
2807
2808 velocity_init_info(vptr, info);
2809
2810 if (bustype == BUS_PCI) {
2811 vptr->pdev = to_pci_dev(dev);
2812
2813 ret = velocity_get_pci_info(vptr);
2814 if (ret < 0)
2815 goto err_free_dev;
2816 } else {
2817 vptr->pdev = NULL;
2818 ret = velocity_get_platform_info(vptr);
2819 if (ret < 0)
2820 goto err_free_dev;
2821 }
2822
2823 regs = ioremap(vptr->memaddr, VELOCITY_IO_SIZE);
2824 if (regs == NULL) {
2825 ret = -EIO;
2826 goto err_free_dev;
2827 }
2828
2829 vptr->mac_regs = regs;
2830 vptr->rev_id = readb(®s->rev_id);
2831
2832 mac_wol_reset(regs);
2833
2834 for (i = 0; i < 6; i++)
2835 netdev->dev_addr[i] = readb(®s->PAR[i]);
2836
2837
2838 drv_string = dev_driver_string(dev);
2839
2840 velocity_get_options(&vptr->options, velocity_nics, drv_string);
2841
2842
2843
2844
2845
2846 vptr->options.flags &= info->flags;
2847
2848
2849
2850
2851
2852 vptr->flags = vptr->options.flags | (info->flags & 0xFF000000UL);
2853
2854 vptr->wol_opts = vptr->options.wol_opts;
2855 vptr->flags |= VELOCITY_FLAGS_WOL_ENABLED;
2856
2857 vptr->phy_id = MII_GET_PHY_ID(vptr->mac_regs);
2858
2859 netdev->netdev_ops = &velocity_netdev_ops;
2860 netdev->ethtool_ops = &velocity_ethtool_ops;
2861 netif_napi_add(netdev, &vptr->napi, velocity_poll,
2862 VELOCITY_NAPI_WEIGHT);
2863
2864 netdev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
2865 NETIF_F_HW_VLAN_CTAG_TX;
2866 netdev->features |= NETIF_F_HW_VLAN_CTAG_TX |
2867 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_VLAN_CTAG_RX |
2868 NETIF_F_IP_CSUM;
2869
2870 ret = register_netdev(netdev);
2871 if (ret < 0)
2872 goto err_iounmap;
2873
2874 if (!velocity_get_link(netdev)) {
2875 netif_carrier_off(netdev);
2876 vptr->mii_status |= VELOCITY_LINK_FAIL;
2877 }
2878
2879 velocity_print_info(vptr);
2880 dev_set_drvdata(vptr->dev, netdev);
2881
2882
2883
2884 velocity_set_power_state(vptr, PCI_D3hot);
2885 velocity_nics++;
2886out:
2887 return ret;
2888
2889err_iounmap:
2890 netif_napi_del(&vptr->napi);
2891 iounmap(regs);
2892err_free_dev:
2893 free_netdev(netdev);
2894 goto out;
2895}
2896
2897
2898
2899
2900
2901
2902
2903
2904
2905static int velocity_remove(struct device *dev)
2906{
2907 struct net_device *netdev = dev_get_drvdata(dev);
2908 struct velocity_info *vptr = netdev_priv(netdev);
2909
2910 unregister_netdev(netdev);
2911 netif_napi_del(&vptr->napi);
2912 iounmap(vptr->mac_regs);
2913 free_netdev(netdev);
2914 velocity_nics--;
2915
2916 return 0;
2917}
2918
2919static int velocity_pci_probe(struct pci_dev *pdev,
2920 const struct pci_device_id *ent)
2921{
2922 const struct velocity_info_tbl *info =
2923 &chip_info_table[ent->driver_data];
2924 int ret;
2925
2926 ret = pci_enable_device(pdev);
2927 if (ret < 0)
2928 return ret;
2929
2930 ret = pci_request_regions(pdev, VELOCITY_NAME);
2931 if (ret < 0) {
2932 dev_err(&pdev->dev, "No PCI resources.\n");
2933 goto fail1;
2934 }
2935
2936 ret = velocity_probe(&pdev->dev, pdev->irq, info, BUS_PCI);
2937 if (ret == 0)
2938 return 0;
2939
2940 pci_release_regions(pdev);
2941fail1:
2942 pci_disable_device(pdev);
2943 return ret;
2944}
2945
2946static void velocity_pci_remove(struct pci_dev *pdev)
2947{
2948 velocity_remove(&pdev->dev);
2949
2950 pci_release_regions(pdev);
2951 pci_disable_device(pdev);
2952}
2953
2954static int velocity_platform_probe(struct platform_device *pdev)
2955{
2956 const struct of_device_id *of_id;
2957 const struct velocity_info_tbl *info;
2958 int irq;
2959
2960 of_id = of_match_device(velocity_of_ids, &pdev->dev);
2961 if (!of_id)
2962 return -EINVAL;
2963 info = of_id->data;
2964
2965 irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
2966 if (!irq)
2967 return -EINVAL;
2968
2969 return velocity_probe(&pdev->dev, irq, info, BUS_PLATFORM);
2970}
2971
2972static int velocity_platform_remove(struct platform_device *pdev)
2973{
2974 velocity_remove(&pdev->dev);
2975
2976 return 0;
2977}
2978
2979#ifdef CONFIG_PM_SLEEP
2980
2981
2982
2983
2984
2985
2986
2987
2988static u16 wol_calc_crc(int size, u8 *pattern, u8 *mask_pattern)
2989{
2990 u16 crc = 0xFFFF;
2991 u8 mask;
2992 int i, j;
2993
2994 for (i = 0; i < size; i++) {
2995 mask = mask_pattern[i];
2996
2997
2998 if (mask == 0x00)
2999 continue;
3000
3001 for (j = 0; j < 8; j++) {
3002 if ((mask & 0x01) == 0) {
3003 mask >>= 1;
3004 continue;
3005 }
3006 mask >>= 1;
3007 crc = crc_ccitt(crc, &(pattern[i * 8 + j]), 1);
3008 }
3009 }
3010
3011 crc = ~crc;
3012 return bitrev32(crc) >> 16;
3013}
3014
3015
3016
3017
3018
3019
3020
3021
3022
3023
3024static int velocity_set_wol(struct velocity_info *vptr)
3025{
3026 struct mac_regs __iomem *regs = vptr->mac_regs;
3027 enum speed_opt spd_dpx = vptr->options.spd_dpx;
3028 static u8 buf[256];
3029 int i;
3030
3031 static u32 mask_pattern[2][4] = {
3032 {0x00203000, 0x000003C0, 0x00000000, 0x0000000},
3033 {0xfffff000, 0xffffffff, 0xffffffff, 0x000ffff}
3034 };
3035
3036 writew(0xFFFF, ®s->WOLCRClr);
3037 writeb(WOLCFG_SAB | WOLCFG_SAM, ®s->WOLCFGSet);
3038 writew(WOLCR_MAGIC_EN, ®s->WOLCRSet);
3039
3040
3041
3042
3043
3044
3045 if (vptr->wol_opts & VELOCITY_WOL_UCAST)
3046 writew(WOLCR_UNICAST_EN, ®s->WOLCRSet);
3047
3048 if (vptr->wol_opts & VELOCITY_WOL_ARP) {
3049 struct arp_packet *arp = (struct arp_packet *) buf;
3050 u16 crc;
3051 memset(buf, 0, sizeof(struct arp_packet) + 7);
3052
3053 for (i = 0; i < 4; i++)
3054 writel(mask_pattern[0][i], ®s->ByteMask[0][i]);
3055
3056 arp->type = htons(ETH_P_ARP);
3057 arp->ar_op = htons(1);
3058
3059 memcpy(arp->ar_tip, vptr->ip_addr, 4);
3060
3061 crc = wol_calc_crc((sizeof(struct arp_packet) + 7) / 8, buf,
3062 (u8 *) & mask_pattern[0][0]);
3063
3064 writew(crc, ®s->PatternCRC[0]);
3065 writew(WOLCR_ARP_EN, ®s->WOLCRSet);
3066 }
3067
3068 BYTE_REG_BITS_ON(PWCFG_WOLTYPE, ®s->PWCFGSet);
3069 BYTE_REG_BITS_ON(PWCFG_LEGACY_WOLEN, ®s->PWCFGSet);
3070
3071 writew(0x0FFF, ®s->WOLSRClr);
3072
3073 if (spd_dpx == SPD_DPX_1000_FULL)
3074 goto mac_done;
3075
3076 if (spd_dpx != SPD_DPX_AUTO)
3077 goto advertise_done;
3078
3079 if (vptr->mii_status & VELOCITY_AUTONEG_ENABLE) {
3080 if (PHYID_GET_PHY_ID(vptr->phy_id) == PHYID_CICADA_CS8201)
3081 MII_REG_BITS_ON(AUXCR_MDPPS, MII_NCONFIG, vptr->mac_regs);
3082
3083 MII_REG_BITS_OFF(ADVERTISE_1000FULL | ADVERTISE_1000HALF, MII_CTRL1000, vptr->mac_regs);
3084 }
3085
3086 if (vptr->mii_status & VELOCITY_SPEED_1000)
3087 MII_REG_BITS_ON(BMCR_ANRESTART, MII_BMCR, vptr->mac_regs);
3088
3089advertise_done:
3090 BYTE_REG_BITS_ON(CHIPGCR_FCMODE, ®s->CHIPGCR);
3091
3092 {
3093 u8 GCR;
3094 GCR = readb(®s->CHIPGCR);
3095 GCR = (GCR & ~CHIPGCR_FCGMII) | CHIPGCR_FCFDX;
3096 writeb(GCR, ®s->CHIPGCR);
3097 }
3098
3099mac_done:
3100 BYTE_REG_BITS_OFF(ISR_PWEI, ®s->ISR);
3101
3102 BYTE_REG_BITS_ON(STICKHW_SWPTAG, ®s->STICKHW);
3103
3104 BYTE_REG_BITS_ON((STICKHW_DS1 | STICKHW_DS0), ®s->STICKHW);
3105
3106 return 0;
3107}
3108
3109
3110
3111
3112
3113
3114
3115
3116
3117
3118
3119static void velocity_save_context(struct velocity_info *vptr, struct velocity_context *context)
3120{
3121 struct mac_regs __iomem *regs = vptr->mac_regs;
3122 u16 i;
3123 u8 __iomem *ptr = (u8 __iomem *)regs;
3124
3125 for (i = MAC_REG_PAR; i < MAC_REG_CR0_CLR; i += 4)
3126 *((u32 *) (context->mac_reg + i)) = readl(ptr + i);
3127
3128 for (i = MAC_REG_MAR; i < MAC_REG_TDCSR_CLR; i += 4)
3129 *((u32 *) (context->mac_reg + i)) = readl(ptr + i);
3130
3131 for (i = MAC_REG_RDBASE_LO; i < MAC_REG_FIFO_TEST0; i += 4)
3132 *((u32 *) (context->mac_reg + i)) = readl(ptr + i);
3133
3134}
3135
3136static int velocity_suspend(struct device *dev)
3137{
3138 struct net_device *netdev = dev_get_drvdata(dev);
3139 struct velocity_info *vptr = netdev_priv(netdev);
3140 unsigned long flags;
3141
3142 if (!netif_running(vptr->netdev))
3143 return 0;
3144
3145 netif_device_detach(vptr->netdev);
3146
3147 spin_lock_irqsave(&vptr->lock, flags);
3148 if (vptr->pdev)
3149 pci_save_state(vptr->pdev);
3150
3151 if (vptr->flags & VELOCITY_FLAGS_WOL_ENABLED) {
3152 velocity_get_ip(vptr);
3153 velocity_save_context(vptr, &vptr->context);
3154 velocity_shutdown(vptr);
3155 velocity_set_wol(vptr);
3156 if (vptr->pdev)
3157 pci_enable_wake(vptr->pdev, PCI_D3hot, 1);
3158 velocity_set_power_state(vptr, PCI_D3hot);
3159 } else {
3160 velocity_save_context(vptr, &vptr->context);
3161 velocity_shutdown(vptr);
3162 if (vptr->pdev)
3163 pci_disable_device(vptr->pdev);
3164 velocity_set_power_state(vptr, PCI_D3hot);
3165 }
3166
3167 spin_unlock_irqrestore(&vptr->lock, flags);
3168 return 0;
3169}
3170
3171
3172
3173
3174
3175
3176
3177
3178
3179static void velocity_restore_context(struct velocity_info *vptr, struct velocity_context *context)
3180{
3181 struct mac_regs __iomem *regs = vptr->mac_regs;
3182 int i;
3183 u8 __iomem *ptr = (u8 __iomem *)regs;
3184
3185 for (i = MAC_REG_PAR; i < MAC_REG_CR0_SET; i += 4)
3186 writel(*((u32 *) (context->mac_reg + i)), ptr + i);
3187
3188
3189 for (i = MAC_REG_CR1_SET; i < MAC_REG_CR0_CLR; i++) {
3190
3191 writeb(~(*((u8 *) (context->mac_reg + i))), ptr + i + 4);
3192
3193 writeb(*((u8 *) (context->mac_reg + i)), ptr + i);
3194 }
3195
3196 for (i = MAC_REG_MAR; i < MAC_REG_IMR; i += 4)
3197 writel(*((u32 *) (context->mac_reg + i)), ptr + i);
3198
3199 for (i = MAC_REG_RDBASE_LO; i < MAC_REG_FIFO_TEST0; i += 4)
3200 writel(*((u32 *) (context->mac_reg + i)), ptr + i);
3201
3202 for (i = MAC_REG_TDCSR_SET; i <= MAC_REG_RDCSR_SET; i++)
3203 writeb(*((u8 *) (context->mac_reg + i)), ptr + i);
3204}
3205
3206static int velocity_resume(struct device *dev)
3207{
3208 struct net_device *netdev = dev_get_drvdata(dev);
3209 struct velocity_info *vptr = netdev_priv(netdev);
3210 unsigned long flags;
3211 int i;
3212
3213 if (!netif_running(vptr->netdev))
3214 return 0;
3215
3216 velocity_set_power_state(vptr, PCI_D0);
3217
3218 if (vptr->pdev) {
3219 pci_enable_wake(vptr->pdev, PCI_D0, 0);
3220 pci_restore_state(vptr->pdev);
3221 }
3222
3223 mac_wol_reset(vptr->mac_regs);
3224
3225 spin_lock_irqsave(&vptr->lock, flags);
3226 velocity_restore_context(vptr, &vptr->context);
3227 velocity_init_registers(vptr, VELOCITY_INIT_WOL);
3228 mac_disable_int(vptr->mac_regs);
3229
3230 velocity_tx_srv(vptr);
3231
3232 for (i = 0; i < vptr->tx.numq; i++) {
3233 if (vptr->tx.used[i])
3234 mac_tx_queue_wake(vptr->mac_regs, i);
3235 }
3236
3237 mac_enable_int(vptr->mac_regs);
3238 spin_unlock_irqrestore(&vptr->lock, flags);
3239 netif_device_attach(vptr->netdev);
3240
3241 return 0;
3242}
3243#endif
3244
3245static SIMPLE_DEV_PM_OPS(velocity_pm_ops, velocity_suspend, velocity_resume);
3246
3247
3248
3249
3250
3251static struct pci_driver velocity_pci_driver = {
3252 .name = VELOCITY_NAME,
3253 .id_table = velocity_pci_id_table,
3254 .probe = velocity_pci_probe,
3255 .remove = velocity_pci_remove,
3256 .driver = {
3257 .pm = &velocity_pm_ops,
3258 },
3259};
3260
3261static struct platform_driver velocity_platform_driver = {
3262 .probe = velocity_platform_probe,
3263 .remove = velocity_platform_remove,
3264 .driver = {
3265 .name = "via-velocity",
3266 .of_match_table = velocity_of_ids,
3267 .pm = &velocity_pm_ops,
3268 },
3269};
3270
3271
3272
3273
3274
3275
3276
3277
3278static int velocity_ethtool_up(struct net_device *dev)
3279{
3280 struct velocity_info *vptr = netdev_priv(dev);
3281 if (!netif_running(dev))
3282 velocity_set_power_state(vptr, PCI_D0);
3283 return 0;
3284}
3285
3286
3287
3288
3289
3290
3291
3292
3293static void velocity_ethtool_down(struct net_device *dev)
3294{
3295 struct velocity_info *vptr = netdev_priv(dev);
3296 if (!netif_running(dev))
3297 velocity_set_power_state(vptr, PCI_D3hot);
3298}
3299
3300static int velocity_get_settings(struct net_device *dev,
3301 struct ethtool_cmd *cmd)
3302{
3303 struct velocity_info *vptr = netdev_priv(dev);
3304 struct mac_regs __iomem *regs = vptr->mac_regs;
3305 u32 status;
3306 status = check_connection_type(vptr->mac_regs);
3307
3308 cmd->supported = SUPPORTED_TP |
3309 SUPPORTED_Autoneg |
3310 SUPPORTED_10baseT_Half |
3311 SUPPORTED_10baseT_Full |
3312 SUPPORTED_100baseT_Half |
3313 SUPPORTED_100baseT_Full |
3314 SUPPORTED_1000baseT_Half |
3315 SUPPORTED_1000baseT_Full;
3316
3317 cmd->advertising = ADVERTISED_TP | ADVERTISED_Autoneg;
3318 if (vptr->options.spd_dpx == SPD_DPX_AUTO) {
3319 cmd->advertising |=
3320 ADVERTISED_10baseT_Half |
3321 ADVERTISED_10baseT_Full |
3322 ADVERTISED_100baseT_Half |
3323 ADVERTISED_100baseT_Full |
3324 ADVERTISED_1000baseT_Half |
3325 ADVERTISED_1000baseT_Full;
3326 } else {
3327 switch (vptr->options.spd_dpx) {
3328 case SPD_DPX_1000_FULL:
3329 cmd->advertising |= ADVERTISED_1000baseT_Full;
3330 break;
3331 case SPD_DPX_100_HALF:
3332 cmd->advertising |= ADVERTISED_100baseT_Half;
3333 break;
3334 case SPD_DPX_100_FULL:
3335 cmd->advertising |= ADVERTISED_100baseT_Full;
3336 break;
3337 case SPD_DPX_10_HALF:
3338 cmd->advertising |= ADVERTISED_10baseT_Half;
3339 break;
3340 case SPD_DPX_10_FULL:
3341 cmd->advertising |= ADVERTISED_10baseT_Full;
3342 break;
3343 default:
3344 break;
3345 }
3346 }
3347
3348 if (status & VELOCITY_SPEED_1000)
3349 ethtool_cmd_speed_set(cmd, SPEED_1000);
3350 else if (status & VELOCITY_SPEED_100)
3351 ethtool_cmd_speed_set(cmd, SPEED_100);
3352 else
3353 ethtool_cmd_speed_set(cmd, SPEED_10);
3354
3355 cmd->autoneg = (status & VELOCITY_AUTONEG_ENABLE) ? AUTONEG_ENABLE : AUTONEG_DISABLE;
3356 cmd->port = PORT_TP;
3357 cmd->transceiver = XCVR_INTERNAL;
3358 cmd->phy_address = readb(®s->MIIADR) & 0x1F;
3359
3360 if (status & VELOCITY_DUPLEX_FULL)
3361 cmd->duplex = DUPLEX_FULL;
3362 else
3363 cmd->duplex = DUPLEX_HALF;
3364
3365 return 0;
3366}
3367
3368static int velocity_set_settings(struct net_device *dev,
3369 struct ethtool_cmd *cmd)
3370{
3371 struct velocity_info *vptr = netdev_priv(dev);
3372 u32 speed = ethtool_cmd_speed(cmd);
3373 u32 curr_status;
3374 u32 new_status = 0;
3375 int ret = 0;
3376
3377 curr_status = check_connection_type(vptr->mac_regs);
3378 curr_status &= (~VELOCITY_LINK_FAIL);
3379
3380 new_status |= ((cmd->autoneg) ? VELOCITY_AUTONEG_ENABLE : 0);
3381 new_status |= ((speed == SPEED_1000) ? VELOCITY_SPEED_1000 : 0);
3382 new_status |= ((speed == SPEED_100) ? VELOCITY_SPEED_100 : 0);
3383 new_status |= ((speed == SPEED_10) ? VELOCITY_SPEED_10 : 0);
3384 new_status |= ((cmd->duplex == DUPLEX_FULL) ? VELOCITY_DUPLEX_FULL : 0);
3385
3386 if ((new_status & VELOCITY_AUTONEG_ENABLE) &&
3387 (new_status != (curr_status | VELOCITY_AUTONEG_ENABLE))) {
3388 ret = -EINVAL;
3389 } else {
3390 enum speed_opt spd_dpx;
3391
3392 if (new_status & VELOCITY_AUTONEG_ENABLE)
3393 spd_dpx = SPD_DPX_AUTO;
3394 else if ((new_status & VELOCITY_SPEED_1000) &&
3395 (new_status & VELOCITY_DUPLEX_FULL)) {
3396 spd_dpx = SPD_DPX_1000_FULL;
3397 } else if (new_status & VELOCITY_SPEED_100)
3398 spd_dpx = (new_status & VELOCITY_DUPLEX_FULL) ?
3399 SPD_DPX_100_FULL : SPD_DPX_100_HALF;
3400 else if (new_status & VELOCITY_SPEED_10)
3401 spd_dpx = (new_status & VELOCITY_DUPLEX_FULL) ?
3402 SPD_DPX_10_FULL : SPD_DPX_10_HALF;
3403 else
3404 return -EOPNOTSUPP;
3405
3406 vptr->options.spd_dpx = spd_dpx;
3407
3408 velocity_set_media_mode(vptr, new_status);
3409 }
3410
3411 return ret;
3412}
3413
3414static void velocity_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
3415{
3416 struct velocity_info *vptr = netdev_priv(dev);
3417
3418 strlcpy(info->driver, VELOCITY_NAME, sizeof(info->driver));
3419 strlcpy(info->version, VELOCITY_VERSION, sizeof(info->version));
3420 if (vptr->pdev)
3421 strlcpy(info->bus_info, pci_name(vptr->pdev),
3422 sizeof(info->bus_info));
3423 else
3424 strlcpy(info->bus_info, "platform", sizeof(info->bus_info));
3425}
3426
3427static void velocity_ethtool_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3428{
3429 struct velocity_info *vptr = netdev_priv(dev);
3430 wol->supported = WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_ARP;
3431 wol->wolopts |= WAKE_MAGIC;
3432
3433
3434
3435
3436 if (vptr->wol_opts & VELOCITY_WOL_UCAST)
3437 wol->wolopts |= WAKE_UCAST;
3438 if (vptr->wol_opts & VELOCITY_WOL_ARP)
3439 wol->wolopts |= WAKE_ARP;
3440 memcpy(&wol->sopass, vptr->wol_passwd, 6);
3441}
3442
3443static int velocity_ethtool_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3444{
3445 struct velocity_info *vptr = netdev_priv(dev);
3446
3447 if (!(wol->wolopts & (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_ARP)))
3448 return -EFAULT;
3449 vptr->wol_opts = VELOCITY_WOL_MAGIC;
3450
3451
3452
3453
3454
3455
3456
3457
3458 if (wol->wolopts & WAKE_MAGIC) {
3459 vptr->wol_opts |= VELOCITY_WOL_MAGIC;
3460 vptr->flags |= VELOCITY_FLAGS_WOL_ENABLED;
3461 }
3462 if (wol->wolopts & WAKE_UCAST) {
3463 vptr->wol_opts |= VELOCITY_WOL_UCAST;
3464 vptr->flags |= VELOCITY_FLAGS_WOL_ENABLED;
3465 }
3466 if (wol->wolopts & WAKE_ARP) {
3467 vptr->wol_opts |= VELOCITY_WOL_ARP;
3468 vptr->flags |= VELOCITY_FLAGS_WOL_ENABLED;
3469 }
3470 memcpy(vptr->wol_passwd, wol->sopass, 6);
3471 return 0;
3472}
3473
3474static u32 velocity_get_msglevel(struct net_device *dev)
3475{
3476 return msglevel;
3477}
3478
3479static void velocity_set_msglevel(struct net_device *dev, u32 value)
3480{
3481 msglevel = value;
3482}
3483
3484static int get_pending_timer_val(int val)
3485{
3486 int mult_bits = val >> 6;
3487 int mult = 1;
3488
3489 switch (mult_bits)
3490 {
3491 case 1:
3492 mult = 4; break;
3493 case 2:
3494 mult = 16; break;
3495 case 3:
3496 mult = 64; break;
3497 case 0:
3498 default:
3499 break;
3500 }
3501
3502 return (val & 0x3f) * mult;
3503}
3504
3505static void set_pending_timer_val(int *val, u32 us)
3506{
3507 u8 mult = 0;
3508 u8 shift = 0;
3509
3510 if (us >= 0x3f) {
3511 mult = 1;
3512 shift = 2;
3513 }
3514 if (us >= 0x3f * 4) {
3515 mult = 2;
3516 shift = 4;
3517 }
3518 if (us >= 0x3f * 16) {
3519 mult = 3;
3520 shift = 6;
3521 }
3522
3523 *val = (mult << 6) | ((us >> shift) & 0x3f);
3524}
3525
3526
3527static int velocity_get_coalesce(struct net_device *dev,
3528 struct ethtool_coalesce *ecmd)
3529{
3530 struct velocity_info *vptr = netdev_priv(dev);
3531
3532 ecmd->tx_max_coalesced_frames = vptr->options.tx_intsup;
3533 ecmd->rx_max_coalesced_frames = vptr->options.rx_intsup;
3534
3535 ecmd->rx_coalesce_usecs = get_pending_timer_val(vptr->options.rxqueue_timer);
3536 ecmd->tx_coalesce_usecs = get_pending_timer_val(vptr->options.txqueue_timer);
3537
3538 return 0;
3539}
3540
3541static int velocity_set_coalesce(struct net_device *dev,
3542 struct ethtool_coalesce *ecmd)
3543{
3544 struct velocity_info *vptr = netdev_priv(dev);
3545 int max_us = 0x3f * 64;
3546 unsigned long flags;
3547
3548
3549 if (ecmd->tx_coalesce_usecs > max_us)
3550 return -EINVAL;
3551 if (ecmd->rx_coalesce_usecs > max_us)
3552 return -EINVAL;
3553
3554 if (ecmd->tx_max_coalesced_frames > 0xff)
3555 return -EINVAL;
3556 if (ecmd->rx_max_coalesced_frames > 0xff)
3557 return -EINVAL;
3558
3559 vptr->options.rx_intsup = ecmd->rx_max_coalesced_frames;
3560 vptr->options.tx_intsup = ecmd->tx_max_coalesced_frames;
3561
3562 set_pending_timer_val(&vptr->options.rxqueue_timer,
3563 ecmd->rx_coalesce_usecs);
3564 set_pending_timer_val(&vptr->options.txqueue_timer,
3565 ecmd->tx_coalesce_usecs);
3566
3567
3568 spin_lock_irqsave(&vptr->lock, flags);
3569 mac_disable_int(vptr->mac_regs);
3570 setup_adaptive_interrupts(vptr);
3571 setup_queue_timers(vptr);
3572
3573 mac_write_int_mask(vptr->int_mask, vptr->mac_regs);
3574 mac_clear_isr(vptr->mac_regs);
3575 mac_enable_int(vptr->mac_regs);
3576 spin_unlock_irqrestore(&vptr->lock, flags);
3577
3578 return 0;
3579}
3580
3581static const char velocity_gstrings[][ETH_GSTRING_LEN] = {
3582 "rx_all",
3583 "rx_ok",
3584 "tx_ok",
3585 "rx_error",
3586 "rx_runt_ok",
3587 "rx_runt_err",
3588 "rx_64",
3589 "tx_64",
3590 "rx_65_to_127",
3591 "tx_65_to_127",
3592 "rx_128_to_255",
3593 "tx_128_to_255",
3594 "rx_256_to_511",
3595 "tx_256_to_511",
3596 "rx_512_to_1023",
3597 "tx_512_to_1023",
3598 "rx_1024_to_1518",
3599 "tx_1024_to_1518",
3600 "tx_ether_collisions",
3601 "rx_crc_errors",
3602 "rx_jumbo",
3603 "tx_jumbo",
3604 "rx_mac_control_frames",
3605 "tx_mac_control_frames",
3606 "rx_frame_alignement_errors",
3607 "rx_long_ok",
3608 "rx_long_err",
3609 "tx_sqe_errors",
3610 "rx_no_buf",
3611 "rx_symbol_errors",
3612 "in_range_length_errors",
3613 "late_collisions"
3614};
3615
3616static void velocity_get_strings(struct net_device *dev, u32 sset, u8 *data)
3617{
3618 switch (sset) {
3619 case ETH_SS_STATS:
3620 memcpy(data, *velocity_gstrings, sizeof(velocity_gstrings));
3621 break;
3622 }
3623}
3624
3625static int velocity_get_sset_count(struct net_device *dev, int sset)
3626{
3627 switch (sset) {
3628 case ETH_SS_STATS:
3629 return ARRAY_SIZE(velocity_gstrings);
3630 default:
3631 return -EOPNOTSUPP;
3632 }
3633}
3634
3635static void velocity_get_ethtool_stats(struct net_device *dev,
3636 struct ethtool_stats *stats, u64 *data)
3637{
3638 if (netif_running(dev)) {
3639 struct velocity_info *vptr = netdev_priv(dev);
3640 u32 *p = vptr->mib_counter;
3641 int i;
3642
3643 spin_lock_irq(&vptr->lock);
3644 velocity_update_hw_mibs(vptr);
3645 spin_unlock_irq(&vptr->lock);
3646
3647 for (i = 0; i < ARRAY_SIZE(velocity_gstrings); i++)
3648 *data++ = *p++;
3649 }
3650}
3651
3652static const struct ethtool_ops velocity_ethtool_ops = {
3653 .get_settings = velocity_get_settings,
3654 .set_settings = velocity_set_settings,
3655 .get_drvinfo = velocity_get_drvinfo,
3656 .get_wol = velocity_ethtool_get_wol,
3657 .set_wol = velocity_ethtool_set_wol,
3658 .get_msglevel = velocity_get_msglevel,
3659 .set_msglevel = velocity_set_msglevel,
3660 .get_link = velocity_get_link,
3661 .get_strings = velocity_get_strings,
3662 .get_sset_count = velocity_get_sset_count,
3663 .get_ethtool_stats = velocity_get_ethtool_stats,
3664 .get_coalesce = velocity_get_coalesce,
3665 .set_coalesce = velocity_set_coalesce,
3666 .begin = velocity_ethtool_up,
3667 .complete = velocity_ethtool_down
3668};
3669
3670#if defined(CONFIG_PM) && defined(CONFIG_INET)
3671static int velocity_netdev_event(struct notifier_block *nb, unsigned long notification, void *ptr)
3672{
3673 struct in_ifaddr *ifa = ptr;
3674 struct net_device *dev = ifa->ifa_dev->dev;
3675
3676 if (dev_net(dev) == &init_net &&
3677 dev->netdev_ops == &velocity_netdev_ops)
3678 velocity_get_ip(netdev_priv(dev));
3679
3680 return NOTIFY_DONE;
3681}
3682
3683static struct notifier_block velocity_inetaddr_notifier = {
3684 .notifier_call = velocity_netdev_event,
3685};
3686
3687static void velocity_register_notifier(void)
3688{
3689 register_inetaddr_notifier(&velocity_inetaddr_notifier);
3690}
3691
3692static void velocity_unregister_notifier(void)
3693{
3694 unregister_inetaddr_notifier(&velocity_inetaddr_notifier);
3695}
3696
3697#else
3698
3699#define velocity_register_notifier() do {} while (0)
3700#define velocity_unregister_notifier() do {} while (0)
3701
3702#endif
3703
3704
3705
3706
3707
3708
3709
3710
3711
3712static int __init velocity_init_module(void)
3713{
3714 int ret_pci, ret_platform;
3715
3716 velocity_register_notifier();
3717
3718 ret_pci = pci_register_driver(&velocity_pci_driver);
3719 ret_platform = platform_driver_register(&velocity_platform_driver);
3720
3721
3722 if ((ret_pci < 0) && (ret_platform < 0)) {
3723 velocity_unregister_notifier();
3724 return ret_pci;
3725 }
3726
3727 return 0;
3728}
3729
3730
3731
3732
3733
3734
3735
3736
3737
3738static void __exit velocity_cleanup_module(void)
3739{
3740 velocity_unregister_notifier();
3741
3742 pci_unregister_driver(&velocity_pci_driver);
3743 platform_driver_unregister(&velocity_platform_driver);
3744}
3745
3746module_init(velocity_init_module);
3747module_exit(velocity_cleanup_module);
3748