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17#ifndef _HAL_H_
18#define _HAL_H_
19
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31
32
33
34#define WCN36XX_HAL_VER_MAJOR 1
35#define WCN36XX_HAL_VER_MINOR 4
36#define WCN36XX_HAL_VER_VERSION 1
37#define WCN36XX_HAL_VER_REVISION 2
38
39
40#define WCN36XX_HAL_MAX_ENUM_SIZE 0x7FFFFFFF
41#define WCN36XX_HAL_MSG_TYPE_MAX_ENUM_SIZE 0x7FFF
42
43
44#define STACFG_MAX_TC 8
45
46
47#define WCN36XX_HAL_MAX_AC 4
48
49#define WCN36XX_HAL_IPV4_ADDR_LEN 4
50
51#define WALN_HAL_STA_INVALID_IDX 0xFF
52#define WCN36XX_HAL_BSS_INVALID_IDX 0xFF
53
54
55#define BEACON_TEMPLATE_SIZE 0x180
56
57
58#define PARAM_BCN_INTERVAL_CHANGED (1 << 0)
59#define PARAM_SHORT_PREAMBLE_CHANGED (1 << 1)
60#define PARAM_SHORT_SLOT_TIME_CHANGED (1 << 2)
61#define PARAM_llACOEXIST_CHANGED (1 << 3)
62#define PARAM_llBCOEXIST_CHANGED (1 << 4)
63#define PARAM_llGCOEXIST_CHANGED (1 << 5)
64#define PARAM_HT20MHZCOEXIST_CHANGED (1<<6)
65#define PARAM_NON_GF_DEVICES_PRESENT_CHANGED (1<<7)
66#define PARAM_RIFS_MODE_CHANGED (1<<8)
67#define PARAM_LSIG_TXOP_FULL_SUPPORT_CHANGED (1<<9)
68#define PARAM_OBSS_MODE_CHANGED (1<<10)
69#define PARAM_BEACON_UPDATE_MASK \
70 (PARAM_BCN_INTERVAL_CHANGED | \
71 PARAM_SHORT_PREAMBLE_CHANGED | \
72 PARAM_SHORT_SLOT_TIME_CHANGED | \
73 PARAM_llACOEXIST_CHANGED | \
74 PARAM_llBCOEXIST_CHANGED | \
75 PARAM_llGCOEXIST_CHANGED | \
76 PARAM_HT20MHZCOEXIST_CHANGED | \
77 PARAM_NON_GF_DEVICES_PRESENT_CHANGED | \
78 PARAM_RIFS_MODE_CHANGED | \
79 PARAM_LSIG_TXOP_FULL_SUPPORT_CHANGED | \
80 PARAM_OBSS_MODE_CHANGED)
81
82
83#define DUMPCMD_RSP_BUFFER 100
84
85
86#define WCN36XX_HAL_VERSION_LENGTH 64
87
88
89enum wcn36xx_hal_host_msg_type {
90
91 WCN36XX_HAL_START_REQ = 0,
92 WCN36XX_HAL_START_RSP = 1,
93 WCN36XX_HAL_STOP_REQ = 2,
94 WCN36XX_HAL_STOP_RSP = 3,
95
96
97 WCN36XX_HAL_INIT_SCAN_REQ = 4,
98 WCN36XX_HAL_INIT_SCAN_RSP = 5,
99 WCN36XX_HAL_START_SCAN_REQ = 6,
100 WCN36XX_HAL_START_SCAN_RSP = 7,
101 WCN36XX_HAL_END_SCAN_REQ = 8,
102 WCN36XX_HAL_END_SCAN_RSP = 9,
103 WCN36XX_HAL_FINISH_SCAN_REQ = 10,
104 WCN36XX_HAL_FINISH_SCAN_RSP = 11,
105
106
107 WCN36XX_HAL_CONFIG_STA_REQ = 12,
108 WCN36XX_HAL_CONFIG_STA_RSP = 13,
109 WCN36XX_HAL_DELETE_STA_REQ = 14,
110 WCN36XX_HAL_DELETE_STA_RSP = 15,
111 WCN36XX_HAL_CONFIG_BSS_REQ = 16,
112 WCN36XX_HAL_CONFIG_BSS_RSP = 17,
113 WCN36XX_HAL_DELETE_BSS_REQ = 18,
114 WCN36XX_HAL_DELETE_BSS_RSP = 19,
115
116
117 WCN36XX_HAL_JOIN_REQ = 20,
118 WCN36XX_HAL_JOIN_RSP = 21,
119 WCN36XX_HAL_POST_ASSOC_REQ = 22,
120 WCN36XX_HAL_POST_ASSOC_RSP = 23,
121
122
123 WCN36XX_HAL_SET_BSSKEY_REQ = 24,
124 WCN36XX_HAL_SET_BSSKEY_RSP = 25,
125 WCN36XX_HAL_SET_STAKEY_REQ = 26,
126 WCN36XX_HAL_SET_STAKEY_RSP = 27,
127 WCN36XX_HAL_RMV_BSSKEY_REQ = 28,
128 WCN36XX_HAL_RMV_BSSKEY_RSP = 29,
129 WCN36XX_HAL_RMV_STAKEY_REQ = 30,
130 WCN36XX_HAL_RMV_STAKEY_RSP = 31,
131
132
133 WCN36XX_HAL_ADD_TS_REQ = 32,
134 WCN36XX_HAL_ADD_TS_RSP = 33,
135 WCN36XX_HAL_DEL_TS_REQ = 34,
136 WCN36XX_HAL_DEL_TS_RSP = 35,
137 WCN36XX_HAL_UPD_EDCA_PARAMS_REQ = 36,
138 WCN36XX_HAL_UPD_EDCA_PARAMS_RSP = 37,
139 WCN36XX_HAL_ADD_BA_REQ = 38,
140 WCN36XX_HAL_ADD_BA_RSP = 39,
141 WCN36XX_HAL_DEL_BA_REQ = 40,
142 WCN36XX_HAL_DEL_BA_RSP = 41,
143
144 WCN36XX_HAL_CH_SWITCH_REQ = 42,
145 WCN36XX_HAL_CH_SWITCH_RSP = 43,
146 WCN36XX_HAL_SET_LINK_ST_REQ = 44,
147 WCN36XX_HAL_SET_LINK_ST_RSP = 45,
148 WCN36XX_HAL_GET_STATS_REQ = 46,
149 WCN36XX_HAL_GET_STATS_RSP = 47,
150 WCN36XX_HAL_UPDATE_CFG_REQ = 48,
151 WCN36XX_HAL_UPDATE_CFG_RSP = 49,
152
153 WCN36XX_HAL_MISSED_BEACON_IND = 50,
154 WCN36XX_HAL_UNKNOWN_ADDR2_FRAME_RX_IND = 51,
155 WCN36XX_HAL_MIC_FAILURE_IND = 52,
156 WCN36XX_HAL_FATAL_ERROR_IND = 53,
157 WCN36XX_HAL_SET_KEYDONE_MSG = 54,
158
159
160 WCN36XX_HAL_DOWNLOAD_NV_REQ = 55,
161 WCN36XX_HAL_DOWNLOAD_NV_RSP = 56,
162
163 WCN36XX_HAL_ADD_BA_SESSION_REQ = 57,
164 WCN36XX_HAL_ADD_BA_SESSION_RSP = 58,
165 WCN36XX_HAL_TRIGGER_BA_REQ = 59,
166 WCN36XX_HAL_TRIGGER_BA_RSP = 60,
167 WCN36XX_HAL_UPDATE_BEACON_REQ = 61,
168 WCN36XX_HAL_UPDATE_BEACON_RSP = 62,
169 WCN36XX_HAL_SEND_BEACON_REQ = 63,
170 WCN36XX_HAL_SEND_BEACON_RSP = 64,
171
172 WCN36XX_HAL_SET_BCASTKEY_REQ = 65,
173 WCN36XX_HAL_SET_BCASTKEY_RSP = 66,
174 WCN36XX_HAL_DELETE_STA_CONTEXT_IND = 67,
175 WCN36XX_HAL_UPDATE_PROBE_RSP_TEMPLATE_REQ = 68,
176 WCN36XX_HAL_UPDATE_PROBE_RSP_TEMPLATE_RSP = 69,
177
178
179 WCN36XX_HAL_PROCESS_PTT_REQ = 70,
180 WCN36XX_HAL_PROCESS_PTT_RSP = 71,
181
182
183 WCN36XX_HAL_SIGNAL_BTAMP_EVENT_REQ = 72,
184 WCN36XX_HAL_SIGNAL_BTAMP_EVENT_RSP = 73,
185 WCN36XX_HAL_TL_HAL_FLUSH_AC_REQ = 74,
186 WCN36XX_HAL_TL_HAL_FLUSH_AC_RSP = 75,
187
188 WCN36XX_HAL_ENTER_IMPS_REQ = 76,
189 WCN36XX_HAL_EXIT_IMPS_REQ = 77,
190 WCN36XX_HAL_ENTER_BMPS_REQ = 78,
191 WCN36XX_HAL_EXIT_BMPS_REQ = 79,
192 WCN36XX_HAL_ENTER_UAPSD_REQ = 80,
193 WCN36XX_HAL_EXIT_UAPSD_REQ = 81,
194 WCN36XX_HAL_UPDATE_UAPSD_PARAM_REQ = 82,
195 WCN36XX_HAL_CONFIGURE_RXP_FILTER_REQ = 83,
196 WCN36XX_HAL_ADD_BCN_FILTER_REQ = 84,
197 WCN36XX_HAL_REM_BCN_FILTER_REQ = 85,
198 WCN36XX_HAL_ADD_WOWL_BCAST_PTRN = 86,
199 WCN36XX_HAL_DEL_WOWL_BCAST_PTRN = 87,
200 WCN36XX_HAL_ENTER_WOWL_REQ = 88,
201 WCN36XX_HAL_EXIT_WOWL_REQ = 89,
202 WCN36XX_HAL_HOST_OFFLOAD_REQ = 90,
203 WCN36XX_HAL_SET_RSSI_THRESH_REQ = 91,
204 WCN36XX_HAL_GET_RSSI_REQ = 92,
205 WCN36XX_HAL_SET_UAPSD_AC_PARAMS_REQ = 93,
206 WCN36XX_HAL_CONFIGURE_APPS_CPU_WAKEUP_STATE_REQ = 94,
207
208 WCN36XX_HAL_ENTER_IMPS_RSP = 95,
209 WCN36XX_HAL_EXIT_IMPS_RSP = 96,
210 WCN36XX_HAL_ENTER_BMPS_RSP = 97,
211 WCN36XX_HAL_EXIT_BMPS_RSP = 98,
212 WCN36XX_HAL_ENTER_UAPSD_RSP = 99,
213 WCN36XX_HAL_EXIT_UAPSD_RSP = 100,
214 WCN36XX_HAL_SET_UAPSD_AC_PARAMS_RSP = 101,
215 WCN36XX_HAL_UPDATE_UAPSD_PARAM_RSP = 102,
216 WCN36XX_HAL_CONFIGURE_RXP_FILTER_RSP = 103,
217 WCN36XX_HAL_ADD_BCN_FILTER_RSP = 104,
218 WCN36XX_HAL_REM_BCN_FILTER_RSP = 105,
219 WCN36XX_HAL_SET_RSSI_THRESH_RSP = 106,
220 WCN36XX_HAL_HOST_OFFLOAD_RSP = 107,
221 WCN36XX_HAL_ADD_WOWL_BCAST_PTRN_RSP = 108,
222 WCN36XX_HAL_DEL_WOWL_BCAST_PTRN_RSP = 109,
223 WCN36XX_HAL_ENTER_WOWL_RSP = 110,
224 WCN36XX_HAL_EXIT_WOWL_RSP = 111,
225 WCN36XX_HAL_RSSI_NOTIFICATION_IND = 112,
226 WCN36XX_HAL_GET_RSSI_RSP = 113,
227 WCN36XX_HAL_CONFIGURE_APPS_CPU_WAKEUP_STATE_RSP = 114,
228
229
230 WCN36XX_HAL_SET_MAX_TX_POWER_REQ = 115,
231 WCN36XX_HAL_SET_MAX_TX_POWER_RSP = 116,
232
233
234 WCN36XX_HAL_AGGR_ADD_TS_REQ = 117,
235 WCN36XX_HAL_AGGR_ADD_TS_RSP = 118,
236
237
238 WCN36XX_HAL_SET_P2P_GONOA_REQ = 119,
239 WCN36XX_HAL_SET_P2P_GONOA_RSP = 120,
240
241
242 WCN36XX_HAL_DUMP_COMMAND_REQ = 121,
243 WCN36XX_HAL_DUMP_COMMAND_RSP = 122,
244
245
246 WCN36XX_HAL_START_OEM_DATA_REQ = 123,
247 WCN36XX_HAL_START_OEM_DATA_RSP = 124,
248
249
250 WCN36XX_HAL_ADD_STA_SELF_REQ = 125,
251 WCN36XX_HAL_ADD_STA_SELF_RSP = 126,
252
253
254 WCN36XX_HAL_DEL_STA_SELF_REQ = 127,
255 WCN36XX_HAL_DEL_STA_SELF_RSP = 128,
256
257
258 WCN36XX_HAL_COEX_IND = 129,
259
260
261 WCN36XX_HAL_OTA_TX_COMPL_IND = 130,
262
263
264 WCN36XX_HAL_HOST_SUSPEND_IND = 131,
265 WCN36XX_HAL_HOST_RESUME_REQ = 132,
266 WCN36XX_HAL_HOST_RESUME_RSP = 133,
267
268 WCN36XX_HAL_SET_TX_POWER_REQ = 134,
269 WCN36XX_HAL_SET_TX_POWER_RSP = 135,
270 WCN36XX_HAL_GET_TX_POWER_REQ = 136,
271 WCN36XX_HAL_GET_TX_POWER_RSP = 137,
272
273 WCN36XX_HAL_P2P_NOA_ATTR_IND = 138,
274
275 WCN36XX_HAL_ENABLE_RADAR_DETECT_REQ = 139,
276 WCN36XX_HAL_ENABLE_RADAR_DETECT_RSP = 140,
277 WCN36XX_HAL_GET_TPC_REPORT_REQ = 141,
278 WCN36XX_HAL_GET_TPC_REPORT_RSP = 142,
279 WCN36XX_HAL_RADAR_DETECT_IND = 143,
280 WCN36XX_HAL_RADAR_DETECT_INTR_IND = 144,
281 WCN36XX_HAL_KEEP_ALIVE_REQ = 145,
282 WCN36XX_HAL_KEEP_ALIVE_RSP = 146,
283
284
285 WCN36XX_HAL_SET_PREF_NETWORK_REQ = 147,
286 WCN36XX_HAL_SET_PREF_NETWORK_RSP = 148,
287 WCN36XX_HAL_SET_RSSI_FILTER_REQ = 149,
288 WCN36XX_HAL_SET_RSSI_FILTER_RSP = 150,
289 WCN36XX_HAL_UPDATE_SCAN_PARAM_REQ = 151,
290 WCN36XX_HAL_UPDATE_SCAN_PARAM_RSP = 152,
291 WCN36XX_HAL_PREF_NETW_FOUND_IND = 153,
292
293 WCN36XX_HAL_SET_TX_PER_TRACKING_REQ = 154,
294 WCN36XX_HAL_SET_TX_PER_TRACKING_RSP = 155,
295 WCN36XX_HAL_TX_PER_HIT_IND = 156,
296
297 WCN36XX_HAL_8023_MULTICAST_LIST_REQ = 157,
298 WCN36XX_HAL_8023_MULTICAST_LIST_RSP = 158,
299
300 WCN36XX_HAL_SET_PACKET_FILTER_REQ = 159,
301 WCN36XX_HAL_SET_PACKET_FILTER_RSP = 160,
302 WCN36XX_HAL_PACKET_FILTER_MATCH_COUNT_REQ = 161,
303 WCN36XX_HAL_PACKET_FILTER_MATCH_COUNT_RSP = 162,
304 WCN36XX_HAL_CLEAR_PACKET_FILTER_REQ = 163,
305 WCN36XX_HAL_CLEAR_PACKET_FILTER_RSP = 164,
306
307
308
309
310
311 WCN36XX_HAL_INIT_SCAN_CON_REQ = 165,
312
313 WCN36XX_HAL_SET_POWER_PARAMS_REQ = 166,
314 WCN36XX_HAL_SET_POWER_PARAMS_RSP = 167,
315
316 WCN36XX_HAL_TSM_STATS_REQ = 168,
317 WCN36XX_HAL_TSM_STATS_RSP = 169,
318
319
320 WCN36XX_HAL_WAKE_REASON_IND = 170,
321
322
323 WCN36XX_HAL_GTK_OFFLOAD_REQ = 171,
324 WCN36XX_HAL_GTK_OFFLOAD_RSP = 172,
325 WCN36XX_HAL_GTK_OFFLOAD_GETINFO_REQ = 173,
326 WCN36XX_HAL_GTK_OFFLOAD_GETINFO_RSP = 174,
327
328 WCN36XX_HAL_FEATURE_CAPS_EXCHANGE_REQ = 175,
329 WCN36XX_HAL_FEATURE_CAPS_EXCHANGE_RSP = 176,
330 WCN36XX_HAL_EXCLUDE_UNENCRYPTED_IND = 177,
331
332 WCN36XX_HAL_SET_THERMAL_MITIGATION_REQ = 178,
333 WCN36XX_HAL_SET_THERMAL_MITIGATION_RSP = 179,
334
335 WCN36XX_HAL_UPDATE_VHT_OP_MODE_REQ = 182,
336 WCN36XX_HAL_UPDATE_VHT_OP_MODE_RSP = 183,
337
338 WCN36XX_HAL_P2P_NOA_START_IND = 184,
339
340 WCN36XX_HAL_GET_ROAM_RSSI_REQ = 185,
341 WCN36XX_HAL_GET_ROAM_RSSI_RSP = 186,
342
343 WCN36XX_HAL_CLASS_B_STATS_IND = 187,
344 WCN36XX_HAL_DEL_BA_IND = 188,
345 WCN36XX_HAL_DHCP_START_IND = 189,
346 WCN36XX_HAL_DHCP_STOP_IND = 190,
347
348 WCN36XX_HAL_MSG_MAX = WCN36XX_HAL_MSG_TYPE_MAX_ENUM_SIZE
349};
350
351
352enum wcn36xx_hal_host_msg_version {
353 WCN36XX_HAL_MSG_VERSION0 = 0,
354 WCN36XX_HAL_MSG_VERSION1 = 1,
355
356 WCN36XX_HAL_MSG_WCNSS_CTRL_VERSION = 0x7FFF,
357 WCN36XX_HAL_MSG_VERSION_MAX_FIELD = WCN36XX_HAL_MSG_WCNSS_CTRL_VERSION
358};
359
360enum driver_type {
361 DRIVER_TYPE_PRODUCTION = 0,
362 DRIVER_TYPE_MFG = 1,
363 DRIVER_TYPE_DVT = 2,
364 DRIVER_TYPE_MAX = WCN36XX_HAL_MAX_ENUM_SIZE
365};
366
367enum wcn36xx_hal_stop_type {
368 HAL_STOP_TYPE_SYS_RESET,
369 HAL_STOP_TYPE_SYS_DEEP_SLEEP,
370 HAL_STOP_TYPE_RF_KILL,
371 HAL_STOP_TYPE_MAX = WCN36XX_HAL_MAX_ENUM_SIZE
372};
373
374enum wcn36xx_hal_sys_mode {
375 HAL_SYS_MODE_NORMAL,
376 HAL_SYS_MODE_LEARN,
377 HAL_SYS_MODE_SCAN,
378 HAL_SYS_MODE_PROMISC,
379 HAL_SYS_MODE_SUSPEND_LINK,
380 HAL_SYS_MODE_ROAM_SCAN,
381 HAL_SYS_MODE_ROAM_SUSPEND_LINK,
382 HAL_SYS_MODE_MAX = WCN36XX_HAL_MAX_ENUM_SIZE
383};
384
385enum phy_chan_bond_state {
386
387 PHY_SINGLE_CHANNEL_CENTERED = 0,
388
389
390 PHY_DOUBLE_CHANNEL_LOW_PRIMARY = 1,
391
392
393 PHY_DOUBLE_CHANNEL_CENTERED = 2,
394
395
396 PHY_DOUBLE_CHANNEL_HIGH_PRIMARY = 3,
397
398
399 PHY_QUADRUPLE_CHANNEL_20MHZ_LOW_40MHZ_CENTERED = 4,
400
401
402 PHY_QUADRUPLE_CHANNEL_20MHZ_CENTERED_40MHZ_CENTERED = 5,
403
404
405 PHY_QUADRUPLE_CHANNEL_20MHZ_HIGH_40MHZ_CENTERED = 6,
406
407
408 PHY_QUADRUPLE_CHANNEL_20MHZ_LOW_40MHZ_LOW = 7,
409
410
411 PHY_QUADRUPLE_CHANNEL_20MHZ_HIGH_40MHZ_LOW = 8,
412
413
414 PHY_QUADRUPLE_CHANNEL_20MHZ_LOW_40MHZ_HIGH = 9,
415
416
417 PHY_QUADRUPLE_CHANNEL_20MHZ_HIGH_40MHZ_HIGH = 10,
418
419 PHY_CHANNEL_BONDING_STATE_MAX = WCN36XX_HAL_MAX_ENUM_SIZE
420};
421
422
423enum wcn36xx_hal_ht_mimo_state {
424
425 WCN36XX_HAL_HT_MIMO_PS_STATIC = 0,
426
427
428 WCN36XX_HAL_HT_MIMO_PS_DYNAMIC = 1,
429
430
431 WCN36XX_HAL_HT_MIMO_PS_NA = 2,
432
433
434 WCN36XX_HAL_HT_MIMO_PS_NO_LIMIT = 3,
435
436 WCN36XX_HAL_HT_MIMO_PS_MAX = WCN36XX_HAL_MAX_ENUM_SIZE
437};
438
439
440enum sta_rate_mode {
441 STA_TAURUS = 0,
442 STA_TITAN,
443 STA_POLARIS,
444 STA_11b,
445 STA_11bg,
446 STA_11a,
447 STA_11n,
448 STA_11ac,
449 STA_INVALID_RATE_MODE = WCN36XX_HAL_MAX_ENUM_SIZE
450};
451
452
453#define WCN36XX_HAL_NUM_DSSS_RATES 4
454
455
456#define WCN36XX_HAL_NUM_OFDM_RATES 8
457
458
459#define WCN36XX_HAL_NUM_POLARIS_RATES 3
460
461#define WCN36XX_HAL_MAC_MAX_SUPPORTED_MCS_SET 16
462
463enum wcn36xx_hal_bss_type {
464 WCN36XX_HAL_INFRASTRUCTURE_MODE,
465
466
467 WCN36XX_HAL_INFRA_AP_MODE,
468
469 WCN36XX_HAL_IBSS_MODE,
470
471
472 WCN36XX_HAL_BTAMP_STA_MODE,
473
474
475 WCN36XX_HAL_BTAMP_AP_MODE,
476
477 WCN36XX_HAL_AUTO_MODE,
478
479 WCN36XX_HAL_DONOT_USE_BSS_TYPE = WCN36XX_HAL_MAX_ENUM_SIZE
480};
481
482enum wcn36xx_hal_nw_type {
483 WCN36XX_HAL_11A_NW_TYPE,
484 WCN36XX_HAL_11B_NW_TYPE,
485 WCN36XX_HAL_11G_NW_TYPE,
486 WCN36XX_HAL_11N_NW_TYPE,
487 WCN36XX_HAL_DONOT_USE_NW_TYPE = WCN36XX_HAL_MAX_ENUM_SIZE
488};
489
490#define WCN36XX_HAL_MAC_RATESET_EID_MAX 12
491
492enum wcn36xx_hal_ht_operating_mode {
493
494 WCN36XX_HAL_HT_OP_MODE_PURE,
495
496
497 WCN36XX_HAL_HT_OP_MODE_OVERLAP_LEGACY,
498
499
500 WCN36XX_HAL_HT_OP_MODE_NO_LEGACY_20MHZ_HT,
501
502
503 WCN36XX_HAL_HT_OP_MODE_MIXED,
504
505 WCN36XX_HAL_HT_OP_MODE_MAX = WCN36XX_HAL_MAX_ENUM_SIZE
506};
507
508
509enum ani_ed_type {
510 WCN36XX_HAL_ED_NONE,
511 WCN36XX_HAL_ED_WEP40,
512 WCN36XX_HAL_ED_WEP104,
513 WCN36XX_HAL_ED_TKIP,
514 WCN36XX_HAL_ED_CCMP,
515 WCN36XX_HAL_ED_WPI,
516 WCN36XX_HAL_ED_AES_128_CMAC,
517 WCN36XX_HAL_ED_NOT_IMPLEMENTED = WCN36XX_HAL_MAX_ENUM_SIZE
518};
519
520#define WLAN_MAX_KEY_RSC_LEN 16
521#define WLAN_WAPI_KEY_RSC_LEN 16
522
523
524#define WCN36XX_HAL_MAC_MAX_KEY_LENGTH 32
525#define WCN36XX_HAL_MAC_MAX_NUM_OF_DEFAULT_KEYS 4
526
527
528
529
530enum ani_key_direction {
531 WCN36XX_HAL_TX_ONLY,
532 WCN36XX_HAL_RX_ONLY,
533 WCN36XX_HAL_TX_RX,
534 WCN36XX_HAL_TX_DEFAULT,
535 WCN36XX_HAL_DONOT_USE_KEY_DIRECTION = WCN36XX_HAL_MAX_ENUM_SIZE
536};
537
538enum ani_wep_type {
539 WCN36XX_HAL_WEP_STATIC,
540 WCN36XX_HAL_WEP_DYNAMIC,
541 WCN36XX_HAL_WEP_MAX = WCN36XX_HAL_MAX_ENUM_SIZE
542};
543
544enum wcn36xx_hal_link_state {
545
546 WCN36XX_HAL_LINK_IDLE_STATE = 0,
547 WCN36XX_HAL_LINK_PREASSOC_STATE = 1,
548 WCN36XX_HAL_LINK_POSTASSOC_STATE = 2,
549 WCN36XX_HAL_LINK_AP_STATE = 3,
550 WCN36XX_HAL_LINK_IBSS_STATE = 4,
551
552
553 WCN36XX_HAL_LINK_BTAMP_PREASSOC_STATE = 5,
554 WCN36XX_HAL_LINK_BTAMP_POSTASSOC_STATE = 6,
555 WCN36XX_HAL_LINK_BTAMP_AP_STATE = 7,
556 WCN36XX_HAL_LINK_BTAMP_STA_STATE = 8,
557
558
559 WCN36XX_HAL_LINK_LEARN_STATE = 9,
560 WCN36XX_HAL_LINK_SCAN_STATE = 10,
561 WCN36XX_HAL_LINK_FINISH_SCAN_STATE = 11,
562 WCN36XX_HAL_LINK_INIT_CAL_STATE = 12,
563 WCN36XX_HAL_LINK_FINISH_CAL_STATE = 13,
564 WCN36XX_HAL_LINK_LISTEN_STATE = 14,
565
566 WCN36XX_HAL_LINK_MAX = WCN36XX_HAL_MAX_ENUM_SIZE
567};
568
569enum wcn36xx_hal_stats_mask {
570 HAL_SUMMARY_STATS_INFO = 0x00000001,
571 HAL_GLOBAL_CLASS_A_STATS_INFO = 0x00000002,
572 HAL_GLOBAL_CLASS_B_STATS_INFO = 0x00000004,
573 HAL_GLOBAL_CLASS_C_STATS_INFO = 0x00000008,
574 HAL_GLOBAL_CLASS_D_STATS_INFO = 0x00000010,
575 HAL_PER_STA_STATS_INFO = 0x00000020
576};
577
578
579enum bt_amp_event_type {
580 BTAMP_EVENT_CONNECTION_START,
581 BTAMP_EVENT_CONNECTION_STOP,
582 BTAMP_EVENT_CONNECTION_TERMINATED,
583
584
585 BTAMP_EVENT_TYPE_MAX = WCN36XX_HAL_MAX_ENUM_SIZE,
586};
587
588
589enum pe_stats_mask {
590 PE_SUMMARY_STATS_INFO = 0x00000001,
591 PE_GLOBAL_CLASS_A_STATS_INFO = 0x00000002,
592 PE_GLOBAL_CLASS_B_STATS_INFO = 0x00000004,
593 PE_GLOBAL_CLASS_C_STATS_INFO = 0x00000008,
594 PE_GLOBAL_CLASS_D_STATS_INFO = 0x00000010,
595 PE_PER_STA_STATS_INFO = 0x00000020,
596
597
598 PE_STATS_TYPE_MAX = WCN36XX_HAL_MAX_ENUM_SIZE
599};
600
601
602
603
604#define WCN36XX_HAL_CFG_STA_ID 0
605#define WCN36XX_HAL_CFG_CURRENT_TX_ANTENNA 1
606#define WCN36XX_HAL_CFG_CURRENT_RX_ANTENNA 2
607#define WCN36XX_HAL_CFG_LOW_GAIN_OVERRIDE 3
608#define WCN36XX_HAL_CFG_POWER_STATE_PER_CHAIN 4
609#define WCN36XX_HAL_CFG_CAL_PERIOD 5
610#define WCN36XX_HAL_CFG_CAL_CONTROL 6
611#define WCN36XX_HAL_CFG_PROXIMITY 7
612#define WCN36XX_HAL_CFG_NETWORK_DENSITY 8
613#define WCN36XX_HAL_CFG_MAX_MEDIUM_TIME 9
614#define WCN36XX_HAL_CFG_MAX_MPDUS_IN_AMPDU 10
615#define WCN36XX_HAL_CFG_RTS_THRESHOLD 11
616#define WCN36XX_HAL_CFG_SHORT_RETRY_LIMIT 12
617#define WCN36XX_HAL_CFG_LONG_RETRY_LIMIT 13
618#define WCN36XX_HAL_CFG_FRAGMENTATION_THRESHOLD 14
619#define WCN36XX_HAL_CFG_DYNAMIC_THRESHOLD_ZERO 15
620#define WCN36XX_HAL_CFG_DYNAMIC_THRESHOLD_ONE 16
621#define WCN36XX_HAL_CFG_DYNAMIC_THRESHOLD_TWO 17
622#define WCN36XX_HAL_CFG_FIXED_RATE 18
623#define WCN36XX_HAL_CFG_RETRYRATE_POLICY 19
624#define WCN36XX_HAL_CFG_RETRYRATE_SECONDARY 20
625#define WCN36XX_HAL_CFG_RETRYRATE_TERTIARY 21
626#define WCN36XX_HAL_CFG_FORCE_POLICY_PROTECTION 22
627#define WCN36XX_HAL_CFG_FIXED_RATE_MULTICAST_24GHZ 23
628#define WCN36XX_HAL_CFG_FIXED_RATE_MULTICAST_5GHZ 24
629#define WCN36XX_HAL_CFG_DEFAULT_RATE_INDEX_24GHZ 25
630#define WCN36XX_HAL_CFG_DEFAULT_RATE_INDEX_5GHZ 26
631#define WCN36XX_HAL_CFG_MAX_BA_SESSIONS 27
632#define WCN36XX_HAL_CFG_PS_DATA_INACTIVITY_TIMEOUT 28
633#define WCN36XX_HAL_CFG_PS_ENABLE_BCN_FILTER 29
634#define WCN36XX_HAL_CFG_PS_ENABLE_RSSI_MONITOR 30
635#define WCN36XX_HAL_CFG_NUM_BEACON_PER_RSSI_AVERAGE 31
636#define WCN36XX_HAL_CFG_STATS_PERIOD 32
637#define WCN36XX_HAL_CFG_CFP_MAX_DURATION 33
638#define WCN36XX_HAL_CFG_FRAME_TRANS_ENABLED 34
639#define WCN36XX_HAL_CFG_DTIM_PERIOD 35
640#define WCN36XX_HAL_CFG_EDCA_WMM_ACBK 36
641#define WCN36XX_HAL_CFG_EDCA_WMM_ACBE 37
642#define WCN36XX_HAL_CFG_EDCA_WMM_ACVO 38
643#define WCN36XX_HAL_CFG_EDCA_WMM_ACVI 39
644#define WCN36XX_HAL_CFG_BA_THRESHOLD_HIGH 40
645#define WCN36XX_HAL_CFG_MAX_BA_BUFFERS 41
646#define WCN36XX_HAL_CFG_RPE_POLLING_THRESHOLD 42
647#define WCN36XX_HAL_CFG_RPE_AGING_THRESHOLD_FOR_AC0_REG 43
648#define WCN36XX_HAL_CFG_RPE_AGING_THRESHOLD_FOR_AC1_REG 44
649#define WCN36XX_HAL_CFG_RPE_AGING_THRESHOLD_FOR_AC2_REG 45
650#define WCN36XX_HAL_CFG_RPE_AGING_THRESHOLD_FOR_AC3_REG 46
651#define WCN36XX_HAL_CFG_NO_OF_ONCHIP_REORDER_SESSIONS 47
652#define WCN36XX_HAL_CFG_PS_LISTEN_INTERVAL 48
653#define WCN36XX_HAL_CFG_PS_HEART_BEAT_THRESHOLD 49
654#define WCN36XX_HAL_CFG_PS_NTH_BEACON_FILTER 50
655#define WCN36XX_HAL_CFG_PS_MAX_PS_POLL 51
656#define WCN36XX_HAL_CFG_PS_MIN_RSSI_THRESHOLD 52
657#define WCN36XX_HAL_CFG_PS_RSSI_FILTER_PERIOD 53
658#define WCN36XX_HAL_CFG_PS_BROADCAST_FRAME_FILTER_ENABLE 54
659#define WCN36XX_HAL_CFG_PS_IGNORE_DTIM 55
660#define WCN36XX_HAL_CFG_PS_ENABLE_BCN_EARLY_TERM 56
661#define WCN36XX_HAL_CFG_DYNAMIC_PS_POLL_VALUE 57
662#define WCN36XX_HAL_CFG_PS_NULLDATA_AP_RESP_TIMEOUT 58
663#define WCN36XX_HAL_CFG_TELE_BCN_WAKEUP_EN 59
664#define WCN36XX_HAL_CFG_TELE_BCN_TRANS_LI 60
665#define WCN36XX_HAL_CFG_TELE_BCN_TRANS_LI_IDLE_BCNS 61
666#define WCN36XX_HAL_CFG_TELE_BCN_MAX_LI 62
667#define WCN36XX_HAL_CFG_TELE_BCN_MAX_LI_IDLE_BCNS 63
668#define WCN36XX_HAL_CFG_TX_PWR_CTRL_ENABLE 64
669#define WCN36XX_HAL_CFG_VALID_RADAR_CHANNEL_LIST 65
670#define WCN36XX_HAL_CFG_TX_POWER_24_20 66
671#define WCN36XX_HAL_CFG_TX_POWER_24_40 67
672#define WCN36XX_HAL_CFG_TX_POWER_50_20 68
673#define WCN36XX_HAL_CFG_TX_POWER_50_40 69
674#define WCN36XX_HAL_CFG_MCAST_BCAST_FILTER_SETTING 70
675#define WCN36XX_HAL_CFG_BCN_EARLY_TERM_WAKEUP_INTERVAL 71
676#define WCN36XX_HAL_CFG_MAX_TX_POWER_2_4 72
677#define WCN36XX_HAL_CFG_MAX_TX_POWER_5 73
678#define WCN36XX_HAL_CFG_INFRA_STA_KEEP_ALIVE_PERIOD 74
679#define WCN36XX_HAL_CFG_ENABLE_CLOSE_LOOP 75
680#define WCN36XX_HAL_CFG_BTC_EXECUTION_MODE 76
681#define WCN36XX_HAL_CFG_BTC_DHCP_BT_SLOTS_TO_BLOCK 77
682#define WCN36XX_HAL_CFG_BTC_A2DP_DHCP_BT_SUB_INTERVALS 78
683#define WCN36XX_HAL_CFG_PS_TX_INACTIVITY_TIMEOUT 79
684#define WCN36XX_HAL_CFG_WCNSS_API_VERSION 80
685#define WCN36XX_HAL_CFG_AP_KEEPALIVE_TIMEOUT 81
686#define WCN36XX_HAL_CFG_GO_KEEPALIVE_TIMEOUT 82
687#define WCN36XX_HAL_CFG_ENABLE_MC_ADDR_LIST 83
688#define WCN36XX_HAL_CFG_BTC_STATIC_LEN_INQ_BT 84
689#define WCN36XX_HAL_CFG_BTC_STATIC_LEN_PAGE_BT 85
690#define WCN36XX_HAL_CFG_BTC_STATIC_LEN_CONN_BT 86
691#define WCN36XX_HAL_CFG_BTC_STATIC_LEN_LE_BT 87
692#define WCN36XX_HAL_CFG_BTC_STATIC_LEN_INQ_WLAN 88
693#define WCN36XX_HAL_CFG_BTC_STATIC_LEN_PAGE_WLAN 89
694#define WCN36XX_HAL_CFG_BTC_STATIC_LEN_CONN_WLAN 90
695#define WCN36XX_HAL_CFG_BTC_STATIC_LEN_LE_WLAN 91
696#define WCN36XX_HAL_CFG_BTC_DYN_MAX_LEN_BT 92
697#define WCN36XX_HAL_CFG_BTC_DYN_MAX_LEN_WLAN 93
698#define WCN36XX_HAL_CFG_BTC_MAX_SCO_BLOCK_PERC 94
699#define WCN36XX_HAL_CFG_BTC_DHCP_PROT_ON_A2DP 95
700#define WCN36XX_HAL_CFG_BTC_DHCP_PROT_ON_SCO 96
701#define WCN36XX_HAL_CFG_ENABLE_UNICAST_FILTER 97
702#define WCN36XX_HAL_CFG_MAX_ASSOC_LIMIT 98
703#define WCN36XX_HAL_CFG_ENABLE_LPWR_IMG_TRANSITION 99
704#define WCN36XX_HAL_CFG_ENABLE_MCC_ADAPTIVE_SCHEDULER 100
705#define WCN36XX_HAL_CFG_ENABLE_DETECT_PS_SUPPORT 101
706#define WCN36XX_HAL_CFG_AP_LINK_MONITOR_TIMEOUT 102
707#define WCN36XX_HAL_CFG_BTC_DWELL_TIME_MULTIPLIER 103
708#define WCN36XX_HAL_CFG_ENABLE_TDLS_OXYGEN_MODE 104
709#define WCN36XX_HAL_CFG_MAX_PARAMS 105
710
711
712
713
714struct wcnss_wlan_version {
715 u8 revision;
716 u8 version;
717 u8 minor;
718 u8 major;
719} __packed;
720
721
722struct wcn36xx_hal_keys {
723 u8 id;
724
725
726 u8 unicast;
727
728 enum ani_key_direction direction;
729
730
731 u8 rsc[WLAN_MAX_KEY_RSC_LEN];
732
733
734 u8 pae_role;
735
736 u16 length;
737 u8 key[WCN36XX_HAL_MAC_MAX_KEY_LENGTH];
738} __packed;
739
740
741
742
743
744struct wcn36xx_hal_set_sta_key_params {
745
746 u16 sta_index;
747
748
749 enum ani_ed_type enc_type;
750
751
752 enum ani_wep_type wep_type;
753
754
755 u8 def_wep_idx;
756
757
758 struct wcn36xx_hal_keys key[WCN36XX_HAL_MAC_MAX_NUM_OF_DEFAULT_KEYS];
759
760
761
762
763
764 u8 single_tid_rc;
765
766} __packed;
767
768
769struct wcn36xx_hal_msg_header {
770 enum wcn36xx_hal_host_msg_type msg_type:16;
771 enum wcn36xx_hal_host_msg_version msg_version:16;
772 u32 len;
773} __packed;
774
775
776struct wcn36xx_hal_cfg {
777
778
779 u16 id;
780
781
782
783 u16 len;
784
785
786 u16 pad_bytes;
787
788
789 u16 reserve;
790
791
792
793} __packed;
794
795struct wcn36xx_hal_mac_start_parameters {
796
797 enum driver_type type;
798
799
800 u32 len;
801
802
803
804
805
806
807
808} __packed;
809
810struct wcn36xx_hal_mac_start_req_msg {
811
812 struct wcn36xx_hal_msg_header header;
813 struct wcn36xx_hal_mac_start_parameters params;
814} __packed;
815
816struct wcn36xx_hal_mac_start_rsp_params {
817
818 u16 status;
819
820
821 u8 stations;
822
823
824 u8 bssids;
825
826
827 struct wcnss_wlan_version version;
828
829
830 u8 crm_version[WCN36XX_HAL_VERSION_LENGTH];
831
832
833 u8 wlan_version[WCN36XX_HAL_VERSION_LENGTH];
834
835} __packed;
836
837struct wcn36xx_hal_mac_start_rsp_msg {
838 struct wcn36xx_hal_msg_header header;
839 struct wcn36xx_hal_mac_start_rsp_params start_rsp_params;
840} __packed;
841
842struct wcn36xx_hal_mac_stop_req_params {
843
844 enum wcn36xx_hal_stop_type reason;
845
846} __packed;
847
848struct wcn36xx_hal_mac_stop_req_msg {
849 struct wcn36xx_hal_msg_header header;
850 struct wcn36xx_hal_mac_stop_req_params stop_req_params;
851} __packed;
852
853struct wcn36xx_hal_mac_stop_rsp_msg {
854 struct wcn36xx_hal_msg_header header;
855
856
857 u32 status;
858} __packed;
859
860struct wcn36xx_hal_update_cfg_req_msg {
861
862
863
864
865 struct wcn36xx_hal_msg_header header;
866
867
868 u32 len;
869
870
871
872
873
874
875
876
877
878} __packed;
879
880struct wcn36xx_hal_update_cfg_rsp_msg {
881 struct wcn36xx_hal_msg_header header;
882
883
884 u32 status;
885
886} __packed;
887
888
889struct wcn36xx_hal_mac_frame_ctl {
890
891#ifndef ANI_LITTLE_BIT_ENDIAN
892
893 u8 subType:4;
894 u8 type:2;
895 u8 protVer:2;
896
897 u8 order:1;
898 u8 wep:1;
899 u8 moreData:1;
900 u8 powerMgmt:1;
901 u8 retry:1;
902 u8 moreFrag:1;
903 u8 fromDS:1;
904 u8 toDS:1;
905
906#else
907
908 u8 protVer:2;
909 u8 type:2;
910 u8 subType:4;
911
912 u8 toDS:1;
913 u8 fromDS:1;
914 u8 moreFrag:1;
915 u8 retry:1;
916 u8 powerMgmt:1;
917 u8 moreData:1;
918 u8 wep:1;
919 u8 order:1;
920
921#endif
922
923};
924
925
926struct wcn36xx_hal_mac_seq_ctl {
927 u8 fragNum:4;
928 u8 seqNumLo:4;
929 u8 seqNumHi:8;
930};
931
932
933struct wcn36xx_hal_mac_mgmt_hdr {
934 struct wcn36xx_hal_mac_frame_ctl fc;
935 u8 durationLo;
936 u8 durationHi;
937 u8 da[6];
938 u8 sa[6];
939 u8 bssId[6];
940 struct wcn36xx_hal_mac_seq_ctl seqControl;
941};
942
943
944#define WCN36XX_HAL_NUM_BSSID 2
945
946
947struct wcn36xx_hal_scan_entry {
948 u8 bss_index[WCN36XX_HAL_NUM_BSSID];
949 u8 active_bss_count;
950};
951
952struct wcn36xx_hal_init_scan_req_msg {
953 struct wcn36xx_hal_msg_header header;
954
955
956
957 enum wcn36xx_hal_sys_mode mode;
958
959
960 u8 bssid[ETH_ALEN];
961
962
963 u8 notify;
964
965
966
967 u8 frame_type;
968
969
970
971
972
973 u8 frame_len;
974
975
976
977 struct wcn36xx_hal_mac_mgmt_hdr mac_mgmt_hdr;
978
979
980 struct wcn36xx_hal_scan_entry scan_entry;
981};
982
983struct wcn36xx_hal_init_scan_con_req_msg {
984 struct wcn36xx_hal_msg_header header;
985
986
987
988 enum wcn36xx_hal_sys_mode mode;
989
990
991 u8 bssid[ETH_ALEN];
992
993
994 u8 notify;
995
996
997
998 u8 frame_type;
999
1000
1001
1002
1003
1004 u8 frame_length;
1005
1006
1007
1008 struct wcn36xx_hal_mac_mgmt_hdr mac_mgmt_hdr;
1009
1010
1011 struct wcn36xx_hal_scan_entry scan_entry;
1012
1013
1014 u8 use_noa;
1015
1016
1017 u16 scan_duration;
1018
1019};
1020
1021struct wcn36xx_hal_init_scan_rsp_msg {
1022 struct wcn36xx_hal_msg_header header;
1023
1024
1025 u32 status;
1026
1027} __packed;
1028
1029struct wcn36xx_hal_start_scan_req_msg {
1030 struct wcn36xx_hal_msg_header header;
1031
1032
1033 u8 scan_channel;
1034} __packed;
1035
1036struct wcn36xx_hal_start_rsp_msg {
1037 struct wcn36xx_hal_msg_header header;
1038
1039
1040 u32 status;
1041
1042 u32 start_tsf[2];
1043 u8 tx_mgmt_power;
1044
1045} __packed;
1046
1047struct wcn36xx_hal_end_scan_req_msg {
1048 struct wcn36xx_hal_msg_header header;
1049
1050
1051
1052
1053 u8 scan_channel;
1054} __packed;
1055
1056struct wcn36xx_hal_end_scan_rsp_msg {
1057 struct wcn36xx_hal_msg_header header;
1058
1059
1060 u32 status;
1061} __packed;
1062
1063struct wcn36xx_hal_finish_scan_req_msg {
1064 struct wcn36xx_hal_msg_header header;
1065
1066
1067
1068 enum wcn36xx_hal_sys_mode mode;
1069
1070
1071 u8 oper_channel;
1072
1073
1074
1075
1076 enum phy_chan_bond_state cb_state;
1077
1078
1079 u8 bssid[ETH_ALEN];
1080
1081
1082 u8 notify;
1083
1084
1085
1086 u8 frame_type;
1087
1088
1089
1090
1091
1092 u8 frame_length;
1093
1094
1095
1096 struct wcn36xx_hal_mac_mgmt_hdr mac_mgmt_hdr;
1097
1098
1099 struct wcn36xx_hal_scan_entry scan_entry;
1100
1101} __packed;
1102
1103struct wcn36xx_hal_finish_scan_rsp_msg {
1104 struct wcn36xx_hal_msg_header header;
1105
1106
1107 u32 status;
1108
1109} __packed;
1110
1111enum wcn36xx_hal_rate_index {
1112 HW_RATE_INDEX_1MBPS = 0x82,
1113 HW_RATE_INDEX_2MBPS = 0x84,
1114 HW_RATE_INDEX_5_5MBPS = 0x8B,
1115 HW_RATE_INDEX_6MBPS = 0x0C,
1116 HW_RATE_INDEX_9MBPS = 0x12,
1117 HW_RATE_INDEX_11MBPS = 0x96,
1118 HW_RATE_INDEX_12MBPS = 0x18,
1119 HW_RATE_INDEX_18MBPS = 0x24,
1120 HW_RATE_INDEX_24MBPS = 0x30,
1121 HW_RATE_INDEX_36MBPS = 0x48,
1122 HW_RATE_INDEX_48MBPS = 0x60,
1123 HW_RATE_INDEX_54MBPS = 0x6C
1124};
1125
1126struct wcn36xx_hal_supported_rates {
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146 enum sta_rate_mode op_rate_mode;
1147
1148
1149
1150 u16 dsss_rates[WCN36XX_HAL_NUM_DSSS_RATES];
1151 u16 ofdm_rates[WCN36XX_HAL_NUM_OFDM_RATES];
1152 u16 legacy_rates[WCN36XX_HAL_NUM_POLARIS_RATES];
1153 u16 reserved;
1154
1155
1156
1157
1158
1159
1160 u32 enhanced_rate_bitmap;
1161
1162
1163
1164
1165
1166 u8 supported_mcs_set[WCN36XX_HAL_MAC_MAX_SUPPORTED_MCS_SET];
1167
1168
1169
1170
1171
1172
1173
1174 u16 rx_highest_data_rate;
1175
1176} __packed;
1177
1178struct wcn36xx_hal_config_sta_params {
1179
1180 u8 bssid[ETH_ALEN];
1181
1182
1183 u16 aid;
1184
1185
1186 u8 type;
1187
1188
1189 u8 short_preamble_supported;
1190
1191
1192 u8 mac[ETH_ALEN];
1193
1194
1195 u16 listen_interval;
1196
1197
1198 u8 wmm_enabled;
1199
1200
1201 u8 ht_capable;
1202
1203
1204 u8 tx_channel_width_set;
1205
1206
1207 u8 rifs_mode;
1208
1209
1210
1211
1212 u8 lsig_txop_protection;
1213
1214
1215
1216 u8 max_ampdu_size;
1217
1218
1219 u8 max_ampdu_density;
1220
1221
1222 u8 max_amsdu_size;
1223
1224
1225 u8 sgi_40mhz;
1226
1227
1228 u8 sgi_20Mhz;
1229
1230
1231
1232 struct wcn36xx_hal_supported_rates supported_rates;
1233
1234
1235 u8 rmf;
1236
1237
1238 u32 encrypt_type;
1239
1240
1241
1242
1243 u8 action;
1244
1245
1246
1247
1248 u8 uapsd;
1249
1250
1251 u8 max_sp_len;
1252
1253
1254
1255 u8 green_field_capable;
1256
1257
1258 enum wcn36xx_hal_ht_mimo_state mimo_ps;
1259
1260
1261 u8 delayed_ba_support;
1262
1263
1264 u8 max_ampdu_duration;
1265
1266
1267
1268
1269
1270 u8 dsss_cck_mode_40mhz;
1271
1272
1273
1274 u8 sta_index;
1275
1276
1277
1278
1279 u8 bssid_index;
1280
1281 u8 p2p;
1282
1283
1284
1285
1286} __packed;
1287
1288struct wcn36xx_hal_config_sta_req_msg {
1289 struct wcn36xx_hal_msg_header header;
1290 struct wcn36xx_hal_config_sta_params sta_params;
1291} __packed;
1292
1293struct wcn36xx_hal_config_sta_params_v1 {
1294
1295 u8 bssid[ETH_ALEN];
1296
1297
1298 u16 aid;
1299
1300
1301 u8 type;
1302
1303
1304 u8 short_preamble_supported;
1305
1306
1307 u8 mac[ETH_ALEN];
1308
1309
1310 u16 listen_interval;
1311
1312
1313 u8 wmm_enabled;
1314
1315
1316 u8 ht_capable;
1317
1318
1319 u8 tx_channel_width_set;
1320
1321
1322 u8 rifs_mode;
1323
1324
1325
1326
1327 u8 lsig_txop_protection;
1328
1329
1330
1331 u8 max_ampdu_size;
1332
1333
1334 u8 max_ampdu_density;
1335
1336
1337 u8 max_amsdu_size;
1338
1339
1340 u8 sgi_40mhz;
1341
1342
1343 u8 sgi_20Mhz;
1344
1345
1346 u8 rmf;
1347
1348
1349 u32 encrypt_type;
1350
1351
1352
1353
1354 u8 action;
1355
1356
1357
1358
1359 u8 uapsd;
1360
1361
1362 u8 max_sp_len;
1363
1364
1365
1366 u8 green_field_capable;
1367
1368
1369 enum wcn36xx_hal_ht_mimo_state mimo_ps;
1370
1371
1372 u8 delayed_ba_support;
1373
1374
1375 u8 max_ampdu_duration;
1376
1377
1378
1379
1380
1381 u8 dsss_cck_mode_40mhz;
1382
1383
1384
1385 u8 sta_index;
1386
1387
1388
1389
1390 u8 bssid_index;
1391
1392 u8 p2p;
1393
1394
1395 u8 reserved;
1396
1397
1398 struct wcn36xx_hal_supported_rates supported_rates;
1399} __packed;
1400
1401struct wcn36xx_hal_config_sta_req_msg_v1 {
1402 struct wcn36xx_hal_msg_header header;
1403 struct wcn36xx_hal_config_sta_params_v1 sta_params;
1404} __packed;
1405
1406struct config_sta_rsp_params {
1407
1408 u32 status;
1409
1410
1411 u8 sta_index;
1412
1413
1414 u8 bssid_index;
1415
1416
1417 u8 dpu_index;
1418
1419
1420 u8 bcast_dpu_index;
1421
1422
1423 u8 bcast_mgmt_dpu_idx;
1424
1425
1426 u8 uc_ucast_sig;
1427
1428
1429 u8 uc_bcast_sig;
1430
1431
1432 u8 uc_mgmt_sig;
1433
1434 u8 p2p;
1435
1436} __packed;
1437
1438struct wcn36xx_hal_config_sta_rsp_msg {
1439 struct wcn36xx_hal_msg_header header;
1440
1441 struct config_sta_rsp_params params;
1442} __packed;
1443
1444
1445struct wcn36xx_hal_delete_sta_req_msg {
1446 struct wcn36xx_hal_msg_header header;
1447
1448
1449 u8 sta_index;
1450
1451} __packed;
1452
1453
1454struct wcn36xx_hal_delete_sta_rsp_msg {
1455 struct wcn36xx_hal_msg_header header;
1456
1457
1458 u32 status;
1459
1460
1461 u8 sta_id;
1462} __packed;
1463
1464
1465
1466struct wcn36xx_hal_rate_set {
1467 u8 num_rates;
1468 u8 rate[WCN36XX_HAL_MAC_RATESET_EID_MAX];
1469} __packed;
1470
1471
1472struct wcn36xx_hal_aci_aifsn {
1473#ifndef ANI_LITTLE_BIT_ENDIAN
1474 u8 rsvd:1;
1475 u8 aci:2;
1476 u8 acm:1;
1477 u8 aifsn:4;
1478#else
1479 u8 aifsn:4;
1480 u8 acm:1;
1481 u8 aci:2;
1482 u8 rsvd:1;
1483#endif
1484} __packed;
1485
1486
1487struct wcn36xx_hal_mac_cw {
1488#ifndef ANI_LITTLE_BIT_ENDIAN
1489 u8 max:4;
1490 u8 min:4;
1491#else
1492 u8 min:4;
1493 u8 max:4;
1494#endif
1495} __packed;
1496
1497struct wcn36xx_hal_edca_param_record {
1498 struct wcn36xx_hal_aci_aifsn aci;
1499 struct wcn36xx_hal_mac_cw cw;
1500 u16 txop_limit;
1501} __packed;
1502
1503struct wcn36xx_hal_mac_ssid {
1504 u8 length;
1505 u8 ssid[32];
1506} __packed;
1507
1508
1509
1510enum wcn36xx_hal_con_mode {
1511 WCN36XX_HAL_STA_MODE = 0,
1512
1513
1514
1515 WCN36XX_HAL_STA_SAP_MODE = 1,
1516
1517 WCN36XX_HAL_P2P_CLIENT_MODE,
1518 WCN36XX_HAL_P2P_GO_MODE,
1519 WCN36XX_HAL_MONITOR_MODE,
1520};
1521
1522
1523
1524
1525
1526
1527enum wcn36xx_hal_concurrency_mode {
1528 HAL_STA = 1,
1529 HAL_SAP = 2,
1530
1531
1532 HAL_STA_SAP = 3,
1533
1534 HAL_P2P_CLIENT = 4,
1535 HAL_P2P_GO = 8,
1536 HAL_MAX_CONCURRENCY_PERSONA = 4
1537};
1538
1539struct wcn36xx_hal_config_bss_params {
1540
1541 u8 bssid[ETH_ALEN];
1542
1543
1544 u8 self_mac_addr[ETH_ALEN];
1545
1546
1547 enum wcn36xx_hal_bss_type bss_type;
1548
1549
1550 u8 oper_mode;
1551
1552
1553 enum wcn36xx_hal_nw_type nw_type;
1554
1555
1556 u8 short_slot_time_supported;
1557
1558
1559 u8 lla_coexist;
1560
1561
1562 u8 llb_coexist;
1563
1564
1565 u8 llg_coexist;
1566
1567
1568 u8 ht20_coexist;
1569
1570
1571 u8 lln_non_gf_coexist;
1572
1573
1574 u8 lsig_tx_op_protection_full_support;
1575
1576
1577 u8 rifs_mode;
1578
1579
1580 u16 beacon_interval;
1581
1582
1583 u8 dtim_period;
1584
1585
1586 u8 tx_channel_width_set;
1587
1588
1589 u8 oper_channel;
1590
1591
1592 u8 ext_channel;
1593
1594
1595 u8 reserved;
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606 struct wcn36xx_hal_config_sta_params sta;
1607
1608 struct wcn36xx_hal_mac_ssid ssid;
1609
1610
1611
1612
1613
1614 u8 action;
1615
1616
1617 struct wcn36xx_hal_rate_set rateset;
1618
1619
1620 u8 ht;
1621
1622
1623 u8 obss_prot_enabled;
1624
1625
1626 u8 rmf;
1627
1628
1629 enum wcn36xx_hal_ht_operating_mode ht_oper_mode;
1630
1631
1632 u8 dual_cts_protection;
1633
1634
1635 u8 max_probe_resp_retry_limit;
1636
1637
1638 u8 hidden_ssid;
1639
1640
1641 u8 proxy_probe_resp;
1642
1643
1644
1645
1646
1647 u8 edca_params_valid;
1648
1649
1650 struct wcn36xx_hal_edca_param_record acbe;
1651
1652
1653 struct wcn36xx_hal_edca_param_record acbk;
1654
1655
1656 struct wcn36xx_hal_edca_param_record acvi;
1657
1658
1659 struct wcn36xx_hal_edca_param_record acvo;
1660
1661
1662 u8 ext_set_sta_key_param_valid;
1663
1664
1665 struct wcn36xx_hal_set_sta_key_params ext_set_sta_key_param;
1666
1667
1668
1669 u8 wcn36xx_hal_persona;
1670
1671 u8 spectrum_mgt_enable;
1672
1673
1674 s8 tx_mgmt_power;
1675
1676
1677
1678 s8 max_tx_power;
1679} __packed;
1680
1681struct wcn36xx_hal_config_bss_req_msg {
1682 struct wcn36xx_hal_msg_header header;
1683 struct wcn36xx_hal_config_bss_params bss_params;
1684} __packed;
1685
1686struct wcn36xx_hal_config_bss_params_v1 {
1687
1688 u8 bssid[ETH_ALEN];
1689
1690
1691 u8 self_mac_addr[ETH_ALEN];
1692
1693
1694 enum wcn36xx_hal_bss_type bss_type;
1695
1696
1697 u8 oper_mode;
1698
1699
1700 enum wcn36xx_hal_nw_type nw_type;
1701
1702
1703 u8 short_slot_time_supported;
1704
1705
1706 u8 lla_coexist;
1707
1708
1709 u8 llb_coexist;
1710
1711
1712 u8 llg_coexist;
1713
1714
1715 u8 ht20_coexist;
1716
1717
1718 u8 lln_non_gf_coexist;
1719
1720
1721 u8 lsig_tx_op_protection_full_support;
1722
1723
1724 u8 rifs_mode;
1725
1726
1727 u16 beacon_interval;
1728
1729
1730 u8 dtim_period;
1731
1732
1733 u8 tx_channel_width_set;
1734
1735
1736 u8 oper_channel;
1737
1738
1739 u8 ext_channel;
1740
1741
1742 u8 reserved;
1743
1744
1745 struct wcn36xx_hal_mac_ssid ssid;
1746
1747
1748
1749
1750
1751 u8 action;
1752
1753
1754 struct wcn36xx_hal_rate_set rateset;
1755
1756
1757 u8 ht;
1758
1759
1760 u8 obss_prot_enabled;
1761
1762
1763 u8 rmf;
1764
1765
1766 enum wcn36xx_hal_ht_operating_mode ht_oper_mode;
1767
1768
1769 u8 dual_cts_protection;
1770
1771
1772 u8 max_probe_resp_retry_limit;
1773
1774
1775 u8 hidden_ssid;
1776
1777
1778 u8 proxy_probe_resp;
1779
1780
1781
1782
1783
1784 u8 edca_params_valid;
1785
1786
1787 struct wcn36xx_hal_edca_param_record acbe;
1788
1789
1790 struct wcn36xx_hal_edca_param_record acbk;
1791
1792
1793 struct wcn36xx_hal_edca_param_record acvi;
1794
1795
1796 struct wcn36xx_hal_edca_param_record acvo;
1797
1798
1799 u8 ext_set_sta_key_param_valid;
1800
1801
1802 struct wcn36xx_hal_set_sta_key_params ext_set_sta_key_param;
1803
1804
1805
1806 u8 wcn36xx_hal_persona;
1807
1808 u8 spectrum_mgt_enable;
1809
1810
1811 s8 tx_mgmt_power;
1812
1813
1814
1815 s8 max_tx_power;
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825 struct wcn36xx_hal_config_sta_params_v1 sta;
1826} __packed;
1827
1828struct wcn36xx_hal_config_bss_req_msg_v1 {
1829 struct wcn36xx_hal_msg_header header;
1830 struct wcn36xx_hal_config_bss_params_v1 bss_params;
1831} __packed;
1832
1833struct wcn36xx_hal_config_bss_rsp_params {
1834
1835 u32 status;
1836
1837
1838 u8 bss_index;
1839
1840
1841 u8 dpu_desc_index;
1842
1843
1844 u8 ucast_dpu_signature;
1845
1846
1847 u8 bcast_dpu_desc_indx;
1848
1849
1850 u8 bcast_dpu_signature;
1851
1852
1853 u8 mgmt_dpu_desc_index;
1854
1855
1856 u8 mgmt_dpu_signature;
1857
1858
1859 u8 bss_sta_index;
1860
1861
1862 u8 bss_self_sta_index;
1863
1864
1865 u8 bss_bcast_sta_idx;
1866
1867
1868 u8 mac[ETH_ALEN];
1869
1870
1871 s8 tx_mgmt_power;
1872
1873} __packed;
1874
1875struct wcn36xx_hal_config_bss_rsp_msg {
1876 struct wcn36xx_hal_msg_header header;
1877 struct wcn36xx_hal_config_bss_rsp_params bss_rsp_params;
1878} __packed;
1879
1880struct wcn36xx_hal_delete_bss_req_msg {
1881 struct wcn36xx_hal_msg_header header;
1882
1883
1884 u8 bss_index;
1885
1886} __packed;
1887
1888struct wcn36xx_hal_delete_bss_rsp_msg {
1889 struct wcn36xx_hal_msg_header header;
1890
1891
1892 u32 status;
1893
1894
1895 u8 bss_index;
1896
1897} __packed;
1898
1899struct wcn36xx_hal_join_req_msg {
1900 struct wcn36xx_hal_msg_header header;
1901
1902
1903 u8 bssid[ETH_ALEN];
1904
1905
1906 u8 channel;
1907
1908
1909 u8 self_sta_mac_addr[ETH_ALEN];
1910
1911
1912 u8 local_power_constraint;
1913
1914
1915 enum phy_chan_bond_state secondary_channel_offset;
1916
1917
1918 enum wcn36xx_hal_link_state link_state;
1919
1920
1921 s8 max_tx_power;
1922} __packed;
1923
1924struct wcn36xx_hal_join_rsp_msg {
1925 struct wcn36xx_hal_msg_header header;
1926
1927
1928 u32 status;
1929
1930
1931 u8 tx_mgmt_power;
1932} __packed;
1933
1934struct post_assoc_req_msg {
1935 struct wcn36xx_hal_msg_header header;
1936
1937 struct wcn36xx_hal_config_sta_params sta_params;
1938 struct wcn36xx_hal_config_bss_params bss_params;
1939};
1940
1941struct post_assoc_rsp_msg {
1942 struct wcn36xx_hal_msg_header header;
1943 struct config_sta_rsp_params sta_rsp_params;
1944 struct wcn36xx_hal_config_bss_rsp_params bss_rsp_params;
1945};
1946
1947
1948struct wcn36xx_hal_set_bss_key_req_msg {
1949 struct wcn36xx_hal_msg_header header;
1950
1951
1952 u8 bss_idx;
1953
1954
1955 enum ani_ed_type enc_type;
1956
1957
1958 u8 num_keys;
1959
1960
1961 struct wcn36xx_hal_keys keys[WCN36XX_HAL_MAC_MAX_NUM_OF_DEFAULT_KEYS];
1962
1963
1964
1965 u8 single_tid_rc;
1966} __packed;
1967
1968
1969struct wcn36xx_hal_set_bss_key_req_msg_tagged {
1970 struct wcn36xx_hal_set_bss_key_req_msg Msg;
1971 u32 tag;
1972} __packed;
1973
1974struct wcn36xx_hal_set_bss_key_rsp_msg {
1975 struct wcn36xx_hal_msg_header header;
1976
1977
1978 u32 status;
1979} __packed;
1980
1981
1982
1983
1984
1985
1986
1987struct wcn36xx_hal_set_sta_key_req_msg {
1988 struct wcn36xx_hal_msg_header header;
1989 struct wcn36xx_hal_set_sta_key_params set_sta_key_params;
1990} __packed;
1991
1992struct wcn36xx_hal_set_sta_key_rsp_msg {
1993 struct wcn36xx_hal_msg_header header;
1994
1995
1996 u32 status;
1997} __packed;
1998
1999struct wcn36xx_hal_remove_bss_key_req_msg {
2000 struct wcn36xx_hal_msg_header header;
2001
2002
2003 u8 bss_idx;
2004
2005
2006 enum ani_ed_type enc_type;
2007
2008
2009 u8 key_id;
2010
2011
2012
2013 enum ani_wep_type wep_type;
2014} __packed;
2015
2016struct wcn36xx_hal_remove_bss_key_rsp_msg {
2017 struct wcn36xx_hal_msg_header header;
2018
2019
2020 u32 status;
2021} __packed;
2022
2023
2024
2025
2026struct wcn36xx_hal_remove_sta_key_req_msg {
2027 struct wcn36xx_hal_msg_header header;
2028
2029
2030 u16 sta_idx;
2031
2032
2033 enum ani_ed_type enc_type;
2034
2035
2036 u8 key_id;
2037
2038
2039
2040 u8 unicast;
2041
2042} __packed;
2043
2044struct wcn36xx_hal_remove_sta_key_rsp_msg {
2045 struct wcn36xx_hal_msg_header header;
2046
2047
2048 u32 status;
2049
2050} __packed;
2051
2052#ifdef FEATURE_OEM_DATA_SUPPORT
2053
2054#ifndef OEM_DATA_REQ_SIZE
2055#define OEM_DATA_REQ_SIZE 134
2056#endif
2057
2058#ifndef OEM_DATA_RSP_SIZE
2059#define OEM_DATA_RSP_SIZE 1968
2060#endif
2061
2062struct start_oem_data_req_msg {
2063 struct wcn36xx_hal_msg_header header;
2064
2065 u32 status;
2066 tSirMacAddr self_mac_addr;
2067 u8 oem_data_req[OEM_DATA_REQ_SIZE];
2068
2069};
2070
2071struct start_oem_data_rsp_msg {
2072 struct wcn36xx_hal_msg_header header;
2073
2074 u8 oem_data_rsp[OEM_DATA_RSP_SIZE];
2075};
2076
2077#endif
2078
2079struct wcn36xx_hal_switch_channel_req_msg {
2080 struct wcn36xx_hal_msg_header header;
2081
2082
2083 u8 channel_number;
2084
2085
2086 u8 local_power_constraint;
2087
2088
2089 enum phy_chan_bond_state secondary_channel_offset;
2090
2091
2092 u8 tx_mgmt_power;
2093
2094
2095 u8 max_tx_power;
2096
2097
2098 u8 self_sta_mac_addr[ETH_ALEN];
2099
2100
2101
2102
2103
2104
2105
2106
2107
2108
2109 u8 bssid[ETH_ALEN];
2110} __packed;
2111
2112struct wcn36xx_hal_switch_channel_rsp_msg {
2113 struct wcn36xx_hal_msg_header header;
2114
2115
2116 u32 status;
2117
2118
2119 u8 channel_number;
2120
2121
2122 u8 tx_mgmt_power;
2123
2124
2125 u8 bssid[ETH_ALEN];
2126
2127} __packed;
2128
2129struct update_edca_params_req_msg {
2130 struct wcn36xx_hal_msg_header header;
2131
2132
2133 u16 bss_index;
2134
2135
2136 struct wcn36xx_hal_edca_param_record acbe;
2137
2138
2139 struct wcn36xx_hal_edca_param_record acbk;
2140
2141
2142 struct wcn36xx_hal_edca_param_record acvi;
2143
2144
2145 struct wcn36xx_hal_edca_param_record acvo;
2146};
2147
2148struct update_edca_params_rsp_msg {
2149 struct wcn36xx_hal_msg_header header;
2150
2151
2152 u32 status;
2153};
2154
2155struct dpu_stats_params {
2156
2157 u16 sta_index;
2158
2159
2160 u8 enc_mode;
2161
2162
2163 u32 status;
2164
2165
2166 u32 send_blocks;
2167 u32 recv_blocks;
2168 u32 replays;
2169 u8 mic_error_cnt;
2170 u32 prot_excl_cnt;
2171 u16 format_err_cnt;
2172 u16 un_decryptable_cnt;
2173 u32 decrypt_err_cnt;
2174 u32 decrypt_ok_cnt;
2175};
2176
2177struct wcn36xx_hal_stats_req_msg {
2178 struct wcn36xx_hal_msg_header header;
2179
2180
2181 u32 sta_id;
2182
2183
2184 u32 stats_mask;
2185};
2186
2187struct ani_summary_stats_info {
2188
2189
2190 u32 retry_cnt[4];
2191
2192
2193
2194
2195 u32 multiple_retry_cnt[4];
2196
2197
2198
2199
2200 u32 tx_frm_cnt[4];
2201
2202
2203
2204 u32 rx_frm_cnt;
2205
2206
2207 u32 frm_dup_cnt;
2208
2209
2210 u32 fail_cnt[4];
2211
2212
2213
2214 u32 rts_fail_cnt;
2215
2216
2217
2218 u32 ack_fail_cnt;
2219
2220
2221
2222 u32 rts_succ_cnt;
2223
2224
2225
2226
2227 u32 rx_discard_cnt;
2228
2229
2230
2231
2232 u32 rx_error_cnt;
2233
2234
2235
2236
2237 u32 tx_byte_cnt;
2238};
2239
2240
2241enum tx_rate_info {
2242
2243 HAL_TX_RATE_LEGACY = 0x1,
2244
2245
2246 HAL_TX_RATE_HT20 = 0x2,
2247
2248
2249 HAL_TX_RATE_HT40 = 0x4,
2250
2251
2252 HAL_TX_RATE_SGI = 0x8,
2253
2254
2255 HAL_TX_RATE_LGI = 0x10
2256};
2257
2258struct ani_global_class_a_stats_info {
2259
2260
2261 u32 rx_frag_cnt;
2262
2263
2264
2265
2266 u32 promiscuous_rx_frag_cnt;
2267
2268
2269
2270
2271
2272 u32 rx_input_sensitivity;
2273
2274
2275
2276 u32 max_pwr;
2277
2278
2279
2280
2281 u32 sync_fail_cnt;
2282
2283
2284
2285 u32 tx_rate;
2286
2287
2288 u32 mcs_index;
2289
2290
2291
2292 u32 tx_rate_flags;
2293};
2294
2295struct ani_global_security_stats {
2296
2297
2298
2299 u32 rx_wep_unencrypted_frm_cnt;
2300
2301
2302
2303 u32 rx_mic_fail_cnt;
2304
2305
2306
2307 u32 tkip_icv_err;
2308
2309
2310
2311 u32 aes_ccmp_format_err;
2312
2313
2314
2315 u32 aes_ccmp_replay_cnt;
2316
2317
2318
2319
2320 u32 aes_ccmp_decrpt_err;
2321
2322
2323
2324 u32 wep_undecryptable_cnt;
2325
2326
2327
2328 u32 wep_icv_err;
2329
2330
2331
2332 u32 rx_decrypt_succ_cnt;
2333
2334
2335
2336 u32 rx_decrypt_fail_cnt;
2337};
2338
2339struct ani_global_class_b_stats_info {
2340 struct ani_global_security_stats uc_stats;
2341 struct ani_global_security_stats mc_bc_stats;
2342};
2343
2344struct ani_global_class_c_stats_info {
2345
2346
2347
2348 u32 rx_amsdu_cnt;
2349
2350
2351
2352 u32 rx_ampdu_cnt;
2353
2354
2355
2356 u32 tx_20_frm_cnt;
2357
2358
2359
2360 u32 rx_20_frm_cnt;
2361
2362
2363
2364 u32 rx_mpdu_in_ampdu_cnt;
2365
2366
2367
2368
2369 u32 ampdu_delimiter_crc_err;
2370};
2371
2372struct ani_per_sta_stats_info {
2373
2374
2375 u32 tx_frag_cnt[4];
2376
2377
2378 u32 tx_ampdu_cnt;
2379
2380
2381
2382 u32 tx_mpdu_in_ampdu_cnt;
2383};
2384
2385struct wcn36xx_hal_stats_rsp_msg {
2386 struct wcn36xx_hal_msg_header header;
2387
2388
2389 u32 status;
2390
2391
2392 u32 sta_index;
2393
2394
2395 u32 stats_mask;
2396
2397
2398 u16 msg_type;
2399
2400
2401 u16 msg_len;
2402};
2403
2404struct wcn36xx_hal_set_link_state_req_msg {
2405 struct wcn36xx_hal_msg_header header;
2406
2407 u8 bssid[ETH_ALEN];
2408 enum wcn36xx_hal_link_state state;
2409 u8 self_mac_addr[ETH_ALEN];
2410
2411} __packed;
2412
2413struct set_link_state_rsp_msg {
2414 struct wcn36xx_hal_msg_header header;
2415
2416
2417 u32 status;
2418};
2419
2420
2421struct wcn36xx_hal_ts_info_tfc {
2422#ifndef ANI_LITTLE_BIT_ENDIAN
2423 u16 ackPolicy:2;
2424 u16 userPrio:3;
2425 u16 psb:1;
2426 u16 aggregation:1;
2427 u16 accessPolicy:2;
2428 u16 direction:2;
2429 u16 tsid:4;
2430 u16 trafficType:1;
2431#else
2432 u16 trafficType:1;
2433 u16 tsid:4;
2434 u16 direction:2;
2435 u16 accessPolicy:2;
2436 u16 aggregation:1;
2437 u16 psb:1;
2438 u16 userPrio:3;
2439 u16 ackPolicy:2;
2440#endif
2441};
2442
2443
2444struct wcn36xx_hal_ts_info_sch {
2445#ifndef ANI_LITTLE_BIT_ENDIAN
2446 u8 rsvd:7;
2447 u8 schedule:1;
2448#else
2449 u8 schedule:1;
2450 u8 rsvd:7;
2451#endif
2452};
2453
2454
2455struct wcn36xx_hal_ts_info {
2456 struct wcn36xx_hal_ts_info_tfc traffic;
2457 struct wcn36xx_hal_ts_info_sch schedule;
2458};
2459
2460
2461struct wcn36xx_hal_tspec_ie {
2462 u8 type;
2463 u8 length;
2464 struct wcn36xx_hal_ts_info ts_info;
2465 u16 nom_msdu_size;
2466 u16 max_msdu_size;
2467 u32 min_svc_interval;
2468 u32 max_svc_interval;
2469 u32 inact_interval;
2470 u32 suspend_interval;
2471 u32 svc_start_time;
2472 u32 min_data_rate;
2473 u32 mean_data_rate;
2474 u32 peak_data_rate;
2475 u32 max_burst_sz;
2476 u32 delay_bound;
2477 u32 min_phy_rate;
2478 u16 surplus_bw;
2479 u16 medium_time;
2480};
2481
2482struct add_ts_req_msg {
2483 struct wcn36xx_hal_msg_header header;
2484
2485
2486 u16 sta_index;
2487
2488
2489 u16 tspec_index;
2490
2491
2492 struct wcn36xx_hal_tspec_ie tspec;
2493
2494
2495
2496
2497 u8 uapsd;
2498
2499
2500
2501
2502 u32 service_interval[WCN36XX_HAL_MAX_AC];
2503
2504
2505 u32 suspend_interval[WCN36XX_HAL_MAX_AC];
2506
2507
2508 u32 delay_interval[WCN36XX_HAL_MAX_AC];
2509};
2510
2511struct add_rs_rsp_msg {
2512 struct wcn36xx_hal_msg_header header;
2513
2514
2515 u32 status;
2516};
2517
2518struct del_ts_req_msg {
2519 struct wcn36xx_hal_msg_header header;
2520
2521
2522 u16 sta_index;
2523
2524
2525 u16 tspec_index;
2526
2527
2528 u8 bssid[ETH_ALEN];
2529};
2530
2531struct del_ts_rsp_msg {
2532 struct wcn36xx_hal_msg_header header;
2533
2534
2535 u32 status;
2536};
2537
2538
2539
2540
2541
2542struct wcn36xx_hal_add_ba_session_req_msg {
2543 struct wcn36xx_hal_msg_header header;
2544
2545
2546 u16 sta_index;
2547
2548
2549 u8 mac_addr[ETH_ALEN];
2550
2551
2552
2553 u8 dialog_token;
2554
2555
2556
2557 u8 tid;
2558
2559
2560
2561 u8 policy;
2562
2563
2564
2565
2566
2567
2568
2569 u16 buffer_size;
2570
2571
2572 u16 timeout;
2573
2574
2575
2576
2577 u16 ssn;
2578
2579
2580
2581
2582 u8 direction;
2583} __packed;
2584
2585struct wcn36xx_hal_add_ba_session_rsp_msg {
2586 struct wcn36xx_hal_msg_header header;
2587
2588
2589 u32 status;
2590
2591
2592 u8 dialog_token;
2593
2594
2595 u8 ba_tid;
2596
2597
2598 u8 ba_buffer_size;
2599
2600 u8 ba_session_id;
2601
2602
2603 u8 win_size;
2604
2605
2606 u8 sta_index;
2607
2608
2609 u16 ssn;
2610} __packed;
2611
2612struct wcn36xx_hal_add_ba_req_msg {
2613 struct wcn36xx_hal_msg_header header;
2614
2615
2616 u8 session_id;
2617
2618
2619 u8 win_size;
2620
2621#ifdef FEATURE_ON_CHIP_REORDERING
2622 u8 reordering_done_on_chip;
2623#endif
2624} __packed;
2625
2626struct wcn36xx_hal_add_ba_rsp_msg {
2627 struct wcn36xx_hal_msg_header header;
2628
2629
2630 u32 status;
2631
2632
2633 u8 dialog_token;
2634} __packed;
2635
2636struct add_ba_info {
2637 u16 ba_enable:1;
2638 u16 starting_seq_num:12;
2639 u16 reserved:3;
2640};
2641
2642struct wcn36xx_hal_trigger_ba_rsp_candidate {
2643 u8 sta_addr[ETH_ALEN];
2644 struct add_ba_info ba_info[STACFG_MAX_TC];
2645} __packed;
2646
2647struct wcn36xx_hal_trigger_ba_req_candidate {
2648 u8 sta_index;
2649 u8 tid_bitmap;
2650} __packed;
2651
2652struct wcn36xx_hal_trigger_ba_req_msg {
2653 struct wcn36xx_hal_msg_header header;
2654
2655
2656 u8 session_id;
2657
2658
2659
2660
2661 u16 candidate_cnt;
2662
2663} __packed;
2664
2665struct wcn36xx_hal_trigger_ba_rsp_msg {
2666 struct wcn36xx_hal_msg_header header;
2667
2668
2669 u8 bssid[ETH_ALEN];
2670
2671
2672 u32 status;
2673
2674
2675
2676
2677 u16 candidate_cnt;
2678} __packed;
2679
2680struct wcn36xx_hal_del_ba_req_msg {
2681 struct wcn36xx_hal_msg_header header;
2682
2683
2684 u16 sta_index;
2685
2686
2687 u8 tid;
2688
2689
2690
2691
2692 u8 direction;
2693} __packed;
2694
2695struct wcn36xx_hal_del_ba_rsp_msg {
2696 struct wcn36xx_hal_msg_header header;
2697
2698
2699 u32 status;
2700} __packed;
2701
2702struct tsm_stats_req_msg {
2703 struct wcn36xx_hal_msg_header header;
2704
2705
2706 u8 tid;
2707
2708 u8 bssid[ETH_ALEN];
2709};
2710
2711struct tsm_stats_rsp_msg {
2712 struct wcn36xx_hal_msg_header header;
2713
2714
2715 u32 status;
2716
2717
2718 u16 uplink_pkt_queue_delay;
2719
2720
2721 u16 uplink_pkt_queue_delay_hist[4];
2722
2723
2724 u32 uplink_pkt_tx_delay;
2725
2726
2727 u16 uplink_pkt_loss;
2728
2729
2730 u16 uplink_pkt_count;
2731
2732
2733 u8 roaming_count;
2734
2735
2736 u16 roaming_delay;
2737};
2738
2739struct set_key_done_msg {
2740 struct wcn36xx_hal_msg_header header;
2741
2742
2743 u8 bssidx;
2744 u8 enc_type;
2745};
2746
2747struct wcn36xx_hal_nv_img_download_req_msg {
2748
2749
2750
2751
2752 struct wcn36xx_hal_msg_header header;
2753
2754
2755
2756
2757
2758
2759
2760
2761
2762 u16 frag_number;
2763
2764
2765
2766
2767
2768
2769 u16 last_fragment;
2770
2771
2772 u32 nv_img_buffer_size;
2773
2774
2775
2776
2777} __packed;
2778
2779struct wcn36xx_hal_nv_img_download_rsp_msg {
2780 struct wcn36xx_hal_msg_header header;
2781
2782
2783
2784 u32 status;
2785} __packed;
2786
2787struct wcn36xx_hal_nv_store_ind {
2788
2789
2790 struct wcn36xx_hal_msg_header header;
2791
2792
2793 u32 table_id;
2794
2795
2796 u32 nv_blob_size;
2797
2798
2799
2800};
2801
2802
2803
2804#define WCN36XX_HAL_CIPHER_SEQ_CTR_SIZE 6
2805
2806
2807
2808
2809struct mic_failure_ind_msg {
2810 struct wcn36xx_hal_msg_header header;
2811
2812 u8 bssid[ETH_ALEN];
2813
2814
2815 u8 src_addr[ETH_ALEN];
2816
2817
2818 u8 ta_addr[ETH_ALEN];
2819
2820 u8 dst_addr[ETH_ALEN];
2821
2822 u8 multicast;
2823
2824
2825 u8 iv1;
2826
2827
2828 u8 key_id;
2829
2830
2831 u8 tsc[WCN36XX_HAL_CIPHER_SEQ_CTR_SIZE];
2832
2833
2834 u8 rx_addr[ETH_ALEN];
2835};
2836
2837struct update_vht_op_mode_req_msg {
2838 struct wcn36xx_hal_msg_header header;
2839
2840 u16 op_mode;
2841 u16 sta_id;
2842};
2843
2844struct update_vht_op_mode_params_rsp_msg {
2845 struct wcn36xx_hal_msg_header header;
2846
2847 u32 status;
2848};
2849
2850struct update_beacon_req_msg {
2851 struct wcn36xx_hal_msg_header header;
2852
2853 u8 bss_index;
2854
2855
2856
2857 u8 short_preamble;
2858
2859
2860 u8 short_slot_time;
2861
2862
2863 u16 beacon_interval;
2864
2865
2866 u8 lla_coexist;
2867 u8 llb_coexist;
2868 u8 llg_coexist;
2869 u8 ht20_coexist;
2870 u8 lln_non_gf_coexist;
2871 u8 lsig_tx_op_protection_full_support;
2872 u8 rifs_mode;
2873
2874 u16 param_change_bitmap;
2875};
2876
2877struct update_beacon_rsp_msg {
2878 struct wcn36xx_hal_msg_header header;
2879 u32 status;
2880};
2881
2882struct wcn36xx_hal_send_beacon_req_msg {
2883 struct wcn36xx_hal_msg_header header;
2884
2885
2886 u32 beacon_length;
2887
2888
2889 u8 beacon[BEACON_TEMPLATE_SIZE];
2890
2891 u8 bssid[ETH_ALEN];
2892
2893
2894 u32 tim_ie_offset;
2895
2896
2897 u16 p2p_ie_offset;
2898} __packed;
2899
2900struct send_beacon_rsp_msg {
2901 struct wcn36xx_hal_msg_header header;
2902 u32 status;
2903} __packed;
2904
2905struct enable_radar_req_msg {
2906 struct wcn36xx_hal_msg_header header;
2907
2908 u8 bssid[ETH_ALEN];
2909 u8 channel;
2910};
2911
2912struct enable_radar_rsp_msg {
2913 struct wcn36xx_hal_msg_header header;
2914
2915
2916 u8 bssid[ETH_ALEN];
2917
2918
2919 u32 status;
2920};
2921
2922struct radar_detect_intr_ind_msg {
2923 struct wcn36xx_hal_msg_header header;
2924
2925 u8 radar_det_channel;
2926};
2927
2928struct radar_detect_ind_msg {
2929 struct wcn36xx_hal_msg_header header;
2930
2931
2932 u8 channel_number;
2933
2934
2935 u16 radar_pulse_width;
2936
2937
2938 u16 num_radar_pulse;
2939};
2940
2941struct wcn36xx_hal_get_tpc_report_req_msg {
2942 struct wcn36xx_hal_msg_header header;
2943
2944 u8 sta[ETH_ALEN];
2945 u8 dialog_token;
2946 u8 txpower;
2947};
2948
2949struct wcn36xx_hal_get_tpc_report_rsp_msg {
2950 struct wcn36xx_hal_msg_header header;
2951
2952
2953 u32 status;
2954};
2955
2956struct wcn36xx_hal_send_probe_resp_req_msg {
2957 struct wcn36xx_hal_msg_header header;
2958
2959 u8 probe_resp_template[BEACON_TEMPLATE_SIZE];
2960 u32 probe_resp_template_len;
2961 u32 proxy_probe_req_valid_ie_bmap[8];
2962 u8 bssid[ETH_ALEN];
2963};
2964
2965struct send_probe_resp_rsp_msg {
2966 struct wcn36xx_hal_msg_header header;
2967
2968
2969 u32 status;
2970};
2971
2972struct send_unknown_frame_rx_ind_msg {
2973 struct wcn36xx_hal_msg_header header;
2974
2975
2976 u32 status;
2977};
2978
2979struct wcn36xx_hal_delete_sta_context_ind_msg {
2980 struct wcn36xx_hal_msg_header header;
2981
2982 u16 aid;
2983 u16 sta_id;
2984
2985
2986 u8 bssid[ETH_ALEN];
2987
2988
2989 u8 addr2[ETH_ALEN];
2990
2991
2992 u16 reason_code;
2993} __packed;
2994
2995struct indicate_del_sta {
2996 struct wcn36xx_hal_msg_header header;
2997 u8 aid;
2998 u8 sta_index;
2999 u8 bss_index;
3000 u8 reason_code;
3001 u32 status;
3002};
3003
3004struct bt_amp_event_msg {
3005 struct wcn36xx_hal_msg_header header;
3006
3007 enum bt_amp_event_type btAmpEventType;
3008};
3009
3010struct bt_amp_event_rsp {
3011 struct wcn36xx_hal_msg_header header;
3012
3013
3014 u32 status;
3015};
3016
3017struct tl_hal_flush_ac_req_msg {
3018 struct wcn36xx_hal_msg_header header;
3019
3020
3021 u8 sta_id;
3022
3023
3024 u8 tid;
3025};
3026
3027struct tl_hal_flush_ac_rsp_msg {
3028 struct wcn36xx_hal_msg_header header;
3029
3030
3031 u8 sta_id;
3032
3033
3034 u8 tid;
3035
3036
3037 u32 status;
3038};
3039
3040struct wcn36xx_hal_enter_imps_req_msg {
3041 struct wcn36xx_hal_msg_header header;
3042};
3043
3044struct wcn36xx_hal_exit_imps_req {
3045 struct wcn36xx_hal_msg_header header;
3046};
3047
3048struct wcn36xx_hal_enter_bmps_req_msg {
3049 struct wcn36xx_hal_msg_header header;
3050
3051 u8 bss_index;
3052
3053
3054#ifndef BUILD_QWPTTSTATIC
3055 u64 tbtt;
3056#endif
3057 u8 dtim_count;
3058
3059
3060
3061 u8 dtim_period;
3062
3063
3064 u32 rssi_filter_period;
3065
3066 u32 num_beacon_per_rssi_average;
3067 u8 rssi_filter_enable;
3068} __packed;
3069
3070struct wcn36xx_hal_exit_bmps_req_msg {
3071 struct wcn36xx_hal_msg_header header;
3072
3073 u8 send_data_null;
3074 u8 bss_index;
3075} __packed;
3076
3077struct wcn36xx_hal_missed_beacon_ind_msg {
3078 struct wcn36xx_hal_msg_header header;
3079
3080 u8 bss_index;
3081} __packed;
3082
3083
3084
3085
3086
3087
3088struct beacon_filter_ie {
3089 u8 element_id;
3090 u8 check_ie_presence;
3091 u8 offset;
3092 u8 value;
3093 u8 bitmask;
3094 u8 ref;
3095};
3096
3097struct wcn36xx_hal_add_bcn_filter_req_msg {
3098 struct wcn36xx_hal_msg_header header;
3099
3100 u16 capability_info;
3101 u16 capability_mask;
3102 u16 beacon_interval;
3103 u16 ie_num;
3104 u8 bss_index;
3105 u8 reserved;
3106};
3107
3108struct wcn36xx_hal_rem_bcn_filter_req {
3109 struct wcn36xx_hal_msg_header header;
3110
3111 u8 ie_Count;
3112 u8 rem_ie_id[1];
3113};
3114
3115#define WCN36XX_HAL_IPV4_ARP_REPLY_OFFLOAD 0
3116#define WCN36XX_HAL_IPV6_NEIGHBOR_DISCOVERY_OFFLOAD 1
3117#define WCN36XX_HAL_IPV6_NS_OFFLOAD 2
3118#define WCN36XX_HAL_IPV6_ADDR_LEN 16
3119#define WCN36XX_HAL_OFFLOAD_DISABLE 0
3120#define WCN36XX_HAL_OFFLOAD_ENABLE 1
3121#define WCN36XX_HAL_OFFLOAD_BCAST_FILTER_ENABLE 0x2
3122#define WCN36XX_HAL_OFFLOAD_ARP_AND_BCAST_FILTER_ENABLE \
3123 (HAL_OFFLOAD_ENABLE|HAL_OFFLOAD_BCAST_FILTER_ENABLE)
3124
3125struct wcn36xx_hal_ns_offload_params {
3126 u8 src_ipv6_addr[WCN36XX_HAL_IPV6_ADDR_LEN];
3127 u8 self_ipv6_addr[WCN36XX_HAL_IPV6_ADDR_LEN];
3128
3129
3130 u8 target_ipv6_addr1[WCN36XX_HAL_IPV6_ADDR_LEN];
3131 u8 target_ipv6_addr2[WCN36XX_HAL_IPV6_ADDR_LEN];
3132
3133 u8 self_addr[ETH_ALEN];
3134 u8 src_ipv6_addr_valid:1;
3135 u8 target_ipv6_addr1_valid:1;
3136 u8 target_ipv6_addr2_valid:1;
3137 u8 reserved1:5;
3138
3139
3140 u8 reserved2;
3141
3142
3143 u32 slot_index;
3144 u8 bss_index;
3145};
3146
3147struct wcn36xx_hal_host_offload_req {
3148 u8 offload_Type;
3149
3150
3151 u8 enable;
3152
3153 union {
3154 u8 host_ipv4_addr[4];
3155 u8 host_ipv6_addr[WCN36XX_HAL_IPV6_ADDR_LEN];
3156 } u;
3157};
3158
3159struct wcn36xx_hal_host_offload_req_msg {
3160 struct wcn36xx_hal_msg_header header;
3161 struct wcn36xx_hal_host_offload_req host_offload_params;
3162 struct wcn36xx_hal_ns_offload_params ns_offload_params;
3163};
3164
3165
3166#define WCN36XX_HAL_KEEP_ALIVE_NULL_PKT 1
3167#define WCN36XX_HAL_KEEP_ALIVE_UNSOLICIT_ARP_RSP 2
3168
3169
3170#define WCN36XX_HAL_KEEP_ALIVE_DISABLE 0
3171#define WCN36XX_HAL_KEEP_ALIVE_ENABLE 1
3172#define WCN36XX_KEEP_ALIVE_TIME_PERIOD 30
3173
3174
3175struct wcn36xx_hal_keep_alive_req_msg {
3176 struct wcn36xx_hal_msg_header header;
3177
3178 u8 packet_type;
3179 u32 time_period;
3180 u8 host_ipv4_addr[WCN36XX_HAL_IPV4_ADDR_LEN];
3181 u8 dest_ipv4_addr[WCN36XX_HAL_IPV4_ADDR_LEN];
3182 u8 dest_addr[ETH_ALEN];
3183 u8 bss_index;
3184} __packed;
3185
3186struct wcn36xx_hal_rssi_threshold_req_msg {
3187 struct wcn36xx_hal_msg_header header;
3188
3189 s8 threshold1:8;
3190 s8 threshold2:8;
3191 s8 threshold3:8;
3192 u8 thres1_pos_notify:1;
3193 u8 thres1_neg_notify:1;
3194 u8 thres2_pos_notify:1;
3195 u8 thres2_neg_notify:1;
3196 u8 thres3_pos_notify:1;
3197 u8 thres3_neg_notify:1;
3198 u8 reserved10:2;
3199};
3200
3201struct wcn36xx_hal_enter_uapsd_req_msg {
3202 struct wcn36xx_hal_msg_header header;
3203
3204 u8 bk_delivery:1;
3205 u8 be_delivery:1;
3206 u8 vi_delivery:1;
3207 u8 vo_delivery:1;
3208 u8 bk_trigger:1;
3209 u8 be_trigger:1;
3210 u8 vi_trigger:1;
3211 u8 vo_trigger:1;
3212 u8 bss_index;
3213};
3214
3215struct wcn36xx_hal_exit_uapsd_req_msg {
3216 struct wcn36xx_hal_msg_header header;
3217 u8 bss_index;
3218};
3219
3220#define WCN36XX_HAL_WOWL_BCAST_PATTERN_MAX_SIZE 128
3221#define WCN36XX_HAL_WOWL_BCAST_MAX_NUM_PATTERNS 16
3222
3223struct wcn36xx_hal_wowl_add_bcast_ptrn_req_msg {
3224 struct wcn36xx_hal_msg_header header;
3225
3226
3227 u8 id;
3228
3229
3230
3231 u8 byte_Offset;
3232
3233
3234 u8 size;
3235
3236
3237 u8 pattern[WCN36XX_HAL_WOWL_BCAST_PATTERN_MAX_SIZE];
3238
3239
3240 u8 mask_size;
3241
3242
3243 u8 mask[WCN36XX_HAL_WOWL_BCAST_PATTERN_MAX_SIZE];
3244
3245
3246 u8 extra[WCN36XX_HAL_WOWL_BCAST_PATTERN_MAX_SIZE];
3247
3248
3249 u8 mask_extra[WCN36XX_HAL_WOWL_BCAST_PATTERN_MAX_SIZE];
3250
3251 u8 bss_index;
3252};
3253
3254struct wcn36xx_hal_wow_del_bcast_ptrn_req_msg {
3255 struct wcn36xx_hal_msg_header header;
3256
3257
3258 u8 id;
3259 u8 bss_index;
3260};
3261
3262struct wcn36xx_hal_wowl_enter_req_msg {
3263 struct wcn36xx_hal_msg_header header;
3264
3265
3266 u8 magic_packet_enable;
3267
3268
3269 u8 magic_pattern[ETH_ALEN];
3270
3271
3272
3273
3274
3275
3276 u8 pattern_filtering_enable;
3277
3278
3279
3280
3281
3282
3283
3284 u8 ucast_pattern_filtering_enable;
3285
3286
3287
3288
3289
3290 u8 wow_channel_switch_receive;
3291
3292
3293
3294
3295
3296 u8 wow_deauth_receive;
3297
3298
3299
3300
3301
3302 u8 wow_disassoc_receive;
3303
3304
3305
3306
3307
3308
3309 u8 wow_max_missed_beacons;
3310
3311
3312
3313
3314
3315
3316 u8 wow_max_sleep;
3317
3318
3319
3320
3321
3322 u8 wow_eap_id_request_enable;
3323
3324
3325
3326
3327 u8 wow_eapol_4way_enable;
3328
3329
3330
3331
3332 u8 wow_net_scan_offload_match;
3333
3334
3335
3336
3337 u8 wow_gtk_rekey_error;
3338
3339
3340
3341 u8 wow_bss_connection_loss;
3342
3343 u8 bss_index;
3344};
3345
3346struct wcn36xx_hal_wowl_exit_req_msg {
3347 struct wcn36xx_hal_msg_header header;
3348
3349 u8 bss_index;
3350};
3351
3352struct wcn36xx_hal_get_rssi_req_msg {
3353 struct wcn36xx_hal_msg_header header;
3354};
3355
3356struct wcn36xx_hal_get_roam_rssi_req_msg {
3357 struct wcn36xx_hal_msg_header header;
3358
3359
3360 u32 sta_id;
3361};
3362
3363struct wcn36xx_hal_set_uapsd_ac_params_req_msg {
3364 struct wcn36xx_hal_msg_header header;
3365
3366
3367 u8 sta_idx;
3368
3369
3370 u8 ac;
3371
3372
3373 u8 up;
3374
3375
3376 u32 service_interval;
3377
3378
3379 u32 suspend_interval;
3380
3381
3382 u32 delay_interval;
3383};
3384
3385struct wcn36xx_hal_configure_rxp_filter_req_msg {
3386 struct wcn36xx_hal_msg_header header;
3387
3388 u8 set_mcst_bcst_filter_setting;
3389 u8 set_mcst_bcst_filter;
3390};
3391
3392struct wcn36xx_hal_enter_imps_rsp_msg {
3393 struct wcn36xx_hal_msg_header header;
3394
3395
3396 u32 status;
3397};
3398
3399struct wcn36xx_hal_exit_imps_rsp_msg {
3400 struct wcn36xx_hal_msg_header header;
3401
3402
3403 u32 status;
3404};
3405
3406struct wcn36xx_hal_enter_bmps_rsp_msg {
3407 struct wcn36xx_hal_msg_header header;
3408
3409
3410 u32 status;
3411
3412 u8 bss_index;
3413} __packed;
3414
3415struct wcn36xx_hal_exit_bmps_rsp_msg {
3416 struct wcn36xx_hal_msg_header header;
3417
3418
3419 u32 status;
3420
3421 u8 bss_index;
3422} __packed;
3423
3424struct wcn36xx_hal_enter_uapsd_rsp_msg {
3425 struct wcn36xx_hal_msg_header header;
3426
3427
3428 u32 status;
3429
3430 u8 bss_index;
3431};
3432
3433struct wcn36xx_hal_exit_uapsd_rsp_msg {
3434 struct wcn36xx_hal_msg_header header;
3435
3436
3437 u32 status;
3438
3439 u8 bss_index;
3440};
3441
3442struct wcn36xx_hal_rssi_notification_ind_msg {
3443 struct wcn36xx_hal_msg_header header;
3444
3445 u32 rssi_thres1_pos_cross:1;
3446 u32 rssi_thres1_neg_cross:1;
3447 u32 rssi_thres2_pos_cross:1;
3448 u32 rssi_thres2_neg_cross:1;
3449 u32 rssi_thres3_pos_cross:1;
3450 u32 rssi_thres3_neg_cross:1;
3451 u32 avg_rssi:8;
3452 u32 reserved:18;
3453
3454};
3455
3456struct wcn36xx_hal_get_rssio_rsp_msg {
3457 struct wcn36xx_hal_msg_header header;
3458
3459
3460 u32 status;
3461 s8 rssi;
3462
3463};
3464
3465struct wcn36xx_hal_get_roam_rssi_rsp_msg {
3466 struct wcn36xx_hal_msg_header header;
3467
3468
3469 u32 status;
3470
3471 u8 sta_id;
3472 s8 rssi;
3473};
3474
3475struct wcn36xx_hal_wowl_enter_rsp_msg {
3476 struct wcn36xx_hal_msg_header header;
3477
3478
3479 u32 status;
3480 u8 bss_index;
3481};
3482
3483struct wcn36xx_hal_wowl_exit_rsp_msg {
3484 struct wcn36xx_hal_msg_header header;
3485
3486
3487 u32 status;
3488 u8 bss_index;
3489};
3490
3491struct wcn36xx_hal_add_bcn_filter_rsp_msg {
3492 struct wcn36xx_hal_msg_header header;
3493
3494
3495 u32 status;
3496};
3497
3498struct wcn36xx_hal_rem_bcn_filter_rsp_msg {
3499 struct wcn36xx_hal_msg_header header;
3500
3501
3502 u32 status;
3503};
3504
3505struct wcn36xx_hal_add_wowl_bcast_ptrn_rsp_msg {
3506 struct wcn36xx_hal_msg_header header;
3507
3508
3509 u32 status;
3510 u8 bss_index;
3511};
3512
3513struct wcn36xx_hal_del_wowl_bcast_ptrn_rsp_msg {
3514 struct wcn36xx_hal_msg_header header;
3515
3516
3517 u32 status;
3518 u8 bss_index;
3519};
3520
3521struct wcn36xx_hal_host_offload_rsp_msg {
3522 struct wcn36xx_hal_msg_header header;
3523
3524
3525 u32 status;
3526};
3527
3528struct wcn36xx_hal_keep_alive_rsp_msg {
3529 struct wcn36xx_hal_msg_header header;
3530
3531
3532 u32 status;
3533};
3534
3535struct wcn36xx_hal_set_rssi_thresh_rsp_msg {
3536 struct wcn36xx_hal_msg_header header;
3537
3538
3539 u32 status;
3540};
3541
3542struct wcn36xx_hal_set_uapsd_ac_params_rsp_msg {
3543 struct wcn36xx_hal_msg_header header;
3544
3545
3546 u32 status;
3547};
3548
3549struct wcn36xx_hal_configure_rxp_filter_rsp_msg {
3550 struct wcn36xx_hal_msg_header header;
3551
3552
3553 u32 status;
3554};
3555
3556struct set_max_tx_pwr_req {
3557 struct wcn36xx_hal_msg_header header;
3558
3559
3560
3561
3562 u8 bssid[ETH_ALEN];
3563
3564 u8 self_addr[ETH_ALEN];
3565
3566
3567 u8 power;
3568};
3569
3570struct set_max_tx_pwr_rsp_msg {
3571 struct wcn36xx_hal_msg_header header;
3572
3573
3574 u8 power;
3575
3576
3577 u32 status;
3578};
3579
3580struct set_tx_pwr_req_msg {
3581 struct wcn36xx_hal_msg_header header;
3582
3583
3584 u32 tx_power;
3585
3586 u8 bss_index;
3587};
3588
3589struct set_tx_pwr_rsp_msg {
3590 struct wcn36xx_hal_msg_header header;
3591
3592
3593 u32 status;
3594};
3595
3596struct get_tx_pwr_req_msg {
3597 struct wcn36xx_hal_msg_header header;
3598
3599 u8 sta_id;
3600};
3601
3602struct get_tx_pwr_rsp_msg {
3603 struct wcn36xx_hal_msg_header header;
3604
3605
3606 u32 status;
3607
3608
3609 u32 tx_power;
3610};
3611
3612struct set_p2p_gonoa_req_msg {
3613 struct wcn36xx_hal_msg_header header;
3614
3615 u8 opp_ps;
3616 u32 ct_window;
3617 u8 count;
3618 u32 duration;
3619 u32 interval;
3620 u32 single_noa_duration;
3621 u8 ps_selection;
3622};
3623
3624struct set_p2p_gonoa_rsp_msg {
3625 struct wcn36xx_hal_msg_header header;
3626
3627
3628 u32 status;
3629};
3630
3631struct wcn36xx_hal_add_sta_self_req {
3632 struct wcn36xx_hal_msg_header header;
3633
3634 u8 self_addr[ETH_ALEN];
3635 u32 status;
3636} __packed;
3637
3638struct wcn36xx_hal_add_sta_self_rsp_msg {
3639 struct wcn36xx_hal_msg_header header;
3640
3641
3642 u32 status;
3643
3644
3645 u8 self_sta_index;
3646
3647
3648 u8 dpu_index;
3649
3650
3651 u8 dpu_signature;
3652} __packed;
3653
3654struct wcn36xx_hal_del_sta_self_req_msg {
3655 struct wcn36xx_hal_msg_header header;
3656
3657 u8 self_addr[ETH_ALEN];
3658} __packed;
3659
3660struct wcn36xx_hal_del_sta_self_rsp_msg {
3661 struct wcn36xx_hal_msg_header header;
3662
3663
3664 u32 status;
3665
3666 u8 self_addr[ETH_ALEN];
3667} __packed;
3668
3669struct aggr_add_ts_req {
3670 struct wcn36xx_hal_msg_header header;
3671
3672
3673 u16 sta_idx;
3674
3675
3676
3677
3678 u16 tspec_index;
3679
3680
3681 struct wcn36xx_hal_tspec_ie tspec[WCN36XX_HAL_MAX_AC];
3682
3683
3684
3685
3686 u8 uapsd;
3687
3688
3689
3690
3691 u32 service_interval[WCN36XX_HAL_MAX_AC];
3692
3693
3694 u32 suspend_interval[WCN36XX_HAL_MAX_AC];
3695
3696
3697 u32 delay_interval[WCN36XX_HAL_MAX_AC];
3698};
3699
3700struct aggr_add_ts_rsp_msg {
3701 struct wcn36xx_hal_msg_header header;
3702
3703
3704 u32 status0;
3705
3706
3707 u32 status1;
3708};
3709
3710struct wcn36xx_hal_configure_apps_cpu_wakeup_state_req_msg {
3711 struct wcn36xx_hal_msg_header header;
3712
3713 u8 is_apps_cpu_awake;
3714};
3715
3716struct wcn36xx_hal_configure_apps_cpu_wakeup_state_rsp_msg {
3717 struct wcn36xx_hal_msg_header header;
3718
3719
3720 u32 status;
3721};
3722
3723struct wcn36xx_hal_dump_cmd_req_msg {
3724 struct wcn36xx_hal_msg_header header;
3725
3726 u32 arg1;
3727 u32 arg2;
3728 u32 arg3;
3729 u32 arg4;
3730 u32 arg5;
3731} __packed;
3732
3733struct wcn36xx_hal_dump_cmd_rsp_msg {
3734 struct wcn36xx_hal_msg_header header;
3735
3736
3737 u32 status;
3738
3739
3740 u32 rsp_length;
3741
3742
3743
3744 u8 rsp_buffer[DUMPCMD_RSP_BUFFER];
3745} __packed;
3746
3747#define WLAN_COEX_IND_DATA_SIZE (4)
3748#define WLAN_COEX_IND_TYPE_DISABLE_HB_MONITOR (0)
3749#define WLAN_COEX_IND_TYPE_ENABLE_HB_MONITOR (1)
3750
3751struct coex_ind_msg {
3752 struct wcn36xx_hal_msg_header header;
3753
3754
3755 u32 type;
3756
3757
3758 u32 data[WLAN_COEX_IND_DATA_SIZE];
3759};
3760
3761struct wcn36xx_hal_tx_compl_ind_msg {
3762 struct wcn36xx_hal_msg_header header;
3763
3764
3765 u32 status;
3766};
3767
3768struct wcn36xx_hal_wlan_host_suspend_ind_msg {
3769 struct wcn36xx_hal_msg_header header;
3770
3771 u32 configured_mcst_bcst_filter_setting;
3772 u32 active_session_count;
3773};
3774
3775struct wcn36xx_hal_wlan_exclude_unencrpted_ind_msg {
3776 struct wcn36xx_hal_msg_header header;
3777
3778 u8 dot11_exclude_unencrypted;
3779 u8 bssid[ETH_ALEN];
3780};
3781
3782struct noa_attr_ind_msg {
3783 struct wcn36xx_hal_msg_header header;
3784
3785 u8 index;
3786 u8 opp_ps_flag;
3787 u16 ctwin;
3788
3789 u16 noa1_interval_count;
3790 u16 bss_index;
3791 u32 noa1_duration;
3792 u32 noa1_interval;
3793 u32 noa1_starttime;
3794
3795 u16 noa2_interval_count;
3796 u16 reserved2;
3797 u32 noa2_duration;
3798 u32 noa2_interval;
3799 u32 noa2_start_time;
3800
3801 u32 status;
3802};
3803
3804struct noa_start_ind_msg {
3805 struct wcn36xx_hal_msg_header header;
3806
3807 u32 status;
3808 u32 bss_index;
3809};
3810
3811struct wcn36xx_hal_wlan_host_resume_req_msg {
3812 struct wcn36xx_hal_msg_header header;
3813
3814 u8 configured_mcst_bcst_filter_setting;
3815};
3816
3817struct wcn36xx_hal_host_resume_rsp_msg {
3818 struct wcn36xx_hal_msg_header header;
3819
3820
3821 u32 status;
3822};
3823
3824struct wcn36xx_hal_del_ba_ind_msg {
3825 struct wcn36xx_hal_msg_header header;
3826
3827 u16 sta_idx;
3828
3829
3830 u8 peer_addr[ETH_ALEN];
3831
3832
3833 u8 ba_tid;
3834
3835
3836
3837
3838
3839 u8 direction;
3840
3841 u32 reason_code;
3842
3843
3844 u8 bssid[ETH_ALEN];
3845};
3846
3847
3848
3849
3850#define WCN36XX_HAL_PNO_MAX_NETW_CHANNELS 26
3851
3852
3853#define WCN36XX_HAL_PNO_MAX_NETW_CHANNELS_EX 60
3854
3855
3856#define WCN36XX_HAL_PNO_MAX_SUPP_NETWORKS 16
3857
3858
3859#define WCN36XX_HAL_PNO_MAX_SCAN_TIMERS 10
3860
3861
3862#define WCN36XX_HAL_PNO_MAX_PROBE_SIZE 450
3863
3864
3865
3866
3867
3868
3869
3870
3871
3872
3873enum pno_mode {
3874 PNO_MODE_IMMEDIATE,
3875 PNO_MODE_ON_SUSPEND,
3876 PNO_MODE_ON_RESUME,
3877 PNO_MODE_MAX = WCN36XX_HAL_MAX_ENUM_SIZE
3878};
3879
3880
3881enum auth_type {
3882 AUTH_TYPE_ANY = 0,
3883 AUTH_TYPE_OPEN_SYSTEM = 1,
3884
3885
3886 AUTH_TYPE_WPA = 2,
3887 AUTH_TYPE_WPA_PSK = 3,
3888
3889 AUTH_TYPE_RSN = 4,
3890 AUTH_TYPE_RSN_PSK = 5,
3891 AUTH_TYPE_FT_RSN = 6,
3892 AUTH_TYPE_FT_RSN_PSK = 7,
3893 AUTH_TYPE_WAPI_WAI_CERTIFICATE = 8,
3894 AUTH_TYPE_WAPI_WAI_PSK = 9,
3895
3896 AUTH_TYPE_MAX = WCN36XX_HAL_MAX_ENUM_SIZE
3897};
3898
3899
3900enum ed_type {
3901 ED_ANY = 0,
3902 ED_NONE = 1,
3903 ED_WEP = 2,
3904 ED_TKIP = 3,
3905 ED_CCMP = 4,
3906 ED_WPI = 5,
3907
3908 ED_TYPE_MAX = WCN36XX_HAL_MAX_ENUM_SIZE
3909};
3910
3911
3912enum ssid_bcast_type {
3913 BCAST_UNKNOWN = 0,
3914 BCAST_NORMAL = 1,
3915 BCAST_HIDDEN = 2,
3916
3917 BCAST_TYPE_MAX = WCN36XX_HAL_MAX_ENUM_SIZE
3918};
3919
3920
3921struct network_type {
3922
3923 struct wcn36xx_hal_mac_ssid ssid;
3924
3925
3926 enum auth_type authentication;
3927
3928
3929 enum ed_type encryption;
3930
3931
3932
3933 u8 channel_count;
3934 u8 channels[WCN36XX_HAL_PNO_MAX_NETW_CHANNELS];
3935
3936
3937 u8 rssi_threshold;
3938};
3939
3940struct scan_timer {
3941
3942 u32 value;
3943
3944
3945
3946 u32 repeat;
3947
3948
3949
3950
3951};
3952
3953
3954struct scan_timers_type {
3955
3956 u8 count;
3957
3958
3959
3960
3961
3962
3963
3964
3965 struct scan_timer values[WCN36XX_HAL_PNO_MAX_SCAN_TIMERS];
3966};
3967
3968
3969struct set_pref_netw_list_req {
3970 struct wcn36xx_hal_msg_header header;
3971
3972
3973 u32 enable;
3974
3975
3976 enum pno_mode mode;
3977
3978
3979 u32 networks_count;
3980
3981
3982 struct network_type networks[WCN36XX_HAL_PNO_MAX_SUPP_NETWORKS];
3983
3984
3985 struct scan_timers_type scan_timers;
3986
3987
3988 u16 band_24g_probe_size;
3989 u8 band_24g_probe_template[WCN36XX_HAL_PNO_MAX_PROBE_SIZE];
3990
3991
3992 u16 band_5g_probe_size;
3993 u8 band_5g_probe_template[WCN36XX_HAL_PNO_MAX_PROBE_SIZE];
3994};
3995
3996
3997struct network_type_new {
3998
3999 struct wcn36xx_hal_mac_ssid ssid;
4000
4001
4002 enum auth_type authentication;
4003
4004
4005 enum ed_type encryption;
4006
4007
4008 enum ssid_bcast_type bcast_network_type;
4009
4010
4011
4012 u8 channel_count;
4013 u8 channels[WCN36XX_HAL_PNO_MAX_NETW_CHANNELS];
4014
4015
4016 u8 rssi_threshold;
4017};
4018
4019
4020struct set_pref_netw_list_req_new {
4021 struct wcn36xx_hal_msg_header header;
4022
4023
4024 u32 enable;
4025
4026
4027 enum pno_mode mode;
4028
4029
4030 u32 networks_count;
4031
4032
4033 struct network_type_new networks[WCN36XX_HAL_PNO_MAX_SUPP_NETWORKS];
4034
4035
4036 struct scan_timers_type scan_timers;
4037
4038
4039 u16 band_24g_probe_size;
4040 u8 band_24g_probe_template[WCN36XX_HAL_PNO_MAX_PROBE_SIZE];
4041
4042
4043 u16 band_5g_probe_size;
4044 u8 band_5g_probe_template[WCN36XX_HAL_PNO_MAX_PROBE_SIZE];
4045};
4046
4047
4048struct set_pref_netw_list_resp {
4049 struct wcn36xx_hal_msg_header header;
4050
4051
4052
4053 u32 status;
4054};
4055
4056
4057struct pref_netw_found_ind {
4058
4059 struct wcn36xx_hal_msg_header header;
4060
4061
4062 struct wcn36xx_hal_mac_ssid ssid;
4063
4064
4065 u8 rssi;
4066};
4067
4068
4069struct set_rssi_filter_req {
4070 struct wcn36xx_hal_msg_header header;
4071
4072
4073 u8 rssi_threshold;
4074};
4075
4076
4077struct set_rssi_filter_resp {
4078 struct wcn36xx_hal_msg_header header;
4079
4080
4081 u32 status;
4082};
4083
4084
4085
4086struct wcn36xx_hal_update_scan_params_req {
4087
4088 struct wcn36xx_hal_msg_header header;
4089
4090
4091 u8 dot11d_enabled;
4092
4093
4094 u8 dot11d_resolved;
4095
4096
4097 u8 channel_count;
4098 u8 channels[WCN36XX_HAL_PNO_MAX_NETW_CHANNELS];
4099
4100
4101 u16 active_min_ch_time;
4102
4103
4104 u16 active_max_ch_time;
4105
4106
4107 u16 passive_min_ch_time;
4108
4109
4110 u16 passive_max_ch_time;
4111
4112
4113 enum phy_chan_bond_state state;
4114} __packed;
4115
4116
4117
4118struct update_scan_params_req_ex {
4119
4120 struct wcn36xx_hal_msg_header header;
4121
4122
4123 u8 dot11d_enabled;
4124
4125
4126 u8 dot11d_resolved;
4127
4128
4129 u8 channel_count;
4130 u8 channels[WCN36XX_HAL_PNO_MAX_NETW_CHANNELS_EX];
4131
4132
4133 u16 active_min_ch_time;
4134
4135
4136 u16 active_max_ch_time;
4137
4138
4139 u16 passive_min_ch_time;
4140
4141
4142 u16 passive_max_ch_time;
4143
4144
4145 enum phy_chan_bond_state state;
4146};
4147
4148
4149
4150struct wcn36xx_hal_update_scan_params_resp {
4151
4152 struct wcn36xx_hal_msg_header header;
4153
4154
4155 u32 status;
4156} __packed;
4157
4158struct wcn36xx_hal_set_tx_per_tracking_req_msg {
4159 struct wcn36xx_hal_msg_header header;
4160
4161
4162 u8 tx_per_tracking_enable;
4163
4164
4165 u8 tx_per_tracking_period;
4166
4167
4168 u8 tx_per_tracking_ratio;
4169
4170
4171
4172 u32 tx_per_tracking_watermark;
4173};
4174
4175struct wcn36xx_hal_set_tx_per_tracking_rsp_msg {
4176 struct wcn36xx_hal_msg_header header;
4177
4178
4179 u32 status;
4180
4181};
4182
4183struct tx_per_hit_ind_msg {
4184 struct wcn36xx_hal_msg_header header;
4185};
4186
4187
4188#define WCN36XX_HAL_PROTOCOL_DATA_LEN 8
4189#define WCN36XX_HAL_MAX_NUM_MULTICAST_ADDRESS 240
4190#define WCN36XX_HAL_MAX_NUM_FILTERS 20
4191#define WCN36XX_HAL_MAX_CMP_PER_FILTER 10
4192
4193enum wcn36xx_hal_receive_packet_filter_type {
4194 HAL_RCV_FILTER_TYPE_INVALID,
4195 HAL_RCV_FILTER_TYPE_FILTER_PKT,
4196 HAL_RCV_FILTER_TYPE_BUFFER_PKT,
4197 HAL_RCV_FILTER_TYPE_MAX_ENUM_SIZE
4198};
4199
4200enum wcn36xx_hal_rcv_pkt_flt_protocol_type {
4201 HAL_FILTER_PROTO_TYPE_INVALID,
4202 HAL_FILTER_PROTO_TYPE_MAC,
4203 HAL_FILTER_PROTO_TYPE_ARP,
4204 HAL_FILTER_PROTO_TYPE_IPV4,
4205 HAL_FILTER_PROTO_TYPE_IPV6,
4206 HAL_FILTER_PROTO_TYPE_UDP,
4207 HAL_FILTER_PROTO_TYPE_MAX
4208};
4209
4210enum wcn36xx_hal_rcv_pkt_flt_cmp_flag_type {
4211 HAL_FILTER_CMP_TYPE_INVALID,
4212 HAL_FILTER_CMP_TYPE_EQUAL,
4213 HAL_FILTER_CMP_TYPE_MASK_EQUAL,
4214 HAL_FILTER_CMP_TYPE_NOT_EQUAL,
4215 HAL_FILTER_CMP_TYPE_MAX
4216};
4217
4218struct wcn36xx_hal_rcv_pkt_filter_params {
4219 u8 protocol_layer;
4220 u8 cmp_flag;
4221
4222
4223 u16 data_length;
4224
4225
4226 u8 data_offset;
4227
4228
4229 u8 reserved;
4230
4231
4232 u8 compare_data[WCN36XX_HAL_PROTOCOL_DATA_LEN];
4233
4234
4235 u8 data_mask[WCN36XX_HAL_PROTOCOL_DATA_LEN];
4236};
4237
4238struct wcn36xx_hal_sessionized_rcv_pkt_filter_cfg_type {
4239 u8 id;
4240 u8 type;
4241 u8 params_count;
4242 u32 coleasce_time;
4243 u8 bss_index;
4244 struct wcn36xx_hal_rcv_pkt_filter_params params[1];
4245};
4246
4247struct wcn36xx_hal_set_rcv_pkt_filter_req_msg {
4248 struct wcn36xx_hal_msg_header header;
4249
4250 u8 id;
4251 u8 type;
4252 u8 params_count;
4253 u32 coalesce_time;
4254 struct wcn36xx_hal_rcv_pkt_filter_params params[1];
4255};
4256
4257struct wcn36xx_hal_rcv_flt_mc_addr_list_type {
4258
4259 u8 data_offset;
4260
4261 u32 mc_addr_count;
4262 u8 mc_addr[ETH_ALEN][WCN36XX_HAL_MAX_NUM_MULTICAST_ADDRESS];
4263 u8 bss_index;
4264};
4265
4266struct wcn36xx_hal_set_pkt_filter_rsp_msg {
4267 struct wcn36xx_hal_msg_header header;
4268
4269
4270 u32 status;
4271
4272 u8 bss_index;
4273};
4274
4275struct wcn36xx_hal_rcv_flt_pkt_match_cnt_req_msg {
4276 struct wcn36xx_hal_msg_header header;
4277
4278 u8 bss_index;
4279};
4280
4281struct wcn36xx_hal_rcv_flt_pkt_match_cnt {
4282 u8 id;
4283 u32 match_cnt;
4284};
4285
4286struct wcn36xx_hal_rcv_flt_pkt_match_cnt_rsp_msg {
4287 struct wcn36xx_hal_msg_header header;
4288
4289
4290 u32 status;
4291
4292 u32 match_count;
4293 struct wcn36xx_hal_rcv_flt_pkt_match_cnt
4294 matches[WCN36XX_HAL_MAX_NUM_FILTERS];
4295 u8 bss_index;
4296};
4297
4298struct wcn36xx_hal_rcv_flt_pkt_clear_param {
4299
4300 u32 status;
4301 u8 id;
4302 u8 bss_index;
4303};
4304
4305struct wcn36xx_hal_rcv_flt_pkt_clear_req_msg {
4306 struct wcn36xx_hal_msg_header header;
4307 struct wcn36xx_hal_rcv_flt_pkt_clear_param param;
4308};
4309
4310struct wcn36xx_hal_rcv_flt_pkt_clear_rsp_msg {
4311 struct wcn36xx_hal_msg_header header;
4312 struct wcn36xx_hal_rcv_flt_pkt_clear_param param;
4313};
4314
4315struct wcn36xx_hal_rcv_flt_pkt_set_mc_list_req_msg {
4316 struct wcn36xx_hal_msg_header header;
4317 struct wcn36xx_hal_rcv_flt_mc_addr_list_type mc_addr_list;
4318};
4319
4320struct wcn36xx_hal_rcv_flt_pkt_set_mc_list_rsp_msg {
4321 struct wcn36xx_hal_msg_header header;
4322 u32 status;
4323 u8 bss_index;
4324};
4325
4326
4327
4328struct wcn36xx_hal_set_power_params_req_msg {
4329 struct wcn36xx_hal_msg_header header;
4330
4331
4332 u32 ignore_dtim;
4333
4334
4335 u32 dtim_period;
4336
4337
4338 u32 listen_interval;
4339
4340
4341 u32 bcast_mcast_filter;
4342
4343
4344 u32 enable_bet;
4345
4346
4347 u32 bet_interval;
4348} __packed;
4349
4350struct wcn36xx_hal_set_power_params_resp {
4351
4352 struct wcn36xx_hal_msg_header header;
4353
4354
4355 u32 status;
4356} __packed;
4357
4358
4359
4360enum place_holder_in_cap_bitmap {
4361 MCC = 0,
4362 P2P = 1,
4363 DOT11AC = 2,
4364 SLM_SESSIONIZATION = 3,
4365 DOT11AC_OPMODE = 4,
4366 SAP32STA = 5,
4367 TDLS = 6,
4368 P2P_GO_NOA_DECOUPLE_INIT_SCAN = 7,
4369 WLANACTIVE_OFFLOAD = 8,
4370 BEACON_OFFLOAD = 9,
4371 SCAN_OFFLOAD = 10,
4372 ROAM_OFFLOAD = 11,
4373 BCN_MISS_OFFLOAD = 12,
4374 STA_POWERSAVE = 13,
4375 STA_ADVANCED_PWRSAVE = 14,
4376 AP_UAPSD = 15,
4377 AP_DFS = 16,
4378 BLOCKACK = 17,
4379 PHY_ERR = 18,
4380 BCN_FILTER = 19,
4381 RTT = 20,
4382 RATECTRL = 21,
4383 WOW = 22,
4384 MAX_FEATURE_SUPPORTED = 128,
4385};
4386
4387#define WCN36XX_HAL_CAPS_SIZE 4
4388
4389struct wcn36xx_hal_feat_caps_msg {
4390
4391 struct wcn36xx_hal_msg_header header;
4392
4393 u32 feat_caps[WCN36XX_HAL_CAPS_SIZE];
4394} __packed;
4395
4396
4397enum gtk_rekey_status {
4398 WCN36XX_HAL_GTK_REKEY_STATUS_SUCCESS = 0,
4399
4400
4401 WCN36XX_HAL_GTK_REKEY_STATUS_NOT_HANDLED = 1,
4402
4403
4404 WCN36XX_HAL_GTK_REKEY_STATUS_MIC_ERROR = 2,
4405
4406
4407 WCN36XX_HAL_GTK_REKEY_STATUS_DECRYPT_ERROR = 3,
4408
4409
4410 WCN36XX_HAL_GTK_REKEY_STATUS_REPLAY_ERROR = 4,
4411
4412
4413 WCN36XX_HAL_GTK_REKEY_STATUS_MISSING_KDE = 5,
4414
4415
4416 WCN36XX_HAL_GTK_REKEY_STATUS_MISSING_IGTK_KDE = 6,
4417
4418
4419 WCN36XX_HAL_GTK_REKEY_STATUS_INSTALL_ERROR = 7,
4420
4421
4422 WCN36XX_HAL_GTK_REKEY_STATUS_IGTK_INSTALL_ERROR = 8,
4423
4424
4425 WCN36XX_HAL_GTK_REKEY_STATUS_RESP_TX_ERROR = 9,
4426
4427
4428 WCN36XX_HAL_GTK_REKEY_STATUS_GEN_ERROR = 255
4429};
4430
4431
4432enum wake_reason_type {
4433 WCN36XX_HAL_WAKE_REASON_NONE = 0,
4434
4435
4436 WCN36XX_HAL_WAKE_REASON_MAGIC_PACKET = 1,
4437
4438
4439 WCN36XX_HAL_WAKE_REASON_PATTERN_MATCH = 2,
4440
4441
4442 WCN36XX_HAL_WAKE_REASON_EAPID_PACKET = 3,
4443
4444
4445 WCN36XX_HAL_WAKE_REASON_EAPOL4WAY_PACKET = 4,
4446
4447
4448 WCN36XX_HAL_WAKE_REASON_NETSCAN_OFFL_MATCH = 5,
4449
4450
4451 WCN36XX_HAL_WAKE_REASON_GTK_REKEY_STATUS = 6,
4452
4453
4454 WCN36XX_HAL_WAKE_REASON_BSS_CONN_LOST = 7,
4455};
4456
4457
4458
4459
4460
4461
4462
4463
4464
4465
4466
4467
4468
4469
4470
4471
4472struct wcn36xx_hal_wake_reason_ind {
4473 struct wcn36xx_hal_msg_header header;
4474
4475
4476 u32 reason;
4477
4478
4479 u32 reason_arg;
4480
4481
4482
4483
4484 u32 stored_data_len;
4485
4486
4487 u32 actual_data_len;
4488
4489
4490
4491 u8 data_start[1];
4492
4493 u32 bss_index:8;
4494 u32 reserved:24;
4495};
4496
4497#define WCN36XX_HAL_GTK_KEK_BYTES 16
4498#define WCN36XX_HAL_GTK_KCK_BYTES 16
4499
4500#define WCN36XX_HAL_GTK_OFFLOAD_FLAGS_DISABLE (1 << 0)
4501
4502#define GTK_SET_BSS_KEY_TAG 0x1234AA55
4503
4504struct wcn36xx_hal_gtk_offload_req_msg {
4505 struct wcn36xx_hal_msg_header header;
4506
4507
4508 u32 flags;
4509
4510
4511 u8 kck[WCN36XX_HAL_GTK_KCK_BYTES];
4512
4513
4514 u8 kek[WCN36XX_HAL_GTK_KEK_BYTES];
4515
4516
4517 u64 key_replay_counter;
4518
4519 u8 bss_index;
4520};
4521
4522struct wcn36xx_hal_gtk_offload_rsp_msg {
4523 struct wcn36xx_hal_msg_header header;
4524
4525
4526 u32 status;
4527
4528 u8 bss_index;
4529};
4530
4531struct wcn36xx_hal_gtk_offload_get_info_req_msg {
4532 struct wcn36xx_hal_msg_header header;
4533 u8 bss_index;
4534};
4535
4536struct wcn36xx_hal_gtk_offload_get_info_rsp_msg {
4537 struct wcn36xx_hal_msg_header header;
4538
4539
4540 u32 status;
4541
4542
4543 u32 last_rekey_status;
4544
4545
4546 u64 key_replay_counter;
4547
4548
4549 u32 total_rekey_count;
4550
4551
4552 u32 gtk_rekey_count;
4553
4554
4555 u32 igtk_rekey_count;
4556
4557 u8 bss_index;
4558};
4559
4560struct dhcp_info {
4561
4562 u8 device_mode;
4563
4564 u8 addr[ETH_ALEN];
4565};
4566
4567struct dhcp_ind_status {
4568 struct wcn36xx_hal_msg_header header;
4569
4570
4571 u32 status;
4572};
4573
4574
4575
4576
4577
4578
4579
4580
4581
4582
4583enum wcn36xx_hal_thermal_mitigation_mode_type {
4584 HAL_THERMAL_MITIGATION_MODE_INVALID = -1,
4585 HAL_THERMAL_MITIGATION_MODE_0,
4586 HAL_THERMAL_MITIGATION_MODE_1,
4587 HAL_THERMAL_MITIGATION_MODE_2,
4588 HAL_THERMAL_MITIGATION_MODE_MAX = WCN36XX_HAL_MAX_ENUM_SIZE,
4589};
4590
4591
4592
4593
4594
4595
4596
4597
4598
4599
4600
4601
4602
4603
4604
4605
4606
4607
4608
4609enum wcn36xx_hal_thermal_mitigation_level_type {
4610 HAL_THERMAL_MITIGATION_LEVEL_INVALID = -1,
4611 HAL_THERMAL_MITIGATION_LEVEL_0,
4612 HAL_THERMAL_MITIGATION_LEVEL_1,
4613 HAL_THERMAL_MITIGATION_LEVEL_2,
4614 HAL_THERMAL_MITIGATION_LEVEL_3,
4615 HAL_THERMAL_MITIGATION_LEVEL_4,
4616 HAL_THERMAL_MITIGATION_LEVEL_MAX = WCN36XX_HAL_MAX_ENUM_SIZE,
4617};
4618
4619
4620
4621struct set_thermal_mitigation_req_msg {
4622 struct wcn36xx_hal_msg_header header;
4623
4624
4625 enum wcn36xx_hal_thermal_mitigation_mode_type mode;
4626
4627
4628 enum wcn36xx_hal_thermal_mitigation_level_type level;
4629};
4630
4631struct set_thermal_mitigation_resp {
4632
4633 struct wcn36xx_hal_msg_header header;
4634
4635
4636 u32 status;
4637};
4638
4639
4640
4641struct stats_class_b_ind {
4642 struct wcn36xx_hal_msg_header header;
4643
4644
4645 u32 duration;
4646
4647
4648
4649
4650 u32 tx_bytes_pushed;
4651 u32 tx_packets_pushed;
4652
4653
4654 u32 rx_bytes_rcvd;
4655 u32 rx_packets_rcvd;
4656 u32 rx_time_total;
4657};
4658
4659#endif
4660