1#ifndef HOSTAP_WLAN_H
2#define HOSTAP_WLAN_H
3
4#include <linux/interrupt.h>
5#include <linux/wireless.h>
6#include <linux/netdevice.h>
7#include <linux/etherdevice.h>
8#include <linux/mutex.h>
9#include <net/iw_handler.h>
10#include <net/ieee80211_radiotap.h>
11#include <net/lib80211.h>
12
13#include "hostap_config.h"
14#include "hostap_common.h"
15
16#define MAX_PARM_DEVICES 8
17#define PARM_MIN_MAX "1-" __MODULE_STRING(MAX_PARM_DEVICES)
18#define DEF_INTS -1, -1, -1, -1, -1, -1, -1
19#define GET_INT_PARM(var,idx) var[var[idx] < 0 ? 0 : idx]
20
21
22
23
24
25
26
27
28#define ETH_P_HOSTAP ETH_P_CONTROL
29
30
31
32struct linux_wlan_ng_val {
33 u32 did;
34 u16 status, len;
35 u32 data;
36} __packed;
37
38struct linux_wlan_ng_prism_hdr {
39 u32 msgcode, msglen;
40 char devname[16];
41 struct linux_wlan_ng_val hosttime, mactime, channel, rssi, sq, signal,
42 noise, rate, istx, frmlen;
43} __packed;
44
45struct linux_wlan_ng_cap_hdr {
46 __be32 version;
47 __be32 length;
48 __be64 mactime;
49 __be64 hosttime;
50 __be32 phytype;
51 __be32 channel;
52 __be32 datarate;
53 __be32 antenna;
54 __be32 priority;
55 __be32 ssi_type;
56 __be32 ssi_signal;
57 __be32 ssi_noise;
58 __be32 preamble;
59 __be32 encoding;
60} __packed;
61
62struct hostap_radiotap_rx {
63 struct ieee80211_radiotap_header hdr;
64 __le64 tsft;
65 u8 rate;
66 u8 padding;
67 __le16 chan_freq;
68 __le16 chan_flags;
69 s8 dbm_antsignal;
70 s8 dbm_antnoise;
71} __packed;
72
73#define LWNG_CAP_DID_BASE (4 | (1 << 6))
74#define LWNG_CAPHDR_VERSION 0x80211001
75
76struct hfa384x_rx_frame {
77
78 __le16 status;
79 __le32 time;
80 u8 silence;
81 u8 signal;
82 u8 rate;
83 u8 rxflow;
84 __le32 reserved;
85
86
87 __le16 frame_control;
88 __le16 duration_id;
89 u8 addr1[ETH_ALEN];
90 u8 addr2[ETH_ALEN];
91 u8 addr3[ETH_ALEN];
92 __le16 seq_ctrl;
93 u8 addr4[ETH_ALEN];
94 __le16 data_len;
95
96
97 u8 dst_addr[ETH_ALEN];
98 u8 src_addr[ETH_ALEN];
99 __be16 len;
100
101
102} __packed;
103
104
105struct hfa384x_tx_frame {
106
107 __le16 status;
108 __le16 reserved1;
109 __le16 reserved2;
110 __le32 sw_support;
111 u8 retry_count;
112 u8 tx_rate;
113 __le16 tx_control;
114
115
116 __le16 frame_control;
117 __le16 duration_id;
118 u8 addr1[ETH_ALEN];
119 u8 addr2[ETH_ALEN];
120 u8 addr3[ETH_ALEN];
121 __le16 seq_ctrl;
122 u8 addr4[ETH_ALEN];
123 __le16 data_len;
124
125
126 u8 dst_addr[ETH_ALEN];
127 u8 src_addr[ETH_ALEN];
128 __be16 len;
129
130
131} __packed;
132
133
134struct hfa384x_rid_hdr
135{
136 __le16 len;
137 __le16 rid;
138} __packed;
139
140
141
142
143#define HFA384X_LEVEL_TO_dBm(v) 0x100 + (v) * 100 / 255 - 100
144
145#define HFA384X_LEVEL_TO_dBm_sign(v) (v) * 100 / 255 - 100
146
147struct hfa384x_scan_request {
148 __le16 channel_list;
149 __le16 txrate;
150} __packed;
151
152struct hfa384x_hostscan_request {
153 __le16 channel_list;
154 __le16 txrate;
155 __le16 target_ssid_len;
156 u8 target_ssid[32];
157} __packed;
158
159struct hfa384x_join_request {
160 u8 bssid[ETH_ALEN];
161 __le16 channel;
162} __packed;
163
164struct hfa384x_info_frame {
165 __le16 len;
166 __le16 type;
167} __packed;
168
169struct hfa384x_comm_tallies {
170 __le16 tx_unicast_frames;
171 __le16 tx_multicast_frames;
172 __le16 tx_fragments;
173 __le16 tx_unicast_octets;
174 __le16 tx_multicast_octets;
175 __le16 tx_deferred_transmissions;
176 __le16 tx_single_retry_frames;
177 __le16 tx_multiple_retry_frames;
178 __le16 tx_retry_limit_exceeded;
179 __le16 tx_discards;
180 __le16 rx_unicast_frames;
181 __le16 rx_multicast_frames;
182 __le16 rx_fragments;
183 __le16 rx_unicast_octets;
184 __le16 rx_multicast_octets;
185 __le16 rx_fcs_errors;
186 __le16 rx_discards_no_buffer;
187 __le16 tx_discards_wrong_sa;
188 __le16 rx_discards_wep_undecryptable;
189 __le16 rx_message_in_msg_fragments;
190 __le16 rx_message_in_bad_msg_fragments;
191} __packed;
192
193struct hfa384x_comm_tallies32 {
194 __le32 tx_unicast_frames;
195 __le32 tx_multicast_frames;
196 __le32 tx_fragments;
197 __le32 tx_unicast_octets;
198 __le32 tx_multicast_octets;
199 __le32 tx_deferred_transmissions;
200 __le32 tx_single_retry_frames;
201 __le32 tx_multiple_retry_frames;
202 __le32 tx_retry_limit_exceeded;
203 __le32 tx_discards;
204 __le32 rx_unicast_frames;
205 __le32 rx_multicast_frames;
206 __le32 rx_fragments;
207 __le32 rx_unicast_octets;
208 __le32 rx_multicast_octets;
209 __le32 rx_fcs_errors;
210 __le32 rx_discards_no_buffer;
211 __le32 tx_discards_wrong_sa;
212 __le32 rx_discards_wep_undecryptable;
213 __le32 rx_message_in_msg_fragments;
214 __le32 rx_message_in_bad_msg_fragments;
215} __packed;
216
217struct hfa384x_scan_result_hdr {
218 __le16 reserved;
219 __le16 scan_reason;
220#define HFA384X_SCAN_IN_PROGRESS 0
221#define HFA384X_SCAN_HOST_INITIATED 1
222#define HFA384X_SCAN_FIRMWARE_INITIATED 2
223#define HFA384X_SCAN_INQUIRY_FROM_HOST 3
224} __packed;
225
226#define HFA384X_SCAN_MAX_RESULTS 32
227
228struct hfa384x_scan_result {
229 __le16 chid;
230 __le16 anl;
231 __le16 sl;
232 u8 bssid[ETH_ALEN];
233 __le16 beacon_interval;
234 __le16 capability;
235 __le16 ssid_len;
236 u8 ssid[32];
237 u8 sup_rates[10];
238 __le16 rate;
239} __packed;
240
241struct hfa384x_hostscan_result {
242 __le16 chid;
243 __le16 anl;
244 __le16 sl;
245 u8 bssid[ETH_ALEN];
246 __le16 beacon_interval;
247 __le16 capability;
248 __le16 ssid_len;
249 u8 ssid[32];
250 u8 sup_rates[10];
251 __le16 rate;
252 __le16 atim;
253} __packed;
254
255struct comm_tallies_sums {
256 unsigned int tx_unicast_frames;
257 unsigned int tx_multicast_frames;
258 unsigned int tx_fragments;
259 unsigned int tx_unicast_octets;
260 unsigned int tx_multicast_octets;
261 unsigned int tx_deferred_transmissions;
262 unsigned int tx_single_retry_frames;
263 unsigned int tx_multiple_retry_frames;
264 unsigned int tx_retry_limit_exceeded;
265 unsigned int tx_discards;
266 unsigned int rx_unicast_frames;
267 unsigned int rx_multicast_frames;
268 unsigned int rx_fragments;
269 unsigned int rx_unicast_octets;
270 unsigned int rx_multicast_octets;
271 unsigned int rx_fcs_errors;
272 unsigned int rx_discards_no_buffer;
273 unsigned int tx_discards_wrong_sa;
274 unsigned int rx_discards_wep_undecryptable;
275 unsigned int rx_message_in_msg_fragments;
276 unsigned int rx_message_in_bad_msg_fragments;
277};
278
279
280struct hfa384x_regs {
281 u16 cmd;
282 u16 evstat;
283 u16 offset0;
284 u16 offset1;
285 u16 swsupport0;
286};
287
288
289#if defined(PRISM2_PCCARD) || defined(PRISM2_PLX)
290
291#define HFA384X_CMD_OFF 0x00
292#define HFA384X_PARAM0_OFF 0x02
293#define HFA384X_PARAM1_OFF 0x04
294#define HFA384X_PARAM2_OFF 0x06
295#define HFA384X_STATUS_OFF 0x08
296#define HFA384X_RESP0_OFF 0x0A
297#define HFA384X_RESP1_OFF 0x0C
298#define HFA384X_RESP2_OFF 0x0E
299#define HFA384X_INFOFID_OFF 0x10
300#define HFA384X_CONTROL_OFF 0x14
301#define HFA384X_SELECT0_OFF 0x18
302#define HFA384X_SELECT1_OFF 0x1A
303#define HFA384X_OFFSET0_OFF 0x1C
304#define HFA384X_OFFSET1_OFF 0x1E
305#define HFA384X_RXFID_OFF 0x20
306#define HFA384X_ALLOCFID_OFF 0x22
307#define HFA384X_TXCOMPLFID_OFF 0x24
308#define HFA384X_SWSUPPORT0_OFF 0x28
309#define HFA384X_SWSUPPORT1_OFF 0x2A
310#define HFA384X_SWSUPPORT2_OFF 0x2C
311#define HFA384X_EVSTAT_OFF 0x30
312#define HFA384X_INTEN_OFF 0x32
313#define HFA384X_EVACK_OFF 0x34
314#define HFA384X_DATA0_OFF 0x36
315#define HFA384X_DATA1_OFF 0x38
316#define HFA384X_AUXPAGE_OFF 0x3A
317#define HFA384X_AUXOFFSET_OFF 0x3C
318#define HFA384X_AUXDATA_OFF 0x3E
319#endif
320
321#ifdef PRISM2_PCI
322
323#define HFA384X_CMD_OFF 0x00
324#define HFA384X_PARAM0_OFF 0x04
325#define HFA384X_PARAM1_OFF 0x08
326#define HFA384X_PARAM2_OFF 0x0C
327#define HFA384X_STATUS_OFF 0x10
328#define HFA384X_RESP0_OFF 0x14
329#define HFA384X_RESP1_OFF 0x18
330#define HFA384X_RESP2_OFF 0x1C
331#define HFA384X_INFOFID_OFF 0x20
332#define HFA384X_CONTROL_OFF 0x28
333#define HFA384X_SELECT0_OFF 0x30
334#define HFA384X_SELECT1_OFF 0x34
335#define HFA384X_OFFSET0_OFF 0x38
336#define HFA384X_OFFSET1_OFF 0x3C
337#define HFA384X_RXFID_OFF 0x40
338#define HFA384X_ALLOCFID_OFF 0x44
339#define HFA384X_TXCOMPLFID_OFF 0x48
340#define HFA384X_PCICOR_OFF 0x4C
341#define HFA384X_SWSUPPORT0_OFF 0x50
342#define HFA384X_SWSUPPORT1_OFF 0x54
343#define HFA384X_SWSUPPORT2_OFF 0x58
344#define HFA384X_PCIHCR_OFF 0x5C
345#define HFA384X_EVSTAT_OFF 0x60
346#define HFA384X_INTEN_OFF 0x64
347#define HFA384X_EVACK_OFF 0x68
348#define HFA384X_DATA0_OFF 0x6C
349#define HFA384X_DATA1_OFF 0x70
350#define HFA384X_AUXPAGE_OFF 0x74
351#define HFA384X_AUXOFFSET_OFF 0x78
352#define HFA384X_AUXDATA_OFF 0x7C
353#define HFA384X_PCI_M0_ADDRH_OFF 0x80
354#define HFA384X_PCI_M0_ADDRL_OFF 0x84
355#define HFA384X_PCI_M0_LEN_OFF 0x88
356#define HFA384X_PCI_M0_CTL_OFF 0x8C
357#define HFA384X_PCI_STATUS_OFF 0x98
358#define HFA384X_PCI_M1_ADDRH_OFF 0xA0
359#define HFA384X_PCI_M1_ADDRL_OFF 0xA4
360#define HFA384X_PCI_M1_LEN_OFF 0xA8
361#define HFA384X_PCI_M1_CTL_OFF 0xAC
362
363
364
365#define HFA384X_PCI_CTL_FROM_BAP (BIT(5) | BIT(1) | BIT(0))
366#define HFA384X_PCI_CTL_TO_BAP (BIT(5) | BIT(0))
367
368#endif
369
370
371
372#define HFA384X_CMDCODE_INIT 0x00
373#define HFA384X_CMDCODE_ENABLE 0x01
374#define HFA384X_CMDCODE_DISABLE 0x02
375#define HFA384X_CMDCODE_ALLOC 0x0A
376#define HFA384X_CMDCODE_TRANSMIT 0x0B
377#define HFA384X_CMDCODE_INQUIRE 0x11
378#define HFA384X_CMDCODE_ACCESS 0x21
379#define HFA384X_CMDCODE_ACCESS_WRITE (0x21 | BIT(8))
380#define HFA384X_CMDCODE_DOWNLOAD 0x22
381#define HFA384X_CMDCODE_READMIF 0x30
382#define HFA384X_CMDCODE_WRITEMIF 0x31
383#define HFA384X_CMDCODE_TEST 0x38
384
385#define HFA384X_CMDCODE_MASK 0x3F
386
387
388#define HFA384X_TEST_CHANGE_CHANNEL 0x08
389#define HFA384X_TEST_MONITOR 0x0B
390#define HFA384X_TEST_STOP 0x0F
391#define HFA384X_TEST_CFG_BITS 0x15
392#define HFA384X_TEST_CFG_BIT_ALC BIT(3)
393
394#define HFA384X_CMD_BUSY BIT(15)
395
396#define HFA384X_CMD_TX_RECLAIM BIT(8)
397
398#define HFA384X_OFFSET_ERR BIT(14)
399#define HFA384X_OFFSET_BUSY BIT(15)
400
401
402
403#define HFA384X_PROGMODE_DISABLE 0
404#define HFA384X_PROGMODE_ENABLE_VOLATILE 1
405#define HFA384X_PROGMODE_ENABLE_NON_VOLATILE 2
406#define HFA384X_PROGMODE_PROGRAM_NON_VOLATILE 3
407
408#define HFA384X_AUX_MAGIC0 0xfe01
409#define HFA384X_AUX_MAGIC1 0xdc23
410#define HFA384X_AUX_MAGIC2 0xba45
411
412#define HFA384X_AUX_PORT_DISABLED 0
413#define HFA384X_AUX_PORT_DISABLE BIT(14)
414#define HFA384X_AUX_PORT_ENABLE BIT(15)
415#define HFA384X_AUX_PORT_ENABLED (BIT(14) | BIT(15))
416#define HFA384X_AUX_PORT_MASK (BIT(14) | BIT(15))
417
418#define PRISM2_PDA_SIZE 1024
419
420
421
422#define HFA384X_EV_TICK BIT(15)
423#define HFA384X_EV_WTERR BIT(14)
424#define HFA384X_EV_INFDROP BIT(13)
425#ifdef PRISM2_PCI
426#define HFA384X_EV_PCI_M1 BIT(9)
427#define HFA384X_EV_PCI_M0 BIT(8)
428#endif
429#define HFA384X_EV_INFO BIT(7)
430#define HFA384X_EV_DTIM BIT(5)
431#define HFA384X_EV_CMD BIT(4)
432#define HFA384X_EV_ALLOC BIT(3)
433#define HFA384X_EV_TXEXC BIT(2)
434#define HFA384X_EV_TX BIT(1)
435#define HFA384X_EV_RX BIT(0)
436
437
438
439#define HFA384X_INFO_HANDOVERADDR 0xF000
440#define HFA384X_INFO_HANDOVERDEAUTHADDR 0xF001
441#define HFA384X_INFO_COMMTALLIES 0xF100
442#define HFA384X_INFO_SCANRESULTS 0xF101
443#define HFA384X_INFO_CHANNELINFORESULTS 0xF102
444#define HFA384X_INFO_HOSTSCANRESULTS 0xF103
445#define HFA384X_INFO_LINKSTATUS 0xF200
446#define HFA384X_INFO_ASSOCSTATUS 0xF201
447#define HFA384X_INFO_AUTHREQ 0xF202
448#define HFA384X_INFO_PSUSERCNT 0xF203
449#define HFA384X_INFO_KEYIDCHANGED 0xF204
450
451enum { HFA384X_LINKSTATUS_CONNECTED = 1,
452 HFA384X_LINKSTATUS_DISCONNECTED = 2,
453 HFA384X_LINKSTATUS_AP_CHANGE = 3,
454 HFA384X_LINKSTATUS_AP_OUT_OF_RANGE = 4,
455 HFA384X_LINKSTATUS_AP_IN_RANGE = 5,
456 HFA384X_LINKSTATUS_ASSOC_FAILED = 6 };
457
458enum { HFA384X_PORTTYPE_BSS = 1, HFA384X_PORTTYPE_WDS = 2,
459 HFA384X_PORTTYPE_PSEUDO_IBSS = 3, HFA384X_PORTTYPE_IBSS = 0,
460 HFA384X_PORTTYPE_HOSTAP = 6 };
461
462#define HFA384X_RATES_1MBPS BIT(0)
463#define HFA384X_RATES_2MBPS BIT(1)
464#define HFA384X_RATES_5MBPS BIT(2)
465#define HFA384X_RATES_11MBPS BIT(3)
466
467#define HFA384X_ROAMING_FIRMWARE 1
468#define HFA384X_ROAMING_HOST 2
469#define HFA384X_ROAMING_DISABLED 3
470
471#define HFA384X_WEPFLAGS_PRIVACYINVOKED BIT(0)
472#define HFA384X_WEPFLAGS_EXCLUDEUNENCRYPTED BIT(1)
473#define HFA384X_WEPFLAGS_HOSTENCRYPT BIT(4)
474#define HFA384X_WEPFLAGS_HOSTDECRYPT BIT(7)
475
476#define HFA384X_RX_STATUS_MSGTYPE (BIT(15) | BIT(14) | BIT(13))
477#define HFA384X_RX_STATUS_PCF BIT(12)
478#define HFA384X_RX_STATUS_MACPORT (BIT(10) | BIT(9) | BIT(8))
479#define HFA384X_RX_STATUS_UNDECR BIT(1)
480#define HFA384X_RX_STATUS_FCSERR BIT(0)
481
482#define HFA384X_RX_STATUS_GET_MSGTYPE(s) \
483(((s) & HFA384X_RX_STATUS_MSGTYPE) >> 13)
484#define HFA384X_RX_STATUS_GET_MACPORT(s) \
485(((s) & HFA384X_RX_STATUS_MACPORT) >> 8)
486
487enum { HFA384X_RX_MSGTYPE_NORMAL = 0, HFA384X_RX_MSGTYPE_RFC1042 = 1,
488 HFA384X_RX_MSGTYPE_BRIDGETUNNEL = 2, HFA384X_RX_MSGTYPE_MGMT = 4 };
489
490
491#define HFA384X_TX_CTRL_ALT_RTRY BIT(5)
492#define HFA384X_TX_CTRL_802_11 BIT(3)
493#define HFA384X_TX_CTRL_802_3 0
494#define HFA384X_TX_CTRL_TX_EX BIT(2)
495#define HFA384X_TX_CTRL_TX_OK BIT(1)
496
497#define HFA384X_TX_STATUS_RETRYERR BIT(0)
498#define HFA384X_TX_STATUS_AGEDERR BIT(1)
499#define HFA384X_TX_STATUS_DISCON BIT(2)
500#define HFA384X_TX_STATUS_FORMERR BIT(3)
501
502
503#define HFA386X_CR_TX_CONFIGURE 0x12
504#define HFA386X_CR_RX_CONFIGURE 0x14
505#define HFA386X_CR_A_D_TEST_MODES2 0x1A
506#define HFA386X_CR_MANUAL_TX_POWER 0x3E
507#define HFA386X_CR_MEASURED_TX_POWER 0x74
508
509
510#ifdef __KERNEL__
511
512#define PRISM2_TXFID_COUNT 8
513#define PRISM2_DATA_MAXLEN 2304
514#define PRISM2_TXFID_LEN (PRISM2_DATA_MAXLEN + sizeof(struct hfa384x_tx_frame))
515#define PRISM2_TXFID_EMPTY 0xffff
516#define PRISM2_TXFID_RESERVED 0xfffe
517#define PRISM2_DUMMY_FID 0xffff
518#define MAX_SSID_LEN 32
519#define MAX_NAME_LEN 32
520
521#define PRISM2_DUMP_RX_HDR BIT(0)
522#define PRISM2_DUMP_TX_HDR BIT(1)
523#define PRISM2_DUMP_TXEXC_HDR BIT(2)
524
525struct hostap_tx_callback_info {
526 u16 idx;
527 void (*func)(struct sk_buff *, int ok, void *);
528 void *data;
529 struct hostap_tx_callback_info *next;
530};
531
532
533
534
535
536
537#define PRISM2_FRAG_CACHE_LEN 4
538
539struct prism2_frag_entry {
540 unsigned long first_frag_time;
541 unsigned int seq;
542 unsigned int last_frag;
543 struct sk_buff *skb;
544 u8 src_addr[ETH_ALEN];
545 u8 dst_addr[ETH_ALEN];
546};
547
548
549struct hostap_cmd_queue {
550 struct list_head list;
551 wait_queue_head_t compl;
552 volatile enum { CMD_SLEEP, CMD_CALLBACK, CMD_COMPLETED } type;
553 void (*callback)(struct net_device *dev, long context, u16 resp0,
554 u16 res);
555 long context;
556 u16 cmd, param0, param1;
557 u16 resp0, res;
558 volatile int issued, issuing;
559
560 atomic_t usecnt;
561 int del_req;
562};
563
564
565#define HOSTAP_HW_NO_DISABLE BIT(0)
566#define HOSTAP_HW_ENABLE_CMDCOMPL BIT(1)
567
568typedef struct local_info local_info_t;
569
570struct prism2_helper_functions {
571
572
573 int (*card_present)(local_info_t *local);
574 void (*cor_sreset)(local_info_t *local);
575 void (*genesis_reset)(local_info_t *local, int hcr);
576
577
578
579
580
581
582
583
584 int (*cmd)(struct net_device *dev, u16 cmd, u16 param0, u16 *param1,
585 u16 *resp0);
586 void (*read_regs)(struct net_device *dev, struct hfa384x_regs *regs);
587 int (*get_rid)(struct net_device *dev, u16 rid, void *buf, int len,
588 int exact_len);
589 int (*set_rid)(struct net_device *dev, u16 rid, void *buf, int len);
590 int (*hw_enable)(struct net_device *dev, int initial);
591 int (*hw_config)(struct net_device *dev, int initial);
592 void (*hw_reset)(struct net_device *dev);
593 void (*hw_shutdown)(struct net_device *dev, int no_disable);
594 int (*reset_port)(struct net_device *dev);
595 void (*schedule_reset)(local_info_t *local);
596 int (*download)(local_info_t *local,
597 struct prism2_download_param *param);
598 int (*tx)(struct sk_buff *skb, struct net_device *dev);
599 int (*set_tim)(struct net_device *dev, int aid, int set);
600 const struct file_operations *read_aux_fops;
601
602 int need_tx_headroom;
603
604 enum { HOSTAP_HW_PCCARD, HOSTAP_HW_PLX, HOSTAP_HW_PCI } hw_type;
605};
606
607
608struct prism2_download_data {
609 u32 dl_cmd;
610 u32 start_addr;
611 u32 num_areas;
612 struct prism2_download_data_area {
613 u32 addr;
614 u32 len;
615 u8 *data;
616 } data[0];
617};
618
619
620#define HOSTAP_MAX_BSS_COUNT 64
621#define MAX_WPA_IE_LEN 64
622
623struct hostap_bss_info {
624 struct list_head list;
625 unsigned long last_update;
626 unsigned int count;
627 u8 bssid[ETH_ALEN];
628 u16 capab_info;
629 u8 ssid[32];
630 size_t ssid_len;
631 u8 wpa_ie[MAX_WPA_IE_LEN];
632 size_t wpa_ie_len;
633 u8 rsn_ie[MAX_WPA_IE_LEN];
634 size_t rsn_ie_len;
635 int chan;
636 int included;
637};
638
639
640
641
642
643
644struct local_info {
645 struct module *hw_module;
646 int card_idx;
647 int dev_enabled;
648 int master_dev_auto_open;
649 int num_dev_open;
650 struct net_device *dev;
651 struct net_device *ddev;
652 struct list_head hostap_interfaces;
653
654
655 rwlock_t iface_lock;
656
657
658 spinlock_t cmdlock, baplock, lock, irq_init_lock;
659 struct mutex rid_bap_mtx;
660 u16 infofid;
661
662
663 spinlock_t txfidlock;
664 int txfid_len;
665 u16 txfid[PRISM2_TXFID_COUNT];
666
667
668 u16 intransmitfid[PRISM2_TXFID_COUNT];
669 int next_txfid;
670
671 int next_alloc;
672
673
674
675#define HOSTAP_BITS_TRANSMIT 0
676#define HOSTAP_BITS_BAP_TASKLET 1
677#define HOSTAP_BITS_BAP_TASKLET2 2
678 unsigned long bits;
679
680 struct ap_data *ap;
681
682 char essid[MAX_SSID_LEN + 1];
683 char name[MAX_NAME_LEN + 1];
684 int name_set;
685 u16 channel_mask;
686 u16 scan_channel_mask;
687 struct comm_tallies_sums comm_tallies;
688 struct proc_dir_entry *proc;
689 int iw_mode;
690 int pseudo_adhoc;
691
692 char bssid[ETH_ALEN];
693 int channel;
694 int beacon_int;
695 int dtim_period;
696 int mtu;
697 int frame_dump;
698 int fw_tx_rate_control;
699 u16 tx_rate_control;
700 u16 basic_rates;
701 int hw_resetting;
702 int hw_ready;
703 int hw_reset_tries;
704 int hw_downloading;
705 int shutdown;
706 int pri_only;
707 int no_pri;
708 int sram_type;
709
710 enum {
711 PRISM2_TXPOWER_AUTO = 0, PRISM2_TXPOWER_OFF,
712 PRISM2_TXPOWER_FIXED, PRISM2_TXPOWER_UNKNOWN
713 } txpower_type;
714 int txpower;
715
716
717 struct list_head cmd_queue;
718
719
720
721#define HOSTAP_CMD_QUEUE_MAX_LEN 16
722 int cmd_queue_len;
723
724
725
726 struct work_struct reset_queue;
727
728
729 int is_promisc;
730 struct work_struct set_multicast_list_queue;
731
732 struct work_struct set_tim_queue;
733 struct list_head set_tim_list;
734 spinlock_t set_tim_lock;
735
736 int wds_max_connections;
737 int wds_connections;
738#define HOSTAP_WDS_BROADCAST_RA BIT(0)
739#define HOSTAP_WDS_AP_CLIENT BIT(1)
740#define HOSTAP_WDS_STANDARD_FRAME BIT(2)
741 u32 wds_type;
742 u16 tx_control;
743 int manual_retry_count;
744
745
746 struct iw_statistics wstats;
747 unsigned long scan_timestamp;
748 enum {
749 PRISM2_MONITOR_80211 = 0, PRISM2_MONITOR_PRISM = 1,
750 PRISM2_MONITOR_CAPHDR = 2, PRISM2_MONITOR_RADIOTAP = 3
751 } monitor_type;
752 int monitor_allow_fcserr;
753
754 int hostapd;
755
756 int hostapd_sta;
757
758 struct net_device *apdev;
759 struct net_device_stats apdevstats;
760
761 char assoc_ap_addr[ETH_ALEN];
762 struct net_device *stadev;
763 struct net_device_stats stadevstats;
764
765#define WEP_KEYS 4
766#define WEP_KEY_LEN 13
767 struct lib80211_crypt_info crypt_info;
768
769 int open_wep;
770 int host_encrypt;
771 int host_decrypt;
772 int privacy_invoked;
773
774 int fw_encrypt_ok;
775
776 int bcrx_sta_key;
777
778
779 struct prism2_frag_entry frag_cache[PRISM2_FRAG_CACHE_LEN];
780 unsigned int frag_next_idx;
781
782 int ieee_802_1x;
783
784 int antsel_tx, antsel_rx;
785 int rts_threshold;
786 int fragm_threshold;
787 int auth_algs;
788
789 int enh_sec;
790 int tallies32;
791
792 struct prism2_helper_functions *func;
793
794 u8 *pda;
795 int fw_ap;
796#define PRISM2_FW_VER(major, minor, variant) \
797(((major) << 16) | ((minor) << 8) | variant)
798 u32 sta_fw_ver;
799
800
801
802 struct tasklet_struct bap_tasklet;
803
804 struct tasklet_struct info_tasklet;
805 struct sk_buff_head info_list;
806
807
808 struct hostap_tx_callback_info *tx_callback;
809
810
811 struct tasklet_struct rx_tasklet;
812 struct sk_buff_head rx_list;
813
814 struct tasklet_struct sta_tx_exc_tasklet;
815 struct sk_buff_head sta_tx_exc_list;
816
817 int host_roaming;
818 unsigned long last_join_time;
819 struct hfa384x_hostscan_result *last_scan_results;
820 int last_scan_results_count;
821 enum { PRISM2_SCAN, PRISM2_HOSTSCAN } last_scan_type;
822 struct work_struct info_queue;
823 unsigned long pending_info;
824#define PRISM2_INFO_PENDING_LINKSTATUS 0
825#define PRISM2_INFO_PENDING_SCANRESULTS 1
826 int prev_link_status;
827 int prev_linkstatus_connected;
828 u8 preferred_ap[ETH_ALEN];
829
830#ifdef PRISM2_CALLBACK
831 void *callback_data;
832
833
834#endif
835
836 wait_queue_head_t hostscan_wq;
837
838
839 struct timer_list passive_scan_timer;
840 int passive_scan_interval;
841 int passive_scan_channel;
842 enum { PASSIVE_SCAN_WAIT, PASSIVE_SCAN_LISTEN } passive_scan_state;
843
844 struct timer_list tick_timer;
845 unsigned long last_tick_timer;
846 unsigned int sw_tick_stuck;
847
848
849
850 unsigned long last_comms_qual_update;
851 int comms_qual;
852 int avg_signal;
853 int avg_noise;
854 struct work_struct comms_qual_update;
855
856
857 int rssi_to_dBm;
858
859
860 struct list_head bss_list;
861 int num_bss_info;
862 int wpa;
863 int tkip_countermeasures;
864 int drop_unencrypted;
865
866
867 u8 *generic_elem;
868 size_t generic_elem_len;
869
870#ifdef PRISM2_DOWNLOAD_SUPPORT
871
872 struct prism2_download_data *dl_pri;
873 struct prism2_download_data *dl_sec;
874#endif
875
876#ifdef PRISM2_IO_DEBUG
877#define PRISM2_IO_DEBUG_SIZE 10000
878 u32 io_debug[PRISM2_IO_DEBUG_SIZE];
879 int io_debug_head;
880 int io_debug_enabled;
881#endif
882
883
884 void *hw_priv;
885};
886
887
888
889
890
891struct hostap_interface {
892 struct list_head list;
893 struct net_device *dev;
894 struct local_info *local;
895 struct net_device_stats stats;
896 struct iw_spy_data spy_data;
897 struct iw_public_data wireless_data;
898
899 enum {
900 HOSTAP_INTERFACE_MASTER,
901 HOSTAP_INTERFACE_MAIN,
902 HOSTAP_INTERFACE_AP,
903 HOSTAP_INTERFACE_STA,
904 HOSTAP_INTERFACE_WDS,
905 } type;
906
907 union {
908 struct hostap_interface_wds {
909 u8 remote_addr[ETH_ALEN];
910 } wds;
911 } u;
912};
913
914
915#define HOSTAP_SKB_TX_DATA_MAGIC 0xf08a36a2
916
917
918
919
920
921
922
923struct hostap_skb_tx_data {
924 unsigned int __padding_for_default_qdiscs;
925 u32 magic;
926 u8 rate;
927#define HOSTAP_TX_FLAGS_WDS BIT(0)
928#define HOSTAP_TX_FLAGS_BUFFERED_FRAME BIT(1)
929#define HOSTAP_TX_FLAGS_ADD_MOREDATA BIT(2)
930 u8 flags;
931 u16 tx_cb_idx;
932 struct hostap_interface *iface;
933 unsigned long jiffies;
934 unsigned short ethertype;
935};
936
937
938#ifndef PRISM2_NO_DEBUG
939
940#define DEBUG_FID BIT(0)
941#define DEBUG_PS BIT(1)
942#define DEBUG_FLOW BIT(2)
943#define DEBUG_AP BIT(3)
944#define DEBUG_HW BIT(4)
945#define DEBUG_EXTRA BIT(5)
946#define DEBUG_EXTRA2 BIT(6)
947#define DEBUG_PS2 BIT(7)
948#define DEBUG_MASK (DEBUG_PS | DEBUG_AP | DEBUG_HW | DEBUG_EXTRA)
949#define PDEBUG(n, args...) \
950do { if ((n) & DEBUG_MASK) printk(KERN_DEBUG args); } while (0)
951#define PDEBUG2(n, args...) \
952do { if ((n) & DEBUG_MASK) printk(args); } while (0)
953
954#else
955
956#define PDEBUG(n, args...)
957#define PDEBUG2(n, args...)
958
959#endif
960
961enum { BAP0 = 0, BAP1 = 1 };
962
963#define PRISM2_IO_DEBUG_CMD_INB 0
964#define PRISM2_IO_DEBUG_CMD_INW 1
965#define PRISM2_IO_DEBUG_CMD_INSW 2
966#define PRISM2_IO_DEBUG_CMD_OUTB 3
967#define PRISM2_IO_DEBUG_CMD_OUTW 4
968#define PRISM2_IO_DEBUG_CMD_OUTSW 5
969#define PRISM2_IO_DEBUG_CMD_ERROR 6
970#define PRISM2_IO_DEBUG_CMD_INTERRUPT 7
971
972#ifdef PRISM2_IO_DEBUG
973
974#define PRISM2_IO_DEBUG_ENTRY(cmd, reg, value) \
975(((cmd) << 24) | ((reg) << 16) | value)
976
977static inline void prism2_io_debug_add(struct net_device *dev, int cmd,
978 int reg, int value)
979{
980 struct hostap_interface *iface = netdev_priv(dev);
981 local_info_t *local = iface->local;
982
983 if (!local->io_debug_enabled)
984 return;
985
986 local->io_debug[local->io_debug_head] = jiffies & 0xffffffff;
987 if (++local->io_debug_head >= PRISM2_IO_DEBUG_SIZE)
988 local->io_debug_head = 0;
989 local->io_debug[local->io_debug_head] =
990 PRISM2_IO_DEBUG_ENTRY(cmd, reg, value);
991 if (++local->io_debug_head >= PRISM2_IO_DEBUG_SIZE)
992 local->io_debug_head = 0;
993}
994
995
996static inline void prism2_io_debug_error(struct net_device *dev, int err)
997{
998 struct hostap_interface *iface = netdev_priv(dev);
999 local_info_t *local = iface->local;
1000 unsigned long flags;
1001
1002 if (!local->io_debug_enabled)
1003 return;
1004
1005 spin_lock_irqsave(&local->lock, flags);
1006 prism2_io_debug_add(dev, PRISM2_IO_DEBUG_CMD_ERROR, 0, err);
1007 if (local->io_debug_enabled == 1) {
1008 local->io_debug_enabled = 0;
1009 printk(KERN_DEBUG "%s: I/O debug stopped\n", dev->name);
1010 }
1011 spin_unlock_irqrestore(&local->lock, flags);
1012}
1013
1014#else
1015
1016static inline void prism2_io_debug_add(struct net_device *dev, int cmd,
1017 int reg, int value)
1018{
1019}
1020
1021static inline void prism2_io_debug_error(struct net_device *dev, int err)
1022{
1023}
1024
1025#endif
1026
1027
1028#ifdef PRISM2_CALLBACK
1029enum {
1030
1031 PRISM2_CALLBACK_ENABLE,
1032
1033
1034 PRISM2_CALLBACK_DISABLE,
1035
1036
1037 PRISM2_CALLBACK_RX_START, PRISM2_CALLBACK_RX_END,
1038 PRISM2_CALLBACK_TX_START, PRISM2_CALLBACK_TX_END
1039};
1040void prism2_callback(local_info_t *local, int event);
1041#else
1042#define prism2_callback(d, e) do { } while (0)
1043#endif
1044
1045#endif
1046
1047#endif
1048