linux/drivers/net/wireless/iwlegacy/4965-mac.c
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   1/******************************************************************************
   2 *
   3 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
   4 *
   5 * Portions of this file are derived from the ipw3945 project, as well
   6 * as portions of the ieee80211 subsystem header files.
   7 *
   8 * This program is free software; you can redistribute it and/or modify it
   9 * under the terms of version 2 of the GNU General Public License as
  10 * published by the Free Software Foundation.
  11 *
  12 * This program is distributed in the hope that it will be useful, but WITHOUT
  13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15 * more details.
  16 *
  17 * You should have received a copy of the GNU General Public License along with
  18 * this program; if not, write to the Free Software Foundation, Inc.,
  19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20 *
  21 * The full GNU General Public License is included in this distribution in the
  22 * file called LICENSE.
  23 *
  24 * Contact Information:
  25 *  Intel Linux Wireless <ilw@linux.intel.com>
  26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27 *
  28 *****************************************************************************/
  29
  30#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  31
  32#include <linux/kernel.h>
  33#include <linux/module.h>
  34#include <linux/init.h>
  35#include <linux/pci.h>
  36#include <linux/pci-aspm.h>
  37#include <linux/slab.h>
  38#include <linux/dma-mapping.h>
  39#include <linux/delay.h>
  40#include <linux/sched.h>
  41#include <linux/skbuff.h>
  42#include <linux/netdevice.h>
  43#include <linux/firmware.h>
  44#include <linux/etherdevice.h>
  45#include <linux/if_arp.h>
  46
  47#include <net/mac80211.h>
  48
  49#include <asm/div64.h>
  50
  51#define DRV_NAME        "iwl4965"
  52
  53#include "common.h"
  54#include "4965.h"
  55
  56/******************************************************************************
  57 *
  58 * module boiler plate
  59 *
  60 ******************************************************************************/
  61
  62/*
  63 * module name, copyright, version, etc.
  64 */
  65#define DRV_DESCRIPTION "Intel(R) Wireless WiFi 4965 driver for Linux"
  66
  67#ifdef CONFIG_IWLEGACY_DEBUG
  68#define VD "d"
  69#else
  70#define VD
  71#endif
  72
  73#define DRV_VERSION     IWLWIFI_VERSION VD
  74
  75MODULE_DESCRIPTION(DRV_DESCRIPTION);
  76MODULE_VERSION(DRV_VERSION);
  77MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  78MODULE_LICENSE("GPL");
  79MODULE_ALIAS("iwl4965");
  80
  81void
  82il4965_check_abort_status(struct il_priv *il, u8 frame_count, u32 status)
  83{
  84        if (frame_count == 1 && status == TX_STATUS_FAIL_RFKILL_FLUSH) {
  85                IL_ERR("Tx flush command to flush out all frames\n");
  86                if (!test_bit(S_EXIT_PENDING, &il->status))
  87                        queue_work(il->workqueue, &il->tx_flush);
  88        }
  89}
  90
  91/*
  92 * EEPROM
  93 */
  94struct il_mod_params il4965_mod_params = {
  95        .restart_fw = 1,
  96        /* the rest are 0 by default */
  97};
  98
  99void
 100il4965_rx_queue_reset(struct il_priv *il, struct il_rx_queue *rxq)
 101{
 102        unsigned long flags;
 103        int i;
 104        spin_lock_irqsave(&rxq->lock, flags);
 105        INIT_LIST_HEAD(&rxq->rx_free);
 106        INIT_LIST_HEAD(&rxq->rx_used);
 107        /* Fill the rx_used queue with _all_ of the Rx buffers */
 108        for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
 109                /* In the reset function, these buffers may have been allocated
 110                 * to an SKB, so we need to unmap and free potential storage */
 111                if (rxq->pool[i].page != NULL) {
 112                        pci_unmap_page(il->pci_dev, rxq->pool[i].page_dma,
 113                                       PAGE_SIZE << il->hw_params.rx_page_order,
 114                                       PCI_DMA_FROMDEVICE);
 115                        __il_free_pages(il, rxq->pool[i].page);
 116                        rxq->pool[i].page = NULL;
 117                }
 118                list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
 119        }
 120
 121        for (i = 0; i < RX_QUEUE_SIZE; i++)
 122                rxq->queue[i] = NULL;
 123
 124        /* Set us so that we have processed and used all buffers, but have
 125         * not restocked the Rx queue with fresh buffers */
 126        rxq->read = rxq->write = 0;
 127        rxq->write_actual = 0;
 128        rxq->free_count = 0;
 129        spin_unlock_irqrestore(&rxq->lock, flags);
 130}
 131
 132int
 133il4965_rx_init(struct il_priv *il, struct il_rx_queue *rxq)
 134{
 135        u32 rb_size;
 136        const u32 rfdnlog = RX_QUEUE_SIZE_LOG;  /* 256 RBDs */
 137        u32 rb_timeout = 0;
 138
 139        if (il->cfg->mod_params->amsdu_size_8K)
 140                rb_size = FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
 141        else
 142                rb_size = FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
 143
 144        /* Stop Rx DMA */
 145        il_wr(il, FH49_MEM_RCSR_CHNL0_CONFIG_REG, 0);
 146
 147        /* Reset driver's Rx queue write idx */
 148        il_wr(il, FH49_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
 149
 150        /* Tell device where to find RBD circular buffer in DRAM */
 151        il_wr(il, FH49_RSCSR_CHNL0_RBDCB_BASE_REG, (u32) (rxq->bd_dma >> 8));
 152
 153        /* Tell device where in DRAM to update its Rx status */
 154        il_wr(il, FH49_RSCSR_CHNL0_STTS_WPTR_REG, rxq->rb_stts_dma >> 4);
 155
 156        /* Enable Rx DMA
 157         * Direct rx interrupts to hosts
 158         * Rx buffer size 4 or 8k
 159         * RB timeout 0x10
 160         * 256 RBDs
 161         */
 162        il_wr(il, FH49_MEM_RCSR_CHNL0_CONFIG_REG,
 163              FH49_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
 164              FH49_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
 165              FH49_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
 166              rb_size |
 167              (rb_timeout << FH49_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS) |
 168              (rfdnlog << FH49_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
 169
 170        /* Set interrupt coalescing timer to default (2048 usecs) */
 171        il_write8(il, CSR_INT_COALESCING, IL_HOST_INT_TIMEOUT_DEF);
 172
 173        return 0;
 174}
 175
 176static void
 177il4965_set_pwr_vmain(struct il_priv *il)
 178{
 179/*
 180 * (for documentation purposes)
 181 * to set power to V_AUX, do:
 182
 183                if (pci_pme_capable(il->pci_dev, PCI_D3cold))
 184                        il_set_bits_mask_prph(il, APMG_PS_CTRL_REG,
 185                                               APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
 186                                               ~APMG_PS_CTRL_MSK_PWR_SRC);
 187 */
 188
 189        il_set_bits_mask_prph(il, APMG_PS_CTRL_REG,
 190                              APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
 191                              ~APMG_PS_CTRL_MSK_PWR_SRC);
 192}
 193
 194int
 195il4965_hw_nic_init(struct il_priv *il)
 196{
 197        unsigned long flags;
 198        struct il_rx_queue *rxq = &il->rxq;
 199        int ret;
 200
 201        spin_lock_irqsave(&il->lock, flags);
 202        il_apm_init(il);
 203        /* Set interrupt coalescing calibration timer to default (512 usecs) */
 204        il_write8(il, CSR_INT_COALESCING, IL_HOST_INT_CALIB_TIMEOUT_DEF);
 205        spin_unlock_irqrestore(&il->lock, flags);
 206
 207        il4965_set_pwr_vmain(il);
 208        il4965_nic_config(il);
 209
 210        /* Allocate the RX queue, or reset if it is already allocated */
 211        if (!rxq->bd) {
 212                ret = il_rx_queue_alloc(il);
 213                if (ret) {
 214                        IL_ERR("Unable to initialize Rx queue\n");
 215                        return -ENOMEM;
 216                }
 217        } else
 218                il4965_rx_queue_reset(il, rxq);
 219
 220        il4965_rx_replenish(il);
 221
 222        il4965_rx_init(il, rxq);
 223
 224        spin_lock_irqsave(&il->lock, flags);
 225
 226        rxq->need_update = 1;
 227        il_rx_queue_update_write_ptr(il, rxq);
 228
 229        spin_unlock_irqrestore(&il->lock, flags);
 230
 231        /* Allocate or reset and init all Tx and Command queues */
 232        if (!il->txq) {
 233                ret = il4965_txq_ctx_alloc(il);
 234                if (ret)
 235                        return ret;
 236        } else
 237                il4965_txq_ctx_reset(il);
 238
 239        set_bit(S_INIT, &il->status);
 240
 241        return 0;
 242}
 243
 244/**
 245 * il4965_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
 246 */
 247static inline __le32
 248il4965_dma_addr2rbd_ptr(struct il_priv *il, dma_addr_t dma_addr)
 249{
 250        return cpu_to_le32((u32) (dma_addr >> 8));
 251}
 252
 253/**
 254 * il4965_rx_queue_restock - refill RX queue from pre-allocated pool
 255 *
 256 * If there are slots in the RX queue that need to be restocked,
 257 * and we have free pre-allocated buffers, fill the ranks as much
 258 * as we can, pulling from rx_free.
 259 *
 260 * This moves the 'write' idx forward to catch up with 'processed', and
 261 * also updates the memory address in the firmware to reference the new
 262 * target buffer.
 263 */
 264void
 265il4965_rx_queue_restock(struct il_priv *il)
 266{
 267        struct il_rx_queue *rxq = &il->rxq;
 268        struct list_head *element;
 269        struct il_rx_buf *rxb;
 270        unsigned long flags;
 271
 272        spin_lock_irqsave(&rxq->lock, flags);
 273        while (il_rx_queue_space(rxq) > 0 && rxq->free_count) {
 274                /* The overwritten rxb must be a used one */
 275                rxb = rxq->queue[rxq->write];
 276                BUG_ON(rxb && rxb->page);
 277
 278                /* Get next free Rx buffer, remove from free list */
 279                element = rxq->rx_free.next;
 280                rxb = list_entry(element, struct il_rx_buf, list);
 281                list_del(element);
 282
 283                /* Point to Rx buffer via next RBD in circular buffer */
 284                rxq->bd[rxq->write] =
 285                    il4965_dma_addr2rbd_ptr(il, rxb->page_dma);
 286                rxq->queue[rxq->write] = rxb;
 287                rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
 288                rxq->free_count--;
 289        }
 290        spin_unlock_irqrestore(&rxq->lock, flags);
 291        /* If the pre-allocated buffer pool is dropping low, schedule to
 292         * refill it */
 293        if (rxq->free_count <= RX_LOW_WATERMARK)
 294                queue_work(il->workqueue, &il->rx_replenish);
 295
 296        /* If we've added more space for the firmware to place data, tell it.
 297         * Increment device's write pointer in multiples of 8. */
 298        if (rxq->write_actual != (rxq->write & ~0x7)) {
 299                spin_lock_irqsave(&rxq->lock, flags);
 300                rxq->need_update = 1;
 301                spin_unlock_irqrestore(&rxq->lock, flags);
 302                il_rx_queue_update_write_ptr(il, rxq);
 303        }
 304}
 305
 306/**
 307 * il4965_rx_replenish - Move all used packet from rx_used to rx_free
 308 *
 309 * When moving to rx_free an SKB is allocated for the slot.
 310 *
 311 * Also restock the Rx queue via il_rx_queue_restock.
 312 * This is called as a scheduled work item (except for during initialization)
 313 */
 314static void
 315il4965_rx_allocate(struct il_priv *il, gfp_t priority)
 316{
 317        struct il_rx_queue *rxq = &il->rxq;
 318        struct list_head *element;
 319        struct il_rx_buf *rxb;
 320        struct page *page;
 321        dma_addr_t page_dma;
 322        unsigned long flags;
 323        gfp_t gfp_mask = priority;
 324
 325        while (1) {
 326                spin_lock_irqsave(&rxq->lock, flags);
 327                if (list_empty(&rxq->rx_used)) {
 328                        spin_unlock_irqrestore(&rxq->lock, flags);
 329                        return;
 330                }
 331                spin_unlock_irqrestore(&rxq->lock, flags);
 332
 333                if (rxq->free_count > RX_LOW_WATERMARK)
 334                        gfp_mask |= __GFP_NOWARN;
 335
 336                if (il->hw_params.rx_page_order > 0)
 337                        gfp_mask |= __GFP_COMP;
 338
 339                /* Alloc a new receive buffer */
 340                page = alloc_pages(gfp_mask, il->hw_params.rx_page_order);
 341                if (!page) {
 342                        if (net_ratelimit())
 343                                D_INFO("alloc_pages failed, " "order: %d\n",
 344                                       il->hw_params.rx_page_order);
 345
 346                        if (rxq->free_count <= RX_LOW_WATERMARK &&
 347                            net_ratelimit())
 348                                IL_ERR("Failed to alloc_pages with %s. "
 349                                       "Only %u free buffers remaining.\n",
 350                                       priority ==
 351                                       GFP_ATOMIC ? "GFP_ATOMIC" : "GFP_KERNEL",
 352                                       rxq->free_count);
 353                        /* We don't reschedule replenish work here -- we will
 354                         * call the restock method and if it still needs
 355                         * more buffers it will schedule replenish */
 356                        return;
 357                }
 358
 359                /* Get physical address of the RB */
 360                page_dma =
 361                    pci_map_page(il->pci_dev, page, 0,
 362                                 PAGE_SIZE << il->hw_params.rx_page_order,
 363                                 PCI_DMA_FROMDEVICE);
 364                if (unlikely(pci_dma_mapping_error(il->pci_dev, page_dma))) {
 365                        __free_pages(page, il->hw_params.rx_page_order);
 366                        break;
 367                }
 368
 369                spin_lock_irqsave(&rxq->lock, flags);
 370
 371                if (list_empty(&rxq->rx_used)) {
 372                        spin_unlock_irqrestore(&rxq->lock, flags);
 373                        pci_unmap_page(il->pci_dev, page_dma,
 374                                       PAGE_SIZE << il->hw_params.rx_page_order,
 375                                       PCI_DMA_FROMDEVICE);
 376                        __free_pages(page, il->hw_params.rx_page_order);
 377                        return;
 378                }
 379
 380                element = rxq->rx_used.next;
 381                rxb = list_entry(element, struct il_rx_buf, list);
 382                list_del(element);
 383
 384                BUG_ON(rxb->page);
 385
 386                rxb->page = page;
 387                rxb->page_dma = page_dma;
 388                list_add_tail(&rxb->list, &rxq->rx_free);
 389                rxq->free_count++;
 390                il->alloc_rxb_page++;
 391
 392                spin_unlock_irqrestore(&rxq->lock, flags);
 393        }
 394}
 395
 396void
 397il4965_rx_replenish(struct il_priv *il)
 398{
 399        unsigned long flags;
 400
 401        il4965_rx_allocate(il, GFP_KERNEL);
 402
 403        spin_lock_irqsave(&il->lock, flags);
 404        il4965_rx_queue_restock(il);
 405        spin_unlock_irqrestore(&il->lock, flags);
 406}
 407
 408void
 409il4965_rx_replenish_now(struct il_priv *il)
 410{
 411        il4965_rx_allocate(il, GFP_ATOMIC);
 412
 413        il4965_rx_queue_restock(il);
 414}
 415
 416/* Assumes that the skb field of the buffers in 'pool' is kept accurate.
 417 * If an SKB has been detached, the POOL needs to have its SKB set to NULL
 418 * This free routine walks the list of POOL entries and if SKB is set to
 419 * non NULL it is unmapped and freed
 420 */
 421void
 422il4965_rx_queue_free(struct il_priv *il, struct il_rx_queue *rxq)
 423{
 424        int i;
 425        for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
 426                if (rxq->pool[i].page != NULL) {
 427                        pci_unmap_page(il->pci_dev, rxq->pool[i].page_dma,
 428                                       PAGE_SIZE << il->hw_params.rx_page_order,
 429                                       PCI_DMA_FROMDEVICE);
 430                        __il_free_pages(il, rxq->pool[i].page);
 431                        rxq->pool[i].page = NULL;
 432                }
 433        }
 434
 435        dma_free_coherent(&il->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
 436                          rxq->bd_dma);
 437        dma_free_coherent(&il->pci_dev->dev, sizeof(struct il_rb_status),
 438                          rxq->rb_stts, rxq->rb_stts_dma);
 439        rxq->bd = NULL;
 440        rxq->rb_stts = NULL;
 441}
 442
 443int
 444il4965_rxq_stop(struct il_priv *il)
 445{
 446        int ret;
 447
 448        _il_wr(il, FH49_MEM_RCSR_CHNL0_CONFIG_REG, 0);
 449        ret = _il_poll_bit(il, FH49_MEM_RSSR_RX_STATUS_REG,
 450                           FH49_RSSR_CHNL0_RX_STATUS_CHNL_IDLE,
 451                           FH49_RSSR_CHNL0_RX_STATUS_CHNL_IDLE,
 452                           1000);
 453        if (ret < 0)
 454                IL_ERR("Can't stop Rx DMA.\n");
 455
 456        return 0;
 457}
 458
 459int
 460il4965_hwrate_to_mac80211_idx(u32 rate_n_flags, enum ieee80211_band band)
 461{
 462        int idx = 0;
 463        int band_offset = 0;
 464
 465        /* HT rate format: mac80211 wants an MCS number, which is just LSB */
 466        if (rate_n_flags & RATE_MCS_HT_MSK) {
 467                idx = (rate_n_flags & 0xff);
 468                return idx;
 469                /* Legacy rate format, search for match in table */
 470        } else {
 471                if (band == IEEE80211_BAND_5GHZ)
 472                        band_offset = IL_FIRST_OFDM_RATE;
 473                for (idx = band_offset; idx < RATE_COUNT_LEGACY; idx++)
 474                        if (il_rates[idx].plcp == (rate_n_flags & 0xFF))
 475                                return idx - band_offset;
 476        }
 477
 478        return -1;
 479}
 480
 481static int
 482il4965_calc_rssi(struct il_priv *il, struct il_rx_phy_res *rx_resp)
 483{
 484        /* data from PHY/DSP regarding signal strength, etc.,
 485         *   contents are always there, not configurable by host.  */
 486        struct il4965_rx_non_cfg_phy *ncphy =
 487            (struct il4965_rx_non_cfg_phy *)rx_resp->non_cfg_phy_buf;
 488        u32 agc =
 489            (le16_to_cpu(ncphy->agc_info) & IL49_AGC_DB_MASK) >>
 490            IL49_AGC_DB_POS;
 491
 492        u32 valid_antennae =
 493            (le16_to_cpu(rx_resp->phy_flags) & IL49_RX_PHY_FLAGS_ANTENNAE_MASK)
 494            >> IL49_RX_PHY_FLAGS_ANTENNAE_OFFSET;
 495        u8 max_rssi = 0;
 496        u32 i;
 497
 498        /* Find max rssi among 3 possible receivers.
 499         * These values are measured by the digital signal processor (DSP).
 500         * They should stay fairly constant even as the signal strength varies,
 501         *   if the radio's automatic gain control (AGC) is working right.
 502         * AGC value (see below) will provide the "interesting" info. */
 503        for (i = 0; i < 3; i++)
 504                if (valid_antennae & (1 << i))
 505                        max_rssi = max(ncphy->rssi_info[i << 1], max_rssi);
 506
 507        D_STATS("Rssi In A %d B %d C %d Max %d AGC dB %d\n",
 508                ncphy->rssi_info[0], ncphy->rssi_info[2], ncphy->rssi_info[4],
 509                max_rssi, agc);
 510
 511        /* dBm = max_rssi dB - agc dB - constant.
 512         * Higher AGC (higher radio gain) means lower signal. */
 513        return max_rssi - agc - IL4965_RSSI_OFFSET;
 514}
 515
 516static u32
 517il4965_translate_rx_status(struct il_priv *il, u32 decrypt_in)
 518{
 519        u32 decrypt_out = 0;
 520
 521        if ((decrypt_in & RX_RES_STATUS_STATION_FOUND) ==
 522            RX_RES_STATUS_STATION_FOUND)
 523                decrypt_out |=
 524                    (RX_RES_STATUS_STATION_FOUND |
 525                     RX_RES_STATUS_NO_STATION_INFO_MISMATCH);
 526
 527        decrypt_out |= (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK);
 528
 529        /* packet was not encrypted */
 530        if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
 531            RX_RES_STATUS_SEC_TYPE_NONE)
 532                return decrypt_out;
 533
 534        /* packet was encrypted with unknown alg */
 535        if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
 536            RX_RES_STATUS_SEC_TYPE_ERR)
 537                return decrypt_out;
 538
 539        /* decryption was not done in HW */
 540        if ((decrypt_in & RX_MPDU_RES_STATUS_DEC_DONE_MSK) !=
 541            RX_MPDU_RES_STATUS_DEC_DONE_MSK)
 542                return decrypt_out;
 543
 544        switch (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) {
 545
 546        case RX_RES_STATUS_SEC_TYPE_CCMP:
 547                /* alg is CCM: check MIC only */
 548                if (!(decrypt_in & RX_MPDU_RES_STATUS_MIC_OK))
 549                        /* Bad MIC */
 550                        decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
 551                else
 552                        decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
 553
 554                break;
 555
 556        case RX_RES_STATUS_SEC_TYPE_TKIP:
 557                if (!(decrypt_in & RX_MPDU_RES_STATUS_TTAK_OK)) {
 558                        /* Bad TTAK */
 559                        decrypt_out |= RX_RES_STATUS_BAD_KEY_TTAK;
 560                        break;
 561                }
 562                /* fall through if TTAK OK */
 563        default:
 564                if (!(decrypt_in & RX_MPDU_RES_STATUS_ICV_OK))
 565                        decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
 566                else
 567                        decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
 568                break;
 569        }
 570
 571        D_RX("decrypt_in:0x%x  decrypt_out = 0x%x\n", decrypt_in, decrypt_out);
 572
 573        return decrypt_out;
 574}
 575
 576#define SMALL_PACKET_SIZE 256
 577
 578static void
 579il4965_pass_packet_to_mac80211(struct il_priv *il, struct ieee80211_hdr *hdr,
 580                               u32 len, u32 ampdu_status, struct il_rx_buf *rxb,
 581                               struct ieee80211_rx_status *stats)
 582{
 583        struct sk_buff *skb;
 584        __le16 fc = hdr->frame_control;
 585
 586        /* We only process data packets if the interface is open */
 587        if (unlikely(!il->is_open)) {
 588                D_DROP("Dropping packet while interface is not open.\n");
 589                return;
 590        }
 591
 592        if (unlikely(test_bit(IL_STOP_REASON_PASSIVE, &il->stop_reason))) {
 593                il_wake_queues_by_reason(il, IL_STOP_REASON_PASSIVE);
 594                D_INFO("Woke queues - frame received on passive channel\n");
 595        }
 596
 597        /* In case of HW accelerated crypto and bad decryption, drop */
 598        if (!il->cfg->mod_params->sw_crypto &&
 599            il_set_decrypted_flag(il, hdr, ampdu_status, stats))
 600                return;
 601
 602        skb = dev_alloc_skb(SMALL_PACKET_SIZE);
 603        if (!skb) {
 604                IL_ERR("dev_alloc_skb failed\n");
 605                return;
 606        }
 607
 608        if (len <= SMALL_PACKET_SIZE) {
 609                memcpy(skb_put(skb, len), hdr, len);
 610        } else {
 611                skb_add_rx_frag(skb, 0, rxb->page, (void *)hdr - rxb_addr(rxb),
 612                                len, PAGE_SIZE << il->hw_params.rx_page_order);
 613                il->alloc_rxb_page--;
 614                rxb->page = NULL;
 615        }
 616
 617        il_update_stats(il, false, fc, len);
 618        memcpy(IEEE80211_SKB_RXCB(skb), stats, sizeof(*stats));
 619
 620        ieee80211_rx(il->hw, skb);
 621}
 622
 623/* Called for N_RX (legacy ABG frames), or
 624 * N_RX_MPDU (HT high-throughput N frames). */
 625static void
 626il4965_hdl_rx(struct il_priv *il, struct il_rx_buf *rxb)
 627{
 628        struct ieee80211_hdr *header;
 629        struct ieee80211_rx_status rx_status = {};
 630        struct il_rx_pkt *pkt = rxb_addr(rxb);
 631        struct il_rx_phy_res *phy_res;
 632        __le32 rx_pkt_status;
 633        struct il_rx_mpdu_res_start *amsdu;
 634        u32 len;
 635        u32 ampdu_status;
 636        u32 rate_n_flags;
 637
 638        /**
 639         * N_RX and N_RX_MPDU are handled differently.
 640         *      N_RX: physical layer info is in this buffer
 641         *      N_RX_MPDU: physical layer info was sent in separate
 642         *              command and cached in il->last_phy_res
 643         *
 644         * Here we set up local variables depending on which command is
 645         * received.
 646         */
 647        if (pkt->hdr.cmd == N_RX) {
 648                phy_res = (struct il_rx_phy_res *)pkt->u.raw;
 649                header =
 650                    (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*phy_res) +
 651                                             phy_res->cfg_phy_cnt);
 652
 653                len = le16_to_cpu(phy_res->byte_count);
 654                rx_pkt_status =
 655                    *(__le32 *) (pkt->u.raw + sizeof(*phy_res) +
 656                                 phy_res->cfg_phy_cnt + len);
 657                ampdu_status = le32_to_cpu(rx_pkt_status);
 658        } else {
 659                if (!il->_4965.last_phy_res_valid) {
 660                        IL_ERR("MPDU frame without cached PHY data\n");
 661                        return;
 662                }
 663                phy_res = &il->_4965.last_phy_res;
 664                amsdu = (struct il_rx_mpdu_res_start *)pkt->u.raw;
 665                header = (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*amsdu));
 666                len = le16_to_cpu(amsdu->byte_count);
 667                rx_pkt_status = *(__le32 *) (pkt->u.raw + sizeof(*amsdu) + len);
 668                ampdu_status =
 669                    il4965_translate_rx_status(il, le32_to_cpu(rx_pkt_status));
 670        }
 671
 672        if ((unlikely(phy_res->cfg_phy_cnt > 20))) {
 673                D_DROP("dsp size out of range [0,20]: %d\n",
 674                       phy_res->cfg_phy_cnt);
 675                return;
 676        }
 677
 678        if (!(rx_pkt_status & RX_RES_STATUS_NO_CRC32_ERROR) ||
 679            !(rx_pkt_status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
 680                D_RX("Bad CRC or FIFO: 0x%08X.\n", le32_to_cpu(rx_pkt_status));
 681                return;
 682        }
 683
 684        /* This will be used in several places later */
 685        rate_n_flags = le32_to_cpu(phy_res->rate_n_flags);
 686
 687        /* rx_status carries information about the packet to mac80211 */
 688        rx_status.mactime = le64_to_cpu(phy_res->timestamp);
 689        rx_status.band =
 690            (phy_res->
 691             phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ? IEEE80211_BAND_2GHZ :
 692            IEEE80211_BAND_5GHZ;
 693        rx_status.freq =
 694            ieee80211_channel_to_frequency(le16_to_cpu(phy_res->channel),
 695                                           rx_status.band);
 696        rx_status.rate_idx =
 697            il4965_hwrate_to_mac80211_idx(rate_n_flags, rx_status.band);
 698        rx_status.flag = 0;
 699
 700        /* TSF isn't reliable. In order to allow smooth user experience,
 701         * this W/A doesn't propagate it to the mac80211 */
 702        /*rx_status.flag |= RX_FLAG_MACTIME_START; */
 703
 704        il->ucode_beacon_time = le32_to_cpu(phy_res->beacon_time_stamp);
 705
 706        /* Find max signal strength (dBm) among 3 antenna/receiver chains */
 707        rx_status.signal = il4965_calc_rssi(il, phy_res);
 708
 709        D_STATS("Rssi %d, TSF %llu\n", rx_status.signal,
 710                (unsigned long long)rx_status.mactime);
 711
 712        /*
 713         * "antenna number"
 714         *
 715         * It seems that the antenna field in the phy flags value
 716         * is actually a bit field. This is undefined by radiotap,
 717         * it wants an actual antenna number but I always get "7"
 718         * for most legacy frames I receive indicating that the
 719         * same frame was received on all three RX chains.
 720         *
 721         * I think this field should be removed in favor of a
 722         * new 802.11n radiotap field "RX chains" that is defined
 723         * as a bitmask.
 724         */
 725        rx_status.antenna =
 726            (le16_to_cpu(phy_res->phy_flags) & RX_RES_PHY_FLAGS_ANTENNA_MSK) >>
 727            RX_RES_PHY_FLAGS_ANTENNA_POS;
 728
 729        /* set the preamble flag if appropriate */
 730        if (phy_res->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
 731                rx_status.flag |= RX_FLAG_SHORTPRE;
 732
 733        /* Set up the HT phy flags */
 734        if (rate_n_flags & RATE_MCS_HT_MSK)
 735                rx_status.flag |= RX_FLAG_HT;
 736        if (rate_n_flags & RATE_MCS_HT40_MSK)
 737                rx_status.flag |= RX_FLAG_40MHZ;
 738        if (rate_n_flags & RATE_MCS_SGI_MSK)
 739                rx_status.flag |= RX_FLAG_SHORT_GI;
 740
 741        if (phy_res->phy_flags & RX_RES_PHY_FLAGS_AGG_MSK) {
 742                /* We know which subframes of an A-MPDU belong
 743                 * together since we get a single PHY response
 744                 * from the firmware for all of them.
 745                 */
 746
 747                rx_status.flag |= RX_FLAG_AMPDU_DETAILS;
 748                rx_status.ampdu_reference = il->_4965.ampdu_ref;
 749        }
 750
 751        il4965_pass_packet_to_mac80211(il, header, len, ampdu_status, rxb,
 752                                       &rx_status);
 753}
 754
 755/* Cache phy data (Rx signal strength, etc) for HT frame (N_RX_PHY).
 756 * This will be used later in il_hdl_rx() for N_RX_MPDU. */
 757static void
 758il4965_hdl_rx_phy(struct il_priv *il, struct il_rx_buf *rxb)
 759{
 760        struct il_rx_pkt *pkt = rxb_addr(rxb);
 761        il->_4965.last_phy_res_valid = true;
 762        il->_4965.ampdu_ref++;
 763        memcpy(&il->_4965.last_phy_res, pkt->u.raw,
 764               sizeof(struct il_rx_phy_res));
 765}
 766
 767static int
 768il4965_get_channels_for_scan(struct il_priv *il, struct ieee80211_vif *vif,
 769                             enum ieee80211_band band, u8 is_active,
 770                             u8 n_probes, struct il_scan_channel *scan_ch)
 771{
 772        struct ieee80211_channel *chan;
 773        const struct ieee80211_supported_band *sband;
 774        const struct il_channel_info *ch_info;
 775        u16 passive_dwell = 0;
 776        u16 active_dwell = 0;
 777        int added, i;
 778        u16 channel;
 779
 780        sband = il_get_hw_mode(il, band);
 781        if (!sband)
 782                return 0;
 783
 784        active_dwell = il_get_active_dwell_time(il, band, n_probes);
 785        passive_dwell = il_get_passive_dwell_time(il, band, vif);
 786
 787        if (passive_dwell <= active_dwell)
 788                passive_dwell = active_dwell + 1;
 789
 790        for (i = 0, added = 0; i < il->scan_request->n_channels; i++) {
 791                chan = il->scan_request->channels[i];
 792
 793                if (chan->band != band)
 794                        continue;
 795
 796                channel = chan->hw_value;
 797                scan_ch->channel = cpu_to_le16(channel);
 798
 799                ch_info = il_get_channel_info(il, band, channel);
 800                if (!il_is_channel_valid(ch_info)) {
 801                        D_SCAN("Channel %d is INVALID for this band.\n",
 802                               channel);
 803                        continue;
 804                }
 805
 806                if (!is_active || il_is_channel_passive(ch_info) ||
 807                    (chan->flags & IEEE80211_CHAN_NO_IR))
 808                        scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE;
 809                else
 810                        scan_ch->type = SCAN_CHANNEL_TYPE_ACTIVE;
 811
 812                if (n_probes)
 813                        scan_ch->type |= IL_SCAN_PROBE_MASK(n_probes);
 814
 815                scan_ch->active_dwell = cpu_to_le16(active_dwell);
 816                scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
 817
 818                /* Set txpower levels to defaults */
 819                scan_ch->dsp_atten = 110;
 820
 821                /* NOTE: if we were doing 6Mb OFDM for scans we'd use
 822                 * power level:
 823                 * scan_ch->tx_gain = ((1 << 5) | (2 << 3)) | 3;
 824                 */
 825                if (band == IEEE80211_BAND_5GHZ)
 826                        scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3;
 827                else
 828                        scan_ch->tx_gain = ((1 << 5) | (5 << 3));
 829
 830                D_SCAN("Scanning ch=%d prob=0x%X [%s %d]\n", channel,
 831                       le32_to_cpu(scan_ch->type),
 832                       (scan_ch->
 833                        type & SCAN_CHANNEL_TYPE_ACTIVE) ? "ACTIVE" : "PASSIVE",
 834                       (scan_ch->
 835                        type & SCAN_CHANNEL_TYPE_ACTIVE) ? active_dwell :
 836                       passive_dwell);
 837
 838                scan_ch++;
 839                added++;
 840        }
 841
 842        D_SCAN("total channels to scan %d\n", added);
 843        return added;
 844}
 845
 846static void
 847il4965_toggle_tx_ant(struct il_priv *il, u8 *ant, u8 valid)
 848{
 849        int i;
 850        u8 ind = *ant;
 851
 852        for (i = 0; i < RATE_ANT_NUM - 1; i++) {
 853                ind = (ind + 1) < RATE_ANT_NUM ? ind + 1 : 0;
 854                if (valid & BIT(ind)) {
 855                        *ant = ind;
 856                        return;
 857                }
 858        }
 859}
 860
 861int
 862il4965_request_scan(struct il_priv *il, struct ieee80211_vif *vif)
 863{
 864        struct il_host_cmd cmd = {
 865                .id = C_SCAN,
 866                .len = sizeof(struct il_scan_cmd),
 867                .flags = CMD_SIZE_HUGE,
 868        };
 869        struct il_scan_cmd *scan;
 870        u32 rate_flags = 0;
 871        u16 cmd_len;
 872        u16 rx_chain = 0;
 873        enum ieee80211_band band;
 874        u8 n_probes = 0;
 875        u8 rx_ant = il->hw_params.valid_rx_ant;
 876        u8 rate;
 877        bool is_active = false;
 878        int chan_mod;
 879        u8 active_chains;
 880        u8 scan_tx_antennas = il->hw_params.valid_tx_ant;
 881        int ret;
 882
 883        lockdep_assert_held(&il->mutex);
 884
 885        if (!il->scan_cmd) {
 886                il->scan_cmd =
 887                    kmalloc(sizeof(struct il_scan_cmd) + IL_MAX_SCAN_SIZE,
 888                            GFP_KERNEL);
 889                if (!il->scan_cmd) {
 890                        D_SCAN("fail to allocate memory for scan\n");
 891                        return -ENOMEM;
 892                }
 893        }
 894        scan = il->scan_cmd;
 895        memset(scan, 0, sizeof(struct il_scan_cmd) + IL_MAX_SCAN_SIZE);
 896
 897        scan->quiet_plcp_th = IL_PLCP_QUIET_THRESH;
 898        scan->quiet_time = IL_ACTIVE_QUIET_TIME;
 899
 900        if (il_is_any_associated(il)) {
 901                u16 interval;
 902                u32 extra;
 903                u32 suspend_time = 100;
 904                u32 scan_suspend_time = 100;
 905
 906                D_INFO("Scanning while associated...\n");
 907                interval = vif->bss_conf.beacon_int;
 908
 909                scan->suspend_time = 0;
 910                scan->max_out_time = cpu_to_le32(200 * 1024);
 911                if (!interval)
 912                        interval = suspend_time;
 913
 914                extra = (suspend_time / interval) << 22;
 915                scan_suspend_time =
 916                    (extra | ((suspend_time % interval) * 1024));
 917                scan->suspend_time = cpu_to_le32(scan_suspend_time);
 918                D_SCAN("suspend_time 0x%X beacon interval %d\n",
 919                       scan_suspend_time, interval);
 920        }
 921
 922        if (il->scan_request->n_ssids) {
 923                int i, p = 0;
 924                D_SCAN("Kicking off active scan\n");
 925                for (i = 0; i < il->scan_request->n_ssids; i++) {
 926                        /* always does wildcard anyway */
 927                        if (!il->scan_request->ssids[i].ssid_len)
 928                                continue;
 929                        scan->direct_scan[p].id = WLAN_EID_SSID;
 930                        scan->direct_scan[p].len =
 931                            il->scan_request->ssids[i].ssid_len;
 932                        memcpy(scan->direct_scan[p].ssid,
 933                               il->scan_request->ssids[i].ssid,
 934                               il->scan_request->ssids[i].ssid_len);
 935                        n_probes++;
 936                        p++;
 937                }
 938                is_active = true;
 939        } else
 940                D_SCAN("Start passive scan.\n");
 941
 942        scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
 943        scan->tx_cmd.sta_id = il->hw_params.bcast_id;
 944        scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
 945
 946        switch (il->scan_band) {
 947        case IEEE80211_BAND_2GHZ:
 948                scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
 949                chan_mod =
 950                    le32_to_cpu(il->active.flags & RXON_FLG_CHANNEL_MODE_MSK) >>
 951                    RXON_FLG_CHANNEL_MODE_POS;
 952                if (chan_mod == CHANNEL_MODE_PURE_40) {
 953                        rate = RATE_6M_PLCP;
 954                } else {
 955                        rate = RATE_1M_PLCP;
 956                        rate_flags = RATE_MCS_CCK_MSK;
 957                }
 958                break;
 959        case IEEE80211_BAND_5GHZ:
 960                rate = RATE_6M_PLCP;
 961                break;
 962        default:
 963                IL_WARN("Invalid scan band\n");
 964                return -EIO;
 965        }
 966
 967        /*
 968         * If active scanning is requested but a certain channel is
 969         * marked passive, we can do active scanning if we detect
 970         * transmissions.
 971         *
 972         * There is an issue with some firmware versions that triggers
 973         * a sysassert on a "good CRC threshold" of zero (== disabled),
 974         * on a radar channel even though this means that we should NOT
 975         * send probes.
 976         *
 977         * The "good CRC threshold" is the number of frames that we
 978         * need to receive during our dwell time on a channel before
 979         * sending out probes -- setting this to a huge value will
 980         * mean we never reach it, but at the same time work around
 981         * the aforementioned issue. Thus use IL_GOOD_CRC_TH_NEVER
 982         * here instead of IL_GOOD_CRC_TH_DISABLED.
 983         */
 984        scan->good_CRC_th =
 985            is_active ? IL_GOOD_CRC_TH_DEFAULT : IL_GOOD_CRC_TH_NEVER;
 986
 987        band = il->scan_band;
 988
 989        if (il->cfg->scan_rx_antennas[band])
 990                rx_ant = il->cfg->scan_rx_antennas[band];
 991
 992        il4965_toggle_tx_ant(il, &il->scan_tx_ant[band], scan_tx_antennas);
 993        rate_flags |= BIT(il->scan_tx_ant[band]) << RATE_MCS_ANT_POS;
 994        scan->tx_cmd.rate_n_flags = cpu_to_le32(rate | rate_flags);
 995
 996        /* In power save mode use one chain, otherwise use all chains */
 997        if (test_bit(S_POWER_PMI, &il->status)) {
 998                /* rx_ant has been set to all valid chains previously */
 999                active_chains =
1000                    rx_ant & ((u8) (il->chain_noise_data.active_chains));
1001                if (!active_chains)
1002                        active_chains = rx_ant;
1003
1004                D_SCAN("chain_noise_data.active_chains: %u\n",
1005                       il->chain_noise_data.active_chains);
1006
1007                rx_ant = il4965_first_antenna(active_chains);
1008        }
1009
1010        /* MIMO is not used here, but value is required */
1011        rx_chain |= il->hw_params.valid_rx_ant << RXON_RX_CHAIN_VALID_POS;
1012        rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS;
1013        rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_SEL_POS;
1014        rx_chain |= 0x1 << RXON_RX_CHAIN_DRIVER_FORCE_POS;
1015        scan->rx_chain = cpu_to_le16(rx_chain);
1016
1017        cmd_len =
1018            il_fill_probe_req(il, (struct ieee80211_mgmt *)scan->data,
1019                              vif->addr, il->scan_request->ie,
1020                              il->scan_request->ie_len,
1021                              IL_MAX_SCAN_SIZE - sizeof(*scan));
1022        scan->tx_cmd.len = cpu_to_le16(cmd_len);
1023
1024        scan->filter_flags |=
1025            (RXON_FILTER_ACCEPT_GRP_MSK | RXON_FILTER_BCON_AWARE_MSK);
1026
1027        scan->channel_count =
1028            il4965_get_channels_for_scan(il, vif, band, is_active, n_probes,
1029                                         (void *)&scan->data[cmd_len]);
1030        if (scan->channel_count == 0) {
1031                D_SCAN("channel count %d\n", scan->channel_count);
1032                return -EIO;
1033        }
1034
1035        cmd.len +=
1036            le16_to_cpu(scan->tx_cmd.len) +
1037            scan->channel_count * sizeof(struct il_scan_channel);
1038        cmd.data = scan;
1039        scan->len = cpu_to_le16(cmd.len);
1040
1041        set_bit(S_SCAN_HW, &il->status);
1042
1043        ret = il_send_cmd_sync(il, &cmd);
1044        if (ret)
1045                clear_bit(S_SCAN_HW, &il->status);
1046
1047        return ret;
1048}
1049
1050int
1051il4965_manage_ibss_station(struct il_priv *il, struct ieee80211_vif *vif,
1052                           bool add)
1053{
1054        struct il_vif_priv *vif_priv = (void *)vif->drv_priv;
1055
1056        if (add)
1057                return il4965_add_bssid_station(il, vif->bss_conf.bssid,
1058                                                &vif_priv->ibss_bssid_sta_id);
1059        return il_remove_station(il, vif_priv->ibss_bssid_sta_id,
1060                                 vif->bss_conf.bssid);
1061}
1062
1063void
1064il4965_free_tfds_in_queue(struct il_priv *il, int sta_id, int tid, int freed)
1065{
1066        lockdep_assert_held(&il->sta_lock);
1067
1068        if (il->stations[sta_id].tid[tid].tfds_in_queue >= freed)
1069                il->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1070        else {
1071                D_TX("free more than tfds_in_queue (%u:%d)\n",
1072                     il->stations[sta_id].tid[tid].tfds_in_queue, freed);
1073                il->stations[sta_id].tid[tid].tfds_in_queue = 0;
1074        }
1075}
1076
1077#define IL_TX_QUEUE_MSK 0xfffff
1078
1079static bool
1080il4965_is_single_rx_stream(struct il_priv *il)
1081{
1082        return il->current_ht_config.smps == IEEE80211_SMPS_STATIC ||
1083            il->current_ht_config.single_chain_sufficient;
1084}
1085
1086#define IL_NUM_RX_CHAINS_MULTIPLE       3
1087#define IL_NUM_RX_CHAINS_SINGLE 2
1088#define IL_NUM_IDLE_CHAINS_DUAL 2
1089#define IL_NUM_IDLE_CHAINS_SINGLE       1
1090
1091/*
1092 * Determine how many receiver/antenna chains to use.
1093 *
1094 * More provides better reception via diversity.  Fewer saves power
1095 * at the expense of throughput, but only when not in powersave to
1096 * start with.
1097 *
1098 * MIMO (dual stream) requires at least 2, but works better with 3.
1099 * This does not determine *which* chains to use, just how many.
1100 */
1101static int
1102il4965_get_active_rx_chain_count(struct il_priv *il)
1103{
1104        /* # of Rx chains to use when expecting MIMO. */
1105        if (il4965_is_single_rx_stream(il))
1106                return IL_NUM_RX_CHAINS_SINGLE;
1107        else
1108                return IL_NUM_RX_CHAINS_MULTIPLE;
1109}
1110
1111/*
1112 * When we are in power saving mode, unless device support spatial
1113 * multiplexing power save, use the active count for rx chain count.
1114 */
1115static int
1116il4965_get_idle_rx_chain_count(struct il_priv *il, int active_cnt)
1117{
1118        /* # Rx chains when idling, depending on SMPS mode */
1119        switch (il->current_ht_config.smps) {
1120        case IEEE80211_SMPS_STATIC:
1121        case IEEE80211_SMPS_DYNAMIC:
1122                return IL_NUM_IDLE_CHAINS_SINGLE;
1123        case IEEE80211_SMPS_OFF:
1124                return active_cnt;
1125        default:
1126                WARN(1, "invalid SMPS mode %d", il->current_ht_config.smps);
1127                return active_cnt;
1128        }
1129}
1130
1131/* up to 4 chains */
1132static u8
1133il4965_count_chain_bitmap(u32 chain_bitmap)
1134{
1135        u8 res;
1136        res = (chain_bitmap & BIT(0)) >> 0;
1137        res += (chain_bitmap & BIT(1)) >> 1;
1138        res += (chain_bitmap & BIT(2)) >> 2;
1139        res += (chain_bitmap & BIT(3)) >> 3;
1140        return res;
1141}
1142
1143/**
1144 * il4965_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
1145 *
1146 * Selects how many and which Rx receivers/antennas/chains to use.
1147 * This should not be used for scan command ... it puts data in wrong place.
1148 */
1149void
1150il4965_set_rxon_chain(struct il_priv *il)
1151{
1152        bool is_single = il4965_is_single_rx_stream(il);
1153        bool is_cam = !test_bit(S_POWER_PMI, &il->status);
1154        u8 idle_rx_cnt, active_rx_cnt, valid_rx_cnt;
1155        u32 active_chains;
1156        u16 rx_chain;
1157
1158        /* Tell uCode which antennas are actually connected.
1159         * Before first association, we assume all antennas are connected.
1160         * Just after first association, il4965_chain_noise_calibration()
1161         *    checks which antennas actually *are* connected. */
1162        if (il->chain_noise_data.active_chains)
1163                active_chains = il->chain_noise_data.active_chains;
1164        else
1165                active_chains = il->hw_params.valid_rx_ant;
1166
1167        rx_chain = active_chains << RXON_RX_CHAIN_VALID_POS;
1168
1169        /* How many receivers should we use? */
1170        active_rx_cnt = il4965_get_active_rx_chain_count(il);
1171        idle_rx_cnt = il4965_get_idle_rx_chain_count(il, active_rx_cnt);
1172
1173        /* correct rx chain count according hw settings
1174         * and chain noise calibration
1175         */
1176        valid_rx_cnt = il4965_count_chain_bitmap(active_chains);
1177        if (valid_rx_cnt < active_rx_cnt)
1178                active_rx_cnt = valid_rx_cnt;
1179
1180        if (valid_rx_cnt < idle_rx_cnt)
1181                idle_rx_cnt = valid_rx_cnt;
1182
1183        rx_chain |= active_rx_cnt << RXON_RX_CHAIN_MIMO_CNT_POS;
1184        rx_chain |= idle_rx_cnt << RXON_RX_CHAIN_CNT_POS;
1185
1186        il->staging.rx_chain = cpu_to_le16(rx_chain);
1187
1188        if (!is_single && active_rx_cnt >= IL_NUM_RX_CHAINS_SINGLE && is_cam)
1189                il->staging.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
1190        else
1191                il->staging.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
1192
1193        D_ASSOC("rx_chain=0x%X active=%d idle=%d\n", il->staging.rx_chain,
1194                active_rx_cnt, idle_rx_cnt);
1195
1196        WARN_ON(active_rx_cnt == 0 || idle_rx_cnt == 0 ||
1197                active_rx_cnt < idle_rx_cnt);
1198}
1199
1200static const char *
1201il4965_get_fh_string(int cmd)
1202{
1203        switch (cmd) {
1204                IL_CMD(FH49_RSCSR_CHNL0_STTS_WPTR_REG);
1205                IL_CMD(FH49_RSCSR_CHNL0_RBDCB_BASE_REG);
1206                IL_CMD(FH49_RSCSR_CHNL0_WPTR);
1207                IL_CMD(FH49_MEM_RCSR_CHNL0_CONFIG_REG);
1208                IL_CMD(FH49_MEM_RSSR_SHARED_CTRL_REG);
1209                IL_CMD(FH49_MEM_RSSR_RX_STATUS_REG);
1210                IL_CMD(FH49_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
1211                IL_CMD(FH49_TSSR_TX_STATUS_REG);
1212                IL_CMD(FH49_TSSR_TX_ERROR_REG);
1213        default:
1214                return "UNKNOWN";
1215        }
1216}
1217
1218int
1219il4965_dump_fh(struct il_priv *il, char **buf, bool display)
1220{
1221        int i;
1222#ifdef CONFIG_IWLEGACY_DEBUG
1223        int pos = 0;
1224        size_t bufsz = 0;
1225#endif
1226        static const u32 fh_tbl[] = {
1227                FH49_RSCSR_CHNL0_STTS_WPTR_REG,
1228                FH49_RSCSR_CHNL0_RBDCB_BASE_REG,
1229                FH49_RSCSR_CHNL0_WPTR,
1230                FH49_MEM_RCSR_CHNL0_CONFIG_REG,
1231                FH49_MEM_RSSR_SHARED_CTRL_REG,
1232                FH49_MEM_RSSR_RX_STATUS_REG,
1233                FH49_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
1234                FH49_TSSR_TX_STATUS_REG,
1235                FH49_TSSR_TX_ERROR_REG
1236        };
1237#ifdef CONFIG_IWLEGACY_DEBUG
1238        if (display) {
1239                bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
1240                *buf = kmalloc(bufsz, GFP_KERNEL);
1241                if (!*buf)
1242                        return -ENOMEM;
1243                pos +=
1244                    scnprintf(*buf + pos, bufsz - pos, "FH register values:\n");
1245                for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
1246                        pos +=
1247                            scnprintf(*buf + pos, bufsz - pos,
1248                                      "  %34s: 0X%08x\n",
1249                                      il4965_get_fh_string(fh_tbl[i]),
1250                                      il_rd(il, fh_tbl[i]));
1251                }
1252                return pos;
1253        }
1254#endif
1255        IL_ERR("FH register values:\n");
1256        for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
1257                IL_ERR("  %34s: 0X%08x\n", il4965_get_fh_string(fh_tbl[i]),
1258                       il_rd(il, fh_tbl[i]));
1259        }
1260        return 0;
1261}
1262
1263static void
1264il4965_hdl_missed_beacon(struct il_priv *il, struct il_rx_buf *rxb)
1265{
1266        struct il_rx_pkt *pkt = rxb_addr(rxb);
1267        struct il_missed_beacon_notif *missed_beacon;
1268
1269        missed_beacon = &pkt->u.missed_beacon;
1270        if (le32_to_cpu(missed_beacon->consecutive_missed_beacons) >
1271            il->missed_beacon_threshold) {
1272                D_CALIB("missed bcn cnsq %d totl %d rcd %d expctd %d\n",
1273                        le32_to_cpu(missed_beacon->consecutive_missed_beacons),
1274                        le32_to_cpu(missed_beacon->total_missed_becons),
1275                        le32_to_cpu(missed_beacon->num_recvd_beacons),
1276                        le32_to_cpu(missed_beacon->num_expected_beacons));
1277                if (!test_bit(S_SCANNING, &il->status))
1278                        il4965_init_sensitivity(il);
1279        }
1280}
1281
1282/* Calculate noise level, based on measurements during network silence just
1283 *   before arriving beacon.  This measurement can be done only if we know
1284 *   exactly when to expect beacons, therefore only when we're associated. */
1285static void
1286il4965_rx_calc_noise(struct il_priv *il)
1287{
1288        struct stats_rx_non_phy *rx_info;
1289        int num_active_rx = 0;
1290        int total_silence = 0;
1291        int bcn_silence_a, bcn_silence_b, bcn_silence_c;
1292        int last_rx_noise;
1293
1294        rx_info = &(il->_4965.stats.rx.general);
1295        bcn_silence_a =
1296            le32_to_cpu(rx_info->beacon_silence_rssi_a) & IN_BAND_FILTER;
1297        bcn_silence_b =
1298            le32_to_cpu(rx_info->beacon_silence_rssi_b) & IN_BAND_FILTER;
1299        bcn_silence_c =
1300            le32_to_cpu(rx_info->beacon_silence_rssi_c) & IN_BAND_FILTER;
1301
1302        if (bcn_silence_a) {
1303                total_silence += bcn_silence_a;
1304                num_active_rx++;
1305        }
1306        if (bcn_silence_b) {
1307                total_silence += bcn_silence_b;
1308                num_active_rx++;
1309        }
1310        if (bcn_silence_c) {
1311                total_silence += bcn_silence_c;
1312                num_active_rx++;
1313        }
1314
1315        /* Average among active antennas */
1316        if (num_active_rx)
1317                last_rx_noise = (total_silence / num_active_rx) - 107;
1318        else
1319                last_rx_noise = IL_NOISE_MEAS_NOT_AVAILABLE;
1320
1321        D_CALIB("inband silence a %u, b %u, c %u, dBm %d\n", bcn_silence_a,
1322                bcn_silence_b, bcn_silence_c, last_rx_noise);
1323}
1324
1325#ifdef CONFIG_IWLEGACY_DEBUGFS
1326/*
1327 *  based on the assumption of all stats counter are in DWORD
1328 *  FIXME: This function is for debugging, do not deal with
1329 *  the case of counters roll-over.
1330 */
1331static void
1332il4965_accumulative_stats(struct il_priv *il, __le32 * stats)
1333{
1334        int i, size;
1335        __le32 *prev_stats;
1336        u32 *accum_stats;
1337        u32 *delta, *max_delta;
1338        struct stats_general_common *general, *accum_general;
1339        struct stats_tx *tx, *accum_tx;
1340
1341        prev_stats = (__le32 *) &il->_4965.stats;
1342        accum_stats = (u32 *) &il->_4965.accum_stats;
1343        size = sizeof(struct il_notif_stats);
1344        general = &il->_4965.stats.general.common;
1345        accum_general = &il->_4965.accum_stats.general.common;
1346        tx = &il->_4965.stats.tx;
1347        accum_tx = &il->_4965.accum_stats.tx;
1348        delta = (u32 *) &il->_4965.delta_stats;
1349        max_delta = (u32 *) &il->_4965.max_delta;
1350
1351        for (i = sizeof(__le32); i < size;
1352             i +=
1353             sizeof(__le32), stats++, prev_stats++, delta++, max_delta++,
1354             accum_stats++) {
1355                if (le32_to_cpu(*stats) > le32_to_cpu(*prev_stats)) {
1356                        *delta =
1357                            (le32_to_cpu(*stats) - le32_to_cpu(*prev_stats));
1358                        *accum_stats += *delta;
1359                        if (*delta > *max_delta)
1360                                *max_delta = *delta;
1361                }
1362        }
1363
1364        /* reset accumulative stats for "no-counter" type stats */
1365        accum_general->temperature = general->temperature;
1366        accum_general->ttl_timestamp = general->ttl_timestamp;
1367}
1368#endif
1369
1370static void
1371il4965_hdl_stats(struct il_priv *il, struct il_rx_buf *rxb)
1372{
1373        const int recalib_seconds = 60;
1374        bool change;
1375        struct il_rx_pkt *pkt = rxb_addr(rxb);
1376
1377        D_RX("Statistics notification received (%d vs %d).\n",
1378             (int)sizeof(struct il_notif_stats),
1379             le32_to_cpu(pkt->len_n_flags) & IL_RX_FRAME_SIZE_MSK);
1380
1381        change =
1382            ((il->_4965.stats.general.common.temperature !=
1383              pkt->u.stats.general.common.temperature) ||
1384             ((il->_4965.stats.flag & STATS_REPLY_FLG_HT40_MODE_MSK) !=
1385              (pkt->u.stats.flag & STATS_REPLY_FLG_HT40_MODE_MSK)));
1386#ifdef CONFIG_IWLEGACY_DEBUGFS
1387        il4965_accumulative_stats(il, (__le32 *) &pkt->u.stats);
1388#endif
1389
1390        /* TODO: reading some of stats is unneeded */
1391        memcpy(&il->_4965.stats, &pkt->u.stats, sizeof(il->_4965.stats));
1392
1393        set_bit(S_STATS, &il->status);
1394
1395        /*
1396         * Reschedule the stats timer to occur in recalib_seconds to ensure
1397         * we get a thermal update even if the uCode doesn't give us one
1398         */
1399        mod_timer(&il->stats_periodic,
1400                  jiffies + msecs_to_jiffies(recalib_seconds * 1000));
1401
1402        if (unlikely(!test_bit(S_SCANNING, &il->status)) &&
1403            (pkt->hdr.cmd == N_STATS)) {
1404                il4965_rx_calc_noise(il);
1405                queue_work(il->workqueue, &il->run_time_calib_work);
1406        }
1407
1408        if (change)
1409                il4965_temperature_calib(il);
1410}
1411
1412static void
1413il4965_hdl_c_stats(struct il_priv *il, struct il_rx_buf *rxb)
1414{
1415        struct il_rx_pkt *pkt = rxb_addr(rxb);
1416
1417        if (le32_to_cpu(pkt->u.stats.flag) & UCODE_STATS_CLEAR_MSK) {
1418#ifdef CONFIG_IWLEGACY_DEBUGFS
1419                memset(&il->_4965.accum_stats, 0,
1420                       sizeof(struct il_notif_stats));
1421                memset(&il->_4965.delta_stats, 0,
1422                       sizeof(struct il_notif_stats));
1423                memset(&il->_4965.max_delta, 0, sizeof(struct il_notif_stats));
1424#endif
1425                D_RX("Statistics have been cleared\n");
1426        }
1427        il4965_hdl_stats(il, rxb);
1428}
1429
1430
1431/*
1432 * mac80211 queues, ACs, hardware queues, FIFOs.
1433 *
1434 * Cf. http://wireless.kernel.org/en/developers/Documentation/mac80211/queues
1435 *
1436 * Mac80211 uses the following numbers, which we get as from it
1437 * by way of skb_get_queue_mapping(skb):
1438 *
1439 *     VO      0
1440 *     VI      1
1441 *     BE      2
1442 *     BK      3
1443 *
1444 *
1445 * Regular (not A-MPDU) frames are put into hardware queues corresponding
1446 * to the FIFOs, see comments in iwl-prph.h. Aggregated frames get their
1447 * own queue per aggregation session (RA/TID combination), such queues are
1448 * set up to map into FIFOs too, for which we need an AC->FIFO mapping. In
1449 * order to map frames to the right queue, we also need an AC->hw queue
1450 * mapping. This is implemented here.
1451 *
1452 * Due to the way hw queues are set up (by the hw specific modules like
1453 * 4965.c), the AC->hw queue mapping is the identity
1454 * mapping.
1455 */
1456
1457static const u8 tid_to_ac[] = {
1458        IEEE80211_AC_BE,
1459        IEEE80211_AC_BK,
1460        IEEE80211_AC_BK,
1461        IEEE80211_AC_BE,
1462        IEEE80211_AC_VI,
1463        IEEE80211_AC_VI,
1464        IEEE80211_AC_VO,
1465        IEEE80211_AC_VO
1466};
1467
1468static inline int
1469il4965_get_ac_from_tid(u16 tid)
1470{
1471        if (likely(tid < ARRAY_SIZE(tid_to_ac)))
1472                return tid_to_ac[tid];
1473
1474        /* no support for TIDs 8-15 yet */
1475        return -EINVAL;
1476}
1477
1478static inline int
1479il4965_get_fifo_from_tid(u16 tid)
1480{
1481        const u8 ac_to_fifo[] = {
1482                IL_TX_FIFO_VO,
1483                IL_TX_FIFO_VI,
1484                IL_TX_FIFO_BE,
1485                IL_TX_FIFO_BK,
1486        };
1487
1488        if (likely(tid < ARRAY_SIZE(tid_to_ac)))
1489                return ac_to_fifo[tid_to_ac[tid]];
1490
1491        /* no support for TIDs 8-15 yet */
1492        return -EINVAL;
1493}
1494
1495/*
1496 * handle build C_TX command notification.
1497 */
1498static void
1499il4965_tx_cmd_build_basic(struct il_priv *il, struct sk_buff *skb,
1500                          struct il_tx_cmd *tx_cmd,
1501                          struct ieee80211_tx_info *info,
1502                          struct ieee80211_hdr *hdr, u8 std_id)
1503{
1504        __le16 fc = hdr->frame_control;
1505        __le32 tx_flags = tx_cmd->tx_flags;
1506
1507        tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
1508        if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
1509                tx_flags |= TX_CMD_FLG_ACK_MSK;
1510                if (ieee80211_is_mgmt(fc))
1511                        tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
1512                if (ieee80211_is_probe_resp(fc) &&
1513                    !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
1514                        tx_flags |= TX_CMD_FLG_TSF_MSK;
1515        } else {
1516                tx_flags &= (~TX_CMD_FLG_ACK_MSK);
1517                tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
1518        }
1519
1520        if (ieee80211_is_back_req(fc))
1521                tx_flags |= TX_CMD_FLG_ACK_MSK | TX_CMD_FLG_IMM_BA_RSP_MASK;
1522
1523        tx_cmd->sta_id = std_id;
1524        if (ieee80211_has_morefrags(fc))
1525                tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
1526
1527        if (ieee80211_is_data_qos(fc)) {
1528                u8 *qc = ieee80211_get_qos_ctl(hdr);
1529                tx_cmd->tid_tspec = qc[0] & 0xf;
1530                tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
1531        } else {
1532                tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
1533        }
1534
1535        il_tx_cmd_protection(il, info, fc, &tx_flags);
1536
1537        tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
1538        if (ieee80211_is_mgmt(fc)) {
1539                if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
1540                        tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3);
1541                else
1542                        tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2);
1543        } else {
1544                tx_cmd->timeout.pm_frame_timeout = 0;
1545        }
1546
1547        tx_cmd->driver_txop = 0;
1548        tx_cmd->tx_flags = tx_flags;
1549        tx_cmd->next_frame_len = 0;
1550}
1551
1552static void
1553il4965_tx_cmd_build_rate(struct il_priv *il,
1554                         struct il_tx_cmd *tx_cmd,
1555                         struct ieee80211_tx_info *info,
1556                         struct ieee80211_sta *sta,
1557                         __le16 fc)
1558{
1559        const u8 rts_retry_limit = 60;
1560        u32 rate_flags;
1561        int rate_idx;
1562        u8 data_retry_limit;
1563        u8 rate_plcp;
1564
1565        /* Set retry limit on DATA packets and Probe Responses */
1566        if (ieee80211_is_probe_resp(fc))
1567                data_retry_limit = 3;
1568        else
1569                data_retry_limit = IL4965_DEFAULT_TX_RETRY;
1570        tx_cmd->data_retry_limit = data_retry_limit;
1571        /* Set retry limit on RTS packets */
1572        tx_cmd->rts_retry_limit = min(data_retry_limit, rts_retry_limit);
1573
1574        /* DATA packets will use the uCode station table for rate/antenna
1575         * selection */
1576        if (ieee80211_is_data(fc)) {
1577                tx_cmd->initial_rate_idx = 0;
1578                tx_cmd->tx_flags |= TX_CMD_FLG_STA_RATE_MSK;
1579                return;
1580        }
1581
1582        /**
1583         * If the current TX rate stored in mac80211 has the MCS bit set, it's
1584         * not really a TX rate.  Thus, we use the lowest supported rate for
1585         * this band.  Also use the lowest supported rate if the stored rate
1586         * idx is invalid.
1587         */
1588        rate_idx = info->control.rates[0].idx;
1589        if ((info->control.rates[0].flags & IEEE80211_TX_RC_MCS) || rate_idx < 0
1590            || rate_idx > RATE_COUNT_LEGACY)
1591                rate_idx = rate_lowest_index(&il->bands[info->band], sta);
1592        /* For 5 GHZ band, remap mac80211 rate indices into driver indices */
1593        if (info->band == IEEE80211_BAND_5GHZ)
1594                rate_idx += IL_FIRST_OFDM_RATE;
1595        /* Get PLCP rate for tx_cmd->rate_n_flags */
1596        rate_plcp = il_rates[rate_idx].plcp;
1597        /* Zero out flags for this packet */
1598        rate_flags = 0;
1599
1600        /* Set CCK flag as needed */
1601        if (rate_idx >= IL_FIRST_CCK_RATE && rate_idx <= IL_LAST_CCK_RATE)
1602                rate_flags |= RATE_MCS_CCK_MSK;
1603
1604        /* Set up antennas */
1605        il4965_toggle_tx_ant(il, &il->mgmt_tx_ant, il->hw_params.valid_tx_ant);
1606        rate_flags |= BIT(il->mgmt_tx_ant) << RATE_MCS_ANT_POS;
1607
1608        /* Set the rate in the TX cmd */
1609        tx_cmd->rate_n_flags = cpu_to_le32(rate_plcp | rate_flags);
1610}
1611
1612static void
1613il4965_tx_cmd_build_hwcrypto(struct il_priv *il, struct ieee80211_tx_info *info,
1614                             struct il_tx_cmd *tx_cmd, struct sk_buff *skb_frag,
1615                             int sta_id)
1616{
1617        struct ieee80211_key_conf *keyconf = info->control.hw_key;
1618
1619        switch (keyconf->cipher) {
1620        case WLAN_CIPHER_SUITE_CCMP:
1621                tx_cmd->sec_ctl = TX_CMD_SEC_CCM;
1622                memcpy(tx_cmd->key, keyconf->key, keyconf->keylen);
1623                if (info->flags & IEEE80211_TX_CTL_AMPDU)
1624                        tx_cmd->tx_flags |= TX_CMD_FLG_AGG_CCMP_MSK;
1625                D_TX("tx_cmd with AES hwcrypto\n");
1626                break;
1627
1628        case WLAN_CIPHER_SUITE_TKIP:
1629                tx_cmd->sec_ctl = TX_CMD_SEC_TKIP;
1630                ieee80211_get_tkip_p2k(keyconf, skb_frag, tx_cmd->key);
1631                D_TX("tx_cmd with tkip hwcrypto\n");
1632                break;
1633
1634        case WLAN_CIPHER_SUITE_WEP104:
1635                tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128;
1636                /* fall through */
1637        case WLAN_CIPHER_SUITE_WEP40:
1638                tx_cmd->sec_ctl |=
1639                    (TX_CMD_SEC_WEP | (keyconf->keyidx & TX_CMD_SEC_MSK) <<
1640                     TX_CMD_SEC_SHIFT);
1641
1642                memcpy(&tx_cmd->key[3], keyconf->key, keyconf->keylen);
1643
1644                D_TX("Configuring packet for WEP encryption " "with key %d\n",
1645                     keyconf->keyidx);
1646                break;
1647
1648        default:
1649                IL_ERR("Unknown encode cipher %x\n", keyconf->cipher);
1650                break;
1651        }
1652}
1653
1654/*
1655 * start C_TX command process
1656 */
1657int
1658il4965_tx_skb(struct il_priv *il,
1659              struct ieee80211_sta *sta,
1660              struct sk_buff *skb)
1661{
1662        struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1663        struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1664        struct il_station_priv *sta_priv = NULL;
1665        struct il_tx_queue *txq;
1666        struct il_queue *q;
1667        struct il_device_cmd *out_cmd;
1668        struct il_cmd_meta *out_meta;
1669        struct il_tx_cmd *tx_cmd;
1670        int txq_id;
1671        dma_addr_t phys_addr;
1672        dma_addr_t txcmd_phys;
1673        dma_addr_t scratch_phys;
1674        u16 len, firstlen, secondlen;
1675        u16 seq_number = 0;
1676        __le16 fc;
1677        u8 hdr_len;
1678        u8 sta_id;
1679        u8 wait_write_ptr = 0;
1680        u8 tid = 0;
1681        u8 *qc = NULL;
1682        unsigned long flags;
1683        bool is_agg = false;
1684
1685        spin_lock_irqsave(&il->lock, flags);
1686        if (il_is_rfkill(il)) {
1687                D_DROP("Dropping - RF KILL\n");
1688                goto drop_unlock;
1689        }
1690
1691        fc = hdr->frame_control;
1692
1693#ifdef CONFIG_IWLEGACY_DEBUG
1694        if (ieee80211_is_auth(fc))
1695                D_TX("Sending AUTH frame\n");
1696        else if (ieee80211_is_assoc_req(fc))
1697                D_TX("Sending ASSOC frame\n");
1698        else if (ieee80211_is_reassoc_req(fc))
1699                D_TX("Sending REASSOC frame\n");
1700#endif
1701
1702        hdr_len = ieee80211_hdrlen(fc);
1703
1704        /* For management frames use broadcast id to do not break aggregation */
1705        if (!ieee80211_is_data(fc))
1706                sta_id = il->hw_params.bcast_id;
1707        else {
1708                /* Find idx into station table for destination station */
1709                sta_id = il_sta_id_or_broadcast(il, sta);
1710
1711                if (sta_id == IL_INVALID_STATION) {
1712                        D_DROP("Dropping - INVALID STATION: %pM\n", hdr->addr1);
1713                        goto drop_unlock;
1714                }
1715        }
1716
1717        D_TX("station Id %d\n", sta_id);
1718
1719        if (sta)
1720                sta_priv = (void *)sta->drv_priv;
1721
1722        if (sta_priv && sta_priv->asleep &&
1723            (info->flags & IEEE80211_TX_CTL_NO_PS_BUFFER)) {
1724                /*
1725                 * This sends an asynchronous command to the device,
1726                 * but we can rely on it being processed before the
1727                 * next frame is processed -- and the next frame to
1728                 * this station is the one that will consume this
1729                 * counter.
1730                 * For now set the counter to just 1 since we do not
1731                 * support uAPSD yet.
1732                 */
1733                il4965_sta_modify_sleep_tx_count(il, sta_id, 1);
1734        }
1735
1736        /* FIXME: remove me ? */
1737        WARN_ON_ONCE(info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM);
1738
1739        /* Access category (AC) is also the queue number */
1740        txq_id = skb_get_queue_mapping(skb);
1741
1742        /* irqs already disabled/saved above when locking il->lock */
1743        spin_lock(&il->sta_lock);
1744
1745        if (ieee80211_is_data_qos(fc)) {
1746                qc = ieee80211_get_qos_ctl(hdr);
1747                tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
1748                if (WARN_ON_ONCE(tid >= MAX_TID_COUNT)) {
1749                        spin_unlock(&il->sta_lock);
1750                        goto drop_unlock;
1751                }
1752                seq_number = il->stations[sta_id].tid[tid].seq_number;
1753                seq_number &= IEEE80211_SCTL_SEQ;
1754                hdr->seq_ctrl =
1755                    hdr->seq_ctrl & cpu_to_le16(IEEE80211_SCTL_FRAG);
1756                hdr->seq_ctrl |= cpu_to_le16(seq_number);
1757                seq_number += 0x10;
1758                /* aggregation is on for this <sta,tid> */
1759                if (info->flags & IEEE80211_TX_CTL_AMPDU &&
1760                    il->stations[sta_id].tid[tid].agg.state == IL_AGG_ON) {
1761                        txq_id = il->stations[sta_id].tid[tid].agg.txq_id;
1762                        is_agg = true;
1763                }
1764        }
1765
1766        txq = &il->txq[txq_id];
1767        q = &txq->q;
1768
1769        if (unlikely(il_queue_space(q) < q->high_mark)) {
1770                spin_unlock(&il->sta_lock);
1771                goto drop_unlock;
1772        }
1773
1774        if (ieee80211_is_data_qos(fc)) {
1775                il->stations[sta_id].tid[tid].tfds_in_queue++;
1776                if (!ieee80211_has_morefrags(fc))
1777                        il->stations[sta_id].tid[tid].seq_number = seq_number;
1778        }
1779
1780        spin_unlock(&il->sta_lock);
1781
1782        txq->skbs[q->write_ptr] = skb;
1783
1784        /* Set up first empty entry in queue's array of Tx/cmd buffers */
1785        out_cmd = txq->cmd[q->write_ptr];
1786        out_meta = &txq->meta[q->write_ptr];
1787        tx_cmd = &out_cmd->cmd.tx;
1788        memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
1789        memset(tx_cmd, 0, sizeof(struct il_tx_cmd));
1790
1791        /*
1792         * Set up the Tx-command (not MAC!) header.
1793         * Store the chosen Tx queue and TFD idx within the sequence field;
1794         * after Tx, uCode's Tx response will return this value so driver can
1795         * locate the frame within the tx queue and do post-tx processing.
1796         */
1797        out_cmd->hdr.cmd = C_TX;
1798        out_cmd->hdr.sequence =
1799            cpu_to_le16((u16)
1800                        (QUEUE_TO_SEQ(txq_id) | IDX_TO_SEQ(q->write_ptr)));
1801
1802        /* Copy MAC header from skb into command buffer */
1803        memcpy(tx_cmd->hdr, hdr, hdr_len);
1804
1805        /* Total # bytes to be transmitted */
1806        tx_cmd->len = cpu_to_le16((u16) skb->len);
1807
1808        if (info->control.hw_key)
1809                il4965_tx_cmd_build_hwcrypto(il, info, tx_cmd, skb, sta_id);
1810
1811        /* TODO need this for burst mode later on */
1812        il4965_tx_cmd_build_basic(il, skb, tx_cmd, info, hdr, sta_id);
1813
1814        il4965_tx_cmd_build_rate(il, tx_cmd, info, sta, fc);
1815
1816        /*
1817         * Use the first empty entry in this queue's command buffer array
1818         * to contain the Tx command and MAC header concatenated together
1819         * (payload data will be in another buffer).
1820         * Size of this varies, due to varying MAC header length.
1821         * If end is not dword aligned, we'll have 2 extra bytes at the end
1822         * of the MAC header (device reads on dword boundaries).
1823         * We'll tell device about this padding later.
1824         */
1825        len = sizeof(struct il_tx_cmd) + sizeof(struct il_cmd_header) + hdr_len;
1826        firstlen = (len + 3) & ~3;
1827
1828        /* Tell NIC about any 2-byte padding after MAC header */
1829        if (firstlen != len)
1830                tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
1831
1832        /* Physical address of this Tx command's header (not MAC header!),
1833         * within command buffer array. */
1834        txcmd_phys =
1835            pci_map_single(il->pci_dev, &out_cmd->hdr, firstlen,
1836                           PCI_DMA_BIDIRECTIONAL);
1837        if (unlikely(pci_dma_mapping_error(il->pci_dev, txcmd_phys)))
1838                goto drop_unlock;
1839
1840        /* Set up TFD's 2nd entry to point directly to remainder of skb,
1841         * if any (802.11 null frames have no payload). */
1842        secondlen = skb->len - hdr_len;
1843        if (secondlen > 0) {
1844                phys_addr =
1845                    pci_map_single(il->pci_dev, skb->data + hdr_len, secondlen,
1846                                   PCI_DMA_TODEVICE);
1847                if (unlikely(pci_dma_mapping_error(il->pci_dev, phys_addr)))
1848                        goto drop_unlock;
1849        }
1850
1851        /* Add buffer containing Tx command and MAC(!) header to TFD's
1852         * first entry */
1853        il->ops->txq_attach_buf_to_tfd(il, txq, txcmd_phys, firstlen, 1, 0);
1854        dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
1855        dma_unmap_len_set(out_meta, len, firstlen);
1856        if (secondlen)
1857                il->ops->txq_attach_buf_to_tfd(il, txq, phys_addr, secondlen,
1858                                               0, 0);
1859
1860        if (!ieee80211_has_morefrags(hdr->frame_control)) {
1861                txq->need_update = 1;
1862        } else {
1863                wait_write_ptr = 1;
1864                txq->need_update = 0;
1865        }
1866
1867        scratch_phys =
1868            txcmd_phys + sizeof(struct il_cmd_header) +
1869            offsetof(struct il_tx_cmd, scratch);
1870
1871        /* take back ownership of DMA buffer to enable update */
1872        pci_dma_sync_single_for_cpu(il->pci_dev, txcmd_phys, firstlen,
1873                                    PCI_DMA_BIDIRECTIONAL);
1874        tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
1875        tx_cmd->dram_msb_ptr = il_get_dma_hi_addr(scratch_phys);
1876
1877        il_update_stats(il, true, fc, skb->len);
1878
1879        D_TX("sequence nr = 0X%x\n", le16_to_cpu(out_cmd->hdr.sequence));
1880        D_TX("tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
1881        il_print_hex_dump(il, IL_DL_TX, (u8 *) tx_cmd, sizeof(*tx_cmd));
1882        il_print_hex_dump(il, IL_DL_TX, (u8 *) tx_cmd->hdr, hdr_len);
1883
1884        /* Set up entry for this TFD in Tx byte-count array */
1885        if (info->flags & IEEE80211_TX_CTL_AMPDU)
1886                il->ops->txq_update_byte_cnt_tbl(il, txq, le16_to_cpu(tx_cmd->len));
1887
1888        pci_dma_sync_single_for_device(il->pci_dev, txcmd_phys, firstlen,
1889                                       PCI_DMA_BIDIRECTIONAL);
1890
1891        /* Tell device the write idx *just past* this latest filled TFD */
1892        q->write_ptr = il_queue_inc_wrap(q->write_ptr, q->n_bd);
1893        il_txq_update_write_ptr(il, txq);
1894        spin_unlock_irqrestore(&il->lock, flags);
1895
1896        /*
1897         * At this point the frame is "transmitted" successfully
1898         * and we will get a TX status notification eventually,
1899         * regardless of the value of ret. "ret" only indicates
1900         * whether or not we should update the write pointer.
1901         */
1902
1903        /*
1904         * Avoid atomic ops if it isn't an associated client.
1905         * Also, if this is a packet for aggregation, don't
1906         * increase the counter because the ucode will stop
1907         * aggregation queues when their respective station
1908         * goes to sleep.
1909         */
1910        if (sta_priv && sta_priv->client && !is_agg)
1911                atomic_inc(&sta_priv->pending_frames);
1912
1913        if (il_queue_space(q) < q->high_mark && il->mac80211_registered) {
1914                if (wait_write_ptr) {
1915                        spin_lock_irqsave(&il->lock, flags);
1916                        txq->need_update = 1;
1917                        il_txq_update_write_ptr(il, txq);
1918                        spin_unlock_irqrestore(&il->lock, flags);
1919                } else {
1920                        il_stop_queue(il, txq);
1921                }
1922        }
1923
1924        return 0;
1925
1926drop_unlock:
1927        spin_unlock_irqrestore(&il->lock, flags);
1928        return -1;
1929}
1930
1931static inline int
1932il4965_alloc_dma_ptr(struct il_priv *il, struct il_dma_ptr *ptr, size_t size)
1933{
1934        ptr->addr = dma_alloc_coherent(&il->pci_dev->dev, size, &ptr->dma,
1935                                       GFP_KERNEL);
1936        if (!ptr->addr)
1937                return -ENOMEM;
1938        ptr->size = size;
1939        return 0;
1940}
1941
1942static inline void
1943il4965_free_dma_ptr(struct il_priv *il, struct il_dma_ptr *ptr)
1944{
1945        if (unlikely(!ptr->addr))
1946                return;
1947
1948        dma_free_coherent(&il->pci_dev->dev, ptr->size, ptr->addr, ptr->dma);
1949        memset(ptr, 0, sizeof(*ptr));
1950}
1951
1952/**
1953 * il4965_hw_txq_ctx_free - Free TXQ Context
1954 *
1955 * Destroy all TX DMA queues and structures
1956 */
1957void
1958il4965_hw_txq_ctx_free(struct il_priv *il)
1959{
1960        int txq_id;
1961
1962        /* Tx queues */
1963        if (il->txq) {
1964                for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++)
1965                        if (txq_id == il->cmd_queue)
1966                                il_cmd_queue_free(il);
1967                        else
1968                                il_tx_queue_free(il, txq_id);
1969        }
1970        il4965_free_dma_ptr(il, &il->kw);
1971
1972        il4965_free_dma_ptr(il, &il->scd_bc_tbls);
1973
1974        /* free tx queue structure */
1975        il_free_txq_mem(il);
1976}
1977
1978/**
1979 * il4965_txq_ctx_alloc - allocate TX queue context
1980 * Allocate all Tx DMA structures and initialize them
1981 *
1982 * @param il
1983 * @return error code
1984 */
1985int
1986il4965_txq_ctx_alloc(struct il_priv *il)
1987{
1988        int ret, txq_id;
1989        unsigned long flags;
1990
1991        /* Free all tx/cmd queues and keep-warm buffer */
1992        il4965_hw_txq_ctx_free(il);
1993
1994        ret =
1995            il4965_alloc_dma_ptr(il, &il->scd_bc_tbls,
1996                                 il->hw_params.scd_bc_tbls_size);
1997        if (ret) {
1998                IL_ERR("Scheduler BC Table allocation failed\n");
1999                goto error_bc_tbls;
2000        }
2001        /* Alloc keep-warm buffer */
2002        ret = il4965_alloc_dma_ptr(il, &il->kw, IL_KW_SIZE);
2003        if (ret) {
2004                IL_ERR("Keep Warm allocation failed\n");
2005                goto error_kw;
2006        }
2007
2008        /* allocate tx queue structure */
2009        ret = il_alloc_txq_mem(il);
2010        if (ret)
2011                goto error;
2012
2013        spin_lock_irqsave(&il->lock, flags);
2014
2015        /* Turn off all Tx DMA fifos */
2016        il4965_txq_set_sched(il, 0);
2017
2018        /* Tell NIC where to find the "keep warm" buffer */
2019        il_wr(il, FH49_KW_MEM_ADDR_REG, il->kw.dma >> 4);
2020
2021        spin_unlock_irqrestore(&il->lock, flags);
2022
2023        /* Alloc and init all Tx queues, including the command queue (#4/#9) */
2024        for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++) {
2025                ret = il_tx_queue_init(il, txq_id);
2026                if (ret) {
2027                        IL_ERR("Tx %d queue init failed\n", txq_id);
2028                        goto error;
2029                }
2030        }
2031
2032        return ret;
2033
2034error:
2035        il4965_hw_txq_ctx_free(il);
2036        il4965_free_dma_ptr(il, &il->kw);
2037error_kw:
2038        il4965_free_dma_ptr(il, &il->scd_bc_tbls);
2039error_bc_tbls:
2040        return ret;
2041}
2042
2043void
2044il4965_txq_ctx_reset(struct il_priv *il)
2045{
2046        int txq_id;
2047        unsigned long flags;
2048
2049        spin_lock_irqsave(&il->lock, flags);
2050
2051        /* Turn off all Tx DMA fifos */
2052        il4965_txq_set_sched(il, 0);
2053        /* Tell NIC where to find the "keep warm" buffer */
2054        il_wr(il, FH49_KW_MEM_ADDR_REG, il->kw.dma >> 4);
2055
2056        spin_unlock_irqrestore(&il->lock, flags);
2057
2058        /* Alloc and init all Tx queues, including the command queue (#4) */
2059        for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++)
2060                il_tx_queue_reset(il, txq_id);
2061}
2062
2063static void
2064il4965_txq_ctx_unmap(struct il_priv *il)
2065{
2066        int txq_id;
2067
2068        if (!il->txq)
2069                return;
2070
2071        /* Unmap DMA from host system and free skb's */
2072        for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++)
2073                if (txq_id == il->cmd_queue)
2074                        il_cmd_queue_unmap(il);
2075                else
2076                        il_tx_queue_unmap(il, txq_id);
2077}
2078
2079/**
2080 * il4965_txq_ctx_stop - Stop all Tx DMA channels
2081 */
2082void
2083il4965_txq_ctx_stop(struct il_priv *il)
2084{
2085        int ch, ret;
2086
2087        _il_wr_prph(il, IL49_SCD_TXFACT, 0);
2088
2089        /* Stop each Tx DMA channel, and wait for it to be idle */
2090        for (ch = 0; ch < il->hw_params.dma_chnl_num; ch++) {
2091                _il_wr(il, FH49_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
2092                ret =
2093                    _il_poll_bit(il, FH49_TSSR_TX_STATUS_REG,
2094                                 FH49_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
2095                                 FH49_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
2096                                 1000);
2097                if (ret < 0)
2098                        IL_ERR("Timeout stopping DMA channel %d [0x%08x]",
2099                               ch, _il_rd(il, FH49_TSSR_TX_STATUS_REG));
2100        }
2101}
2102
2103/*
2104 * Find first available (lowest unused) Tx Queue, mark it "active".
2105 * Called only when finding queue for aggregation.
2106 * Should never return anything < 7, because they should already
2107 * be in use as EDCA AC (0-3), Command (4), reserved (5, 6)
2108 */
2109static int
2110il4965_txq_ctx_activate_free(struct il_priv *il)
2111{
2112        int txq_id;
2113
2114        for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++)
2115                if (!test_and_set_bit(txq_id, &il->txq_ctx_active_msk))
2116                        return txq_id;
2117        return -1;
2118}
2119
2120/**
2121 * il4965_tx_queue_stop_scheduler - Stop queue, but keep configuration
2122 */
2123static void
2124il4965_tx_queue_stop_scheduler(struct il_priv *il, u16 txq_id)
2125{
2126        /* Simply stop the queue, but don't change any configuration;
2127         * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
2128        il_wr_prph(il, IL49_SCD_QUEUE_STATUS_BITS(txq_id),
2129                   (0 << IL49_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
2130                   (1 << IL49_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
2131}
2132
2133/**
2134 * il4965_tx_queue_set_q2ratid - Map unique receiver/tid combination to a queue
2135 */
2136static int
2137il4965_tx_queue_set_q2ratid(struct il_priv *il, u16 ra_tid, u16 txq_id)
2138{
2139        u32 tbl_dw_addr;
2140        u32 tbl_dw;
2141        u16 scd_q2ratid;
2142
2143        scd_q2ratid = ra_tid & IL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
2144
2145        tbl_dw_addr =
2146            il->scd_base_addr + IL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
2147
2148        tbl_dw = il_read_targ_mem(il, tbl_dw_addr);
2149
2150        if (txq_id & 0x1)
2151                tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
2152        else
2153                tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
2154
2155        il_write_targ_mem(il, tbl_dw_addr, tbl_dw);
2156
2157        return 0;
2158}
2159
2160/**
2161 * il4965_tx_queue_agg_enable - Set up & enable aggregation for selected queue
2162 *
2163 * NOTE:  txq_id must be greater than IL49_FIRST_AMPDU_QUEUE,
2164 *        i.e. it must be one of the higher queues used for aggregation
2165 */
2166static int
2167il4965_txq_agg_enable(struct il_priv *il, int txq_id, int tx_fifo, int sta_id,
2168                      int tid, u16 ssn_idx)
2169{
2170        unsigned long flags;
2171        u16 ra_tid;
2172        int ret;
2173
2174        if ((IL49_FIRST_AMPDU_QUEUE > txq_id) ||
2175            (IL49_FIRST_AMPDU_QUEUE +
2176             il->cfg->num_of_ampdu_queues <= txq_id)) {
2177                IL_WARN("queue number out of range: %d, must be %d to %d\n",
2178                        txq_id, IL49_FIRST_AMPDU_QUEUE,
2179                        IL49_FIRST_AMPDU_QUEUE +
2180                        il->cfg->num_of_ampdu_queues - 1);
2181                return -EINVAL;
2182        }
2183
2184        ra_tid = BUILD_RAxTID(sta_id, tid);
2185
2186        /* Modify device's station table to Tx this TID */
2187        ret = il4965_sta_tx_modify_enable_tid(il, sta_id, tid);
2188        if (ret)
2189                return ret;
2190
2191        spin_lock_irqsave(&il->lock, flags);
2192
2193        /* Stop this Tx queue before configuring it */
2194        il4965_tx_queue_stop_scheduler(il, txq_id);
2195
2196        /* Map receiver-address / traffic-ID to this queue */
2197        il4965_tx_queue_set_q2ratid(il, ra_tid, txq_id);
2198
2199        /* Set this queue as a chain-building queue */
2200        il_set_bits_prph(il, IL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
2201
2202        /* Place first TFD at idx corresponding to start sequence number.
2203         * Assumes that ssn_idx is valid (!= 0xFFF) */
2204        il->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
2205        il->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
2206        il4965_set_wr_ptrs(il, txq_id, ssn_idx);
2207
2208        /* Set up Tx win size and frame limit for this queue */
2209        il_write_targ_mem(il,
2210                          il->scd_base_addr +
2211                          IL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id),
2212                          (SCD_WIN_SIZE << IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS)
2213                          & IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
2214
2215        il_write_targ_mem(il,
2216                          il->scd_base_addr +
2217                          IL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
2218                          (SCD_FRAME_LIMIT <<
2219                           IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
2220                          IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
2221
2222        il_set_bits_prph(il, IL49_SCD_INTERRUPT_MASK, (1 << txq_id));
2223
2224        /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
2225        il4965_tx_queue_set_status(il, &il->txq[txq_id], tx_fifo, 1);
2226
2227        spin_unlock_irqrestore(&il->lock, flags);
2228
2229        return 0;
2230}
2231
2232int
2233il4965_tx_agg_start(struct il_priv *il, struct ieee80211_vif *vif,
2234                    struct ieee80211_sta *sta, u16 tid, u16 * ssn)
2235{
2236        int sta_id;
2237        int tx_fifo;
2238        int txq_id;
2239        int ret;
2240        unsigned long flags;
2241        struct il_tid_data *tid_data;
2242
2243        /* FIXME: warning if tx fifo not found ? */
2244        tx_fifo = il4965_get_fifo_from_tid(tid);
2245        if (unlikely(tx_fifo < 0))
2246                return tx_fifo;
2247
2248        D_HT("%s on ra = %pM tid = %d\n", __func__, sta->addr, tid);
2249
2250        sta_id = il_sta_id(sta);
2251        if (sta_id == IL_INVALID_STATION) {
2252                IL_ERR("Start AGG on invalid station\n");
2253                return -ENXIO;
2254        }
2255        if (unlikely(tid >= MAX_TID_COUNT))
2256                return -EINVAL;
2257
2258        if (il->stations[sta_id].tid[tid].agg.state != IL_AGG_OFF) {
2259                IL_ERR("Start AGG when state is not IL_AGG_OFF !\n");
2260                return -ENXIO;
2261        }
2262
2263        txq_id = il4965_txq_ctx_activate_free(il);
2264        if (txq_id == -1) {
2265                IL_ERR("No free aggregation queue available\n");
2266                return -ENXIO;
2267        }
2268
2269        spin_lock_irqsave(&il->sta_lock, flags);
2270        tid_data = &il->stations[sta_id].tid[tid];
2271        *ssn = IEEE80211_SEQ_TO_SN(tid_data->seq_number);
2272        tid_data->agg.txq_id = txq_id;
2273        il_set_swq_id(&il->txq[txq_id], il4965_get_ac_from_tid(tid), txq_id);
2274        spin_unlock_irqrestore(&il->sta_lock, flags);
2275
2276        ret = il4965_txq_agg_enable(il, txq_id, tx_fifo, sta_id, tid, *ssn);
2277        if (ret)
2278                return ret;
2279
2280        spin_lock_irqsave(&il->sta_lock, flags);
2281        tid_data = &il->stations[sta_id].tid[tid];
2282        if (tid_data->tfds_in_queue == 0) {
2283                D_HT("HW queue is empty\n");
2284                tid_data->agg.state = IL_AGG_ON;
2285                ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
2286        } else {
2287                D_HT("HW queue is NOT empty: %d packets in HW queue\n",
2288                     tid_data->tfds_in_queue);
2289                tid_data->agg.state = IL_EMPTYING_HW_QUEUE_ADDBA;
2290        }
2291        spin_unlock_irqrestore(&il->sta_lock, flags);
2292        return ret;
2293}
2294
2295/**
2296 * txq_id must be greater than IL49_FIRST_AMPDU_QUEUE
2297 * il->lock must be held by the caller
2298 */
2299static int
2300il4965_txq_agg_disable(struct il_priv *il, u16 txq_id, u16 ssn_idx, u8 tx_fifo)
2301{
2302        if ((IL49_FIRST_AMPDU_QUEUE > txq_id) ||
2303            (IL49_FIRST_AMPDU_QUEUE +
2304             il->cfg->num_of_ampdu_queues <= txq_id)) {
2305                IL_WARN("queue number out of range: %d, must be %d to %d\n",
2306                        txq_id, IL49_FIRST_AMPDU_QUEUE,
2307                        IL49_FIRST_AMPDU_QUEUE +
2308                        il->cfg->num_of_ampdu_queues - 1);
2309                return -EINVAL;
2310        }
2311
2312        il4965_tx_queue_stop_scheduler(il, txq_id);
2313
2314        il_clear_bits_prph(il, IL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
2315
2316        il->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
2317        il->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
2318        /* supposes that ssn_idx is valid (!= 0xFFF) */
2319        il4965_set_wr_ptrs(il, txq_id, ssn_idx);
2320
2321        il_clear_bits_prph(il, IL49_SCD_INTERRUPT_MASK, (1 << txq_id));
2322        il_txq_ctx_deactivate(il, txq_id);
2323        il4965_tx_queue_set_status(il, &il->txq[txq_id], tx_fifo, 0);
2324
2325        return 0;
2326}
2327
2328int
2329il4965_tx_agg_stop(struct il_priv *il, struct ieee80211_vif *vif,
2330                   struct ieee80211_sta *sta, u16 tid)
2331{
2332        int tx_fifo_id, txq_id, sta_id, ssn;
2333        struct il_tid_data *tid_data;
2334        int write_ptr, read_ptr;
2335        unsigned long flags;
2336
2337        /* FIXME: warning if tx_fifo_id not found ? */
2338        tx_fifo_id = il4965_get_fifo_from_tid(tid);
2339        if (unlikely(tx_fifo_id < 0))
2340                return tx_fifo_id;
2341
2342        sta_id = il_sta_id(sta);
2343
2344        if (sta_id == IL_INVALID_STATION) {
2345                IL_ERR("Invalid station for AGG tid %d\n", tid);
2346                return -ENXIO;
2347        }
2348
2349        spin_lock_irqsave(&il->sta_lock, flags);
2350
2351        tid_data = &il->stations[sta_id].tid[tid];
2352        ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4;
2353        txq_id = tid_data->agg.txq_id;
2354
2355        switch (il->stations[sta_id].tid[tid].agg.state) {
2356        case IL_EMPTYING_HW_QUEUE_ADDBA:
2357                /*
2358                 * This can happen if the peer stops aggregation
2359                 * again before we've had a chance to drain the
2360                 * queue we selected previously, i.e. before the
2361                 * session was really started completely.
2362                 */
2363                D_HT("AGG stop before setup done\n");
2364                goto turn_off;
2365        case IL_AGG_ON:
2366                break;
2367        default:
2368                IL_WARN("Stopping AGG while state not ON or starting\n");
2369        }
2370
2371        write_ptr = il->txq[txq_id].q.write_ptr;
2372        read_ptr = il->txq[txq_id].q.read_ptr;
2373
2374        /* The queue is not empty */
2375        if (write_ptr != read_ptr) {
2376                D_HT("Stopping a non empty AGG HW QUEUE\n");
2377                il->stations[sta_id].tid[tid].agg.state =
2378                    IL_EMPTYING_HW_QUEUE_DELBA;
2379                spin_unlock_irqrestore(&il->sta_lock, flags);
2380                return 0;
2381        }
2382
2383        D_HT("HW queue is empty\n");
2384turn_off:
2385        il->stations[sta_id].tid[tid].agg.state = IL_AGG_OFF;
2386
2387        /* do not restore/save irqs */
2388        spin_unlock(&il->sta_lock);
2389        spin_lock(&il->lock);
2390
2391        /*
2392         * the only reason this call can fail is queue number out of range,
2393         * which can happen if uCode is reloaded and all the station
2394         * information are lost. if it is outside the range, there is no need
2395         * to deactivate the uCode queue, just return "success" to allow
2396         *  mac80211 to clean up it own data.
2397         */
2398        il4965_txq_agg_disable(il, txq_id, ssn, tx_fifo_id);
2399        spin_unlock_irqrestore(&il->lock, flags);
2400
2401        ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
2402
2403        return 0;
2404}
2405
2406int
2407il4965_txq_check_empty(struct il_priv *il, int sta_id, u8 tid, int txq_id)
2408{
2409        struct il_queue *q = &il->txq[txq_id].q;
2410        u8 *addr = il->stations[sta_id].sta.sta.addr;
2411        struct il_tid_data *tid_data = &il->stations[sta_id].tid[tid];
2412
2413        lockdep_assert_held(&il->sta_lock);
2414
2415        switch (il->stations[sta_id].tid[tid].agg.state) {
2416        case IL_EMPTYING_HW_QUEUE_DELBA:
2417                /* We are reclaiming the last packet of the */
2418                /* aggregated HW queue */
2419                if (txq_id == tid_data->agg.txq_id &&
2420                    q->read_ptr == q->write_ptr) {
2421                        u16 ssn = IEEE80211_SEQ_TO_SN(tid_data->seq_number);
2422                        int tx_fifo = il4965_get_fifo_from_tid(tid);
2423                        D_HT("HW queue empty: continue DELBA flow\n");
2424                        il4965_txq_agg_disable(il, txq_id, ssn, tx_fifo);
2425                        tid_data->agg.state = IL_AGG_OFF;
2426                        ieee80211_stop_tx_ba_cb_irqsafe(il->vif, addr, tid);
2427                }
2428                break;
2429        case IL_EMPTYING_HW_QUEUE_ADDBA:
2430                /* We are reclaiming the last packet of the queue */
2431                if (tid_data->tfds_in_queue == 0) {
2432                        D_HT("HW queue empty: continue ADDBA flow\n");
2433                        tid_data->agg.state = IL_AGG_ON;
2434                        ieee80211_start_tx_ba_cb_irqsafe(il->vif, addr, tid);
2435                }
2436                break;
2437        }
2438
2439        return 0;
2440}
2441
2442static void
2443il4965_non_agg_tx_status(struct il_priv *il, const u8 *addr1)
2444{
2445        struct ieee80211_sta *sta;
2446        struct il_station_priv *sta_priv;
2447
2448        rcu_read_lock();
2449        sta = ieee80211_find_sta(il->vif, addr1);
2450        if (sta) {
2451                sta_priv = (void *)sta->drv_priv;
2452                /* avoid atomic ops if this isn't a client */
2453                if (sta_priv->client &&
2454                    atomic_dec_return(&sta_priv->pending_frames) == 0)
2455                        ieee80211_sta_block_awake(il->hw, sta, false);
2456        }
2457        rcu_read_unlock();
2458}
2459
2460static void
2461il4965_tx_status(struct il_priv *il, struct sk_buff *skb, bool is_agg)
2462{
2463        struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2464
2465        if (!is_agg)
2466                il4965_non_agg_tx_status(il, hdr->addr1);
2467
2468        ieee80211_tx_status_irqsafe(il->hw, skb);
2469}
2470
2471int
2472il4965_tx_queue_reclaim(struct il_priv *il, int txq_id, int idx)
2473{
2474        struct il_tx_queue *txq = &il->txq[txq_id];
2475        struct il_queue *q = &txq->q;
2476        int nfreed = 0;
2477        struct ieee80211_hdr *hdr;
2478        struct sk_buff *skb;
2479
2480        if (idx >= q->n_bd || il_queue_used(q, idx) == 0) {
2481                IL_ERR("Read idx for DMA queue txq id (%d), idx %d, "
2482                       "is out of range [0-%d] %d %d.\n", txq_id, idx, q->n_bd,
2483                       q->write_ptr, q->read_ptr);
2484                return 0;
2485        }
2486
2487        for (idx = il_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;
2488             q->read_ptr = il_queue_inc_wrap(q->read_ptr, q->n_bd)) {
2489
2490                skb = txq->skbs[txq->q.read_ptr];
2491
2492                if (WARN_ON_ONCE(skb == NULL))
2493                        continue;
2494
2495                hdr = (struct ieee80211_hdr *) skb->data;
2496                if (ieee80211_is_data_qos(hdr->frame_control))
2497                        nfreed++;
2498
2499                il4965_tx_status(il, skb, txq_id >= IL4965_FIRST_AMPDU_QUEUE);
2500
2501                txq->skbs[txq->q.read_ptr] = NULL;
2502                il->ops->txq_free_tfd(il, txq);
2503        }
2504        return nfreed;
2505}
2506
2507/**
2508 * il4965_tx_status_reply_compressed_ba - Update tx status from block-ack
2509 *
2510 * Go through block-ack's bitmap of ACK'd frames, update driver's record of
2511 * ACK vs. not.  This gets sent to mac80211, then to rate scaling algo.
2512 */
2513static int
2514il4965_tx_status_reply_compressed_ba(struct il_priv *il, struct il_ht_agg *agg,
2515                                     struct il_compressed_ba_resp *ba_resp)
2516{
2517        int i, sh, ack;
2518        u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl);
2519        u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
2520        int successes = 0;
2521        struct ieee80211_tx_info *info;
2522        u64 bitmap, sent_bitmap;
2523
2524        if (unlikely(!agg->wait_for_ba)) {
2525                if (unlikely(ba_resp->bitmap))
2526                        IL_ERR("Received BA when not expected\n");
2527                return -EINVAL;
2528        }
2529
2530        /* Mark that the expected block-ack response arrived */
2531        agg->wait_for_ba = 0;
2532        D_TX_REPLY("BA %d %d\n", agg->start_idx, ba_resp->seq_ctl);
2533
2534        /* Calculate shift to align block-ack bits with our Tx win bits */
2535        sh = agg->start_idx - SEQ_TO_IDX(seq_ctl >> 4);
2536        if (sh < 0)             /* tbw something is wrong with indices */
2537                sh += 0x100;
2538
2539        if (agg->frame_count > (64 - sh)) {
2540                D_TX_REPLY("more frames than bitmap size");
2541                return -1;
2542        }
2543
2544        /* don't use 64-bit values for now */
2545        bitmap = le64_to_cpu(ba_resp->bitmap) >> sh;
2546
2547        /* check for success or failure according to the
2548         * transmitted bitmap and block-ack bitmap */
2549        sent_bitmap = bitmap & agg->bitmap;
2550
2551        /* For each frame attempted in aggregation,
2552         * update driver's record of tx frame's status. */
2553        i = 0;
2554        while (sent_bitmap) {
2555                ack = sent_bitmap & 1ULL;
2556                successes += ack;
2557                D_TX_REPLY("%s ON i=%d idx=%d raw=%d\n", ack ? "ACK" : "NACK",
2558                           i, (agg->start_idx + i) & 0xff, agg->start_idx + i);
2559                sent_bitmap >>= 1;
2560                ++i;
2561        }
2562
2563        D_TX_REPLY("Bitmap %llx\n", (unsigned long long)bitmap);
2564
2565        info = IEEE80211_SKB_CB(il->txq[scd_flow].skbs[agg->start_idx]);
2566        memset(&info->status, 0, sizeof(info->status));
2567        info->flags |= IEEE80211_TX_STAT_ACK;
2568        info->flags |= IEEE80211_TX_STAT_AMPDU;
2569        info->status.ampdu_ack_len = successes;
2570        info->status.ampdu_len = agg->frame_count;
2571        il4965_hwrate_to_tx_control(il, agg->rate_n_flags, info);
2572
2573        return 0;
2574}
2575
2576static inline bool
2577il4965_is_tx_success(u32 status)
2578{
2579        status &= TX_STATUS_MSK;
2580        return (status == TX_STATUS_SUCCESS || status == TX_STATUS_DIRECT_DONE);
2581}
2582
2583static u8
2584il4965_find_station(struct il_priv *il, const u8 *addr)
2585{
2586        int i;
2587        int start = 0;
2588        int ret = IL_INVALID_STATION;
2589        unsigned long flags;
2590
2591        if (il->iw_mode == NL80211_IFTYPE_ADHOC)
2592                start = IL_STA_ID;
2593
2594        if (is_broadcast_ether_addr(addr))
2595                return il->hw_params.bcast_id;
2596
2597        spin_lock_irqsave(&il->sta_lock, flags);
2598        for (i = start; i < il->hw_params.max_stations; i++)
2599                if (il->stations[i].used &&
2600                    ether_addr_equal(il->stations[i].sta.sta.addr, addr)) {
2601                        ret = i;
2602                        goto out;
2603                }
2604
2605        D_ASSOC("can not find STA %pM total %d\n", addr, il->num_stations);
2606
2607out:
2608        /*
2609         * It may be possible that more commands interacting with stations
2610         * arrive before we completed processing the adding of
2611         * station
2612         */
2613        if (ret != IL_INVALID_STATION &&
2614            (!(il->stations[ret].used & IL_STA_UCODE_ACTIVE) ||
2615             ((il->stations[ret].used & IL_STA_UCODE_ACTIVE) &&
2616              (il->stations[ret].used & IL_STA_UCODE_INPROGRESS)))) {
2617                IL_ERR("Requested station info for sta %d before ready.\n",
2618                       ret);
2619                ret = IL_INVALID_STATION;
2620        }
2621        spin_unlock_irqrestore(&il->sta_lock, flags);
2622        return ret;
2623}
2624
2625static int
2626il4965_get_ra_sta_id(struct il_priv *il, struct ieee80211_hdr *hdr)
2627{
2628        if (il->iw_mode == NL80211_IFTYPE_STATION)
2629                return IL_AP_ID;
2630        else {
2631                u8 *da = ieee80211_get_DA(hdr);
2632
2633                return il4965_find_station(il, da);
2634        }
2635}
2636
2637static inline u32
2638il4965_get_scd_ssn(struct il4965_tx_resp *tx_resp)
2639{
2640        return le32_to_cpup(&tx_resp->u.status +
2641                            tx_resp->frame_count) & IEEE80211_MAX_SN;
2642}
2643
2644static inline u32
2645il4965_tx_status_to_mac80211(u32 status)
2646{
2647        status &= TX_STATUS_MSK;
2648
2649        switch (status) {
2650        case TX_STATUS_SUCCESS:
2651        case TX_STATUS_DIRECT_DONE:
2652                return IEEE80211_TX_STAT_ACK;
2653        case TX_STATUS_FAIL_DEST_PS:
2654                return IEEE80211_TX_STAT_TX_FILTERED;
2655        default:
2656                return 0;
2657        }
2658}
2659
2660/**
2661 * il4965_tx_status_reply_tx - Handle Tx response for frames in aggregation queue
2662 */
2663static int
2664il4965_tx_status_reply_tx(struct il_priv *il, struct il_ht_agg *agg,
2665                          struct il4965_tx_resp *tx_resp, int txq_id,
2666                          u16 start_idx)
2667{
2668        u16 status;
2669        struct agg_tx_status *frame_status = tx_resp->u.agg_status;
2670        struct ieee80211_tx_info *info = NULL;
2671        struct ieee80211_hdr *hdr = NULL;
2672        u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
2673        int i, sh, idx;
2674        u16 seq;
2675        if (agg->wait_for_ba)
2676                D_TX_REPLY("got tx response w/o block-ack\n");
2677
2678        agg->frame_count = tx_resp->frame_count;
2679        agg->start_idx = start_idx;
2680        agg->rate_n_flags = rate_n_flags;
2681        agg->bitmap = 0;
2682
2683        /* num frames attempted by Tx command */
2684        if (agg->frame_count == 1) {
2685                /* Only one frame was attempted; no block-ack will arrive */
2686                status = le16_to_cpu(frame_status[0].status);
2687                idx = start_idx;
2688
2689                D_TX_REPLY("FrameCnt = %d, StartIdx=%d idx=%d\n",
2690                           agg->frame_count, agg->start_idx, idx);
2691
2692                info = IEEE80211_SKB_CB(il->txq[txq_id].skbs[idx]);
2693                info->status.rates[0].count = tx_resp->failure_frame + 1;
2694                info->flags &= ~IEEE80211_TX_CTL_AMPDU;
2695                info->flags |= il4965_tx_status_to_mac80211(status);
2696                il4965_hwrate_to_tx_control(il, rate_n_flags, info);
2697
2698                D_TX_REPLY("1 Frame 0x%x failure :%d\n", status & 0xff,
2699                           tx_resp->failure_frame);
2700                D_TX_REPLY("Rate Info rate_n_flags=%x\n", rate_n_flags);
2701
2702                agg->wait_for_ba = 0;
2703        } else {
2704                /* Two or more frames were attempted; expect block-ack */
2705                u64 bitmap = 0;
2706                int start = agg->start_idx;
2707                struct sk_buff *skb;
2708
2709                /* Construct bit-map of pending frames within Tx win */
2710                for (i = 0; i < agg->frame_count; i++) {
2711                        u16 sc;
2712                        status = le16_to_cpu(frame_status[i].status);
2713                        seq = le16_to_cpu(frame_status[i].sequence);
2714                        idx = SEQ_TO_IDX(seq);
2715                        txq_id = SEQ_TO_QUEUE(seq);
2716
2717                        if (status &
2718                            (AGG_TX_STATE_FEW_BYTES_MSK |
2719                             AGG_TX_STATE_ABORT_MSK))
2720                                continue;
2721
2722                        D_TX_REPLY("FrameCnt = %d, txq_id=%d idx=%d\n",
2723                                   agg->frame_count, txq_id, idx);
2724
2725                        skb = il->txq[txq_id].skbs[idx];
2726                        if (WARN_ON_ONCE(skb == NULL))
2727                                return -1;
2728                        hdr = (struct ieee80211_hdr *) skb->data;
2729
2730                        sc = le16_to_cpu(hdr->seq_ctrl);
2731                        if (idx != (IEEE80211_SEQ_TO_SN(sc) & 0xff)) {
2732                                IL_ERR("BUG_ON idx doesn't match seq control"
2733                                       " idx=%d, seq_idx=%d, seq=%d\n", idx,
2734                                       IEEE80211_SEQ_TO_SN(sc), hdr->seq_ctrl);
2735                                return -1;
2736                        }
2737
2738                        D_TX_REPLY("AGG Frame i=%d idx %d seq=%d\n", i, idx,
2739                                   IEEE80211_SEQ_TO_SN(sc));
2740
2741                        sh = idx - start;
2742                        if (sh > 64) {
2743                                sh = (start - idx) + 0xff;
2744                                bitmap = bitmap << sh;
2745                                sh = 0;
2746                                start = idx;
2747                        } else if (sh < -64)
2748                                sh = 0xff - (start - idx);
2749                        else if (sh < 0) {
2750                                sh = start - idx;
2751                                start = idx;
2752                                bitmap = bitmap << sh;
2753                                sh = 0;
2754                        }
2755                        bitmap |= 1ULL << sh;
2756                        D_TX_REPLY("start=%d bitmap=0x%llx\n", start,
2757                                   (unsigned long long)bitmap);
2758                }
2759
2760                agg->bitmap = bitmap;
2761                agg->start_idx = start;
2762                D_TX_REPLY("Frames %d start_idx=%d bitmap=0x%llx\n",
2763                           agg->frame_count, agg->start_idx,
2764                           (unsigned long long)agg->bitmap);
2765
2766                if (bitmap)
2767                        agg->wait_for_ba = 1;
2768        }
2769        return 0;
2770}
2771
2772/**
2773 * il4965_hdl_tx - Handle standard (non-aggregation) Tx response
2774 */
2775static void
2776il4965_hdl_tx(struct il_priv *il, struct il_rx_buf *rxb)
2777{
2778        struct il_rx_pkt *pkt = rxb_addr(rxb);
2779        u16 sequence = le16_to_cpu(pkt->hdr.sequence);
2780        int txq_id = SEQ_TO_QUEUE(sequence);
2781        int idx = SEQ_TO_IDX(sequence);
2782        struct il_tx_queue *txq = &il->txq[txq_id];
2783        struct sk_buff *skb;
2784        struct ieee80211_hdr *hdr;
2785        struct ieee80211_tx_info *info;
2786        struct il4965_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
2787        u32 status = le32_to_cpu(tx_resp->u.status);
2788        int uninitialized_var(tid);
2789        int sta_id;
2790        int freed;
2791        u8 *qc = NULL;
2792        unsigned long flags;
2793
2794        if (idx >= txq->q.n_bd || il_queue_used(&txq->q, idx) == 0) {
2795                IL_ERR("Read idx for DMA queue txq_id (%d) idx %d "
2796                       "is out of range [0-%d] %d %d\n", txq_id, idx,
2797                       txq->q.n_bd, txq->q.write_ptr, txq->q.read_ptr);
2798                return;
2799        }
2800
2801        txq->time_stamp = jiffies;
2802
2803        skb = txq->skbs[txq->q.read_ptr];
2804        info = IEEE80211_SKB_CB(skb);
2805        memset(&info->status, 0, sizeof(info->status));
2806
2807        hdr = (struct ieee80211_hdr *) skb->data;
2808        if (ieee80211_is_data_qos(hdr->frame_control)) {
2809                qc = ieee80211_get_qos_ctl(hdr);
2810                tid = qc[0] & 0xf;
2811        }
2812
2813        sta_id = il4965_get_ra_sta_id(il, hdr);
2814        if (txq->sched_retry && unlikely(sta_id == IL_INVALID_STATION)) {
2815                IL_ERR("Station not known\n");
2816                return;
2817        }
2818
2819        /*
2820         * Firmware will not transmit frame on passive channel, if it not yet
2821         * received some valid frame on that channel. When this error happen
2822         * we have to wait until firmware will unblock itself i.e. when we
2823         * note received beacon or other frame. We unblock queues in
2824         * il4965_pass_packet_to_mac80211 or in il_mac_bss_info_changed.
2825         */
2826        if (unlikely((status & TX_STATUS_MSK) == TX_STATUS_FAIL_PASSIVE_NO_RX) &&
2827            il->iw_mode == NL80211_IFTYPE_STATION) {
2828                il_stop_queues_by_reason(il, IL_STOP_REASON_PASSIVE);
2829                D_INFO("Stopped queues - RX waiting on passive channel\n");
2830        }
2831
2832        spin_lock_irqsave(&il->sta_lock, flags);
2833        if (txq->sched_retry) {
2834                const u32 scd_ssn = il4965_get_scd_ssn(tx_resp);
2835                struct il_ht_agg *agg = NULL;
2836                WARN_ON(!qc);
2837
2838                agg = &il->stations[sta_id].tid[tid].agg;
2839
2840                il4965_tx_status_reply_tx(il, agg, tx_resp, txq_id, idx);
2841
2842                /* check if BAR is needed */
2843                if (tx_resp->frame_count == 1 &&
2844                    !il4965_is_tx_success(status))
2845                        info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
2846
2847                if (txq->q.read_ptr != (scd_ssn & 0xff)) {
2848                        idx = il_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
2849                        D_TX_REPLY("Retry scheduler reclaim scd_ssn "
2850                                   "%d idx %d\n", scd_ssn, idx);
2851                        freed = il4965_tx_queue_reclaim(il, txq_id, idx);
2852                        if (qc)
2853                                il4965_free_tfds_in_queue(il, sta_id, tid,
2854                                                          freed);
2855
2856                        if (il->mac80211_registered &&
2857                            il_queue_space(&txq->q) > txq->q.low_mark &&
2858                            agg->state != IL_EMPTYING_HW_QUEUE_DELBA)
2859                                il_wake_queue(il, txq);
2860                }
2861        } else {
2862                info->status.rates[0].count = tx_resp->failure_frame + 1;
2863                info->flags |= il4965_tx_status_to_mac80211(status);
2864                il4965_hwrate_to_tx_control(il,
2865                                            le32_to_cpu(tx_resp->rate_n_flags),
2866                                            info);
2867
2868                D_TX_REPLY("TXQ %d status %s (0x%08x) "
2869                           "rate_n_flags 0x%x retries %d\n", txq_id,
2870                           il4965_get_tx_fail_reason(status), status,
2871                           le32_to_cpu(tx_resp->rate_n_flags),
2872                           tx_resp->failure_frame);
2873
2874                freed = il4965_tx_queue_reclaim(il, txq_id, idx);
2875                if (qc && likely(sta_id != IL_INVALID_STATION))
2876                        il4965_free_tfds_in_queue(il, sta_id, tid, freed);
2877                else if (sta_id == IL_INVALID_STATION)
2878                        D_TX_REPLY("Station not known\n");
2879
2880                if (il->mac80211_registered &&
2881                    il_queue_space(&txq->q) > txq->q.low_mark)
2882                        il_wake_queue(il, txq);
2883        }
2884        if (qc && likely(sta_id != IL_INVALID_STATION))
2885                il4965_txq_check_empty(il, sta_id, tid, txq_id);
2886
2887        il4965_check_abort_status(il, tx_resp->frame_count, status);
2888
2889        spin_unlock_irqrestore(&il->sta_lock, flags);
2890}
2891
2892/**
2893 * translate ucode response to mac80211 tx status control values
2894 */
2895void
2896il4965_hwrate_to_tx_control(struct il_priv *il, u32 rate_n_flags,
2897                            struct ieee80211_tx_info *info)
2898{
2899        struct ieee80211_tx_rate *r = &info->status.rates[0];
2900
2901        info->status.antenna =
2902            ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS);
2903        if (rate_n_flags & RATE_MCS_HT_MSK)
2904                r->flags |= IEEE80211_TX_RC_MCS;
2905        if (rate_n_flags & RATE_MCS_GF_MSK)
2906                r->flags |= IEEE80211_TX_RC_GREEN_FIELD;
2907        if (rate_n_flags & RATE_MCS_HT40_MSK)
2908                r->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
2909        if (rate_n_flags & RATE_MCS_DUP_MSK)
2910                r->flags |= IEEE80211_TX_RC_DUP_DATA;
2911        if (rate_n_flags & RATE_MCS_SGI_MSK)
2912                r->flags |= IEEE80211_TX_RC_SHORT_GI;
2913        r->idx = il4965_hwrate_to_mac80211_idx(rate_n_flags, info->band);
2914}
2915
2916/**
2917 * il4965_hdl_compressed_ba - Handler for N_COMPRESSED_BA
2918 *
2919 * Handles block-acknowledge notification from device, which reports success
2920 * of frames sent via aggregation.
2921 */
2922static void
2923il4965_hdl_compressed_ba(struct il_priv *il, struct il_rx_buf *rxb)
2924{
2925        struct il_rx_pkt *pkt = rxb_addr(rxb);
2926        struct il_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba;
2927        struct il_tx_queue *txq = NULL;
2928        struct il_ht_agg *agg;
2929        int idx;
2930        int sta_id;
2931        int tid;
2932        unsigned long flags;
2933
2934        /* "flow" corresponds to Tx queue */
2935        u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
2936
2937        /* "ssn" is start of block-ack Tx win, corresponds to idx
2938         * (in Tx queue's circular buffer) of first TFD/frame in win */
2939        u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn);
2940
2941        if (scd_flow >= il->hw_params.max_txq_num) {
2942                IL_ERR("BUG_ON scd_flow is bigger than number of queues\n");
2943                return;
2944        }
2945
2946        txq = &il->txq[scd_flow];
2947        sta_id = ba_resp->sta_id;
2948        tid = ba_resp->tid;
2949        agg = &il->stations[sta_id].tid[tid].agg;
2950        if (unlikely(agg->txq_id != scd_flow)) {
2951                /*
2952                 * FIXME: this is a uCode bug which need to be addressed,
2953                 * log the information and return for now!
2954                 * since it is possible happen very often and in order
2955                 * not to fill the syslog, don't enable the logging by default
2956                 */
2957                D_TX_REPLY("BA scd_flow %d does not match txq_id %d\n",
2958                           scd_flow, agg->txq_id);
2959                return;
2960        }
2961
2962        /* Find idx just before block-ack win */
2963        idx = il_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd);
2964
2965        spin_lock_irqsave(&il->sta_lock, flags);
2966
2967        D_TX_REPLY("N_COMPRESSED_BA [%d] Received from %pM, " "sta_id = %d\n",
2968                   agg->wait_for_ba, (u8 *) &ba_resp->sta_addr_lo32,
2969                   ba_resp->sta_id);
2970        D_TX_REPLY("TID = %d, SeqCtl = %d, bitmap = 0x%llx," "scd_flow = "
2971                   "%d, scd_ssn = %d\n", ba_resp->tid, ba_resp->seq_ctl,
2972                   (unsigned long long)le64_to_cpu(ba_resp->bitmap),
2973                   ba_resp->scd_flow, ba_resp->scd_ssn);
2974        D_TX_REPLY("DAT start_idx = %d, bitmap = 0x%llx\n", agg->start_idx,
2975                   (unsigned long long)agg->bitmap);
2976
2977        /* Update driver's record of ACK vs. not for each frame in win */
2978        il4965_tx_status_reply_compressed_ba(il, agg, ba_resp);
2979
2980        /* Release all TFDs before the SSN, i.e. all TFDs in front of
2981         * block-ack win (we assume that they've been successfully
2982         * transmitted ... if not, it's too late anyway). */
2983        if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) {
2984                /* calculate mac80211 ampdu sw queue to wake */
2985                int freed = il4965_tx_queue_reclaim(il, scd_flow, idx);
2986                il4965_free_tfds_in_queue(il, sta_id, tid, freed);
2987
2988                if (il_queue_space(&txq->q) > txq->q.low_mark &&
2989                    il->mac80211_registered &&
2990                    agg->state != IL_EMPTYING_HW_QUEUE_DELBA)
2991                        il_wake_queue(il, txq);
2992
2993                il4965_txq_check_empty(il, sta_id, tid, scd_flow);
2994        }
2995
2996        spin_unlock_irqrestore(&il->sta_lock, flags);
2997}
2998
2999#ifdef CONFIG_IWLEGACY_DEBUG
3000const char *
3001il4965_get_tx_fail_reason(u32 status)
3002{
3003#define TX_STATUS_FAIL(x) case TX_STATUS_FAIL_ ## x: return #x
3004#define TX_STATUS_POSTPONE(x) case TX_STATUS_POSTPONE_ ## x: return #x
3005
3006        switch (status & TX_STATUS_MSK) {
3007        case TX_STATUS_SUCCESS:
3008                return "SUCCESS";
3009                TX_STATUS_POSTPONE(DELAY);
3010                TX_STATUS_POSTPONE(FEW_BYTES);
3011                TX_STATUS_POSTPONE(QUIET_PERIOD);
3012                TX_STATUS_POSTPONE(CALC_TTAK);
3013                TX_STATUS_FAIL(INTERNAL_CROSSED_RETRY);
3014                TX_STATUS_FAIL(SHORT_LIMIT);
3015                TX_STATUS_FAIL(LONG_LIMIT);
3016                TX_STATUS_FAIL(FIFO_UNDERRUN);
3017                TX_STATUS_FAIL(DRAIN_FLOW);
3018                TX_STATUS_FAIL(RFKILL_FLUSH);
3019                TX_STATUS_FAIL(LIFE_EXPIRE);
3020                TX_STATUS_FAIL(DEST_PS);
3021                TX_STATUS_FAIL(HOST_ABORTED);
3022                TX_STATUS_FAIL(BT_RETRY);
3023                TX_STATUS_FAIL(STA_INVALID);
3024                TX_STATUS_FAIL(FRAG_DROPPED);
3025                TX_STATUS_FAIL(TID_DISABLE);
3026                TX_STATUS_FAIL(FIFO_FLUSHED);
3027                TX_STATUS_FAIL(INSUFFICIENT_CF_POLL);
3028                TX_STATUS_FAIL(PASSIVE_NO_RX);
3029                TX_STATUS_FAIL(NO_BEACON_ON_RADAR);
3030        }
3031
3032        return "UNKNOWN";
3033
3034#undef TX_STATUS_FAIL
3035#undef TX_STATUS_POSTPONE
3036}
3037#endif /* CONFIG_IWLEGACY_DEBUG */
3038
3039static struct il_link_quality_cmd *
3040il4965_sta_alloc_lq(struct il_priv *il, u8 sta_id)
3041{
3042        int i, r;
3043        struct il_link_quality_cmd *link_cmd;
3044        u32 rate_flags = 0;
3045        __le32 rate_n_flags;
3046
3047        link_cmd = kzalloc(sizeof(struct il_link_quality_cmd), GFP_KERNEL);
3048        if (!link_cmd) {
3049                IL_ERR("Unable to allocate memory for LQ cmd.\n");
3050                return NULL;
3051        }
3052        /* Set up the rate scaling to start at selected rate, fall back
3053         * all the way down to 1M in IEEE order, and then spin on 1M */
3054        if (il->band == IEEE80211_BAND_5GHZ)
3055                r = RATE_6M_IDX;
3056        else
3057                r = RATE_1M_IDX;
3058
3059        if (r >= IL_FIRST_CCK_RATE && r <= IL_LAST_CCK_RATE)
3060                rate_flags |= RATE_MCS_CCK_MSK;
3061
3062        rate_flags |=
3063            il4965_first_antenna(il->hw_params.
3064                                 valid_tx_ant) << RATE_MCS_ANT_POS;
3065        rate_n_flags = cpu_to_le32(il_rates[r].plcp | rate_flags);
3066        for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++)
3067                link_cmd->rs_table[i].rate_n_flags = rate_n_flags;
3068
3069        link_cmd->general_params.single_stream_ant_msk =
3070            il4965_first_antenna(il->hw_params.valid_tx_ant);
3071
3072        link_cmd->general_params.dual_stream_ant_msk =
3073            il->hw_params.valid_tx_ant & ~il4965_first_antenna(il->hw_params.
3074                                                               valid_tx_ant);
3075        if (!link_cmd->general_params.dual_stream_ant_msk) {
3076                link_cmd->general_params.dual_stream_ant_msk = ANT_AB;
3077        } else if (il4965_num_of_ant(il->hw_params.valid_tx_ant) == 2) {
3078                link_cmd->general_params.dual_stream_ant_msk =
3079                    il->hw_params.valid_tx_ant;
3080        }
3081
3082        link_cmd->agg_params.agg_dis_start_th = LINK_QUAL_AGG_DISABLE_START_DEF;
3083        link_cmd->agg_params.agg_time_limit =
3084            cpu_to_le16(LINK_QUAL_AGG_TIME_LIMIT_DEF);
3085
3086        link_cmd->sta_id = sta_id;
3087
3088        return link_cmd;
3089}
3090
3091/*
3092 * il4965_add_bssid_station - Add the special IBSS BSSID station
3093 *
3094 * Function sleeps.
3095 */
3096int
3097il4965_add_bssid_station(struct il_priv *il, const u8 *addr, u8 *sta_id_r)
3098{
3099        int ret;
3100        u8 sta_id;
3101        struct il_link_quality_cmd *link_cmd;
3102        unsigned long flags;
3103
3104        if (sta_id_r)
3105                *sta_id_r = IL_INVALID_STATION;
3106
3107        ret = il_add_station_common(il, addr, 0, NULL, &sta_id);
3108        if (ret) {
3109                IL_ERR("Unable to add station %pM\n", addr);
3110                return ret;
3111        }
3112
3113        if (sta_id_r)
3114                *sta_id_r = sta_id;
3115
3116        spin_lock_irqsave(&il->sta_lock, flags);
3117        il->stations[sta_id].used |= IL_STA_LOCAL;
3118        spin_unlock_irqrestore(&il->sta_lock, flags);
3119
3120        /* Set up default rate scaling table in device's station table */
3121        link_cmd = il4965_sta_alloc_lq(il, sta_id);
3122        if (!link_cmd) {
3123                IL_ERR("Unable to initialize rate scaling for station %pM.\n",
3124                       addr);
3125                return -ENOMEM;
3126        }
3127
3128        ret = il_send_lq_cmd(il, link_cmd, CMD_SYNC, true);
3129        if (ret)
3130                IL_ERR("Link quality command failed (%d)\n", ret);
3131
3132        spin_lock_irqsave(&il->sta_lock, flags);
3133        il->stations[sta_id].lq = link_cmd;
3134        spin_unlock_irqrestore(&il->sta_lock, flags);
3135
3136        return 0;
3137}
3138
3139static int
3140il4965_static_wepkey_cmd(struct il_priv *il, bool send_if_empty)
3141{
3142        int i;
3143        u8 buff[sizeof(struct il_wep_cmd) +
3144                sizeof(struct il_wep_key) * WEP_KEYS_MAX];
3145        struct il_wep_cmd *wep_cmd = (struct il_wep_cmd *)buff;
3146        size_t cmd_size = sizeof(struct il_wep_cmd);
3147        struct il_host_cmd cmd = {
3148                .id = C_WEPKEY,
3149                .data = wep_cmd,
3150                .flags = CMD_SYNC,
3151        };
3152        bool not_empty = false;
3153
3154        might_sleep();
3155
3156        memset(wep_cmd, 0,
3157               cmd_size + (sizeof(struct il_wep_key) * WEP_KEYS_MAX));
3158
3159        for (i = 0; i < WEP_KEYS_MAX; i++) {
3160                u8 key_size = il->_4965.wep_keys[i].key_size;
3161
3162                wep_cmd->key[i].key_idx = i;
3163                if (key_size) {
3164                        wep_cmd->key[i].key_offset = i;
3165                        not_empty = true;
3166                } else
3167                        wep_cmd->key[i].key_offset = WEP_INVALID_OFFSET;
3168
3169                wep_cmd->key[i].key_size = key_size;
3170                memcpy(&wep_cmd->key[i].key[3], il->_4965.wep_keys[i].key, key_size);
3171        }
3172
3173        wep_cmd->global_key_type = WEP_KEY_WEP_TYPE;
3174        wep_cmd->num_keys = WEP_KEYS_MAX;
3175
3176        cmd_size += sizeof(struct il_wep_key) * WEP_KEYS_MAX;
3177        cmd.len = cmd_size;
3178
3179        if (not_empty || send_if_empty)
3180                return il_send_cmd(il, &cmd);
3181        else
3182                return 0;
3183}
3184
3185int
3186il4965_restore_default_wep_keys(struct il_priv *il)
3187{
3188        lockdep_assert_held(&il->mutex);
3189
3190        return il4965_static_wepkey_cmd(il, false);
3191}
3192
3193int
3194il4965_remove_default_wep_key(struct il_priv *il,
3195                              struct ieee80211_key_conf *keyconf)
3196{
3197        int ret;
3198        int idx = keyconf->keyidx;
3199
3200        lockdep_assert_held(&il->mutex);
3201
3202        D_WEP("Removing default WEP key: idx=%d\n", idx);
3203
3204        memset(&il->_4965.wep_keys[idx], 0, sizeof(struct il_wep_key));
3205        if (il_is_rfkill(il)) {
3206                D_WEP("Not sending C_WEPKEY command due to RFKILL.\n");
3207                /* but keys in device are clear anyway so return success */
3208                return 0;
3209        }
3210        ret = il4965_static_wepkey_cmd(il, 1);
3211        D_WEP("Remove default WEP key: idx=%d ret=%d\n", idx, ret);
3212
3213        return ret;
3214}
3215
3216int
3217il4965_set_default_wep_key(struct il_priv *il,
3218                           struct ieee80211_key_conf *keyconf)
3219{
3220        int ret;
3221        int len = keyconf->keylen;
3222        int idx = keyconf->keyidx;
3223
3224        lockdep_assert_held(&il->mutex);
3225
3226        if (len != WEP_KEY_LEN_128 && len != WEP_KEY_LEN_64) {
3227                D_WEP("Bad WEP key length %d\n", keyconf->keylen);
3228                return -EINVAL;
3229        }
3230
3231        keyconf->flags &= ~IEEE80211_KEY_FLAG_GENERATE_IV;
3232        keyconf->hw_key_idx = HW_KEY_DEFAULT;
3233        il->stations[IL_AP_ID].keyinfo.cipher = keyconf->cipher;
3234
3235        il->_4965.wep_keys[idx].key_size = len;
3236        memcpy(&il->_4965.wep_keys[idx].key, &keyconf->key, len);
3237
3238        ret = il4965_static_wepkey_cmd(il, false);
3239
3240        D_WEP("Set default WEP key: len=%d idx=%d ret=%d\n", len, idx, ret);
3241        return ret;
3242}
3243
3244static int
3245il4965_set_wep_dynamic_key_info(struct il_priv *il,
3246                                struct ieee80211_key_conf *keyconf, u8 sta_id)
3247{
3248        unsigned long flags;
3249        __le16 key_flags = 0;
3250        struct il_addsta_cmd sta_cmd;
3251
3252        lockdep_assert_held(&il->mutex);
3253
3254        keyconf->flags &= ~IEEE80211_KEY_FLAG_GENERATE_IV;
3255
3256        key_flags |= (STA_KEY_FLG_WEP | STA_KEY_FLG_MAP_KEY_MSK);
3257        key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
3258        key_flags &= ~STA_KEY_FLG_INVALID;
3259
3260        if (keyconf->keylen == WEP_KEY_LEN_128)
3261                key_flags |= STA_KEY_FLG_KEY_SIZE_MSK;
3262
3263        if (sta_id == il->hw_params.bcast_id)
3264                key_flags |= STA_KEY_MULTICAST_MSK;
3265
3266        spin_lock_irqsave(&il->sta_lock, flags);
3267
3268        il->stations[sta_id].keyinfo.cipher = keyconf->cipher;
3269        il->stations[sta_id].keyinfo.keylen = keyconf->keylen;
3270        il->stations[sta_id].keyinfo.keyidx = keyconf->keyidx;
3271
3272        memcpy(il->stations[sta_id].keyinfo.key, keyconf->key, keyconf->keylen);
3273
3274        memcpy(&il->stations[sta_id].sta.key.key[3], keyconf->key,
3275               keyconf->keylen);
3276
3277        if ((il->stations[sta_id].sta.key.
3278             key_flags & STA_KEY_FLG_ENCRYPT_MSK) == STA_KEY_FLG_NO_ENC)
3279                il->stations[sta_id].sta.key.key_offset =
3280                    il_get_free_ucode_key_idx(il);
3281        /* else, we are overriding an existing key => no need to allocated room
3282         * in uCode. */
3283
3284        WARN(il->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET,
3285             "no space for a new key");
3286
3287        il->stations[sta_id].sta.key.key_flags = key_flags;
3288        il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
3289        il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3290
3291        memcpy(&sta_cmd, &il->stations[sta_id].sta,
3292               sizeof(struct il_addsta_cmd));
3293        spin_unlock_irqrestore(&il->sta_lock, flags);
3294
3295        return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
3296}
3297
3298static int
3299il4965_set_ccmp_dynamic_key_info(struct il_priv *il,
3300                                 struct ieee80211_key_conf *keyconf, u8 sta_id)
3301{
3302        unsigned long flags;
3303        __le16 key_flags = 0;
3304        struct il_addsta_cmd sta_cmd;
3305
3306        lockdep_assert_held(&il->mutex);
3307
3308        key_flags |= (STA_KEY_FLG_CCMP | STA_KEY_FLG_MAP_KEY_MSK);
3309        key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
3310        key_flags &= ~STA_KEY_FLG_INVALID;
3311
3312        if (sta_id == il->hw_params.bcast_id)
3313                key_flags |= STA_KEY_MULTICAST_MSK;
3314
3315        keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
3316
3317        spin_lock_irqsave(&il->sta_lock, flags);
3318        il->stations[sta_id].keyinfo.cipher = keyconf->cipher;
3319        il->stations[sta_id].keyinfo.keylen = keyconf->keylen;
3320
3321        memcpy(il->stations[sta_id].keyinfo.key, keyconf->key, keyconf->keylen);
3322
3323        memcpy(il->stations[sta_id].sta.key.key, keyconf->key, keyconf->keylen);
3324
3325        if ((il->stations[sta_id].sta.key.
3326             key_flags & STA_KEY_FLG_ENCRYPT_MSK) == STA_KEY_FLG_NO_ENC)
3327                il->stations[sta_id].sta.key.key_offset =
3328                    il_get_free_ucode_key_idx(il);
3329        /* else, we are overriding an existing key => no need to allocated room
3330         * in uCode. */
3331
3332        WARN(il->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET,
3333             "no space for a new key");
3334
3335        il->stations[sta_id].sta.key.key_flags = key_flags;
3336        il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
3337        il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3338
3339        memcpy(&sta_cmd, &il->stations[sta_id].sta,
3340               sizeof(struct il_addsta_cmd));
3341        spin_unlock_irqrestore(&il->sta_lock, flags);
3342
3343        return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
3344}
3345
3346static int
3347il4965_set_tkip_dynamic_key_info(struct il_priv *il,
3348                                 struct ieee80211_key_conf *keyconf, u8 sta_id)
3349{
3350        unsigned long flags;
3351        int ret = 0;
3352        __le16 key_flags = 0;
3353
3354        key_flags |= (STA_KEY_FLG_TKIP | STA_KEY_FLG_MAP_KEY_MSK);
3355        key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
3356        key_flags &= ~STA_KEY_FLG_INVALID;
3357
3358        if (sta_id == il->hw_params.bcast_id)
3359                key_flags |= STA_KEY_MULTICAST_MSK;
3360
3361        keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
3362        keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
3363
3364        spin_lock_irqsave(&il->sta_lock, flags);
3365
3366        il->stations[sta_id].keyinfo.cipher = keyconf->cipher;
3367        il->stations[sta_id].keyinfo.keylen = 16;
3368
3369        if ((il->stations[sta_id].sta.key.
3370             key_flags & STA_KEY_FLG_ENCRYPT_MSK) == STA_KEY_FLG_NO_ENC)
3371                il->stations[sta_id].sta.key.key_offset =
3372                    il_get_free_ucode_key_idx(il);
3373        /* else, we are overriding an existing key => no need to allocated room
3374         * in uCode. */
3375
3376        WARN(il->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET,
3377             "no space for a new key");
3378
3379        il->stations[sta_id].sta.key.key_flags = key_flags;
3380
3381        /* This copy is acutally not needed: we get the key with each TX */
3382        memcpy(il->stations[sta_id].keyinfo.key, keyconf->key, 16);
3383
3384        memcpy(il->stations[sta_id].sta.key.key, keyconf->key, 16);
3385
3386        spin_unlock_irqrestore(&il->sta_lock, flags);
3387
3388        return ret;
3389}
3390
3391void
3392il4965_update_tkip_key(struct il_priv *il, struct ieee80211_key_conf *keyconf,
3393                       struct ieee80211_sta *sta, u32 iv32, u16 *phase1key)
3394{
3395        u8 sta_id;
3396        unsigned long flags;
3397        int i;
3398
3399        if (il_scan_cancel(il)) {
3400                /* cancel scan failed, just live w/ bad key and rely
3401                   briefly on SW decryption */
3402                return;
3403        }
3404
3405        sta_id = il_sta_id_or_broadcast(il, sta);
3406        if (sta_id == IL_INVALID_STATION)
3407                return;
3408
3409        spin_lock_irqsave(&il->sta_lock, flags);
3410
3411        il->stations[sta_id].sta.key.tkip_rx_tsc_byte2 = (u8) iv32;
3412
3413        for (i = 0; i < 5; i++)
3414                il->stations[sta_id].sta.key.tkip_rx_ttak[i] =
3415                    cpu_to_le16(phase1key[i]);
3416
3417        il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
3418        il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3419
3420        il_send_add_sta(il, &il->stations[sta_id].sta, CMD_ASYNC);
3421
3422        spin_unlock_irqrestore(&il->sta_lock, flags);
3423}
3424
3425int
3426il4965_remove_dynamic_key(struct il_priv *il,
3427                          struct ieee80211_key_conf *keyconf, u8 sta_id)
3428{
3429        unsigned long flags;
3430        u16 key_flags;
3431        u8 keyidx;
3432        struct il_addsta_cmd sta_cmd;
3433
3434        lockdep_assert_held(&il->mutex);
3435
3436        il->_4965.key_mapping_keys--;
3437
3438        spin_lock_irqsave(&il->sta_lock, flags);
3439        key_flags = le16_to_cpu(il->stations[sta_id].sta.key.key_flags);
3440        keyidx = (key_flags >> STA_KEY_FLG_KEYID_POS) & 0x3;
3441
3442        D_WEP("Remove dynamic key: idx=%d sta=%d\n", keyconf->keyidx, sta_id);
3443
3444        if (keyconf->keyidx != keyidx) {
3445                /* We need to remove a key with idx different that the one
3446                 * in the uCode. This means that the key we need to remove has
3447                 * been replaced by another one with different idx.
3448                 * Don't do anything and return ok
3449                 */
3450                spin_unlock_irqrestore(&il->sta_lock, flags);
3451                return 0;
3452        }
3453
3454        if (il->stations[sta_id].sta.key.key_flags & STA_KEY_FLG_INVALID) {
3455                IL_WARN("Removing wrong key %d 0x%x\n", keyconf->keyidx,
3456                        key_flags);
3457                spin_unlock_irqrestore(&il->sta_lock, flags);
3458                return 0;
3459        }
3460
3461        if (!test_and_clear_bit
3462            (il->stations[sta_id].sta.key.key_offset, &il->ucode_key_table))
3463                IL_ERR("idx %d not used in uCode key table.\n",
3464                       il->stations[sta_id].sta.key.key_offset);
3465        memset(&il->stations[sta_id].keyinfo, 0, sizeof(struct il_hw_key));
3466        memset(&il->stations[sta_id].sta.key, 0, sizeof(struct il4965_keyinfo));
3467        il->stations[sta_id].sta.key.key_flags =
3468            STA_KEY_FLG_NO_ENC | STA_KEY_FLG_INVALID;
3469        il->stations[sta_id].sta.key.key_offset = keyconf->hw_key_idx;
3470        il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
3471        il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3472
3473        if (il_is_rfkill(il)) {
3474                D_WEP
3475                    ("Not sending C_ADD_STA command because RFKILL enabled.\n");
3476                spin_unlock_irqrestore(&il->sta_lock, flags);
3477                return 0;
3478        }
3479        memcpy(&sta_cmd, &il->stations[sta_id].sta,
3480               sizeof(struct il_addsta_cmd));
3481        spin_unlock_irqrestore(&il->sta_lock, flags);
3482
3483        return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
3484}
3485
3486int
3487il4965_set_dynamic_key(struct il_priv *il, struct ieee80211_key_conf *keyconf,
3488                       u8 sta_id)
3489{
3490        int ret;
3491
3492        lockdep_assert_held(&il->mutex);
3493
3494        il->_4965.key_mapping_keys++;
3495        keyconf->hw_key_idx = HW_KEY_DYNAMIC;
3496
3497        switch (keyconf->cipher) {
3498        case WLAN_CIPHER_SUITE_CCMP:
3499                ret =
3500                    il4965_set_ccmp_dynamic_key_info(il, keyconf, sta_id);
3501                break;
3502        case WLAN_CIPHER_SUITE_TKIP:
3503                ret =
3504                    il4965_set_tkip_dynamic_key_info(il, keyconf, sta_id);
3505                break;
3506        case WLAN_CIPHER_SUITE_WEP40:
3507        case WLAN_CIPHER_SUITE_WEP104:
3508                ret = il4965_set_wep_dynamic_key_info(il, keyconf, sta_id);
3509                break;
3510        default:
3511                IL_ERR("Unknown alg: %s cipher = %x\n", __func__,
3512                       keyconf->cipher);
3513                ret = -EINVAL;
3514        }
3515
3516        D_WEP("Set dynamic key: cipher=%x len=%d idx=%d sta=%d ret=%d\n",
3517              keyconf->cipher, keyconf->keylen, keyconf->keyidx, sta_id, ret);
3518
3519        return ret;
3520}
3521
3522/**
3523 * il4965_alloc_bcast_station - add broadcast station into driver's station table.
3524 *
3525 * This adds the broadcast station into the driver's station table
3526 * and marks it driver active, so that it will be restored to the
3527 * device at the next best time.
3528 */
3529int
3530il4965_alloc_bcast_station(struct il_priv *il)
3531{
3532        struct il_link_quality_cmd *link_cmd;
3533        unsigned long flags;
3534        u8 sta_id;
3535
3536        spin_lock_irqsave(&il->sta_lock, flags);
3537        sta_id = il_prep_station(il, il_bcast_addr, false, NULL);
3538        if (sta_id == IL_INVALID_STATION) {
3539                IL_ERR("Unable to prepare broadcast station\n");
3540                spin_unlock_irqrestore(&il->sta_lock, flags);
3541
3542                return -EINVAL;
3543        }
3544
3545        il->stations[sta_id].used |= IL_STA_DRIVER_ACTIVE;
3546        il->stations[sta_id].used |= IL_STA_BCAST;
3547        spin_unlock_irqrestore(&il->sta_lock, flags);
3548
3549        link_cmd = il4965_sta_alloc_lq(il, sta_id);
3550        if (!link_cmd) {
3551                IL_ERR
3552                    ("Unable to initialize rate scaling for bcast station.\n");
3553                return -ENOMEM;
3554        }
3555
3556        spin_lock_irqsave(&il->sta_lock, flags);
3557        il->stations[sta_id].lq = link_cmd;
3558        spin_unlock_irqrestore(&il->sta_lock, flags);
3559
3560        return 0;
3561}
3562
3563/**
3564 * il4965_update_bcast_station - update broadcast station's LQ command
3565 *
3566 * Only used by iwl4965. Placed here to have all bcast station management
3567 * code together.
3568 */
3569static int
3570il4965_update_bcast_station(struct il_priv *il)
3571{
3572        unsigned long flags;
3573        struct il_link_quality_cmd *link_cmd;
3574        u8 sta_id = il->hw_params.bcast_id;
3575
3576        link_cmd = il4965_sta_alloc_lq(il, sta_id);
3577        if (!link_cmd) {
3578                IL_ERR("Unable to initialize rate scaling for bcast sta.\n");
3579                return -ENOMEM;
3580        }
3581
3582        spin_lock_irqsave(&il->sta_lock, flags);
3583        if (il->stations[sta_id].lq)
3584                kfree(il->stations[sta_id].lq);
3585        else
3586                D_INFO("Bcast sta rate scaling has not been initialized.\n");
3587        il->stations[sta_id].lq = link_cmd;
3588        spin_unlock_irqrestore(&il->sta_lock, flags);
3589
3590        return 0;
3591}
3592
3593int
3594il4965_update_bcast_stations(struct il_priv *il)
3595{
3596        return il4965_update_bcast_station(il);
3597}
3598
3599/**
3600 * il4965_sta_tx_modify_enable_tid - Enable Tx for this TID in station table
3601 */
3602int
3603il4965_sta_tx_modify_enable_tid(struct il_priv *il, int sta_id, int tid)
3604{
3605        unsigned long flags;
3606        struct il_addsta_cmd sta_cmd;
3607
3608        lockdep_assert_held(&il->mutex);
3609
3610        /* Remove "disable" flag, to enable Tx for this TID */
3611        spin_lock_irqsave(&il->sta_lock, flags);
3612        il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_TID_DISABLE_TX;
3613        il->stations[sta_id].sta.tid_disable_tx &= cpu_to_le16(~(1 << tid));
3614        il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3615        memcpy(&sta_cmd, &il->stations[sta_id].sta,
3616               sizeof(struct il_addsta_cmd));
3617        spin_unlock_irqrestore(&il->sta_lock, flags);
3618
3619        return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
3620}
3621
3622int
3623il4965_sta_rx_agg_start(struct il_priv *il, struct ieee80211_sta *sta, int tid,
3624                        u16 ssn)
3625{
3626        unsigned long flags;
3627        int sta_id;
3628        struct il_addsta_cmd sta_cmd;
3629
3630        lockdep_assert_held(&il->mutex);
3631
3632        sta_id = il_sta_id(sta);
3633        if (sta_id == IL_INVALID_STATION)
3634                return -ENXIO;
3635
3636        spin_lock_irqsave(&il->sta_lock, flags);
3637        il->stations[sta_id].sta.station_flags_msk = 0;
3638        il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_ADDBA_TID_MSK;
3639        il->stations[sta_id].sta.add_immediate_ba_tid = (u8) tid;
3640        il->stations[sta_id].sta.add_immediate_ba_ssn = cpu_to_le16(ssn);
3641        il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3642        memcpy(&sta_cmd, &il->stations[sta_id].sta,
3643               sizeof(struct il_addsta_cmd));
3644        spin_unlock_irqrestore(&il->sta_lock, flags);
3645
3646        return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
3647}
3648
3649int
3650il4965_sta_rx_agg_stop(struct il_priv *il, struct ieee80211_sta *sta, int tid)
3651{
3652        unsigned long flags;
3653        int sta_id;
3654        struct il_addsta_cmd sta_cmd;
3655
3656        lockdep_assert_held(&il->mutex);
3657
3658        sta_id = il_sta_id(sta);
3659        if (sta_id == IL_INVALID_STATION) {
3660                IL_ERR("Invalid station for AGG tid %d\n", tid);
3661                return -ENXIO;
3662        }
3663
3664        spin_lock_irqsave(&il->sta_lock, flags);
3665        il->stations[sta_id].sta.station_flags_msk = 0;
3666        il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_DELBA_TID_MSK;
3667        il->stations[sta_id].sta.remove_immediate_ba_tid = (u8) tid;
3668        il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3669        memcpy(&sta_cmd, &il->stations[sta_id].sta,
3670               sizeof(struct il_addsta_cmd));
3671        spin_unlock_irqrestore(&il->sta_lock, flags);
3672
3673        return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
3674}
3675
3676void
3677il4965_sta_modify_sleep_tx_count(struct il_priv *il, int sta_id, int cnt)
3678{
3679        unsigned long flags;
3680
3681        spin_lock_irqsave(&il->sta_lock, flags);
3682        il->stations[sta_id].sta.station_flags |= STA_FLG_PWR_SAVE_MSK;
3683        il->stations[sta_id].sta.station_flags_msk = STA_FLG_PWR_SAVE_MSK;
3684        il->stations[sta_id].sta.sta.modify_mask =
3685            STA_MODIFY_SLEEP_TX_COUNT_MSK;
3686        il->stations[sta_id].sta.sleep_tx_count = cpu_to_le16(cnt);
3687        il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3688        il_send_add_sta(il, &il->stations[sta_id].sta, CMD_ASYNC);
3689        spin_unlock_irqrestore(&il->sta_lock, flags);
3690
3691}
3692
3693void
3694il4965_update_chain_flags(struct il_priv *il)
3695{
3696        if (il->ops->set_rxon_chain) {
3697                il->ops->set_rxon_chain(il);
3698                if (il->active.rx_chain != il->staging.rx_chain)
3699                        il_commit_rxon(il);
3700        }
3701}
3702
3703static void
3704il4965_clear_free_frames(struct il_priv *il)
3705{
3706        struct list_head *element;
3707
3708        D_INFO("%d frames on pre-allocated heap on clear.\n", il->frames_count);
3709
3710        while (!list_empty(&il->free_frames)) {
3711                element = il->free_frames.next;
3712                list_del(element);
3713                kfree(list_entry(element, struct il_frame, list));
3714                il->frames_count--;
3715        }
3716
3717        if (il->frames_count) {
3718                IL_WARN("%d frames still in use.  Did we lose one?\n",
3719                        il->frames_count);
3720                il->frames_count = 0;
3721        }
3722}
3723
3724static struct il_frame *
3725il4965_get_free_frame(struct il_priv *il)
3726{
3727        struct il_frame *frame;
3728        struct list_head *element;
3729        if (list_empty(&il->free_frames)) {
3730                frame = kzalloc(sizeof(*frame), GFP_KERNEL);
3731                if (!frame) {
3732                        IL_ERR("Could not allocate frame!\n");
3733                        return NULL;
3734                }
3735
3736                il->frames_count++;
3737                return frame;
3738        }
3739
3740        element = il->free_frames.next;
3741        list_del(element);
3742        return list_entry(element, struct il_frame, list);
3743}
3744
3745static void
3746il4965_free_frame(struct il_priv *il, struct il_frame *frame)
3747{
3748        memset(frame, 0, sizeof(*frame));
3749        list_add(&frame->list, &il->free_frames);
3750}
3751
3752static u32
3753il4965_fill_beacon_frame(struct il_priv *il, struct ieee80211_hdr *hdr,
3754                         int left)
3755{
3756        lockdep_assert_held(&il->mutex);
3757
3758        if (!il->beacon_skb)
3759                return 0;
3760
3761        if (il->beacon_skb->len > left)
3762                return 0;
3763
3764        memcpy(hdr, il->beacon_skb->data, il->beacon_skb->len);
3765
3766        return il->beacon_skb->len;
3767}
3768
3769/* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
3770static void
3771il4965_set_beacon_tim(struct il_priv *il,
3772                      struct il_tx_beacon_cmd *tx_beacon_cmd, u8 * beacon,
3773                      u32 frame_size)
3774{
3775        u16 tim_idx;
3776        struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
3777
3778        /*
3779         * The idx is relative to frame start but we start looking at the
3780         * variable-length part of the beacon.
3781         */
3782        tim_idx = mgmt->u.beacon.variable - beacon;
3783
3784        /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
3785        while ((tim_idx < (frame_size - 2)) &&
3786               (beacon[tim_idx] != WLAN_EID_TIM))
3787                tim_idx += beacon[tim_idx + 1] + 2;
3788
3789        /* If TIM field was found, set variables */
3790        if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
3791                tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
3792                tx_beacon_cmd->tim_size = beacon[tim_idx + 1];
3793        } else
3794                IL_WARN("Unable to find TIM Element in beacon\n");
3795}
3796
3797static unsigned int
3798il4965_hw_get_beacon_cmd(struct il_priv *il, struct il_frame *frame)
3799{
3800        struct il_tx_beacon_cmd *tx_beacon_cmd;
3801        u32 frame_size;
3802        u32 rate_flags;
3803        u32 rate;
3804        /*
3805         * We have to set up the TX command, the TX Beacon command, and the
3806         * beacon contents.
3807         */
3808
3809        lockdep_assert_held(&il->mutex);
3810
3811        if (!il->beacon_enabled) {
3812                IL_ERR("Trying to build beacon without beaconing enabled\n");
3813                return 0;
3814        }
3815
3816        /* Initialize memory */
3817        tx_beacon_cmd = &frame->u.beacon;
3818        memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
3819
3820        /* Set up TX beacon contents */
3821        frame_size =
3822            il4965_fill_beacon_frame(il, tx_beacon_cmd->frame,
3823                                     sizeof(frame->u) - sizeof(*tx_beacon_cmd));
3824        if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
3825                return 0;
3826        if (!frame_size)
3827                return 0;
3828
3829        /* Set up TX command fields */
3830        tx_beacon_cmd->tx.len = cpu_to_le16((u16) frame_size);
3831        tx_beacon_cmd->tx.sta_id = il->hw_params.bcast_id;
3832        tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
3833        tx_beacon_cmd->tx.tx_flags =
3834            TX_CMD_FLG_SEQ_CTL_MSK | TX_CMD_FLG_TSF_MSK |
3835            TX_CMD_FLG_STA_RATE_MSK;
3836
3837        /* Set up TX beacon command fields */
3838        il4965_set_beacon_tim(il, tx_beacon_cmd, (u8 *) tx_beacon_cmd->frame,
3839                              frame_size);
3840
3841        /* Set up packet rate and flags */
3842        rate = il_get_lowest_plcp(il);
3843        il4965_toggle_tx_ant(il, &il->mgmt_tx_ant, il->hw_params.valid_tx_ant);
3844        rate_flags = BIT(il->mgmt_tx_ant) << RATE_MCS_ANT_POS;
3845        if ((rate >= IL_FIRST_CCK_RATE) && (rate <= IL_LAST_CCK_RATE))
3846                rate_flags |= RATE_MCS_CCK_MSK;
3847        tx_beacon_cmd->tx.rate_n_flags = cpu_to_le32(rate | rate_flags);
3848
3849        return sizeof(*tx_beacon_cmd) + frame_size;
3850}
3851
3852int
3853il4965_send_beacon_cmd(struct il_priv *il)
3854{
3855        struct il_frame *frame;
3856        unsigned int frame_size;
3857        int rc;
3858
3859        frame = il4965_get_free_frame(il);
3860        if (!frame) {
3861                IL_ERR("Could not obtain free frame buffer for beacon "
3862                       "command.\n");
3863                return -ENOMEM;
3864        }
3865
3866        frame_size = il4965_hw_get_beacon_cmd(il, frame);
3867        if (!frame_size) {
3868                IL_ERR("Error configuring the beacon command\n");
3869                il4965_free_frame(il, frame);
3870                return -EINVAL;
3871        }
3872
3873        rc = il_send_cmd_pdu(il, C_TX_BEACON, frame_size, &frame->u.cmd[0]);
3874
3875        il4965_free_frame(il, frame);
3876
3877        return rc;
3878}
3879
3880static inline dma_addr_t
3881il4965_tfd_tb_get_addr(struct il_tfd *tfd, u8 idx)
3882{
3883        struct il_tfd_tb *tb = &tfd->tbs[idx];
3884
3885        dma_addr_t addr = get_unaligned_le32(&tb->lo);
3886        if (sizeof(dma_addr_t) > sizeof(u32))
3887                addr |=
3888                    ((dma_addr_t) (le16_to_cpu(tb->hi_n_len) & 0xF) << 16) <<
3889                    16;
3890
3891        return addr;
3892}
3893
3894static inline u16
3895il4965_tfd_tb_get_len(struct il_tfd *tfd, u8 idx)
3896{
3897        struct il_tfd_tb *tb = &tfd->tbs[idx];
3898
3899        return le16_to_cpu(tb->hi_n_len) >> 4;
3900}
3901
3902static inline void
3903il4965_tfd_set_tb(struct il_tfd *tfd, u8 idx, dma_addr_t addr, u16 len)
3904{
3905        struct il_tfd_tb *tb = &tfd->tbs[idx];
3906        u16 hi_n_len = len << 4;
3907
3908        put_unaligned_le32(addr, &tb->lo);
3909        if (sizeof(dma_addr_t) > sizeof(u32))
3910                hi_n_len |= ((addr >> 16) >> 16) & 0xF;
3911
3912        tb->hi_n_len = cpu_to_le16(hi_n_len);
3913
3914        tfd->num_tbs = idx + 1;
3915}
3916
3917static inline u8
3918il4965_tfd_get_num_tbs(struct il_tfd *tfd)
3919{
3920        return tfd->num_tbs & 0x1f;
3921}
3922
3923/**
3924 * il4965_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
3925 * @il - driver ilate data
3926 * @txq - tx queue
3927 *
3928 * Does NOT advance any TFD circular buffer read/write idxes
3929 * Does NOT free the TFD itself (which is within circular buffer)
3930 */
3931void
3932il4965_hw_txq_free_tfd(struct il_priv *il, struct il_tx_queue *txq)
3933{
3934        struct il_tfd *tfd_tmp = (struct il_tfd *)txq->tfds;
3935        struct il_tfd *tfd;
3936        struct pci_dev *dev = il->pci_dev;
3937        int idx = txq->q.read_ptr;
3938        int i;
3939        int num_tbs;
3940
3941        tfd = &tfd_tmp[idx];
3942
3943        /* Sanity check on number of chunks */
3944        num_tbs = il4965_tfd_get_num_tbs(tfd);
3945
3946        if (num_tbs >= IL_NUM_OF_TBS) {
3947                IL_ERR("Too many chunks: %i\n", num_tbs);
3948                /* @todo issue fatal error, it is quite serious situation */
3949                return;
3950        }
3951
3952        /* Unmap tx_cmd */
3953        if (num_tbs)
3954                pci_unmap_single(dev, dma_unmap_addr(&txq->meta[idx], mapping),
3955                                 dma_unmap_len(&txq->meta[idx], len),
3956                                 PCI_DMA_BIDIRECTIONAL);
3957
3958        /* Unmap chunks, if any. */
3959        for (i = 1; i < num_tbs; i++)
3960                pci_unmap_single(dev, il4965_tfd_tb_get_addr(tfd, i),
3961                                 il4965_tfd_tb_get_len(tfd, i),
3962                                 PCI_DMA_TODEVICE);
3963
3964        /* free SKB */
3965        if (txq->skbs) {
3966                struct sk_buff *skb = txq->skbs[txq->q.read_ptr];
3967
3968                /* can be called from irqs-disabled context */
3969                if (skb) {
3970                        dev_kfree_skb_any(skb);
3971                        txq->skbs[txq->q.read_ptr] = NULL;
3972                }
3973        }
3974}
3975
3976int
3977il4965_hw_txq_attach_buf_to_tfd(struct il_priv *il, struct il_tx_queue *txq,
3978                                dma_addr_t addr, u16 len, u8 reset, u8 pad)
3979{
3980        struct il_queue *q;
3981        struct il_tfd *tfd, *tfd_tmp;
3982        u32 num_tbs;
3983
3984        q = &txq->q;
3985        tfd_tmp = (struct il_tfd *)txq->tfds;
3986        tfd = &tfd_tmp[q->write_ptr];
3987
3988        if (reset)
3989                memset(tfd, 0, sizeof(*tfd));
3990
3991        num_tbs = il4965_tfd_get_num_tbs(tfd);
3992
3993        /* Each TFD can point to a maximum 20 Tx buffers */
3994        if (num_tbs >= IL_NUM_OF_TBS) {
3995                IL_ERR("Error can not send more than %d chunks\n",
3996                       IL_NUM_OF_TBS);
3997                return -EINVAL;
3998        }
3999
4000        BUG_ON(addr & ~DMA_BIT_MASK(36));
4001        if (unlikely(addr & ~IL_TX_DMA_MASK))
4002                IL_ERR("Unaligned address = %llx\n", (unsigned long long)addr);
4003
4004        il4965_tfd_set_tb(tfd, num_tbs, addr, len);
4005
4006        return 0;
4007}
4008
4009/*
4010 * Tell nic where to find circular buffer of Tx Frame Descriptors for
4011 * given Tx queue, and enable the DMA channel used for that queue.
4012 *
4013 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
4014 * channels supported in hardware.
4015 */
4016int
4017il4965_hw_tx_queue_init(struct il_priv *il, struct il_tx_queue *txq)
4018{
4019        int txq_id = txq->q.id;
4020
4021        /* Circular buffer (TFD queue in DRAM) physical base address */
4022        il_wr(il, FH49_MEM_CBBC_QUEUE(txq_id), txq->q.dma_addr >> 8);
4023
4024        return 0;
4025}
4026
4027/******************************************************************************
4028 *
4029 * Generic RX handler implementations
4030 *
4031 ******************************************************************************/
4032static void
4033il4965_hdl_alive(struct il_priv *il, struct il_rx_buf *rxb)
4034{
4035        struct il_rx_pkt *pkt = rxb_addr(rxb);
4036        struct il_alive_resp *palive;
4037        struct delayed_work *pwork;
4038
4039        palive = &pkt->u.alive_frame;
4040
4041        D_INFO("Alive ucode status 0x%08X revision " "0x%01X 0x%01X\n",
4042               palive->is_valid, palive->ver_type, palive->ver_subtype);
4043
4044        if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
4045                D_INFO("Initialization Alive received.\n");
4046                memcpy(&il->card_alive_init, &pkt->u.alive_frame,
4047                       sizeof(struct il_init_alive_resp));
4048                pwork = &il->init_alive_start;
4049        } else {
4050                D_INFO("Runtime Alive received.\n");
4051                memcpy(&il->card_alive, &pkt->u.alive_frame,
4052                       sizeof(struct il_alive_resp));
4053                pwork = &il->alive_start;
4054        }
4055
4056        /* We delay the ALIVE response by 5ms to
4057         * give the HW RF Kill time to activate... */
4058        if (palive->is_valid == UCODE_VALID_OK)
4059                queue_delayed_work(il->workqueue, pwork, msecs_to_jiffies(5));
4060        else
4061                IL_WARN("uCode did not respond OK.\n");
4062}
4063
4064/**
4065 * il4965_bg_stats_periodic - Timer callback to queue stats
4066 *
4067 * This callback is provided in order to send a stats request.
4068 *
4069 * This timer function is continually reset to execute within
4070 * 60 seconds since the last N_STATS was received.  We need to
4071 * ensure we receive the stats in order to update the temperature
4072 * used for calibrating the TXPOWER.
4073 */
4074static void
4075il4965_bg_stats_periodic(unsigned long data)
4076{
4077        struct il_priv *il = (struct il_priv *)data;
4078
4079        if (test_bit(S_EXIT_PENDING, &il->status))
4080                return;
4081
4082        /* dont send host command if rf-kill is on */
4083        if (!il_is_ready_rf(il))
4084                return;
4085
4086        il_send_stats_request(il, CMD_ASYNC, false);
4087}
4088
4089static void
4090il4965_hdl_beacon(struct il_priv *il, struct il_rx_buf *rxb)
4091{
4092        struct il_rx_pkt *pkt = rxb_addr(rxb);
4093        struct il4965_beacon_notif *beacon =
4094            (struct il4965_beacon_notif *)pkt->u.raw;
4095#ifdef CONFIG_IWLEGACY_DEBUG
4096        u8 rate = il4965_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
4097
4098        D_RX("beacon status %x retries %d iss %d tsf:0x%.8x%.8x rate %d\n",
4099             le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
4100             beacon->beacon_notify_hdr.failure_frame,
4101             le32_to_cpu(beacon->ibss_mgr_status),
4102             le32_to_cpu(beacon->high_tsf), le32_to_cpu(beacon->low_tsf), rate);
4103#endif
4104        il->ibss_manager = le32_to_cpu(beacon->ibss_mgr_status);
4105}
4106
4107static void
4108il4965_perform_ct_kill_task(struct il_priv *il)
4109{
4110        unsigned long flags;
4111
4112        D_POWER("Stop all queues\n");
4113
4114        if (il->mac80211_registered)
4115                ieee80211_stop_queues(il->hw);
4116
4117        _il_wr(il, CSR_UCODE_DRV_GP1_SET,
4118               CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
4119        _il_rd(il, CSR_UCODE_DRV_GP1);
4120
4121        spin_lock_irqsave(&il->reg_lock, flags);
4122        if (likely(_il_grab_nic_access(il)))
4123                _il_release_nic_access(il);
4124        spin_unlock_irqrestore(&il->reg_lock, flags);
4125}
4126
4127/* Handle notification from uCode that card's power state is changing
4128 * due to software, hardware, or critical temperature RFKILL */
4129static void
4130il4965_hdl_card_state(struct il_priv *il, struct il_rx_buf *rxb)
4131{
4132        struct il_rx_pkt *pkt = rxb_addr(rxb);
4133        u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
4134        unsigned long status = il->status;
4135
4136        D_RF_KILL("Card state received: HW:%s SW:%s CT:%s\n",
4137                  (flags & HW_CARD_DISABLED) ? "Kill" : "On",
4138                  (flags & SW_CARD_DISABLED) ? "Kill" : "On",
4139                  (flags & CT_CARD_DISABLED) ? "Reached" : "Not reached");
4140
4141        if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED | CT_CARD_DISABLED)) {
4142
4143                _il_wr(il, CSR_UCODE_DRV_GP1_SET,
4144                       CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
4145
4146                il_wr(il, HBUS_TARG_MBX_C, HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
4147
4148                if (!(flags & RXON_CARD_DISABLED)) {
4149                        _il_wr(il, CSR_UCODE_DRV_GP1_CLR,
4150                               CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
4151                        il_wr(il, HBUS_TARG_MBX_C,
4152                              HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
4153                }
4154        }
4155
4156        if (flags & CT_CARD_DISABLED)
4157                il4965_perform_ct_kill_task(il);
4158
4159        if (flags & HW_CARD_DISABLED)
4160                set_bit(S_RFKILL, &il->status);
4161        else
4162                clear_bit(S_RFKILL, &il->status);
4163
4164        if (!(flags & RXON_CARD_DISABLED))
4165                il_scan_cancel(il);
4166
4167        if ((test_bit(S_RFKILL, &status) !=
4168             test_bit(S_RFKILL, &il->status)))
4169                wiphy_rfkill_set_hw_state(il->hw->wiphy,
4170                                          test_bit(S_RFKILL, &il->status));
4171        else
4172                wake_up(&il->wait_command_queue);
4173}
4174
4175/**
4176 * il4965_setup_handlers - Initialize Rx handler callbacks
4177 *
4178 * Setup the RX handlers for each of the reply types sent from the uCode
4179 * to the host.
4180 *
4181 * This function chains into the hardware specific files for them to setup
4182 * any hardware specific handlers as well.
4183 */
4184static void
4185il4965_setup_handlers(struct il_priv *il)
4186{
4187        il->handlers[N_ALIVE] = il4965_hdl_alive;
4188        il->handlers[N_ERROR] = il_hdl_error;
4189        il->handlers[N_CHANNEL_SWITCH] = il_hdl_csa;
4190        il->handlers[N_SPECTRUM_MEASUREMENT] = il_hdl_spectrum_measurement;
4191        il->handlers[N_PM_SLEEP] = il_hdl_pm_sleep;
4192        il->handlers[N_PM_DEBUG_STATS] = il_hdl_pm_debug_stats;
4193        il->handlers[N_BEACON] = il4965_hdl_beacon;
4194
4195        /*
4196         * The same handler is used for both the REPLY to a discrete
4197         * stats request from the host as well as for the periodic
4198         * stats notifications (after received beacons) from the uCode.
4199         */
4200        il->handlers[C_STATS] = il4965_hdl_c_stats;
4201        il->handlers[N_STATS] = il4965_hdl_stats;
4202
4203        il_setup_rx_scan_handlers(il);
4204
4205        /* status change handler */
4206        il->handlers[N_CARD_STATE] = il4965_hdl_card_state;
4207
4208        il->handlers[N_MISSED_BEACONS] = il4965_hdl_missed_beacon;
4209        /* Rx handlers */
4210        il->handlers[N_RX_PHY] = il4965_hdl_rx_phy;
4211        il->handlers[N_RX_MPDU] = il4965_hdl_rx;
4212        il->handlers[N_RX] = il4965_hdl_rx;
4213        /* block ack */
4214        il->handlers[N_COMPRESSED_BA] = il4965_hdl_compressed_ba;
4215        /* Tx response */
4216        il->handlers[C_TX] = il4965_hdl_tx;
4217}
4218
4219/**
4220 * il4965_rx_handle - Main entry function for receiving responses from uCode
4221 *
4222 * Uses the il->handlers callback function array to invoke
4223 * the appropriate handlers, including command responses,
4224 * frame-received notifications, and other notifications.
4225 */
4226void
4227il4965_rx_handle(struct il_priv *il)
4228{
4229        struct il_rx_buf *rxb;
4230        struct il_rx_pkt *pkt;
4231        struct il_rx_queue *rxq = &il->rxq;
4232        u32 r, i;
4233        int reclaim;
4234        unsigned long flags;
4235        u8 fill_rx = 0;
4236        u32 count = 8;
4237        int total_empty;
4238
4239        /* uCode's read idx (stored in shared DRAM) indicates the last Rx
4240         * buffer that the driver may process (last buffer filled by ucode). */
4241        r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
4242        i = rxq->read;
4243
4244        /* Rx interrupt, but nothing sent from uCode */
4245        if (i == r)
4246                D_RX("r = %d, i = %d\n", r, i);
4247
4248        /* calculate total frames need to be restock after handling RX */
4249        total_empty = r - rxq->write_actual;
4250        if (total_empty < 0)
4251                total_empty += RX_QUEUE_SIZE;
4252
4253        if (total_empty > (RX_QUEUE_SIZE / 2))
4254                fill_rx = 1;
4255
4256        while (i != r) {
4257                int len;
4258
4259                rxb = rxq->queue[i];
4260
4261                /* If an RXB doesn't have a Rx queue slot associated with it,
4262                 * then a bug has been introduced in the queue refilling
4263                 * routines -- catch it here */
4264                BUG_ON(rxb == NULL);
4265
4266                rxq->queue[i] = NULL;
4267
4268                pci_unmap_page(il->pci_dev, rxb->page_dma,
4269                               PAGE_SIZE << il->hw_params.rx_page_order,
4270                               PCI_DMA_FROMDEVICE);
4271                pkt = rxb_addr(rxb);
4272
4273                len = le32_to_cpu(pkt->len_n_flags) & IL_RX_FRAME_SIZE_MSK;
4274                len += sizeof(u32);     /* account for status word */
4275
4276                reclaim = il_need_reclaim(il, pkt);
4277
4278                /* Based on type of command response or notification,
4279                 *   handle those that need handling via function in
4280                 *   handlers table.  See il4965_setup_handlers() */
4281                if (il->handlers[pkt->hdr.cmd]) {
4282                        D_RX("r = %d, i = %d, %s, 0x%02x\n", r, i,
4283                             il_get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
4284                        il->isr_stats.handlers[pkt->hdr.cmd]++;
4285                        il->handlers[pkt->hdr.cmd] (il, rxb);
4286                } else {
4287                        /* No handling needed */
4288                        D_RX("r %d i %d No handler needed for %s, 0x%02x\n", r,
4289                             i, il_get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
4290                }
4291
4292                /*
4293                 * XXX: After here, we should always check rxb->page
4294                 * against NULL before touching it or its virtual
4295                 * memory (pkt). Because some handler might have
4296                 * already taken or freed the pages.
4297                 */
4298
4299                if (reclaim) {
4300                        /* Invoke any callbacks, transfer the buffer to caller,
4301                         * and fire off the (possibly) blocking il_send_cmd()
4302                         * as we reclaim the driver command queue */
4303                        if (rxb->page)
4304                                il_tx_cmd_complete(il, rxb);
4305                        else
4306                                IL_WARN("Claim null rxb?\n");
4307                }
4308
4309                /* Reuse the page if possible. For notification packets and
4310                 * SKBs that fail to Rx correctly, add them back into the
4311                 * rx_free list for reuse later. */
4312                spin_lock_irqsave(&rxq->lock, flags);
4313                if (rxb->page != NULL) {
4314                        rxb->page_dma =
4315                            pci_map_page(il->pci_dev, rxb->page, 0,
4316                                         PAGE_SIZE << il->hw_params.
4317                                         rx_page_order, PCI_DMA_FROMDEVICE);
4318
4319                        if (unlikely(pci_dma_mapping_error(il->pci_dev,
4320                                                           rxb->page_dma))) {
4321                                __il_free_pages(il, rxb->page);
4322                                rxb->page = NULL;
4323                                list_add_tail(&rxb->list, &rxq->rx_used);
4324                        } else {
4325                                list_add_tail(&rxb->list, &rxq->rx_free);
4326                                rxq->free_count++;
4327                        }
4328                } else
4329                        list_add_tail(&rxb->list, &rxq->rx_used);
4330
4331                spin_unlock_irqrestore(&rxq->lock, flags);
4332
4333                i = (i + 1) & RX_QUEUE_MASK;
4334                /* If there are a lot of unused frames,
4335                 * restock the Rx queue so ucode wont assert. */
4336                if (fill_rx) {
4337                        count++;
4338                        if (count >= 8) {
4339                                rxq->read = i;
4340                                il4965_rx_replenish_now(il);
4341                                count = 0;
4342                        }
4343                }
4344        }
4345
4346        /* Backtrack one entry */
4347        rxq->read = i;
4348        if (fill_rx)
4349                il4965_rx_replenish_now(il);
4350        else
4351                il4965_rx_queue_restock(il);
4352}
4353
4354/* call this function to flush any scheduled tasklet */
4355static inline void
4356il4965_synchronize_irq(struct il_priv *il)
4357{
4358        /* wait to make sure we flush pending tasklet */
4359        synchronize_irq(il->pci_dev->irq);
4360        tasklet_kill(&il->irq_tasklet);
4361}
4362
4363static void
4364il4965_irq_tasklet(struct il_priv *il)
4365{
4366        u32 inta, handled = 0;
4367        u32 inta_fh;
4368        unsigned long flags;
4369        u32 i;
4370#ifdef CONFIG_IWLEGACY_DEBUG
4371        u32 inta_mask;
4372#endif
4373
4374        spin_lock_irqsave(&il->lock, flags);
4375
4376        /* Ack/clear/reset pending uCode interrupts.
4377         * Note:  Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
4378         *  and will clear only when CSR_FH_INT_STATUS gets cleared. */
4379        inta = _il_rd(il, CSR_INT);
4380        _il_wr(il, CSR_INT, inta);
4381
4382        /* Ack/clear/reset pending flow-handler (DMA) interrupts.
4383         * Any new interrupts that happen after this, either while we're
4384         * in this tasklet, or later, will show up in next ISR/tasklet. */
4385        inta_fh = _il_rd(il, CSR_FH_INT_STATUS);
4386        _il_wr(il, CSR_FH_INT_STATUS, inta_fh);
4387
4388#ifdef CONFIG_IWLEGACY_DEBUG
4389        if (il_get_debug_level(il) & IL_DL_ISR) {
4390                /* just for debug */
4391                inta_mask = _il_rd(il, CSR_INT_MASK);
4392                D_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", inta,
4393                      inta_mask, inta_fh);
4394        }
4395#endif
4396
4397        spin_unlock_irqrestore(&il->lock, flags);
4398
4399        /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
4400         * atomic, make sure that inta covers all the interrupts that
4401         * we've discovered, even if FH interrupt came in just after
4402         * reading CSR_INT. */
4403        if (inta_fh & CSR49_FH_INT_RX_MASK)
4404                inta |= CSR_INT_BIT_FH_RX;
4405        if (inta_fh & CSR49_FH_INT_TX_MASK)
4406                inta |= CSR_INT_BIT_FH_TX;
4407
4408        /* Now service all interrupt bits discovered above. */
4409        if (inta & CSR_INT_BIT_HW_ERR) {
4410                IL_ERR("Hardware error detected.  Restarting.\n");
4411
4412                /* Tell the device to stop sending interrupts */
4413                il_disable_interrupts(il);
4414
4415                il->isr_stats.hw++;
4416                il_irq_handle_error(il);
4417
4418                handled |= CSR_INT_BIT_HW_ERR;
4419
4420                return;
4421        }
4422#ifdef CONFIG_IWLEGACY_DEBUG
4423        if (il_get_debug_level(il) & (IL_DL_ISR)) {
4424                /* NIC fires this, but we don't use it, redundant with WAKEUP */
4425                if (inta & CSR_INT_BIT_SCD) {
4426                        D_ISR("Scheduler finished to transmit "
4427                              "the frame/frames.\n");
4428                        il->isr_stats.sch++;
4429                }
4430
4431                /* Alive notification via Rx interrupt will do the real work */
4432                if (inta & CSR_INT_BIT_ALIVE) {
4433                        D_ISR("Alive interrupt\n");
4434                        il->isr_stats.alive++;
4435                }
4436        }
4437#endif
4438        /* Safely ignore these bits for debug checks below */
4439        inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
4440
4441        /* HW RF KILL switch toggled */
4442        if (inta & CSR_INT_BIT_RF_KILL) {
4443                int hw_rf_kill = 0;
4444
4445                if (!(_il_rd(il, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
4446                        hw_rf_kill = 1;
4447
4448                IL_WARN("RF_KILL bit toggled to %s.\n",
4449                        hw_rf_kill ? "disable radio" : "enable radio");
4450
4451                il->isr_stats.rfkill++;
4452
4453                /* driver only loads ucode once setting the interface up.
4454                 * the driver allows loading the ucode even if the radio
4455                 * is killed. Hence update the killswitch state here. The
4456                 * rfkill handler will care about restarting if needed.
4457                 */
4458                if (hw_rf_kill) {
4459                        set_bit(S_RFKILL, &il->status);
4460                } else {
4461                        clear_bit(S_RFKILL, &il->status);
4462                        il_force_reset(il, true);
4463                }
4464                wiphy_rfkill_set_hw_state(il->hw->wiphy, hw_rf_kill);
4465
4466                handled |= CSR_INT_BIT_RF_KILL;
4467        }
4468
4469        /* Chip got too hot and stopped itself */
4470        if (inta & CSR_INT_BIT_CT_KILL) {
4471                IL_ERR("Microcode CT kill error detected.\n");
4472                il->isr_stats.ctkill++;
4473                handled |= CSR_INT_BIT_CT_KILL;
4474        }
4475
4476        /* Error detected by uCode */
4477        if (inta & CSR_INT_BIT_SW_ERR) {
4478                IL_ERR("Microcode SW error detected. " " Restarting 0x%X.\n",
4479                       inta);
4480                il->isr_stats.sw++;
4481                il_irq_handle_error(il);
4482                handled |= CSR_INT_BIT_SW_ERR;
4483        }
4484
4485        /*
4486         * uCode wakes up after power-down sleep.
4487         * Tell device about any new tx or host commands enqueued,
4488         * and about any Rx buffers made available while asleep.
4489         */
4490        if (inta & CSR_INT_BIT_WAKEUP) {
4491                D_ISR("Wakeup interrupt\n");
4492                il_rx_queue_update_write_ptr(il, &il->rxq);
4493                for (i = 0; i < il->hw_params.max_txq_num; i++)
4494                        il_txq_update_write_ptr(il, &il->txq[i]);
4495                il->isr_stats.wakeup++;
4496                handled |= CSR_INT_BIT_WAKEUP;
4497        }
4498
4499        /* All uCode command responses, including Tx command responses,
4500         * Rx "responses" (frame-received notification), and other
4501         * notifications from uCode come through here*/
4502        if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
4503                il4965_rx_handle(il);
4504                il->isr_stats.rx++;
4505                handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
4506        }
4507
4508        /* This "Tx" DMA channel is used only for loading uCode */
4509        if (inta & CSR_INT_BIT_FH_TX) {
4510                D_ISR("uCode load interrupt\n");
4511                il->isr_stats.tx++;
4512                handled |= CSR_INT_BIT_FH_TX;
4513                /* Wake up uCode load routine, now that load is complete */
4514                il->ucode_write_complete = 1;
4515                wake_up(&il->wait_command_queue);
4516        }
4517
4518        if (inta & ~handled) {
4519                IL_ERR("Unhandled INTA bits 0x%08x\n", inta & ~handled);
4520                il->isr_stats.unhandled++;
4521        }
4522
4523        if (inta & ~(il->inta_mask)) {
4524                IL_WARN("Disabled INTA bits 0x%08x were pending\n",
4525                        inta & ~il->inta_mask);
4526                IL_WARN("   with FH49_INT = 0x%08x\n", inta_fh);
4527        }
4528
4529        /* Re-enable all interrupts */
4530        /* only Re-enable if disabled by irq */
4531        if (test_bit(S_INT_ENABLED, &il->status))
4532                il_enable_interrupts(il);
4533        /* Re-enable RF_KILL if it occurred */
4534        else if (handled & CSR_INT_BIT_RF_KILL)
4535                il_enable_rfkill_int(il);
4536
4537#ifdef CONFIG_IWLEGACY_DEBUG
4538        if (il_get_debug_level(il) & (IL_DL_ISR)) {
4539                inta = _il_rd(il, CSR_INT);
4540                inta_mask = _il_rd(il, CSR_INT_MASK);
4541                inta_fh = _il_rd(il, CSR_FH_INT_STATUS);
4542                D_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
4543                      "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
4544        }
4545#endif
4546}
4547
4548/*****************************************************************************
4549 *
4550 * sysfs attributes
4551 *
4552 *****************************************************************************/
4553
4554#ifdef CONFIG_IWLEGACY_DEBUG
4555
4556/*
4557 * The following adds a new attribute to the sysfs representation
4558 * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
4559 * used for controlling the debug level.
4560 *
4561 * See the level definitions in iwl for details.
4562 *
4563 * The debug_level being managed using sysfs below is a per device debug
4564 * level that is used instead of the global debug level if it (the per
4565 * device debug level) is set.
4566 */
4567static ssize_t
4568il4965_show_debug_level(struct device *d, struct device_attribute *attr,
4569                        char *buf)
4570{
4571        struct il_priv *il = dev_get_drvdata(d);
4572        return sprintf(buf, "0x%08X\n", il_get_debug_level(il));
4573}
4574
4575static ssize_t
4576il4965_store_debug_level(struct device *d, struct device_attribute *attr,
4577                         const char *buf, size_t count)
4578{
4579        struct il_priv *il = dev_get_drvdata(d);
4580        unsigned long val;
4581        int ret;
4582
4583        ret = kstrtoul(buf, 0, &val);
4584        if (ret)
4585                IL_ERR("%s is not in hex or decimal form.\n", buf);
4586        else
4587                il->debug_level = val;
4588
4589        return strnlen(buf, count);
4590}
4591
4592static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO, il4965_show_debug_level,
4593                   il4965_store_debug_level);
4594
4595#endif /* CONFIG_IWLEGACY_DEBUG */
4596
4597static ssize_t
4598il4965_show_temperature(struct device *d, struct device_attribute *attr,
4599                        char *buf)
4600{
4601        struct il_priv *il = dev_get_drvdata(d);
4602
4603        if (!il_is_alive(il))
4604                return -EAGAIN;
4605
4606        return sprintf(buf, "%d\n", il->temperature);
4607}
4608
4609static DEVICE_ATTR(temperature, S_IRUGO, il4965_show_temperature, NULL);
4610
4611static ssize_t
4612il4965_show_tx_power(struct device *d, struct device_attribute *attr, char *buf)
4613{
4614        struct il_priv *il = dev_get_drvdata(d);
4615
4616        if (!il_is_ready_rf(il))
4617                return sprintf(buf, "off\n");
4618        else
4619                return sprintf(buf, "%d\n", il->tx_power_user_lmt);
4620}
4621
4622static ssize_t
4623il4965_store_tx_power(struct device *d, struct device_attribute *attr,
4624                      const char *buf, size_t count)
4625{
4626        struct il_priv *il = dev_get_drvdata(d);
4627        unsigned long val;
4628        int ret;
4629
4630        ret = kstrtoul(buf, 10, &val);
4631        if (ret)
4632                IL_INFO("%s is not in decimal form.\n", buf);
4633        else {
4634                ret = il_set_tx_power(il, val, false);
4635                if (ret)
4636                        IL_ERR("failed setting tx power (0x%08x).\n", ret);
4637                else
4638                        ret = count;
4639        }
4640        return ret;
4641}
4642
4643static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, il4965_show_tx_power,
4644                   il4965_store_tx_power);
4645
4646static struct attribute *il_sysfs_entries[] = {
4647        &dev_attr_temperature.attr,
4648        &dev_attr_tx_power.attr,
4649#ifdef CONFIG_IWLEGACY_DEBUG
4650        &dev_attr_debug_level.attr,
4651#endif
4652        NULL
4653};
4654
4655static struct attribute_group il_attribute_group = {
4656        .name = NULL,           /* put in device directory */
4657        .attrs = il_sysfs_entries,
4658};
4659
4660/******************************************************************************
4661 *
4662 * uCode download functions
4663 *
4664 ******************************************************************************/
4665
4666static void
4667il4965_dealloc_ucode_pci(struct il_priv *il)
4668{
4669        il_free_fw_desc(il->pci_dev, &il->ucode_code);
4670        il_free_fw_desc(il->pci_dev, &il->ucode_data);
4671        il_free_fw_desc(il->pci_dev, &il->ucode_data_backup);
4672        il_free_fw_desc(il->pci_dev, &il->ucode_init);
4673        il_free_fw_desc(il->pci_dev, &il->ucode_init_data);
4674        il_free_fw_desc(il->pci_dev, &il->ucode_boot);
4675}
4676
4677static void
4678il4965_nic_start(struct il_priv *il)
4679{
4680        /* Remove all resets to allow NIC to operate */
4681        _il_wr(il, CSR_RESET, 0);
4682}
4683
4684static void il4965_ucode_callback(const struct firmware *ucode_raw,
4685                                  void *context);
4686static int il4965_mac_setup_register(struct il_priv *il, u32 max_probe_length);
4687
4688static int __must_check
4689il4965_request_firmware(struct il_priv *il, bool first)
4690{
4691        const char *name_pre = il->cfg->fw_name_pre;
4692        char tag[8];
4693
4694        if (first) {
4695                il->fw_idx = il->cfg->ucode_api_max;
4696                sprintf(tag, "%d", il->fw_idx);
4697        } else {
4698                il->fw_idx--;
4699                sprintf(tag, "%d", il->fw_idx);
4700        }
4701
4702        if (il->fw_idx < il->cfg->ucode_api_min) {
4703                IL_ERR("no suitable firmware found!\n");
4704                return -ENOENT;
4705        }
4706
4707        sprintf(il->firmware_name, "%s%s%s", name_pre, tag, ".ucode");
4708
4709        D_INFO("attempting to load firmware '%s'\n", il->firmware_name);
4710
4711        return request_firmware_nowait(THIS_MODULE, 1, il->firmware_name,
4712                                       &il->pci_dev->dev, GFP_KERNEL, il,
4713                                       il4965_ucode_callback);
4714}
4715
4716struct il4965_firmware_pieces {
4717        const void *inst, *data, *init, *init_data, *boot;
4718        size_t inst_size, data_size, init_size, init_data_size, boot_size;
4719};
4720
4721static int
4722il4965_load_firmware(struct il_priv *il, const struct firmware *ucode_raw,
4723                     struct il4965_firmware_pieces *pieces)
4724{
4725        struct il_ucode_header *ucode = (void *)ucode_raw->data;
4726        u32 api_ver, hdr_size;
4727        const u8 *src;
4728
4729        il->ucode_ver = le32_to_cpu(ucode->ver);
4730        api_ver = IL_UCODE_API(il->ucode_ver);
4731
4732        switch (api_ver) {
4733        default:
4734        case 0:
4735        case 1:
4736        case 2:
4737                hdr_size = 24;
4738                if (ucode_raw->size < hdr_size) {
4739                        IL_ERR("File size too small!\n");
4740                        return -EINVAL;
4741                }
4742                pieces->inst_size = le32_to_cpu(ucode->v1.inst_size);
4743                pieces->data_size = le32_to_cpu(ucode->v1.data_size);
4744                pieces->init_size = le32_to_cpu(ucode->v1.init_size);
4745                pieces->init_data_size = le32_to_cpu(ucode->v1.init_data_size);
4746                pieces->boot_size = le32_to_cpu(ucode->v1.boot_size);
4747                src = ucode->v1.data;
4748                break;
4749        }
4750
4751        /* Verify size of file vs. image size info in file's header */
4752        if (ucode_raw->size !=
4753            hdr_size + pieces->inst_size + pieces->data_size +
4754            pieces->init_size + pieces->init_data_size + pieces->boot_size) {
4755
4756                IL_ERR("uCode file size %d does not match expected size\n",
4757                       (int)ucode_raw->size);
4758                return -EINVAL;
4759        }
4760
4761        pieces->inst = src;
4762        src += pieces->inst_size;
4763        pieces->data = src;
4764        src += pieces->data_size;
4765        pieces->init = src;
4766        src += pieces->init_size;
4767        pieces->init_data = src;
4768        src += pieces->init_data_size;
4769        pieces->boot = src;
4770        src += pieces->boot_size;
4771
4772        return 0;
4773}
4774
4775/**
4776 * il4965_ucode_callback - callback when firmware was loaded
4777 *
4778 * If loaded successfully, copies the firmware into buffers
4779 * for the card to fetch (via DMA).
4780 */
4781static void
4782il4965_ucode_callback(const struct firmware *ucode_raw, void *context)
4783{
4784        struct il_priv *il = context;
4785        struct il_ucode_header *ucode;
4786        int err;
4787        struct il4965_firmware_pieces pieces;
4788        const unsigned int api_max = il->cfg->ucode_api_max;
4789        const unsigned int api_min = il->cfg->ucode_api_min;
4790        u32 api_ver;
4791
4792        u32 max_probe_length = 200;
4793        u32 standard_phy_calibration_size =
4794            IL_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE;
4795
4796        memset(&pieces, 0, sizeof(pieces));
4797
4798        if (!ucode_raw) {
4799                if (il->fw_idx <= il->cfg->ucode_api_max)
4800                        IL_ERR("request for firmware file '%s' failed.\n",
4801                               il->firmware_name);
4802                goto try_again;
4803        }
4804
4805        D_INFO("Loaded firmware file '%s' (%zd bytes).\n", il->firmware_name,
4806               ucode_raw->size);
4807
4808        /* Make sure that we got at least the API version number */
4809        if (ucode_raw->size < 4) {
4810                IL_ERR("File size way too small!\n");
4811                goto try_again;
4812        }
4813
4814        /* Data from ucode file:  header followed by uCode images */
4815        ucode = (struct il_ucode_header *)ucode_raw->data;
4816
4817        err = il4965_load_firmware(il, ucode_raw, &pieces);
4818
4819        if (err)
4820                goto try_again;
4821
4822        api_ver = IL_UCODE_API(il->ucode_ver);
4823
4824        /*
4825         * api_ver should match the api version forming part of the
4826         * firmware filename ... but we don't check for that and only rely
4827         * on the API version read from firmware header from here on forward
4828         */
4829        if (api_ver < api_min || api_ver > api_max) {
4830                IL_ERR("Driver unable to support your firmware API. "
4831                       "Driver supports v%u, firmware is v%u.\n", api_max,
4832                       api_ver);
4833                goto try_again;
4834        }
4835
4836        if (api_ver != api_max)
4837                IL_ERR("Firmware has old API version. Expected v%u, "
4838                       "got v%u. New firmware can be obtained "
4839                       "from http://www.intellinuxwireless.org.\n", api_max,
4840                       api_ver);
4841
4842        IL_INFO("loaded firmware version %u.%u.%u.%u\n",
4843                IL_UCODE_MAJOR(il->ucode_ver), IL_UCODE_MINOR(il->ucode_ver),
4844                IL_UCODE_API(il->ucode_ver), IL_UCODE_SERIAL(il->ucode_ver));
4845
4846        snprintf(il->hw->wiphy->fw_version, sizeof(il->hw->wiphy->fw_version),
4847                 "%u.%u.%u.%u", IL_UCODE_MAJOR(il->ucode_ver),
4848                 IL_UCODE_MINOR(il->ucode_ver), IL_UCODE_API(il->ucode_ver),
4849                 IL_UCODE_SERIAL(il->ucode_ver));
4850
4851        /*
4852         * For any of the failures below (before allocating pci memory)
4853         * we will try to load a version with a smaller API -- maybe the
4854         * user just got a corrupted version of the latest API.
4855         */
4856
4857        D_INFO("f/w package hdr ucode version raw = 0x%x\n", il->ucode_ver);
4858        D_INFO("f/w package hdr runtime inst size = %Zd\n", pieces.inst_size);
4859        D_INFO("f/w package hdr runtime data size = %Zd\n", pieces.data_size);
4860        D_INFO("f/w package hdr init inst size = %Zd\n", pieces.init_size);
4861        D_INFO("f/w package hdr init data size = %Zd\n", pieces.init_data_size);
4862        D_INFO("f/w package hdr boot inst size = %Zd\n", pieces.boot_size);
4863
4864        /* Verify that uCode images will fit in card's SRAM */
4865        if (pieces.inst_size > il->hw_params.max_inst_size) {
4866                IL_ERR("uCode instr len %Zd too large to fit in\n",
4867                       pieces.inst_size);
4868                goto try_again;
4869        }
4870
4871        if (pieces.data_size > il->hw_params.max_data_size) {
4872                IL_ERR("uCode data len %Zd too large to fit in\n",
4873                       pieces.data_size);
4874                goto try_again;
4875        }
4876
4877        if (pieces.init_size > il->hw_params.max_inst_size) {
4878                IL_ERR("uCode init instr len %Zd too large to fit in\n",
4879                       pieces.init_size);
4880                goto try_again;
4881        }
4882
4883        if (pieces.init_data_size > il->hw_params.max_data_size) {
4884                IL_ERR("uCode init data len %Zd too large to fit in\n",
4885                       pieces.init_data_size);
4886                goto try_again;
4887        }
4888
4889        if (pieces.boot_size > il->hw_params.max_bsm_size) {
4890                IL_ERR("uCode boot instr len %Zd too large to fit in\n",
4891                       pieces.boot_size);
4892                goto try_again;
4893        }
4894
4895        /* Allocate ucode buffers for card's bus-master loading ... */
4896
4897        /* Runtime instructions and 2 copies of data:
4898         * 1) unmodified from disk
4899         * 2) backup cache for save/restore during power-downs */
4900        il->ucode_code.len = pieces.inst_size;
4901        il_alloc_fw_desc(il->pci_dev, &il->ucode_code);
4902
4903        il->ucode_data.len = pieces.data_size;
4904        il_alloc_fw_desc(il->pci_dev, &il->ucode_data);
4905
4906        il->ucode_data_backup.len = pieces.data_size;
4907        il_alloc_fw_desc(il->pci_dev, &il->ucode_data_backup);
4908
4909        if (!il->ucode_code.v_addr || !il->ucode_data.v_addr ||
4910            !il->ucode_data_backup.v_addr)
4911                goto err_pci_alloc;
4912
4913        /* Initialization instructions and data */
4914        if (pieces.init_size && pieces.init_data_size) {
4915                il->ucode_init.len = pieces.init_size;
4916                il_alloc_fw_desc(il->pci_dev, &il->ucode_init);
4917
4918                il->ucode_init_data.len = pieces.init_data_size;
4919                il_alloc_fw_desc(il->pci_dev, &il->ucode_init_data);
4920
4921                if (!il->ucode_init.v_addr || !il->ucode_init_data.v_addr)
4922                        goto err_pci_alloc;
4923        }
4924
4925        /* Bootstrap (instructions only, no data) */
4926        if (pieces.boot_size) {
4927                il->ucode_boot.len = pieces.boot_size;
4928                il_alloc_fw_desc(il->pci_dev, &il->ucode_boot);
4929
4930                if (!il->ucode_boot.v_addr)
4931                        goto err_pci_alloc;
4932        }
4933
4934        /* Now that we can no longer fail, copy information */
4935
4936        il->sta_key_max_num = STA_KEY_MAX_NUM;
4937
4938        /* Copy images into buffers for card's bus-master reads ... */
4939
4940        /* Runtime instructions (first block of data in file) */
4941        D_INFO("Copying (but not loading) uCode instr len %Zd\n",
4942               pieces.inst_size);
4943        memcpy(il->ucode_code.v_addr, pieces.inst, pieces.inst_size);
4944
4945        D_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
4946               il->ucode_code.v_addr, (u32) il->ucode_code.p_addr);
4947
4948        /*
4949         * Runtime data
4950         * NOTE:  Copy into backup buffer will be done in il_up()
4951         */
4952        D_INFO("Copying (but not loading) uCode data len %Zd\n",
4953               pieces.data_size);
4954        memcpy(il->ucode_data.v_addr, pieces.data, pieces.data_size);
4955        memcpy(il->ucode_data_backup.v_addr, pieces.data, pieces.data_size);
4956
4957        /* Initialization instructions */
4958        if (pieces.init_size) {
4959                D_INFO("Copying (but not loading) init instr len %Zd\n",
4960                       pieces.init_size);
4961                memcpy(il->ucode_init.v_addr, pieces.init, pieces.init_size);
4962        }
4963
4964        /* Initialization data */
4965        if (pieces.init_data_size) {
4966                D_INFO("Copying (but not loading) init data len %Zd\n",
4967                       pieces.init_data_size);
4968                memcpy(il->ucode_init_data.v_addr, pieces.init_data,
4969                       pieces.init_data_size);
4970        }
4971
4972        /* Bootstrap instructions */
4973        D_INFO("Copying (but not loading) boot instr len %Zd\n",
4974               pieces.boot_size);
4975        memcpy(il->ucode_boot.v_addr, pieces.boot, pieces.boot_size);
4976
4977        /*
4978         * figure out the offset of chain noise reset and gain commands
4979         * base on the size of standard phy calibration commands table size
4980         */
4981        il->_4965.phy_calib_chain_noise_reset_cmd =
4982            standard_phy_calibration_size;
4983        il->_4965.phy_calib_chain_noise_gain_cmd =
4984            standard_phy_calibration_size + 1;
4985
4986        /**************************************************
4987         * This is still part of probe() in a sense...
4988         *
4989         * 9. Setup and register with mac80211 and debugfs
4990         **************************************************/
4991        err = il4965_mac_setup_register(il, max_probe_length);
4992        if (err)
4993                goto out_unbind;
4994
4995        err = il_dbgfs_register(il, DRV_NAME);
4996        if (err)
4997                IL_ERR("failed to create debugfs files. Ignoring error: %d\n",
4998                       err);
4999
5000        err = sysfs_create_group(&il->pci_dev->dev.kobj, &il_attribute_group);
5001        if (err) {
5002                IL_ERR("failed to create sysfs device attributes\n");
5003                goto out_unbind;
5004        }
5005
5006        /* We have our copies now, allow OS release its copies */
5007        release_firmware(ucode_raw);
5008        complete(&il->_4965.firmware_loading_complete);
5009        return;
5010
5011try_again:
5012        /* try next, if any */
5013        if (il4965_request_firmware(il, false))
5014                goto out_unbind;
5015        release_firmware(ucode_raw);
5016        return;
5017
5018err_pci_alloc:
5019        IL_ERR("failed to allocate pci memory\n");
5020        il4965_dealloc_ucode_pci(il);
5021out_unbind:
5022        complete(&il->_4965.firmware_loading_complete);
5023        device_release_driver(&il->pci_dev->dev);
5024        release_firmware(ucode_raw);
5025}
5026
5027static const char *const desc_lookup_text[] = {
5028        "OK",
5029        "FAIL",
5030        "BAD_PARAM",
5031        "BAD_CHECKSUM",
5032        "NMI_INTERRUPT_WDG",
5033        "SYSASSERT",
5034        "FATAL_ERROR",
5035        "BAD_COMMAND",
5036        "HW_ERROR_TUNE_LOCK",
5037        "HW_ERROR_TEMPERATURE",
5038        "ILLEGAL_CHAN_FREQ",
5039        "VCC_NOT_STBL",
5040        "FH49_ERROR",
5041        "NMI_INTERRUPT_HOST",
5042        "NMI_INTERRUPT_ACTION_PT",
5043        "NMI_INTERRUPT_UNKNOWN",
5044        "UCODE_VERSION_MISMATCH",
5045        "HW_ERROR_ABS_LOCK",
5046        "HW_ERROR_CAL_LOCK_FAIL",
5047        "NMI_INTERRUPT_INST_ACTION_PT",
5048        "NMI_INTERRUPT_DATA_ACTION_PT",
5049        "NMI_TRM_HW_ER",
5050        "NMI_INTERRUPT_TRM",
5051        "NMI_INTERRUPT_BREAK_POINT",
5052        "DEBUG_0",
5053        "DEBUG_1",
5054        "DEBUG_2",
5055        "DEBUG_3",
5056};
5057
5058static struct {
5059        char *name;
5060        u8 num;
5061} advanced_lookup[] = {
5062        {
5063        "NMI_INTERRUPT_WDG", 0x34}, {
5064        "SYSASSERT", 0x35}, {
5065        "UCODE_VERSION_MISMATCH", 0x37}, {
5066        "BAD_COMMAND", 0x38}, {
5067        "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C}, {
5068        "FATAL_ERROR", 0x3D}, {
5069        "NMI_TRM_HW_ERR", 0x46}, {
5070        "NMI_INTERRUPT_TRM", 0x4C}, {
5071        "NMI_INTERRUPT_BREAK_POINT", 0x54}, {
5072        "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C}, {
5073        "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64}, {
5074        "NMI_INTERRUPT_HOST", 0x66}, {
5075        "NMI_INTERRUPT_ACTION_PT", 0x7C}, {
5076        "NMI_INTERRUPT_UNKNOWN", 0x84}, {
5077        "NMI_INTERRUPT_INST_ACTION_PT", 0x86}, {
5078"ADVANCED_SYSASSERT", 0},};
5079
5080static const char *
5081il4965_desc_lookup(u32 num)
5082{
5083        int i;
5084        int max = ARRAY_SIZE(desc_lookup_text);
5085
5086        if (num < max)
5087                return desc_lookup_text[num];
5088
5089        max = ARRAY_SIZE(advanced_lookup) - 1;
5090        for (i = 0; i < max; i++) {
5091                if (advanced_lookup[i].num == num)
5092                        break;
5093        }
5094        return advanced_lookup[i].name;
5095}
5096
5097#define ERROR_START_OFFSET  (1 * sizeof(u32))
5098#define ERROR_ELEM_SIZE     (7 * sizeof(u32))
5099
5100void
5101il4965_dump_nic_error_log(struct il_priv *il)
5102{
5103        u32 data2, line;
5104        u32 desc, time, count, base, data1;
5105        u32 blink1, blink2, ilink1, ilink2;
5106        u32 pc, hcmd;
5107
5108        if (il->ucode_type == UCODE_INIT)
5109                base = le32_to_cpu(il->card_alive_init.error_event_table_ptr);
5110        else
5111                base = le32_to_cpu(il->card_alive.error_event_table_ptr);
5112
5113        if (!il->ops->is_valid_rtc_data_addr(base)) {
5114                IL_ERR("Not valid error log pointer 0x%08X for %s uCode\n",
5115                       base, (il->ucode_type == UCODE_INIT) ? "Init" : "RT");
5116                return;
5117        }
5118
5119        count = il_read_targ_mem(il, base);
5120
5121        if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
5122                IL_ERR("Start IWL Error Log Dump:\n");
5123                IL_ERR("Status: 0x%08lX, count: %d\n", il->status, count);
5124        }
5125
5126        desc = il_read_targ_mem(il, base + 1 * sizeof(u32));
5127        il->isr_stats.err_code = desc;
5128        pc = il_read_targ_mem(il, base + 2 * sizeof(u32));
5129        blink1 = il_read_targ_mem(il, base + 3 * sizeof(u32));
5130        blink2 = il_read_targ_mem(il, base + 4 * sizeof(u32));
5131        ilink1 = il_read_targ_mem(il, base + 5 * sizeof(u32));
5132        ilink2 = il_read_targ_mem(il, base + 6 * sizeof(u32));
5133        data1 = il_read_targ_mem(il, base + 7 * sizeof(u32));
5134        data2 = il_read_targ_mem(il, base + 8 * sizeof(u32));
5135        line = il_read_targ_mem(il, base + 9 * sizeof(u32));
5136        time = il_read_targ_mem(il, base + 11 * sizeof(u32));
5137        hcmd = il_read_targ_mem(il, base + 22 * sizeof(u32));
5138
5139        IL_ERR("Desc                                  Time       "
5140               "data1      data2      line\n");
5141        IL_ERR("%-28s (0x%04X) %010u 0x%08X 0x%08X %u\n",
5142               il4965_desc_lookup(desc), desc, time, data1, data2, line);
5143        IL_ERR("pc      blink1  blink2  ilink1  ilink2  hcmd\n");
5144        IL_ERR("0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n", pc, blink1,
5145               blink2, ilink1, ilink2, hcmd);
5146}
5147
5148static void
5149il4965_rf_kill_ct_config(struct il_priv *il)
5150{
5151        struct il_ct_kill_config cmd;
5152        unsigned long flags;
5153        int ret = 0;
5154
5155        spin_lock_irqsave(&il->lock, flags);
5156        _il_wr(il, CSR_UCODE_DRV_GP1_CLR,
5157               CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
5158        spin_unlock_irqrestore(&il->lock, flags);
5159
5160        cmd.critical_temperature_R =
5161            cpu_to_le32(il->hw_params.ct_kill_threshold);
5162
5163        ret = il_send_cmd_pdu(il, C_CT_KILL_CONFIG, sizeof(cmd), &cmd);
5164        if (ret)
5165                IL_ERR("C_CT_KILL_CONFIG failed\n");
5166        else
5167                D_INFO("C_CT_KILL_CONFIG " "succeeded, "
5168                       "critical temperature is %d\n",
5169                       il->hw_params.ct_kill_threshold);
5170}
5171
5172static const s8 default_queue_to_tx_fifo[] = {
5173        IL_TX_FIFO_VO,
5174        IL_TX_FIFO_VI,
5175        IL_TX_FIFO_BE,
5176        IL_TX_FIFO_BK,
5177        IL49_CMD_FIFO_NUM,
5178        IL_TX_FIFO_UNUSED,
5179        IL_TX_FIFO_UNUSED,
5180};
5181
5182#define IL_MASK(lo, hi) ((1 << (hi)) | ((1 << (hi)) - (1 << (lo))))
5183
5184static int
5185il4965_alive_notify(struct il_priv *il)
5186{
5187        u32 a;
5188        unsigned long flags;
5189        int i, chan;
5190        u32 reg_val;
5191
5192        spin_lock_irqsave(&il->lock, flags);
5193
5194        /* Clear 4965's internal Tx Scheduler data base */
5195        il->scd_base_addr = il_rd_prph(il, IL49_SCD_SRAM_BASE_ADDR);
5196        a = il->scd_base_addr + IL49_SCD_CONTEXT_DATA_OFFSET;
5197        for (; a < il->scd_base_addr + IL49_SCD_TX_STTS_BITMAP_OFFSET; a += 4)
5198                il_write_targ_mem(il, a, 0);
5199        for (; a < il->scd_base_addr + IL49_SCD_TRANSLATE_TBL_OFFSET; a += 4)
5200                il_write_targ_mem(il, a, 0);
5201        for (;
5202             a <
5203             il->scd_base_addr +
5204             IL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(il->hw_params.max_txq_num);
5205             a += 4)
5206                il_write_targ_mem(il, a, 0);
5207
5208        /* Tel 4965 where to find Tx byte count tables */
5209        il_wr_prph(il, IL49_SCD_DRAM_BASE_ADDR, il->scd_bc_tbls.dma >> 10);
5210
5211        /* Enable DMA channel */
5212        for (chan = 0; chan < FH49_TCSR_CHNL_NUM; chan++)
5213                il_wr(il, FH49_TCSR_CHNL_TX_CONFIG_REG(chan),
5214                      FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
5215                      FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
5216
5217        /* Update FH chicken bits */
5218        reg_val = il_rd(il, FH49_TX_CHICKEN_BITS_REG);
5219        il_wr(il, FH49_TX_CHICKEN_BITS_REG,
5220              reg_val | FH49_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
5221
5222        /* Disable chain mode for all queues */
5223        il_wr_prph(il, IL49_SCD_QUEUECHAIN_SEL, 0);
5224
5225        /* Initialize each Tx queue (including the command queue) */
5226        for (i = 0; i < il->hw_params.max_txq_num; i++) {
5227
5228                /* TFD circular buffer read/write idxes */
5229                il_wr_prph(il, IL49_SCD_QUEUE_RDPTR(i), 0);
5230                il_wr(il, HBUS_TARG_WRPTR, 0 | (i << 8));
5231
5232                /* Max Tx Window size for Scheduler-ACK mode */
5233                il_write_targ_mem(il,
5234                                  il->scd_base_addr +
5235                                  IL49_SCD_CONTEXT_QUEUE_OFFSET(i),
5236                                  (SCD_WIN_SIZE <<
5237                                   IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
5238                                  IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
5239
5240                /* Frame limit */
5241                il_write_targ_mem(il,
5242                                  il->scd_base_addr +
5243                                  IL49_SCD_CONTEXT_QUEUE_OFFSET(i) +
5244                                  sizeof(u32),
5245                                  (SCD_FRAME_LIMIT <<
5246                                   IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
5247                                  IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
5248
5249        }
5250        il_wr_prph(il, IL49_SCD_INTERRUPT_MASK,
5251                   (1 << il->hw_params.max_txq_num) - 1);
5252
5253        /* Activate all Tx DMA/FIFO channels */
5254        il4965_txq_set_sched(il, IL_MASK(0, 6));
5255
5256        il4965_set_wr_ptrs(il, IL_DEFAULT_CMD_QUEUE_NUM, 0);
5257
5258        /* make sure all queue are not stopped */
5259        memset(&il->queue_stopped[0], 0, sizeof(il->queue_stopped));
5260        for (i = 0; i < 4; i++)
5261                atomic_set(&il->queue_stop_count[i], 0);
5262
5263        /* reset to 0 to enable all the queue first */
5264        il->txq_ctx_active_msk = 0;
5265        /* Map each Tx/cmd queue to its corresponding fifo */
5266        BUILD_BUG_ON(ARRAY_SIZE(default_queue_to_tx_fifo) != 7);
5267
5268        for (i = 0; i < ARRAY_SIZE(default_queue_to_tx_fifo); i++) {
5269                int ac = default_queue_to_tx_fifo[i];
5270
5271                il_txq_ctx_activate(il, i);
5272
5273                if (ac == IL_TX_FIFO_UNUSED)
5274                        continue;
5275
5276                il4965_tx_queue_set_status(il, &il->txq[i], ac, 0);
5277        }
5278
5279        spin_unlock_irqrestore(&il->lock, flags);
5280
5281        return 0;
5282}
5283
5284/**
5285 * il4965_alive_start - called after N_ALIVE notification received
5286 *                   from protocol/runtime uCode (initialization uCode's
5287 *                   Alive gets handled by il_init_alive_start()).
5288 */
5289static void
5290il4965_alive_start(struct il_priv *il)
5291{
5292        int ret = 0;
5293
5294        D_INFO("Runtime Alive received.\n");
5295
5296        if (il->card_alive.is_valid != UCODE_VALID_OK) {
5297                /* We had an error bringing up the hardware, so take it
5298                 * all the way back down so we can try again */
5299                D_INFO("Alive failed.\n");
5300                goto restart;
5301        }
5302
5303        /* Initialize uCode has loaded Runtime uCode ... verify inst image.
5304         * This is a paranoid check, because we would not have gotten the
5305         * "runtime" alive if code weren't properly loaded.  */
5306        if (il4965_verify_ucode(il)) {
5307                /* Runtime instruction load was bad;
5308                 * take it all the way back down so we can try again */
5309                D_INFO("Bad runtime uCode load.\n");
5310                goto restart;
5311        }
5312
5313        ret = il4965_alive_notify(il);
5314        if (ret) {
5315                IL_WARN("Could not complete ALIVE transition [ntf]: %d\n", ret);
5316                goto restart;
5317        }
5318
5319        /* After the ALIVE response, we can send host commands to the uCode */
5320        set_bit(S_ALIVE, &il->status);
5321
5322        /* Enable watchdog to monitor the driver tx queues */
5323        il_setup_watchdog(il);
5324
5325        if (il_is_rfkill(il))
5326                return;
5327
5328        ieee80211_wake_queues(il->hw);
5329
5330        il->active_rate = RATES_MASK;
5331
5332        il_power_update_mode(il, true);
5333        D_INFO("Updated power mode\n");
5334
5335        if (il_is_associated(il)) {
5336                struct il_rxon_cmd *active_rxon =
5337                    (struct il_rxon_cmd *)&il->active;
5338                /* apply any changes in staging */
5339                il->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
5340                active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
5341        } else {
5342                /* Initialize our rx_config data */
5343                il_connection_init_rx_config(il);
5344
5345                if (il->ops->set_rxon_chain)
5346                        il->ops->set_rxon_chain(il);
5347        }
5348
5349        /* Configure bluetooth coexistence if enabled */
5350        il_send_bt_config(il);
5351
5352        il4965_reset_run_time_calib(il);
5353
5354        set_bit(S_READY, &il->status);
5355
5356        /* Configure the adapter for unassociated operation */
5357        il_commit_rxon(il);
5358
5359        /* At this point, the NIC is initialized and operational */
5360        il4965_rf_kill_ct_config(il);
5361
5362        D_INFO("ALIVE processing complete.\n");
5363        wake_up(&il->wait_command_queue);
5364
5365        return;
5366
5367restart:
5368        queue_work(il->workqueue, &il->restart);
5369}
5370
5371static void il4965_cancel_deferred_work(struct il_priv *il);
5372
5373static void
5374__il4965_down(struct il_priv *il)
5375{
5376        unsigned long flags;
5377        int exit_pending;
5378
5379        D_INFO(DRV_NAME " is going down\n");
5380
5381        il_scan_cancel_timeout(il, 200);
5382
5383        exit_pending = test_and_set_bit(S_EXIT_PENDING, &il->status);
5384
5385        /* Stop TX queues watchdog. We need to have S_EXIT_PENDING bit set
5386         * to prevent rearm timer */
5387        del_timer_sync(&il->watchdog);
5388
5389        il_clear_ucode_stations(il);
5390
5391        /* FIXME: race conditions ? */
5392        spin_lock_irq(&il->sta_lock);
5393        /*
5394         * Remove all key information that is not stored as part
5395         * of station information since mac80211 may not have had
5396         * a chance to remove all the keys. When device is
5397         * reconfigured by mac80211 after an error all keys will
5398         * be reconfigured.
5399         */
5400        memset(il->_4965.wep_keys, 0, sizeof(il->_4965.wep_keys));
5401        il->_4965.key_mapping_keys = 0;
5402        spin_unlock_irq(&il->sta_lock);
5403
5404        il_dealloc_bcast_stations(il);
5405        il_clear_driver_stations(il);
5406
5407        /* Unblock any waiting calls */
5408        wake_up_all(&il->wait_command_queue);
5409
5410        /* Wipe out the EXIT_PENDING status bit if we are not actually
5411         * exiting the module */
5412        if (!exit_pending)
5413                clear_bit(S_EXIT_PENDING, &il->status);
5414
5415        /* stop and reset the on-board processor */
5416        _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
5417
5418        /* tell the device to stop sending interrupts */
5419        spin_lock_irqsave(&il->lock, flags);
5420        il_disable_interrupts(il);
5421        spin_unlock_irqrestore(&il->lock, flags);
5422        il4965_synchronize_irq(il);
5423
5424        if (il->mac80211_registered)
5425                ieee80211_stop_queues(il->hw);
5426
5427        /* If we have not previously called il_init() then
5428         * clear all bits but the RF Kill bit and return */
5429        if (!il_is_init(il)) {
5430                il->status =
5431                    test_bit(S_RFKILL, &il->status) << S_RFKILL |
5432                    test_bit(S_GEO_CONFIGURED, &il->status) << S_GEO_CONFIGURED |
5433                    test_bit(S_EXIT_PENDING, &il->status) << S_EXIT_PENDING;
5434                goto exit;
5435        }
5436
5437        /* ...otherwise clear out all the status bits but the RF Kill
5438         * bit and continue taking the NIC down. */
5439        il->status &=
5440            test_bit(S_RFKILL, &il->status) << S_RFKILL |
5441            test_bit(S_GEO_CONFIGURED, &il->status) << S_GEO_CONFIGURED |
5442            test_bit(S_FW_ERROR, &il->status) << S_FW_ERROR |
5443            test_bit(S_EXIT_PENDING, &il->status) << S_EXIT_PENDING;
5444
5445        /*
5446         * We disabled and synchronized interrupt, and priv->mutex is taken, so
5447         * here is the only thread which will program device registers, but
5448         * still have lockdep assertions, so we are taking reg_lock.
5449         */
5450        spin_lock_irq(&il->reg_lock);
5451        /* FIXME: il_grab_nic_access if rfkill is off ? */
5452
5453        il4965_txq_ctx_stop(il);
5454        il4965_rxq_stop(il);
5455        /* Power-down device's busmaster DMA clocks */
5456        _il_wr_prph(il, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
5457        udelay(5);
5458        /* Make sure (redundant) we've released our request to stay awake */
5459        _il_clear_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
5460        /* Stop the device, and put it in low power state */
5461        _il_apm_stop(il);
5462
5463        spin_unlock_irq(&il->reg_lock);
5464
5465        il4965_txq_ctx_unmap(il);
5466exit:
5467        memset(&il->card_alive, 0, sizeof(struct il_alive_resp));
5468
5469        dev_kfree_skb(il->beacon_skb);
5470        il->beacon_skb = NULL;
5471
5472        /* clear out any free frames */
5473        il4965_clear_free_frames(il);
5474}
5475
5476static void
5477il4965_down(struct il_priv *il)
5478{
5479        mutex_lock(&il->mutex);
5480        __il4965_down(il);
5481        mutex_unlock(&il->mutex);
5482
5483        il4965_cancel_deferred_work(il);
5484}
5485
5486
5487static void
5488il4965_set_hw_ready(struct il_priv *il)
5489{
5490        int ret;
5491
5492        il_set_bit(il, CSR_HW_IF_CONFIG_REG,
5493                   CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
5494
5495        /* See if we got it */
5496        ret = _il_poll_bit(il, CSR_HW_IF_CONFIG_REG,
5497                           CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
5498                           CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
5499                           100);
5500        if (ret >= 0)
5501                il->hw_ready = true;
5502
5503        D_INFO("hardware %s ready\n", (il->hw_ready) ? "" : "not");
5504}
5505
5506static void
5507il4965_prepare_card_hw(struct il_priv *il)
5508{
5509        int ret;
5510
5511        il->hw_ready = false;
5512
5513        il4965_set_hw_ready(il);
5514        if (il->hw_ready)
5515                return;
5516
5517        /* If HW is not ready, prepare the conditions to check again */
5518        il_set_bit(il, CSR_HW_IF_CONFIG_REG, CSR_HW_IF_CONFIG_REG_PREPARE);
5519
5520        ret =
5521            _il_poll_bit(il, CSR_HW_IF_CONFIG_REG,
5522                         ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
5523                         CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
5524
5525        /* HW should be ready by now, check again. */
5526        if (ret != -ETIMEDOUT)
5527                il4965_set_hw_ready(il);
5528}
5529
5530#define MAX_HW_RESTARTS 5
5531
5532static int
5533__il4965_up(struct il_priv *il)
5534{
5535        int i;
5536        int ret;
5537
5538        if (test_bit(S_EXIT_PENDING, &il->status)) {
5539                IL_WARN("Exit pending; will not bring the NIC up\n");
5540                return -EIO;
5541        }
5542
5543        if (!il->ucode_data_backup.v_addr || !il->ucode_data.v_addr) {
5544                IL_ERR("ucode not available for device bringup\n");
5545                return -EIO;
5546        }
5547
5548        ret = il4965_alloc_bcast_station(il);
5549        if (ret) {
5550                il_dealloc_bcast_stations(il);
5551                return ret;
5552        }
5553
5554        il4965_prepare_card_hw(il);
5555        if (!il->hw_ready) {
5556                IL_ERR("HW not ready\n");
5557                return -EIO;
5558        }
5559
5560        /* If platform's RF_KILL switch is NOT set to KILL */
5561        if (_il_rd(il, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
5562                clear_bit(S_RFKILL, &il->status);
5563        else {
5564                set_bit(S_RFKILL, &il->status);
5565                wiphy_rfkill_set_hw_state(il->hw->wiphy, true);
5566
5567                il_enable_rfkill_int(il);
5568                IL_WARN("Radio disabled by HW RF Kill switch\n");
5569                return 0;
5570        }
5571
5572        _il_wr(il, CSR_INT, 0xFFFFFFFF);
5573
5574        /* must be initialised before il_hw_nic_init */
5575        il->cmd_queue = IL_DEFAULT_CMD_QUEUE_NUM;
5576
5577        ret = il4965_hw_nic_init(il);
5578        if (ret) {
5579                IL_ERR("Unable to init nic\n");
5580                return ret;
5581        }
5582
5583        /* make sure rfkill handshake bits are cleared */
5584        _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
5585        _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
5586
5587        /* clear (again), then enable host interrupts */
5588        _il_wr(il, CSR_INT, 0xFFFFFFFF);
5589        il_enable_interrupts(il);
5590
5591        /* really make sure rfkill handshake bits are cleared */
5592        _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
5593        _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
5594
5595        /* Copy original ucode data image from disk into backup cache.
5596         * This will be used to initialize the on-board processor's
5597         * data SRAM for a clean start when the runtime program first loads. */
5598        memcpy(il->ucode_data_backup.v_addr, il->ucode_data.v_addr,
5599               il->ucode_data.len);
5600
5601        for (i = 0; i < MAX_HW_RESTARTS; i++) {
5602
5603                /* load bootstrap state machine,
5604                 * load bootstrap program into processor's memory,
5605                 * prepare to load the "initialize" uCode */
5606                ret = il->ops->load_ucode(il);
5607
5608                if (ret) {
5609                        IL_ERR("Unable to set up bootstrap uCode: %d\n", ret);
5610                        continue;
5611                }
5612
5613                /* start card; "initialize" will load runtime ucode */
5614                il4965_nic_start(il);
5615
5616                D_INFO(DRV_NAME " is coming up\n");
5617
5618                return 0;
5619        }
5620
5621        set_bit(S_EXIT_PENDING, &il->status);
5622        __il4965_down(il);
5623        clear_bit(S_EXIT_PENDING, &il->status);
5624
5625        /* tried to restart and config the device for as long as our
5626         * patience could withstand */
5627        IL_ERR("Unable to initialize device after %d attempts.\n", i);
5628        return -EIO;
5629}
5630
5631/*****************************************************************************
5632 *
5633 * Workqueue callbacks
5634 *
5635 *****************************************************************************/
5636
5637static void
5638il4965_bg_init_alive_start(struct work_struct *data)
5639{
5640        struct il_priv *il =
5641            container_of(data, struct il_priv, init_alive_start.work);
5642
5643        mutex_lock(&il->mutex);
5644        if (test_bit(S_EXIT_PENDING, &il->status))
5645                goto out;
5646
5647        il->ops->init_alive_start(il);
5648out:
5649        mutex_unlock(&il->mutex);
5650}
5651
5652static void
5653il4965_bg_alive_start(struct work_struct *data)
5654{
5655        struct il_priv *il =
5656            container_of(data, struct il_priv, alive_start.work);
5657
5658        mutex_lock(&il->mutex);
5659        if (test_bit(S_EXIT_PENDING, &il->status))
5660                goto out;
5661
5662        il4965_alive_start(il);
5663out:
5664        mutex_unlock(&il->mutex);
5665}
5666
5667static void
5668il4965_bg_run_time_calib_work(struct work_struct *work)
5669{
5670        struct il_priv *il = container_of(work, struct il_priv,
5671                                          run_time_calib_work);
5672
5673        mutex_lock(&il->mutex);
5674
5675        if (test_bit(S_EXIT_PENDING, &il->status) ||
5676            test_bit(S_SCANNING, &il->status)) {
5677                mutex_unlock(&il->mutex);
5678                return;
5679        }
5680
5681        if (il->start_calib) {
5682                il4965_chain_noise_calibration(il, (void *)&il->_4965.stats);
5683                il4965_sensitivity_calibration(il, (void *)&il->_4965.stats);
5684        }
5685
5686        mutex_unlock(&il->mutex);
5687}
5688
5689static void
5690il4965_bg_restart(struct work_struct *data)
5691{
5692        struct il_priv *il = container_of(data, struct il_priv, restart);
5693
5694        if (test_bit(S_EXIT_PENDING, &il->status))
5695                return;
5696
5697        if (test_and_clear_bit(S_FW_ERROR, &il->status)) {
5698                mutex_lock(&il->mutex);
5699                il->is_open = 0;
5700
5701                __il4965_down(il);
5702
5703                mutex_unlock(&il->mutex);
5704                il4965_cancel_deferred_work(il);
5705                ieee80211_restart_hw(il->hw);
5706        } else {
5707                il4965_down(il);
5708
5709                mutex_lock(&il->mutex);
5710                if (test_bit(S_EXIT_PENDING, &il->status)) {
5711                        mutex_unlock(&il->mutex);
5712                        return;
5713                }
5714
5715                __il4965_up(il);
5716                mutex_unlock(&il->mutex);
5717        }
5718}
5719
5720static void
5721il4965_bg_rx_replenish(struct work_struct *data)
5722{
5723        struct il_priv *il = container_of(data, struct il_priv, rx_replenish);
5724
5725        if (test_bit(S_EXIT_PENDING, &il->status))
5726                return;
5727
5728        mutex_lock(&il->mutex);
5729        il4965_rx_replenish(il);
5730        mutex_unlock(&il->mutex);
5731}
5732
5733/*****************************************************************************
5734 *
5735 * mac80211 entry point functions
5736 *
5737 *****************************************************************************/
5738
5739#define UCODE_READY_TIMEOUT     (4 * HZ)
5740
5741/*
5742 * Not a mac80211 entry point function, but it fits in with all the
5743 * other mac80211 functions grouped here.
5744 */
5745static int
5746il4965_mac_setup_register(struct il_priv *il, u32 max_probe_length)
5747{
5748        int ret;
5749        struct ieee80211_hw *hw = il->hw;
5750
5751        hw->rate_control_algorithm = "iwl-4965-rs";
5752
5753        /* Tell mac80211 our characteristics */
5754        ieee80211_hw_set(hw, SUPPORTS_DYNAMIC_PS);
5755        ieee80211_hw_set(hw, SUPPORTS_PS);
5756        ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS);
5757        ieee80211_hw_set(hw, SPECTRUM_MGMT);
5758        ieee80211_hw_set(hw, NEED_DTIM_BEFORE_ASSOC);
5759        ieee80211_hw_set(hw, SIGNAL_DBM);
5760        ieee80211_hw_set(hw, AMPDU_AGGREGATION);
5761        if (il->cfg->sku & IL_SKU_N)
5762                hw->wiphy->features |= NL80211_FEATURE_DYNAMIC_SMPS |
5763                                       NL80211_FEATURE_STATIC_SMPS;
5764
5765        hw->sta_data_size = sizeof(struct il_station_priv);
5766        hw->vif_data_size = sizeof(struct il_vif_priv);
5767
5768        hw->wiphy->interface_modes =
5769            BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_ADHOC);
5770
5771        hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN;
5772        hw->wiphy->regulatory_flags |= REGULATORY_CUSTOM_REG |
5773                                       REGULATORY_DISABLE_BEACON_HINTS;
5774
5775        /*
5776         * For now, disable PS by default because it affects
5777         * RX performance significantly.
5778         */
5779        hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
5780
5781        hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
5782        /* we create the 802.11 header and a zero-length SSID element */
5783        hw->wiphy->max_scan_ie_len = max_probe_length - 24 - 2;
5784
5785        /* Default value; 4 EDCA QOS priorities */
5786        hw->queues = 4;
5787
5788        hw->max_listen_interval = IL_CONN_MAX_LISTEN_INTERVAL;
5789
5790        if (il->bands[IEEE80211_BAND_2GHZ].n_channels)
5791                il->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
5792                    &il->bands[IEEE80211_BAND_2GHZ];
5793        if (il->bands[IEEE80211_BAND_5GHZ].n_channels)
5794                il->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
5795                    &il->bands[IEEE80211_BAND_5GHZ];
5796
5797        il_leds_init(il);
5798
5799        ret = ieee80211_register_hw(il->hw);
5800        if (ret) {
5801                IL_ERR("Failed to register hw (error %d)\n", ret);
5802                return ret;
5803        }
5804        il->mac80211_registered = 1;
5805
5806        return 0;
5807}
5808
5809int
5810il4965_mac_start(struct ieee80211_hw *hw)
5811{
5812        struct il_priv *il = hw->priv;
5813        int ret;
5814
5815        D_MAC80211("enter\n");
5816
5817        /* we should be verifying the device is ready to be opened */
5818        mutex_lock(&il->mutex);
5819        ret = __il4965_up(il);
5820        mutex_unlock(&il->mutex);
5821
5822        if (ret)
5823                return ret;
5824
5825        if (il_is_rfkill(il))
5826                goto out;
5827
5828        D_INFO("Start UP work done.\n");
5829
5830        /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
5831         * mac80211 will not be run successfully. */
5832        ret = wait_event_timeout(il->wait_command_queue,
5833                                 test_bit(S_READY, &il->status),
5834                                 UCODE_READY_TIMEOUT);
5835        if (!ret) {
5836                if (!test_bit(S_READY, &il->status)) {
5837                        IL_ERR("START_ALIVE timeout after %dms.\n",
5838                                jiffies_to_msecs(UCODE_READY_TIMEOUT));
5839                        return -ETIMEDOUT;
5840                }
5841        }
5842
5843        il4965_led_enable(il);
5844
5845out:
5846        il->is_open = 1;
5847        D_MAC80211("leave\n");
5848        return 0;
5849}
5850
5851void
5852il4965_mac_stop(struct ieee80211_hw *hw)
5853{
5854        struct il_priv *il = hw->priv;
5855
5856        D_MAC80211("enter\n");
5857
5858        if (!il->is_open)
5859                return;
5860
5861        il->is_open = 0;
5862
5863        il4965_down(il);
5864
5865        flush_workqueue(il->workqueue);
5866
5867        /* User space software may expect getting rfkill changes
5868         * even if interface is down */
5869        _il_wr(il, CSR_INT, 0xFFFFFFFF);
5870        il_enable_rfkill_int(il);
5871
5872        D_MAC80211("leave\n");
5873}
5874
5875void
5876il4965_mac_tx(struct ieee80211_hw *hw,
5877              struct ieee80211_tx_control *control,
5878              struct sk_buff *skb)
5879{
5880        struct il_priv *il = hw->priv;
5881
5882        D_MACDUMP("enter\n");
5883
5884        D_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
5885             ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
5886
5887        if (il4965_tx_skb(il, control->sta, skb))
5888                dev_kfree_skb_any(skb);
5889
5890        D_MACDUMP("leave\n");
5891}
5892
5893void
5894il4965_mac_update_tkip_key(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
5895                           struct ieee80211_key_conf *keyconf,
5896                           struct ieee80211_sta *sta, u32 iv32, u16 * phase1key)
5897{
5898        struct il_priv *il = hw->priv;
5899
5900        D_MAC80211("enter\n");
5901
5902        il4965_update_tkip_key(il, keyconf, sta, iv32, phase1key);
5903
5904        D_MAC80211("leave\n");
5905}
5906
5907int
5908il4965_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
5909                   struct ieee80211_vif *vif, struct ieee80211_sta *sta,
5910                   struct ieee80211_key_conf *key)
5911{
5912        struct il_priv *il = hw->priv;
5913        int ret;
5914        u8 sta_id;
5915        bool is_default_wep_key = false;
5916
5917        D_MAC80211("enter\n");
5918
5919        if (il->cfg->mod_params->sw_crypto) {
5920                D_MAC80211("leave - hwcrypto disabled\n");
5921                return -EOPNOTSUPP;
5922        }
5923
5924        /*
5925         * To support IBSS RSN, don't program group keys in IBSS, the
5926         * hardware will then not attempt to decrypt the frames.
5927         */
5928        if (vif->type == NL80211_IFTYPE_ADHOC &&
5929            !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
5930                D_MAC80211("leave - ad-hoc group key\n");
5931                return -EOPNOTSUPP;
5932        }
5933
5934        sta_id = il_sta_id_or_broadcast(il, sta);
5935        if (sta_id == IL_INVALID_STATION)
5936                return -EINVAL;
5937
5938        mutex_lock(&il->mutex);
5939        il_scan_cancel_timeout(il, 100);
5940
5941        /*
5942         * If we are getting WEP group key and we didn't receive any key mapping
5943         * so far, we are in legacy wep mode (group key only), otherwise we are
5944         * in 1X mode.
5945         * In legacy wep mode, we use another host command to the uCode.
5946         */
5947        if ((key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
5948             key->cipher == WLAN_CIPHER_SUITE_WEP104) && !sta) {
5949                if (cmd == SET_KEY)
5950                        is_default_wep_key = !il->_4965.key_mapping_keys;
5951                else
5952                        is_default_wep_key =
5953                            (key->hw_key_idx == HW_KEY_DEFAULT);
5954        }
5955
5956        switch (cmd) {
5957        case SET_KEY:
5958                if (is_default_wep_key)
5959                        ret = il4965_set_default_wep_key(il, key);
5960                else
5961                        ret = il4965_set_dynamic_key(il, key, sta_id);
5962
5963                D_MAC80211("enable hwcrypto key\n");
5964                break;
5965        case DISABLE_KEY:
5966                if (is_default_wep_key)
5967                        ret = il4965_remove_default_wep_key(il, key);
5968                else
5969                        ret = il4965_remove_dynamic_key(il, key, sta_id);
5970
5971                D_MAC80211("disable hwcrypto key\n");
5972                break;
5973        default:
5974                ret = -EINVAL;
5975        }
5976
5977        mutex_unlock(&il->mutex);
5978        D_MAC80211("leave\n");
5979
5980        return ret;
5981}
5982
5983int
5984il4965_mac_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
5985                        enum ieee80211_ampdu_mlme_action action,
5986                        struct ieee80211_sta *sta, u16 tid, u16 * ssn,
5987                        u8 buf_size, bool amsdu)
5988{
5989        struct il_priv *il = hw->priv;
5990        int ret = -EINVAL;
5991
5992        D_HT("A-MPDU action on addr %pM tid %d\n", sta->addr, tid);
5993
5994        if (!(il->cfg->sku & IL_SKU_N))
5995                return -EACCES;
5996
5997        mutex_lock(&il->mutex);
5998
5999        switch (action) {
6000        case IEEE80211_AMPDU_RX_START:
6001                D_HT("start Rx\n");
6002                ret = il4965_sta_rx_agg_start(il, sta, tid, *ssn);
6003                break;
6004        case IEEE80211_AMPDU_RX_STOP:
6005                D_HT("stop Rx\n");
6006                ret = il4965_sta_rx_agg_stop(il, sta, tid);
6007                if (test_bit(S_EXIT_PENDING, &il->status))
6008                        ret = 0;
6009                break;
6010        case IEEE80211_AMPDU_TX_START:
6011                D_HT("start Tx\n");
6012                ret = il4965_tx_agg_start(il, vif, sta, tid, ssn);
6013                break;
6014        case IEEE80211_AMPDU_TX_STOP_CONT:
6015        case IEEE80211_AMPDU_TX_STOP_FLUSH:
6016        case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
6017                D_HT("stop Tx\n");
6018                ret = il4965_tx_agg_stop(il, vif, sta, tid);
6019                if (test_bit(S_EXIT_PENDING, &il->status))
6020                        ret = 0;
6021                break;
6022        case IEEE80211_AMPDU_TX_OPERATIONAL:
6023                ret = 0;
6024                break;
6025        }
6026        mutex_unlock(&il->mutex);
6027
6028        return ret;
6029}
6030
6031int
6032il4965_mac_sta_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
6033                   struct ieee80211_sta *sta)
6034{
6035        struct il_priv *il = hw->priv;
6036        struct il_station_priv *sta_priv = (void *)sta->drv_priv;
6037        bool is_ap = vif->type == NL80211_IFTYPE_STATION;
6038        int ret;
6039        u8 sta_id;
6040
6041        D_INFO("received request to add station %pM\n", sta->addr);
6042        mutex_lock(&il->mutex);
6043        D_INFO("proceeding to add station %pM\n", sta->addr);
6044        sta_priv->common.sta_id = IL_INVALID_STATION;
6045
6046        atomic_set(&sta_priv->pending_frames, 0);
6047
6048        ret =
6049            il_add_station_common(il, sta->addr, is_ap, sta, &sta_id);
6050        if (ret) {
6051                IL_ERR("Unable to add station %pM (%d)\n", sta->addr, ret);
6052                /* Should we return success if return code is EEXIST ? */
6053                mutex_unlock(&il->mutex);
6054                return ret;
6055        }
6056
6057        sta_priv->common.sta_id = sta_id;
6058
6059        /* Initialize rate scaling */
6060        D_INFO("Initializing rate scaling for station %pM\n", sta->addr);
6061        il4965_rs_rate_init(il, sta, sta_id);
6062        mutex_unlock(&il->mutex);
6063
6064        return 0;
6065}
6066
6067void
6068il4965_mac_channel_switch(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
6069                          struct ieee80211_channel_switch *ch_switch)
6070{
6071        struct il_priv *il = hw->priv;
6072        const struct il_channel_info *ch_info;
6073        struct ieee80211_conf *conf = &hw->conf;
6074        struct ieee80211_channel *channel = ch_switch->chandef.chan;
6075        struct il_ht_config *ht_conf = &il->current_ht_config;
6076        u16 ch;
6077
6078        D_MAC80211("enter\n");
6079
6080        mutex_lock(&il->mutex);
6081
6082        if (il_is_rfkill(il))
6083                goto out;
6084
6085        if (test_bit(S_EXIT_PENDING, &il->status) ||
6086            test_bit(S_SCANNING, &il->status) ||
6087            test_bit(S_CHANNEL_SWITCH_PENDING, &il->status))
6088                goto out;
6089
6090        if (!il_is_associated(il))
6091                goto out;
6092
6093        if (!il->ops->set_channel_switch)
6094                goto out;
6095
6096        ch = channel->hw_value;
6097        if (le16_to_cpu(il->active.channel) == ch)
6098                goto out;
6099
6100        ch_info = il_get_channel_info(il, channel->band, ch);
6101        if (!il_is_channel_valid(ch_info)) {
6102                D_MAC80211("invalid channel\n");
6103                goto out;
6104        }
6105
6106        spin_lock_irq(&il->lock);
6107
6108        il->current_ht_config.smps = conf->smps_mode;
6109
6110        /* Configure HT40 channels */
6111        switch (cfg80211_get_chandef_type(&ch_switch->chandef)) {
6112        case NL80211_CHAN_NO_HT:
6113        case NL80211_CHAN_HT20:
6114                il->ht.is_40mhz = false;
6115                il->ht.extension_chan_offset = IEEE80211_HT_PARAM_CHA_SEC_NONE;
6116                break;
6117        case NL80211_CHAN_HT40MINUS:
6118                il->ht.extension_chan_offset = IEEE80211_HT_PARAM_CHA_SEC_BELOW;
6119                il->ht.is_40mhz = true;
6120                break;
6121        case NL80211_CHAN_HT40PLUS:
6122                il->ht.extension_chan_offset = IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
6123                il->ht.is_40mhz = true;
6124                break;
6125        }
6126
6127        if ((le16_to_cpu(il->staging.channel) != ch))
6128                il->staging.flags = 0;
6129
6130        il_set_rxon_channel(il, channel);
6131        il_set_rxon_ht(il, ht_conf);
6132        il_set_flags_for_band(il, channel->band, il->vif);
6133
6134        spin_unlock_irq(&il->lock);
6135
6136        il_set_rate(il);
6137        /*
6138         * at this point, staging_rxon has the
6139         * configuration for channel switch
6140         */
6141        set_bit(S_CHANNEL_SWITCH_PENDING, &il->status);
6142        il->switch_channel = cpu_to_le16(ch);
6143        if (il->ops->set_channel_switch(il, ch_switch)) {
6144                clear_bit(S_CHANNEL_SWITCH_PENDING, &il->status);
6145                il->switch_channel = 0;
6146                ieee80211_chswitch_done(il->vif, false);
6147        }
6148
6149out:
6150        mutex_unlock(&il->mutex);
6151        D_MAC80211("leave\n");
6152}
6153
6154void
6155il4965_configure_filter(struct ieee80211_hw *hw, unsigned int changed_flags,
6156                        unsigned int *total_flags, u64 multicast)
6157{
6158        struct il_priv *il = hw->priv;
6159        __le32 filter_or = 0, filter_nand = 0;
6160
6161#define CHK(test, flag) do { \
6162        if (*total_flags & (test))              \
6163                filter_or |= (flag);            \
6164        else                                    \
6165                filter_nand |= (flag);          \
6166        } while (0)
6167
6168        D_MAC80211("Enter: changed: 0x%x, total: 0x%x\n", changed_flags,
6169                   *total_flags);
6170
6171        CHK(FIF_OTHER_BSS, RXON_FILTER_PROMISC_MSK);
6172        /* Setting _just_ RXON_FILTER_CTL2HOST_MSK causes FH errors */
6173        CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_PROMISC_MSK);
6174        CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK);
6175
6176#undef CHK
6177
6178        mutex_lock(&il->mutex);
6179
6180        il->staging.filter_flags &= ~filter_nand;
6181        il->staging.filter_flags |= filter_or;
6182
6183        /*
6184         * Not committing directly because hardware can perform a scan,
6185         * but we'll eventually commit the filter flags change anyway.
6186         */
6187
6188        mutex_unlock(&il->mutex);
6189
6190        /*
6191         * Receiving all multicast frames is always enabled by the
6192         * default flags setup in il_connection_init_rx_config()
6193         * since we currently do not support programming multicast
6194         * filters into the device.
6195         */
6196        *total_flags &=
6197            FIF_OTHER_BSS | FIF_ALLMULTI |
6198            FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
6199}
6200
6201/*****************************************************************************
6202 *
6203 * driver setup and teardown
6204 *
6205 *****************************************************************************/
6206
6207static void
6208il4965_bg_txpower_work(struct work_struct *work)
6209{
6210        struct il_priv *il = container_of(work, struct il_priv,
6211                                          txpower_work);
6212
6213        mutex_lock(&il->mutex);
6214
6215        /* If a scan happened to start before we got here
6216         * then just return; the stats notification will
6217         * kick off another scheduled work to compensate for
6218         * any temperature delta we missed here. */
6219        if (test_bit(S_EXIT_PENDING, &il->status) ||
6220            test_bit(S_SCANNING, &il->status))
6221                goto out;
6222
6223        /* Regardless of if we are associated, we must reconfigure the
6224         * TX power since frames can be sent on non-radar channels while
6225         * not associated */
6226        il->ops->send_tx_power(il);
6227
6228        /* Update last_temperature to keep is_calib_needed from running
6229         * when it isn't needed... */
6230        il->last_temperature = il->temperature;
6231out:
6232        mutex_unlock(&il->mutex);
6233}
6234
6235static void
6236il4965_setup_deferred_work(struct il_priv *il)
6237{
6238        il->workqueue = create_singlethread_workqueue(DRV_NAME);
6239
6240        init_waitqueue_head(&il->wait_command_queue);
6241
6242        INIT_WORK(&il->restart, il4965_bg_restart);
6243        INIT_WORK(&il->rx_replenish, il4965_bg_rx_replenish);
6244        INIT_WORK(&il->run_time_calib_work, il4965_bg_run_time_calib_work);
6245        INIT_DELAYED_WORK(&il->init_alive_start, il4965_bg_init_alive_start);
6246        INIT_DELAYED_WORK(&il->alive_start, il4965_bg_alive_start);
6247
6248        il_setup_scan_deferred_work(il);
6249
6250        INIT_WORK(&il->txpower_work, il4965_bg_txpower_work);
6251
6252        setup_timer(&il->stats_periodic, il4965_bg_stats_periodic,
6253                    (unsigned long)il);
6254
6255        setup_timer(&il->watchdog, il_bg_watchdog, (unsigned long)il);
6256
6257        tasklet_init(&il->irq_tasklet,
6258                     (void (*)(unsigned long))il4965_irq_tasklet,
6259                     (unsigned long)il);
6260}
6261
6262static void
6263il4965_cancel_deferred_work(struct il_priv *il)
6264{
6265        cancel_work_sync(&il->txpower_work);
6266        cancel_delayed_work_sync(&il->init_alive_start);
6267        cancel_delayed_work(&il->alive_start);
6268        cancel_work_sync(&il->run_time_calib_work);
6269
6270        il_cancel_scan_deferred_work(il);
6271
6272        del_timer_sync(&il->stats_periodic);
6273}
6274
6275static void
6276il4965_init_hw_rates(struct il_priv *il, struct ieee80211_rate *rates)
6277{
6278        int i;
6279
6280        for (i = 0; i < RATE_COUNT_LEGACY; i++) {
6281                rates[i].bitrate = il_rates[i].ieee * 5;
6282                rates[i].hw_value = i;  /* Rate scaling will work on idxes */
6283                rates[i].hw_value_short = i;
6284                rates[i].flags = 0;
6285                if ((i >= IL_FIRST_CCK_RATE) && (i <= IL_LAST_CCK_RATE)) {
6286                        /*
6287                         * If CCK != 1M then set short preamble rate flag.
6288                         */
6289                        rates[i].flags |=
6290                            (il_rates[i].plcp ==
6291                             RATE_1M_PLCP) ? 0 : IEEE80211_RATE_SHORT_PREAMBLE;
6292                }
6293        }
6294}
6295
6296/*
6297 * Acquire il->lock before calling this function !
6298 */
6299void
6300il4965_set_wr_ptrs(struct il_priv *il, int txq_id, u32 idx)
6301{
6302        il_wr(il, HBUS_TARG_WRPTR, (idx & 0xff) | (txq_id << 8));
6303        il_wr_prph(il, IL49_SCD_QUEUE_RDPTR(txq_id), idx);
6304}
6305
6306void
6307il4965_tx_queue_set_status(struct il_priv *il, struct il_tx_queue *txq,
6308                           int tx_fifo_id, int scd_retry)
6309{
6310        int txq_id = txq->q.id;
6311
6312        /* Find out whether to activate Tx queue */
6313        int active = test_bit(txq_id, &il->txq_ctx_active_msk) ? 1 : 0;
6314
6315        /* Set up and activate */
6316        il_wr_prph(il, IL49_SCD_QUEUE_STATUS_BITS(txq_id),
6317                   (active << IL49_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
6318                   (tx_fifo_id << IL49_SCD_QUEUE_STTS_REG_POS_TXF) |
6319                   (scd_retry << IL49_SCD_QUEUE_STTS_REG_POS_WSL) |
6320                   (scd_retry << IL49_SCD_QUEUE_STTS_REG_POS_SCD_ACK) |
6321                   IL49_SCD_QUEUE_STTS_REG_MSK);
6322
6323        txq->sched_retry = scd_retry;
6324
6325        D_INFO("%s %s Queue %d on AC %d\n", active ? "Activate" : "Deactivate",
6326               scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
6327}
6328
6329static const struct ieee80211_ops il4965_mac_ops = {
6330        .tx = il4965_mac_tx,
6331        .start = il4965_mac_start,
6332        .stop = il4965_mac_stop,
6333        .add_interface = il_mac_add_interface,
6334        .remove_interface = il_mac_remove_interface,
6335        .change_interface = il_mac_change_interface,
6336        .config = il_mac_config,
6337        .configure_filter = il4965_configure_filter,
6338        .set_key = il4965_mac_set_key,
6339        .update_tkip_key = il4965_mac_update_tkip_key,
6340        .conf_tx = il_mac_conf_tx,
6341        .reset_tsf = il_mac_reset_tsf,
6342        .bss_info_changed = il_mac_bss_info_changed,
6343        .ampdu_action = il4965_mac_ampdu_action,
6344        .hw_scan = il_mac_hw_scan,
6345        .sta_add = il4965_mac_sta_add,
6346        .sta_remove = il_mac_sta_remove,
6347        .channel_switch = il4965_mac_channel_switch,
6348        .tx_last_beacon = il_mac_tx_last_beacon,
6349        .flush = il_mac_flush,
6350};
6351
6352static int
6353il4965_init_drv(struct il_priv *il)
6354{
6355        int ret;
6356
6357        spin_lock_init(&il->sta_lock);
6358        spin_lock_init(&il->hcmd_lock);
6359
6360        INIT_LIST_HEAD(&il->free_frames);
6361
6362        mutex_init(&il->mutex);
6363
6364        il->ieee_channels = NULL;
6365        il->ieee_rates = NULL;
6366        il->band = IEEE80211_BAND_2GHZ;
6367
6368        il->iw_mode = NL80211_IFTYPE_STATION;
6369        il->current_ht_config.smps = IEEE80211_SMPS_STATIC;
6370        il->missed_beacon_threshold = IL_MISSED_BEACON_THRESHOLD_DEF;
6371
6372        /* initialize force reset */
6373        il->force_reset.reset_duration = IL_DELAY_NEXT_FORCE_FW_RELOAD;
6374
6375        /* Choose which receivers/antennas to use */
6376        if (il->ops->set_rxon_chain)
6377                il->ops->set_rxon_chain(il);
6378
6379        il_init_scan_params(il);
6380
6381        ret = il_init_channel_map(il);
6382        if (ret) {
6383                IL_ERR("initializing regulatory failed: %d\n", ret);
6384                goto err;
6385        }
6386
6387        ret = il_init_geos(il);
6388        if (ret) {
6389                IL_ERR("initializing geos failed: %d\n", ret);
6390                goto err_free_channel_map;
6391        }
6392        il4965_init_hw_rates(il, il->ieee_rates);
6393
6394        return 0;
6395
6396err_free_channel_map:
6397        il_free_channel_map(il);
6398err:
6399        return ret;
6400}
6401
6402static void
6403il4965_uninit_drv(struct il_priv *il)
6404{
6405        il_free_geos(il);
6406        il_free_channel_map(il);
6407        kfree(il->scan_cmd);
6408}
6409
6410static void
6411il4965_hw_detect(struct il_priv *il)
6412{
6413        il->hw_rev = _il_rd(il, CSR_HW_REV);
6414        il->hw_wa_rev = _il_rd(il, CSR_HW_REV_WA_REG);
6415        il->rev_id = il->pci_dev->revision;
6416        D_INFO("HW Revision ID = 0x%X\n", il->rev_id);
6417}
6418
6419static struct il_sensitivity_ranges il4965_sensitivity = {
6420        .min_nrg_cck = 97,
6421        .max_nrg_cck = 0,       /* not used, set to 0 */
6422
6423        .auto_corr_min_ofdm = 85,
6424        .auto_corr_min_ofdm_mrc = 170,
6425        .auto_corr_min_ofdm_x1 = 105,
6426        .auto_corr_min_ofdm_mrc_x1 = 220,
6427
6428        .auto_corr_max_ofdm = 120,
6429        .auto_corr_max_ofdm_mrc = 210,
6430        .auto_corr_max_ofdm_x1 = 140,
6431        .auto_corr_max_ofdm_mrc_x1 = 270,
6432
6433        .auto_corr_min_cck = 125,
6434        .auto_corr_max_cck = 200,
6435        .auto_corr_min_cck_mrc = 200,
6436        .auto_corr_max_cck_mrc = 400,
6437
6438        .nrg_th_cck = 100,
6439        .nrg_th_ofdm = 100,
6440
6441        .barker_corr_th_min = 190,
6442        .barker_corr_th_min_mrc = 390,
6443        .nrg_th_cca = 62,
6444};
6445
6446static void
6447il4965_set_hw_params(struct il_priv *il)
6448{
6449        il->hw_params.bcast_id = IL4965_BROADCAST_ID;
6450        il->hw_params.max_rxq_size = RX_QUEUE_SIZE;
6451        il->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
6452        if (il->cfg->mod_params->amsdu_size_8K)
6453                il->hw_params.rx_page_order = get_order(IL_RX_BUF_SIZE_8K);
6454        else
6455                il->hw_params.rx_page_order = get_order(IL_RX_BUF_SIZE_4K);
6456
6457        il->hw_params.max_beacon_itrvl = IL_MAX_UCODE_BEACON_INTERVAL;
6458
6459        if (il->cfg->mod_params->disable_11n)
6460                il->cfg->sku &= ~IL_SKU_N;
6461
6462        if (il->cfg->mod_params->num_of_queues >= IL_MIN_NUM_QUEUES &&
6463            il->cfg->mod_params->num_of_queues <= IL49_NUM_QUEUES)
6464                il->cfg->num_of_queues =
6465                    il->cfg->mod_params->num_of_queues;
6466
6467        il->hw_params.max_txq_num = il->cfg->num_of_queues;
6468        il->hw_params.dma_chnl_num = FH49_TCSR_CHNL_NUM;
6469        il->hw_params.scd_bc_tbls_size =
6470            il->cfg->num_of_queues *
6471            sizeof(struct il4965_scd_bc_tbl);
6472
6473        il->hw_params.tfd_size = sizeof(struct il_tfd);
6474        il->hw_params.max_stations = IL4965_STATION_COUNT;
6475        il->hw_params.max_data_size = IL49_RTC_DATA_SIZE;
6476        il->hw_params.max_inst_size = IL49_RTC_INST_SIZE;
6477        il->hw_params.max_bsm_size = BSM_SRAM_SIZE;
6478        il->hw_params.ht40_channel = BIT(IEEE80211_BAND_5GHZ);
6479
6480        il->hw_params.rx_wrt_ptr_reg = FH49_RSCSR_CHNL0_WPTR;
6481
6482        il->hw_params.tx_chains_num = il4965_num_of_ant(il->cfg->valid_tx_ant);
6483        il->hw_params.rx_chains_num = il4965_num_of_ant(il->cfg->valid_rx_ant);
6484        il->hw_params.valid_tx_ant = il->cfg->valid_tx_ant;
6485        il->hw_params.valid_rx_ant = il->cfg->valid_rx_ant;
6486
6487        il->hw_params.ct_kill_threshold =
6488           CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD_LEGACY);
6489
6490        il->hw_params.sens = &il4965_sensitivity;
6491        il->hw_params.beacon_time_tsf_bits = IL4965_EXT_BEACON_TIME_POS;
6492}
6493
6494static int
6495il4965_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
6496{
6497        int err = 0;
6498        struct il_priv *il;
6499        struct ieee80211_hw *hw;
6500        struct il_cfg *cfg = (struct il_cfg *)(ent->driver_data);
6501        unsigned long flags;
6502        u16 pci_cmd;
6503
6504        /************************
6505         * 1. Allocating HW data
6506         ************************/
6507
6508        hw = ieee80211_alloc_hw(sizeof(struct il_priv), &il4965_mac_ops);
6509        if (!hw) {
6510                err = -ENOMEM;
6511                goto out;
6512        }
6513        il = hw->priv;
6514        il->hw = hw;
6515        SET_IEEE80211_DEV(hw, &pdev->dev);
6516
6517        D_INFO("*** LOAD DRIVER ***\n");
6518        il->cfg = cfg;
6519        il->ops = &il4965_ops;
6520#ifdef CONFIG_IWLEGACY_DEBUGFS
6521        il->debugfs_ops = &il4965_debugfs_ops;
6522#endif
6523        il->pci_dev = pdev;
6524        il->inta_mask = CSR_INI_SET_MASK;
6525
6526        /**************************
6527         * 2. Initializing PCI bus
6528         **************************/
6529        pci_disable_link_state(pdev,
6530                               PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
6531                               PCIE_LINK_STATE_CLKPM);
6532
6533        if (pci_enable_device(pdev)) {
6534                err = -ENODEV;
6535                goto out_ieee80211_free_hw;
6536        }
6537
6538        pci_set_master(pdev);
6539
6540        err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
6541        if (!err)
6542                err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
6543        if (err) {
6544                err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6545                if (!err)
6546                        err =
6547                            pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
6548                /* both attempts failed: */
6549                if (err) {
6550                        IL_WARN("No suitable DMA available.\n");
6551                        goto out_pci_disable_device;
6552                }
6553        }
6554
6555        err = pci_request_regions(pdev, DRV_NAME);
6556        if (err)
6557                goto out_pci_disable_device;
6558
6559        pci_set_drvdata(pdev, il);
6560
6561        /***********************
6562         * 3. Read REV register
6563         ***********************/
6564        il->hw_base = pci_ioremap_bar(pdev, 0);
6565        if (!il->hw_base) {
6566                err = -ENODEV;
6567                goto out_pci_release_regions;
6568        }
6569
6570        D_INFO("pci_resource_len = 0x%08llx\n",
6571               (unsigned long long)pci_resource_len(pdev, 0));
6572        D_INFO("pci_resource_base = %p\n", il->hw_base);
6573
6574        /* these spin locks will be used in apm_ops.init and EEPROM access
6575         * we should init now
6576         */
6577        spin_lock_init(&il->reg_lock);
6578        spin_lock_init(&il->lock);
6579
6580        /*
6581         * stop and reset the on-board processor just in case it is in a
6582         * strange state ... like being left stranded by a primary kernel
6583         * and this is now the kdump kernel trying to start up
6584         */
6585        _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
6586
6587        il4965_hw_detect(il);
6588        IL_INFO("Detected %s, REV=0x%X\n", il->cfg->name, il->hw_rev);
6589
6590        /* We disable the RETRY_TIMEOUT register (0x41) to keep
6591         * PCI Tx retries from interfering with C3 CPU state */
6592        pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
6593
6594        il4965_prepare_card_hw(il);
6595        if (!il->hw_ready) {
6596                IL_WARN("Failed, HW not ready\n");
6597                err = -EIO;
6598                goto out_iounmap;
6599        }
6600
6601        /*****************
6602         * 4. Read EEPROM
6603         *****************/
6604        /* Read the EEPROM */
6605        err = il_eeprom_init(il);
6606        if (err) {
6607                IL_ERR("Unable to init EEPROM\n");
6608                goto out_iounmap;
6609        }
6610        err = il4965_eeprom_check_version(il);
6611        if (err)
6612                goto out_free_eeprom;
6613
6614        /* extract MAC Address */
6615        il4965_eeprom_get_mac(il, il->addresses[0].addr);
6616        D_INFO("MAC address: %pM\n", il->addresses[0].addr);
6617        il->hw->wiphy->addresses = il->addresses;
6618        il->hw->wiphy->n_addresses = 1;
6619
6620        /************************
6621         * 5. Setup HW constants
6622         ************************/
6623        il4965_set_hw_params(il);
6624
6625        /*******************
6626         * 6. Setup il
6627         *******************/
6628
6629        err = il4965_init_drv(il);
6630        if (err)
6631                goto out_free_eeprom;
6632        /* At this point both hw and il are initialized. */
6633
6634        /********************
6635         * 7. Setup services
6636         ********************/
6637        spin_lock_irqsave(&il->lock, flags);
6638        il_disable_interrupts(il);
6639        spin_unlock_irqrestore(&il->lock, flags);
6640
6641        pci_enable_msi(il->pci_dev);
6642
6643        err = request_irq(il->pci_dev->irq, il_isr, IRQF_SHARED, DRV_NAME, il);
6644        if (err) {
6645                IL_ERR("Error allocating IRQ %d\n", il->pci_dev->irq);
6646                goto out_disable_msi;
6647        }
6648
6649        il4965_setup_deferred_work(il);
6650        il4965_setup_handlers(il);
6651
6652        /*********************************************
6653         * 8. Enable interrupts and read RFKILL state
6654         *********************************************/
6655
6656        /* enable rfkill interrupt: hw bug w/a */
6657        pci_read_config_word(il->pci_dev, PCI_COMMAND, &pci_cmd);
6658        if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
6659                pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
6660                pci_write_config_word(il->pci_dev, PCI_COMMAND, pci_cmd);
6661        }
6662
6663        il_enable_rfkill_int(il);
6664
6665        /* If platform's RF_KILL switch is NOT set to KILL */
6666        if (_il_rd(il, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
6667                clear_bit(S_RFKILL, &il->status);
6668        else
6669                set_bit(S_RFKILL, &il->status);
6670
6671        wiphy_rfkill_set_hw_state(il->hw->wiphy,
6672                                  test_bit(S_RFKILL, &il->status));
6673
6674        il_power_initialize(il);
6675
6676        init_completion(&il->_4965.firmware_loading_complete);
6677
6678        err = il4965_request_firmware(il, true);
6679        if (err)
6680                goto out_destroy_workqueue;
6681
6682        return 0;
6683
6684out_destroy_workqueue:
6685        destroy_workqueue(il->workqueue);
6686        il->workqueue = NULL;
6687        free_irq(il->pci_dev->irq, il);
6688out_disable_msi:
6689        pci_disable_msi(il->pci_dev);
6690        il4965_uninit_drv(il);
6691out_free_eeprom:
6692        il_eeprom_free(il);
6693out_iounmap:
6694        iounmap(il->hw_base);
6695out_pci_release_regions:
6696        pci_release_regions(pdev);
6697out_pci_disable_device:
6698        pci_disable_device(pdev);
6699out_ieee80211_free_hw:
6700        ieee80211_free_hw(il->hw);
6701out:
6702        return err;
6703}
6704
6705static void
6706il4965_pci_remove(struct pci_dev *pdev)
6707{
6708        struct il_priv *il = pci_get_drvdata(pdev);
6709        unsigned long flags;
6710
6711        if (!il)
6712                return;
6713
6714        wait_for_completion(&il->_4965.firmware_loading_complete);
6715
6716        D_INFO("*** UNLOAD DRIVER ***\n");
6717
6718        il_dbgfs_unregister(il);
6719        sysfs_remove_group(&pdev->dev.kobj, &il_attribute_group);
6720
6721        /* ieee80211_unregister_hw call wil cause il_mac_stop to
6722         * to be called and il4965_down since we are removing the device
6723         * we need to set S_EXIT_PENDING bit.
6724         */
6725        set_bit(S_EXIT_PENDING, &il->status);
6726
6727        il_leds_exit(il);
6728
6729        if (il->mac80211_registered) {
6730                ieee80211_unregister_hw(il->hw);
6731                il->mac80211_registered = 0;
6732        } else {
6733                il4965_down(il);
6734        }
6735
6736        /*
6737         * Make sure device is reset to low power before unloading driver.
6738         * This may be redundant with il4965_down(), but there are paths to
6739         * run il4965_down() without calling apm_ops.stop(), and there are
6740         * paths to avoid running il4965_down() at all before leaving driver.
6741         * This (inexpensive) call *makes sure* device is reset.
6742         */
6743        il_apm_stop(il);
6744
6745        /* make sure we flush any pending irq or
6746         * tasklet for the driver
6747         */
6748        spin_lock_irqsave(&il->lock, flags);
6749        il_disable_interrupts(il);
6750        spin_unlock_irqrestore(&il->lock, flags);
6751
6752        il4965_synchronize_irq(il);
6753
6754        il4965_dealloc_ucode_pci(il);
6755
6756        if (il->rxq.bd)
6757                il4965_rx_queue_free(il, &il->rxq);
6758        il4965_hw_txq_ctx_free(il);
6759
6760        il_eeprom_free(il);
6761
6762        /*netif_stop_queue(dev); */
6763        flush_workqueue(il->workqueue);
6764
6765        /* ieee80211_unregister_hw calls il_mac_stop, which flushes
6766         * il->workqueue... so we can't take down the workqueue
6767         * until now... */
6768        destroy_workqueue(il->workqueue);
6769        il->workqueue = NULL;
6770
6771        free_irq(il->pci_dev->irq, il);
6772        pci_disable_msi(il->pci_dev);
6773        iounmap(il->hw_base);
6774        pci_release_regions(pdev);
6775        pci_disable_device(pdev);
6776
6777        il4965_uninit_drv(il);
6778
6779        dev_kfree_skb(il->beacon_skb);
6780
6781        ieee80211_free_hw(il->hw);
6782}
6783
6784/*
6785 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
6786 * must be called under il->lock and mac access
6787 */
6788void
6789il4965_txq_set_sched(struct il_priv *il, u32 mask)
6790{
6791        il_wr_prph(il, IL49_SCD_TXFACT, mask);
6792}
6793
6794/*****************************************************************************
6795 *
6796 * driver and module entry point
6797 *
6798 *****************************************************************************/
6799
6800/* Hardware specific file defines the PCI IDs table for that hardware module */
6801static const struct pci_device_id il4965_hw_card_ids[] = {
6802        {IL_PCI_DEVICE(0x4229, PCI_ANY_ID, il4965_cfg)},
6803        {IL_PCI_DEVICE(0x4230, PCI_ANY_ID, il4965_cfg)},
6804        {0}
6805};
6806MODULE_DEVICE_TABLE(pci, il4965_hw_card_ids);
6807
6808static struct pci_driver il4965_driver = {
6809        .name = DRV_NAME,
6810        .id_table = il4965_hw_card_ids,
6811        .probe = il4965_pci_probe,
6812        .remove = il4965_pci_remove,
6813        .driver.pm = IL_LEGACY_PM_OPS,
6814};
6815
6816static int __init
6817il4965_init(void)
6818{
6819
6820        int ret;
6821        pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
6822        pr_info(DRV_COPYRIGHT "\n");
6823
6824        ret = il4965_rate_control_register();
6825        if (ret) {
6826                pr_err("Unable to register rate control algorithm: %d\n", ret);
6827                return ret;
6828        }
6829
6830        ret = pci_register_driver(&il4965_driver);
6831        if (ret) {
6832                pr_err("Unable to initialize PCI module\n");
6833                goto error_register;
6834        }
6835
6836        return ret;
6837
6838error_register:
6839        il4965_rate_control_unregister();
6840        return ret;
6841}
6842
6843static void __exit
6844il4965_exit(void)
6845{
6846        pci_unregister_driver(&il4965_driver);
6847        il4965_rate_control_unregister();
6848}
6849
6850module_exit(il4965_exit);
6851module_init(il4965_init);
6852
6853#ifdef CONFIG_IWLEGACY_DEBUG
6854module_param_named(debug, il_debug_level, uint, S_IRUGO | S_IWUSR);
6855MODULE_PARM_DESC(debug, "debug output mask");
6856#endif
6857
6858module_param_named(swcrypto, il4965_mod_params.sw_crypto, int, S_IRUGO);
6859MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
6860module_param_named(queues_num, il4965_mod_params.num_of_queues, int, S_IRUGO);
6861MODULE_PARM_DESC(queues_num, "number of hw queues.");
6862module_param_named(11n_disable, il4965_mod_params.disable_11n, int, S_IRUGO);
6863MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
6864module_param_named(amsdu_size_8K, il4965_mod_params.amsdu_size_8K, int,
6865                   S_IRUGO);
6866MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size (default 0 [disabled])");
6867module_param_named(fw_restart, il4965_mod_params.restart_fw, int, S_IRUGO);
6868MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
6869