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22#ifndef __WLCORE_H__
23#define __WLCORE_H__
24
25#include <linux/platform_device.h>
26
27#include "wlcore_i.h"
28#include "event.h"
29#include "boot.h"
30
31
32#define WLCORE_MAX_TX_DESCRIPTORS 32
33
34
35
36
37
38#define WLCORE_NUM_MAC_ADDRESSES 3
39
40
41#define WLCORE_MAX_TXPWR 25
42
43
44struct wl1271_tx_hw_descr;
45enum wl_rx_buf_align;
46struct wl1271_rx_descriptor;
47
48struct wlcore_ops {
49 int (*setup)(struct wl1271 *wl);
50 int (*identify_chip)(struct wl1271 *wl);
51 int (*identify_fw)(struct wl1271 *wl);
52 int (*boot)(struct wl1271 *wl);
53 int (*plt_init)(struct wl1271 *wl);
54 int (*trigger_cmd)(struct wl1271 *wl, int cmd_box_addr,
55 void *buf, size_t len);
56 int (*ack_event)(struct wl1271 *wl);
57 int (*wait_for_event)(struct wl1271 *wl, enum wlcore_wait_event event,
58 bool *timeout);
59 int (*process_mailbox_events)(struct wl1271 *wl);
60 u32 (*calc_tx_blocks)(struct wl1271 *wl, u32 len, u32 spare_blks);
61 void (*set_tx_desc_blocks)(struct wl1271 *wl,
62 struct wl1271_tx_hw_descr *desc,
63 u32 blks, u32 spare_blks);
64 void (*set_tx_desc_data_len)(struct wl1271 *wl,
65 struct wl1271_tx_hw_descr *desc,
66 struct sk_buff *skb);
67 enum wl_rx_buf_align (*get_rx_buf_align)(struct wl1271 *wl,
68 u32 rx_desc);
69 int (*prepare_read)(struct wl1271 *wl, u32 rx_desc, u32 len);
70 u32 (*get_rx_packet_len)(struct wl1271 *wl, void *rx_data,
71 u32 data_len);
72 int (*tx_delayed_compl)(struct wl1271 *wl);
73 void (*tx_immediate_compl)(struct wl1271 *wl);
74 int (*hw_init)(struct wl1271 *wl);
75 int (*init_vif)(struct wl1271 *wl, struct wl12xx_vif *wlvif);
76 void (*convert_fw_status)(struct wl1271 *wl, void *raw_fw_status,
77 struct wl_fw_status *fw_status);
78 u32 (*sta_get_ap_rate_mask)(struct wl1271 *wl,
79 struct wl12xx_vif *wlvif);
80 int (*get_pg_ver)(struct wl1271 *wl, s8 *ver);
81 int (*get_mac)(struct wl1271 *wl);
82 void (*set_tx_desc_csum)(struct wl1271 *wl,
83 struct wl1271_tx_hw_descr *desc,
84 struct sk_buff *skb);
85 void (*set_rx_csum)(struct wl1271 *wl,
86 struct wl1271_rx_descriptor *desc,
87 struct sk_buff *skb);
88 u32 (*ap_get_mimo_wide_rate_mask)(struct wl1271 *wl,
89 struct wl12xx_vif *wlvif);
90 int (*debugfs_init)(struct wl1271 *wl, struct dentry *rootdir);
91 int (*handle_static_data)(struct wl1271 *wl,
92 struct wl1271_static_data *static_data);
93 int (*scan_start)(struct wl1271 *wl, struct wl12xx_vif *wlvif,
94 struct cfg80211_scan_request *req);
95 int (*scan_stop)(struct wl1271 *wl, struct wl12xx_vif *wlvif);
96 int (*sched_scan_start)(struct wl1271 *wl, struct wl12xx_vif *wlvif,
97 struct cfg80211_sched_scan_request *req,
98 struct ieee80211_scan_ies *ies);
99 void (*sched_scan_stop)(struct wl1271 *wl, struct wl12xx_vif *wlvif);
100 int (*get_spare_blocks)(struct wl1271 *wl, bool is_gem);
101 int (*set_key)(struct wl1271 *wl, enum set_key_cmd cmd,
102 struct ieee80211_vif *vif,
103 struct ieee80211_sta *sta,
104 struct ieee80211_key_conf *key_conf);
105 int (*channel_switch)(struct wl1271 *wl,
106 struct wl12xx_vif *wlvif,
107 struct ieee80211_channel_switch *ch_switch);
108 u32 (*pre_pkt_send)(struct wl1271 *wl, u32 buf_offset, u32 last_len);
109 void (*sta_rc_update)(struct wl1271 *wl, struct wl12xx_vif *wlvif);
110 int (*set_peer_cap)(struct wl1271 *wl,
111 struct ieee80211_sta_ht_cap *ht_cap,
112 bool allow_ht_operation,
113 u32 rate_set, u8 hlid);
114 u32 (*convert_hwaddr)(struct wl1271 *wl, u32 hwaddr);
115 bool (*lnk_high_prio)(struct wl1271 *wl, u8 hlid,
116 struct wl1271_link *lnk);
117 bool (*lnk_low_prio)(struct wl1271 *wl, u8 hlid,
118 struct wl1271_link *lnk);
119 int (*interrupt_notify)(struct wl1271 *wl, bool action);
120 int (*rx_ba_filter)(struct wl1271 *wl, bool action);
121 int (*ap_sleep)(struct wl1271 *wl);
122 int (*smart_config_start)(struct wl1271 *wl, u32 group_bitmap);
123 int (*smart_config_stop)(struct wl1271 *wl);
124 int (*smart_config_set_group_key)(struct wl1271 *wl, u16 group_id,
125 u8 key_len, u8 *key);
126 int (*set_cac)(struct wl1271 *wl, struct wl12xx_vif *wlvif,
127 bool start);
128 int (*dfs_master_restart)(struct wl1271 *wl, struct wl12xx_vif *wlvif);
129};
130
131enum wlcore_partitions {
132 PART_DOWN,
133 PART_WORK,
134 PART_BOOT,
135 PART_DRPW,
136 PART_TOP_PRCM_ELP_SOC,
137 PART_PHY_INIT,
138
139 PART_TABLE_LEN,
140};
141
142struct wlcore_partition {
143 u32 size;
144 u32 start;
145};
146
147struct wlcore_partition_set {
148 struct wlcore_partition mem;
149 struct wlcore_partition reg;
150 struct wlcore_partition mem2;
151 struct wlcore_partition mem3;
152};
153
154enum wlcore_registers {
155
156 REG_ECPU_CONTROL,
157 REG_INTERRUPT_NO_CLEAR,
158 REG_INTERRUPT_ACK,
159 REG_COMMAND_MAILBOX_PTR,
160 REG_EVENT_MAILBOX_PTR,
161 REG_INTERRUPT_TRIG,
162 REG_INTERRUPT_MASK,
163 REG_PC_ON_RECOVERY,
164 REG_CHIP_ID_B,
165 REG_CMD_MBOX_ADDRESS,
166
167
168 REG_SLV_MEM_DATA,
169 REG_SLV_REG_DATA,
170
171
172 REG_RAW_FW_STATUS_ADDR,
173
174 REG_TABLE_LEN,
175};
176
177struct wl1271_stats {
178 void *fw_stats;
179 unsigned long fw_stats_update;
180 size_t fw_stats_len;
181
182 unsigned int retry_count;
183 unsigned int excessive_retries;
184};
185
186struct wl1271 {
187 bool initialized;
188 struct ieee80211_hw *hw;
189 bool mac80211_registered;
190
191 struct device *dev;
192 struct platform_device *pdev;
193
194 void *if_priv;
195
196 struct wl1271_if_operations *if_ops;
197
198 int irq;
199
200 int irq_flags;
201
202 spinlock_t wl_lock;
203
204 enum wlcore_state state;
205 enum wl12xx_fw_type fw_type;
206 bool plt;
207 enum plt_mode plt_mode;
208 u8 fem_manuf;
209 u8 last_vif_count;
210 struct mutex mutex;
211
212 unsigned long flags;
213
214 struct wlcore_partition_set curr_part;
215
216 struct wl1271_chip chip;
217
218 int cmd_box_addr;
219
220 u8 *fw;
221 size_t fw_len;
222 void *nvs;
223 size_t nvs_len;
224
225 s8 hw_pg_ver;
226
227
228 u32 fuse_oui_addr;
229 u32 fuse_nic_addr;
230
231
232 struct mac_address addresses[WLCORE_NUM_MAC_ADDRESSES];
233 int channel;
234 u8 system_hlid;
235
236 unsigned long links_map[BITS_TO_LONGS(WLCORE_MAX_LINKS)];
237 unsigned long roles_map[BITS_TO_LONGS(WL12XX_MAX_ROLES)];
238 unsigned long roc_map[BITS_TO_LONGS(WL12XX_MAX_ROLES)];
239 unsigned long rate_policies_map[
240 BITS_TO_LONGS(WL12XX_MAX_RATE_POLICIES)];
241 unsigned long klv_templates_map[
242 BITS_TO_LONGS(WLCORE_MAX_KLV_TEMPLATES)];
243
244 u8 session_ids[WLCORE_MAX_LINKS];
245
246 struct list_head wlvif_list;
247
248 u8 sta_count;
249 u8 ap_count;
250
251 struct wl1271_acx_mem_map *target_mem_map;
252
253
254 u32 tx_blocks_freed;
255 u32 tx_blocks_available;
256 u32 tx_allocated_blocks;
257 u32 tx_results_count;
258
259
260 u32 tx_pkts_freed[NUM_TX_QUEUES];
261 u32 tx_allocated_pkts[NUM_TX_QUEUES];
262
263
264 u32 tx_packets_count;
265
266
267 s64 time_offset;
268
269
270 int tx_queue_count[NUM_TX_QUEUES];
271 unsigned long queue_stop_reasons[
272 NUM_TX_QUEUES * WLCORE_NUM_MAC_ADDRESSES];
273
274
275 struct sk_buff_head deferred_rx_queue;
276
277
278 struct sk_buff_head deferred_tx_queue;
279
280 struct work_struct tx_work;
281 struct workqueue_struct *freezable_wq;
282
283
284 unsigned long tx_frames_map[BITS_TO_LONGS(WLCORE_MAX_TX_DESCRIPTORS)];
285 struct sk_buff *tx_frames[WLCORE_MAX_TX_DESCRIPTORS];
286 int tx_frames_cnt;
287
288
289 u32 rx_counter;
290
291
292 u8 *aggr_buf;
293 u32 aggr_buf_size;
294
295
296 struct sk_buff *dummy_packet;
297
298
299 struct work_struct netstack_work;
300
301
302 u8 *fwlog;
303
304
305 ssize_t fwlog_size;
306
307
308 u32 fwlog_end;
309
310
311 u32 fw_mem_block_size;
312
313
314 wait_queue_head_t fwlog_waitq;
315
316
317 struct work_struct recovery_work;
318 bool watchdog_recovery;
319
320
321 u32 reg_ch_conf_last[2] __aligned(8);
322
323 u32 reg_ch_conf_pending[2];
324
325
326 void *mbox;
327
328
329 u32 event_mask;
330
331 u32 ap_event_mask;
332
333
334 u32 mbox_size;
335 u32 mbox_ptr[2];
336
337
338 struct wl12xx_vif *scan_wlvif;
339 struct wl1271_scan scan;
340 struct delayed_work scan_complete_work;
341
342 struct ieee80211_vif *roc_vif;
343 struct delayed_work roc_complete_work;
344
345 struct wl12xx_vif *sched_vif;
346
347
348 enum ieee80211_band band;
349
350 struct completion *elp_compl;
351 struct delayed_work elp_work;
352
353
354 int power_level;
355
356 struct wl1271_stats stats;
357
358 __le32 *buffer_32;
359 u32 buffer_cmd;
360 u32 buffer_busyword[WL1271_BUSY_WORD_CNT];
361
362 void *raw_fw_status;
363 struct wl_fw_status *fw_status;
364 struct wl1271_tx_hw_res_if *tx_res_if;
365
366
367 struct wlcore_conf conf;
368
369 bool sg_enabled;
370
371 bool enable_11a;
372
373 int recovery_count;
374
375
376 s8 noise;
377
378
379 struct ieee80211_supported_band bands[WLCORE_NUM_BANDS];
380
381
382
383
384
385 bool wow_enabled;
386 bool irq_wake_enabled;
387
388
389
390
391
392 struct wl1271_link links[WLCORE_MAX_LINKS];
393
394
395 int active_link_count;
396
397
398 unsigned long fw_fast_lnk_map;
399
400
401 unsigned long ap_fw_ps_map;
402
403
404 unsigned long ap_ps_map;
405
406
407 unsigned int quirks;
408
409
410 int ba_rx_session_count;
411
412
413 int ba_rx_session_count_max;
414
415
416 int active_sta_count;
417
418
419 bool ofdm_only_ap;
420
421
422 struct wl12xx_vif *last_wlvif;
423
424
425 struct delayed_work tx_watchdog_work;
426
427 struct wlcore_ops *ops;
428
429 const struct wlcore_partition_set *ptable;
430
431 const int *rtable;
432
433 const char *plt_fw_name;
434 const char *sr_fw_name;
435 const char *mr_fw_name;
436
437 u8 scan_templ_id_2_4;
438 u8 scan_templ_id_5;
439 u8 sched_scan_templ_id_2_4;
440 u8 sched_scan_templ_id_5;
441 u8 max_channels_5;
442
443
444 void *priv;
445
446
447 u32 num_tx_desc;
448
449 u32 num_rx_desc;
450
451 u8 num_links;
452
453 u8 max_ap_stations;
454
455
456 const u8 **band_rate_to_idx;
457
458
459 u8 hw_tx_rate_tbl_size;
460
461
462 u8 hw_min_ht_rate;
463
464
465 struct ieee80211_sta_ht_cap ht_cap[WLCORE_NUM_BANDS];
466
467
468 enum nl80211_dfs_regions dfs_region;
469
470
471 size_t fw_status_len;
472 size_t fw_status_priv_len;
473
474
475 unsigned long rx_filter_enabled[BITS_TO_LONGS(WL1271_MAX_RX_FILTERS)];
476
477
478 size_t static_data_priv_len;
479
480
481 enum nl80211_channel_type channel_type;
482
483
484 struct mutex flush_mutex;
485
486
487 int sleep_auth;
488
489
490 int num_mac_addr;
491
492
493 unsigned int min_sr_fw_ver[NUM_FW_VER];
494
495
496 unsigned int min_mr_fw_ver[NUM_FW_VER];
497
498 struct completion nvs_loading_complete;
499
500
501 const struct ieee80211_iface_combination *iface_combinations;
502 u8 n_iface_combinations;
503
504
505 u32 dynamic_fw_traces;
506};
507
508int wlcore_probe(struct wl1271 *wl, struct platform_device *pdev);
509int wlcore_remove(struct platform_device *pdev);
510struct ieee80211_hw *wlcore_alloc_hw(size_t priv_size, u32 aggr_buf_size,
511 u32 mbox_size);
512int wlcore_free_hw(struct wl1271 *wl);
513int wlcore_set_key(struct wl1271 *wl, enum set_key_cmd cmd,
514 struct ieee80211_vif *vif,
515 struct ieee80211_sta *sta,
516 struct ieee80211_key_conf *key_conf);
517void wlcore_regdomain_config(struct wl1271 *wl);
518void wlcore_update_inconn_sta(struct wl1271 *wl, struct wl12xx_vif *wlvif,
519 struct wl1271_station *wl_sta, bool in_conn);
520
521static inline void
522wlcore_set_ht_cap(struct wl1271 *wl, enum ieee80211_band band,
523 struct ieee80211_sta_ht_cap *ht_cap)
524{
525 memcpy(&wl->ht_cap[band], ht_cap, sizeof(*ht_cap));
526}
527
528
529#define WLCORE_FW_VER_IGNORE -1
530
531static inline void
532wlcore_set_min_fw_ver(struct wl1271 *wl, unsigned int chip,
533 unsigned int iftype_sr, unsigned int major_sr,
534 unsigned int subtype_sr, unsigned int minor_sr,
535 unsigned int iftype_mr, unsigned int major_mr,
536 unsigned int subtype_mr, unsigned int minor_mr)
537{
538 wl->min_sr_fw_ver[FW_VER_CHIP] = chip;
539 wl->min_sr_fw_ver[FW_VER_IF_TYPE] = iftype_sr;
540 wl->min_sr_fw_ver[FW_VER_MAJOR] = major_sr;
541 wl->min_sr_fw_ver[FW_VER_SUBTYPE] = subtype_sr;
542 wl->min_sr_fw_ver[FW_VER_MINOR] = minor_sr;
543
544 wl->min_mr_fw_ver[FW_VER_CHIP] = chip;
545 wl->min_mr_fw_ver[FW_VER_IF_TYPE] = iftype_mr;
546 wl->min_mr_fw_ver[FW_VER_MAJOR] = major_mr;
547 wl->min_mr_fw_ver[FW_VER_SUBTYPE] = subtype_mr;
548 wl->min_mr_fw_ver[FW_VER_MINOR] = minor_mr;
549}
550
551
552#define CHUNK_SIZE 16384
553
554
555
556
557#define WLCORE_QUIRK_END_OF_TRANSACTION BIT(0)
558
559
560#define WLCORE_QUIRK_START_STA_FAILS BIT(1)
561
562
563#define WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN BIT(2)
564
565
566#define WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN BIT(3)
567
568
569#define WLCORE_QUIRK_FWLOG_NOT_IMPLEMENTED BIT(4)
570
571
572#define WLCORE_QUIRK_LEGACY_NVS BIT(5)
573
574
575#define WLCORE_QUIRK_TX_PAD_LAST_FRAME BIT(7)
576
577
578#define WLCORE_QUIRK_TKIP_HEADER_SPACE BIT(8)
579
580
581#define WLCORE_QUIRK_NO_SCHED_SCAN_WHILE_CONN BIT(9)
582
583
584#define WLCORE_QUIRK_DUAL_PROBE_TMPL BIT(10)
585
586
587#define WLCORE_QUIRK_REGDOMAIN_CONF BIT(11)
588
589
590#define WLCORE_QUIRK_AP_ZERO_SESSION_ID BIT(12)
591
592
593#define HW_ACCESS_ELP_CTRL_REG 0x1FFFC
594
595
596#define ELPCTRL_WAKE_UP 0x1
597#define ELPCTRL_WAKE_UP_WLAN_READY 0x5
598#define ELPCTRL_SLEEP 0x0
599
600#define ELPCTRL_WLAN_READY 0x2
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615#define INTR_TRIG_TX_PROC0 BIT(2)
616
617
618
619
620
621
622#define INTR_TRIG_RX_PROC0 BIT(3)
623
624#define INTR_TRIG_DEBUG_ACK BIT(4)
625
626#define INTR_TRIG_STATE_CHANGED BIT(5)
627
628
629
630
631
632
633
634
635#define INTR_TRIG_RX_PROC1 BIT(17)
636
637
638
639
640
641
642#define INTR_TRIG_TX_PROC1 BIT(18)
643
644#define ACX_SLV_SOFT_RESET_BIT BIT(1)
645#define SOFT_RESET_MAX_TIME 1000000
646#define SOFT_RESET_STALL_TIME 1000
647
648#define ECPU_CONTROL_HALT 0x00000101
649
650#define WELP_ARM_COMMAND_VAL 0x4
651
652#endif
653