LXR linux/drivers/scsi/mpt3sas/mpi/mpi2

   1/*
   2 * Copyright (c) 2000-2014 LSI Corporation.
   3 *
   4 *
   5 *          Name:  mpi2_ioc.h
   6 *         Title:  MPI IOC, Port, Event, FW Download, and FW Upload messages
   7 * Creation Date:  October 11, 2006
   8 *
   9 * mpi2_ioc.h Version:  02.00.24
  10 *
  11 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25
  12 *       prefix are for use only on MPI v2.5 products, and must not be used
  13 *       with MPI v2.0 products. Unless otherwise noted, names beginning with
  14 *       MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products.
  15 *
  16 * Version History
  17 * ---------------
  18 *
  19 * Date      Version   Description
  20 * --------  --------  ------------------------------------------------------
  21 * 04-30-07  02.00.00  Corresponds to Fusion-MPT MPI Specification Rev A.
  22 * 06-04-07  02.00.01  In IOCFacts Reply structure, renamed MaxDevices to
  23 *                     MaxTargets.
  24 *                     Added TotalImageSize field to FWDownload Request.
  25 *                     Added reserved words to FWUpload Request.
  26 * 06-26-07  02.00.02  Added IR Configuration Change List Event.
  27 * 08-31-07  02.00.03  Removed SystemReplyQueueDepth field from the IOCInit
  28 *                     request and replaced it with
  29 *                     ReplyDescriptorPostQueueDepth and ReplyFreeQueueDepth.
  30 *                     Replaced the MinReplyQueueDepth field of the IOCFacts
  31 *                     reply with MaxReplyDescriptorPostQueueDepth.
  32 *                     Added MPI2_RDPQ_DEPTH_MIN define to specify the minimum
  33 *                     depth for the Reply Descriptor Post Queue.
  34 *                     Added SASAddress field to Initiator Device Table
  35 *                     Overflow Event data.
  36 * 10-31-07  02.00.04  Added ReasonCode MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING
  37 *                     for SAS Initiator Device Status Change Event data.
  38 *                     Modified Reason Code defines for SAS Topology Change
  39 *                     List Event data, including adding a bit for PHY Vacant
  40 *                     status, and adding a mask for the Reason Code.
  41 *                     Added define for
  42 *                     MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING.
  43 *                     Added define for MPI2_EXT_IMAGE_TYPE_MEGARAID.
  44 * 12-18-07  02.00.05  Added Boot Status defines for the IOCExceptions field of
  45 *                     the IOCFacts Reply.
  46 *                     Removed MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define.
  47 *                     Moved MPI2_VERSION_UNION to mpi2.h.
  48 *                     Changed MPI2_EVENT_NOTIFICATION_REQUEST to use masks
  49 *                     instead of enables, and added SASBroadcastPrimitiveMasks
  50 *                     field.
  51 *                     Added Log Entry Added Event and related structure.
  52 * 02-29-08  02.00.06  Added define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID.
  53 *                     Removed define MPI2_IOCFACTS_PROTOCOL_SMP_TARGET.
  54 *                     Added MaxVolumes and MaxPersistentEntries fields to
  55 *                     IOCFacts reply.
  56 *                     Added ProtocalFlags and IOCCapabilities fields to
  57 *                     MPI2_FW_IMAGE_HEADER.
  58 *                     Removed MPI2_PORTENABLE_FLAGS_ENABLE_SINGLE_PORT.
  59 * 03-03-08  02.00.07  Fixed MPI2_FW_IMAGE_HEADER by changing Reserved26 to
  60 *                     a U16 (from a U32).
  61 *                     Removed extra 's' from EventMasks name.
  62 * 06-27-08  02.00.08  Fixed an offset in a comment.
  63 * 10-02-08  02.00.09  Removed SystemReplyFrameSize from MPI2_IOC_INIT_REQUEST.
  64 *                     Removed CurReplyFrameSize from MPI2_IOC_FACTS_REPLY and
  65 *                     renamed MinReplyFrameSize to ReplyFrameSize.
  66 *                     Added MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX.
  67 *                     Added two new RAIDOperation values for Integrated RAID
  68 *                     Operations Status Event data.
  69 *                     Added four new IR Configuration Change List Event data
  70 *                     ReasonCode values.
  71 *                     Added two new ReasonCode defines for SAS Device Status
  72 *                     Change Event data.
  73 *                     Added three new DiscoveryStatus bits for the SAS
  74 *                     Discovery event data.
  75 *                     Added Multiplexing Status Change bit to the PhyStatus
  76 *                     field of the SAS Topology Change List event data.
  77 *                     Removed define for MPI2_INIT_IMAGE_BOOTFLAGS_XMEMCOPY.
  78 *                     BootFlags are now product-specific.
  79 *                     Added defines for the indivdual signature bytes
  80 *                     for MPI2_INIT_IMAGE_FOOTER.
  81 * 01-19-09  02.00.10  Added MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY define.
  82 *                     Added MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR
  83 *                     define.
  84 *                     Added MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE
  85 *                     define.
  86 *                     Removed MPI2_EVENT_SAS_DISC_DS_SATA_INIT_FAILURE define.
  87 * 05-06-09  02.00.11  Added MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR define.
  88 *                     Added MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX define.
  89 *                     Added two new reason codes for SAS Device Status Change
  90 *                     Event.
  91 *                     Added new event: SAS PHY Counter.
  92 * 07-30-09  02.00.12  Added GPIO Interrupt event define and structure.
  93 *                     Added MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define.
  94 *                     Added new product id family for 2208.
  95 * 10-28-09  02.00.13  Added HostMSIxVectors field to MPI2_IOC_INIT_REQUEST.
  96 *                     Added MaxMSIxVectors field to MPI2_IOC_FACTS_REPLY.
  97 *                     Added MinDevHandle field to MPI2_IOC_FACTS_REPLY.
  98 *                     Added MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY.
  99 *                     Added MPI2_EVENT_HOST_BASED_DISCOVERY_PHY define.
 100 *                     Added MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER define.
 101 *                     Added Host Based Discovery Phy Event data.
 102 *                     Added defines for ProductID Product field
 103 *                     (MPI2_FW_HEADER_PID_).
 104 *                     Modified values for SAS ProductID Family
 105 *                     (MPI2_FW_HEADER_PID_FAMILY_).
 106 * 02-10-10  02.00.14  Added SAS Quiesce Event structure and defines.
 107 *                     Added PowerManagementControl Request structures and
 108 *                     defines.
 109 * 05-12-10  02.00.15  Marked Task Set Full Event as obsolete.
 110 *                     Added MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY define.
 111 * 11-10-10  02.00.16  Added MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC.
 112 * 02-23-11  02.00.17  Added SAS NOTIFY Primitive event, and added
 113 *                     SASNotifyPrimitiveMasks field to
 114 *                     MPI2_EVENT_NOTIFICATION_REQUEST.
 115 *                     Added Temperature Threshold Event.
 116 *                     Added Host Message Event.
 117 *                     Added Send Host Message request and reply.
 118 * 05-25-11  02.00.18  For Extended Image Header, added
 119 *                     MPI2_EXT_IMAGE_TYPE_MIN_PRODUCT_SPECIFIC and
 120 *                     MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC defines.
 121 *                     Deprecated MPI2_EXT_IMAGE_TYPE_MAX define.
 122 * 08-24-11  02.00.19  Added PhysicalPort field to
 123 *                     MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE structure.
 124 *                     Marked MPI2_PM_CONTROL_FEATURE_PCIE_LINK as obsolete.
 125 * 11-18-11  02.00.20  Incorporating additions for MPI v2.5.
 126 * 03-29-12  02.00.21  Added a product specific range to event values.
 127 * 07-26-12  02.00.22  Added MPI2_IOCFACTS_EXCEPT_PARTIAL_MEMORY_FAILURE.
 128 *                     Added ElapsedSeconds field to
 129 *                     MPI2_EVENT_DATA_IR_OPERATION_STATUS.
 130 * 08-19-13  02.00.23  For IOCInit, added MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE
 131 *                      and MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY.
 132 *                      Added MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE.
 133 *                      Added MPI2_FW_DOWNLOAD_ITYPE_PUBLIC_KEY.
 134 *                      Added Encrypted Hash Extended Image.
 135 * 12-05-13  02.00.24  Added MPI25_HASH_IMAGE_TYPE_BIOS.
 136 * --------------------------------------------------------------------------
 137 */
 138
 139#ifndef MPI2_IOC_H
 140#define MPI2_IOC_H
 141
 142/*****************************************************************************
 143*
 144*              IOC Messages
 145*
 146*****************************************************************************/
 147
 148/****************************************************************************
 149* IOCInit message
 150****************************************************************************/
 151
 152/*IOCInit Request message */
 153typedef struct _MPI2_IOC_INIT_REQUEST {
 154        U8 WhoInit;             /*0x00 */
 155        U8 Reserved1;           /*0x01 */
 156        U8 ChainOffset;         /*0x02 */
 157        U8 Function;            /*0x03 */
 158        U16 Reserved2;          /*0x04 */
 159        U8 Reserved3;           /*0x06 */
 160        U8 MsgFlags;            /*0x07 */
 161        U8 VP_ID;               /*0x08 */
 162        U8 VF_ID;               /*0x09 */
 163        U16 Reserved4;          /*0x0A */
 164        U16 MsgVersion;         /*0x0C */
 165        U16 HeaderVersion;      /*0x0E */
 166        U32 Reserved5;          /*0x10 */
 167        U16 Reserved6;          /*0x14 */
 168        U8 Reserved7;           /*0x16 */
 169        U8 HostMSIxVectors;     /*0x17 */
 170        U16 Reserved8;          /*0x18 */
 171        U16 SystemRequestFrameSize;     /*0x1A */
 172        U16 ReplyDescriptorPostQueueDepth;      /*0x1C */
 173        U16 ReplyFreeQueueDepth;        /*0x1E */
 174        U32 SenseBufferAddressHigh;     /*0x20 */
 175        U32 SystemReplyAddressHigh;     /*0x24 */
 176        U64 SystemRequestFrameBaseAddress;      /*0x28 */
 177        U64 ReplyDescriptorPostQueueAddress;    /*0x30 */
 178        U64 ReplyFreeQueueAddress;      /*0x38 */
 179        U64 TimeStamp;          /*0x40 */
 180} MPI2_IOC_INIT_REQUEST, *PTR_MPI2_IOC_INIT_REQUEST,
 181        Mpi2IOCInitRequest_t, *pMpi2IOCInitRequest_t;
 182
 183/*WhoInit values */
 184#define MPI2_WHOINIT_NOT_INITIALIZED            (0x00)
 185#define MPI2_WHOINIT_SYSTEM_BIOS                (0x01)
 186#define MPI2_WHOINIT_ROM_BIOS                   (0x02)
 187#define MPI2_WHOINIT_PCI_PEER                   (0x03)
 188#define MPI2_WHOINIT_HOST_DRIVER                (0x04)
 189#define MPI2_WHOINIT_MANUFACTURER               (0x05)
 190
 191/* MsgFlags */
 192#define MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE    (0x01)
 193
 194
 195/*MsgVersion */
 196#define MPI2_IOCINIT_MSGVERSION_MAJOR_MASK      (0xFF00)
 197#define MPI2_IOCINIT_MSGVERSION_MAJOR_SHIFT     (8)
 198#define MPI2_IOCINIT_MSGVERSION_MINOR_MASK      (0x00FF)
 199#define MPI2_IOCINIT_MSGVERSION_MINOR_SHIFT     (0)
 200
 201/*HeaderVersion */
 202#define MPI2_IOCINIT_HDRVERSION_UNIT_MASK       (0xFF00)
 203#define MPI2_IOCINIT_HDRVERSION_UNIT_SHIFT      (8)
 204#define MPI2_IOCINIT_HDRVERSION_DEV_MASK        (0x00FF)
 205#define MPI2_IOCINIT_HDRVERSION_DEV_SHIFT       (0)
 206
 207/*minimum depth for a Reply Descriptor Post Queue */
 208#define MPI2_RDPQ_DEPTH_MIN                     (16)
 209
 210/* Reply Descriptor Post Queue Array Entry */
 211typedef struct _MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY {
 212        U64                 RDPQBaseAddress;                    /* 0x00 */
 213        U32                 Reserved1;                          /* 0x08 */
 214        U32                 Reserved2;                          /* 0x0C */
 215} MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY,
 216*PTR_MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY,
 217Mpi2IOCInitRDPQArrayEntry, *pMpi2IOCInitRDPQArrayEntry;
 218
 219
 220/*IOCInit Reply message */
 221typedef struct _MPI2_IOC_INIT_REPLY {
 222        U8 WhoInit;             /*0x00 */
 223        U8 Reserved1;           /*0x01 */
 224        U8 MsgLength;           /*0x02 */
 225        U8 Function;            /*0x03 */
 226        U16 Reserved2;          /*0x04 */
 227        U8 Reserved3;           /*0x06 */
 228        U8 MsgFlags;            /*0x07 */
 229        U8 VP_ID;               /*0x08 */
 230        U8 VF_ID;               /*0x09 */
 231        U16 Reserved4;          /*0x0A */
 232        U16 Reserved5;          /*0x0C */
 233        U16 IOCStatus;          /*0x0E */
 234        U32 IOCLogInfo;         /*0x10 */
 235} MPI2_IOC_INIT_REPLY, *PTR_MPI2_IOC_INIT_REPLY,
 236        Mpi2IOCInitReply_t, *pMpi2IOCInitReply_t;
 237
 238/****************************************************************************
 239* IOCFacts message
 240****************************************************************************/
 241
 242/*IOCFacts Request message */
 243typedef struct _MPI2_IOC_FACTS_REQUEST {
 244        U16 Reserved1;          /*0x00 */
 245        U8 ChainOffset;         /*0x02 */
 246        U8 Function;            /*0x03 */
 247        U16 Reserved2;          /*0x04 */
 248        U8 Reserved3;           /*0x06 */
 249        U8 MsgFlags;            /*0x07 */
 250        U8 VP_ID;               /*0x08 */
 251        U8 VF_ID;               /*0x09 */
 252        U16 Reserved4;          /*0x0A */
 253} MPI2_IOC_FACTS_REQUEST, *PTR_MPI2_IOC_FACTS_REQUEST,
 254        Mpi2IOCFactsRequest_t, *pMpi2IOCFactsRequest_t;
 255
 256/*IOCFacts Reply message */
 257typedef struct _MPI2_IOC_FACTS_REPLY {
 258        U16 MsgVersion;         /*0x00 */
 259        U8 MsgLength;           /*0x02 */
 260        U8 Function;            /*0x03 */
 261        U16 HeaderVersion;      /*0x04 */
 262        U8 IOCNumber;           /*0x06 */
 263        U8 MsgFlags;            /*0x07 */
 264        U8 VP_ID;               /*0x08 */
 265        U8 VF_ID;               /*0x09 */
 266        U16 Reserved1;          /*0x0A */
 267        U16 IOCExceptions;      /*0x0C */
 268        U16 IOCStatus;          /*0x0E */
 269        U32 IOCLogInfo;         /*0x10 */
 270        U8 MaxChainDepth;       /*0x14 */
 271        U8 WhoInit;             /*0x15 */
 272        U8 NumberOfPorts;       /*0x16 */
 273        U8 MaxMSIxVectors;      /*0x17 */
 274        U16 RequestCredit;      /*0x18 */
 275        U16 ProductID;          /*0x1A */
 276        U32 IOCCapabilities;    /*0x1C */
 277        MPI2_VERSION_UNION FWVersion;   /*0x20 */
 278        U16 IOCRequestFrameSize;        /*0x24 */
 279        U16 IOCMaxChainSegmentSize;     /*0x26 */
 280        U16 MaxInitiators;      /*0x28 */
 281        U16 MaxTargets;         /*0x2A */
 282        U16 MaxSasExpanders;    /*0x2C */
 283        U16 MaxEnclosures;      /*0x2E */
 284        U16 ProtocolFlags;      /*0x30 */
 285        U16 HighPriorityCredit; /*0x32 */
 286        U16 MaxReplyDescriptorPostQueueDepth;   /*0x34 */
 287        U8 ReplyFrameSize;      /*0x36 */
 288        U8 MaxVolumes;          /*0x37 */
 289        U16 MaxDevHandle;       /*0x38 */
 290        U16 MaxPersistentEntries;       /*0x3A */
 291        U16 MinDevHandle;       /*0x3C */
 292        U16 Reserved4;          /*0x3E */
 293} MPI2_IOC_FACTS_REPLY, *PTR_MPI2_IOC_FACTS_REPLY,
 294        Mpi2IOCFactsReply_t, *pMpi2IOCFactsReply_t;
 295
 296/*MsgVersion */
 297#define MPI2_IOCFACTS_MSGVERSION_MAJOR_MASK             (0xFF00)
 298#define MPI2_IOCFACTS_MSGVERSION_MAJOR_SHIFT            (8)
 299#define MPI2_IOCFACTS_MSGVERSION_MINOR_MASK             (0x00FF)
 300#define MPI2_IOCFACTS_MSGVERSION_MINOR_SHIFT            (0)
 301
 302/*HeaderVersion */
 303#define MPI2_IOCFACTS_HDRVERSION_UNIT_MASK              (0xFF00)
 304#define MPI2_IOCFACTS_HDRVERSION_UNIT_SHIFT             (8)
 305#define MPI2_IOCFACTS_HDRVERSION_DEV_MASK               (0x00FF)
 306#define MPI2_IOCFACTS_HDRVERSION_DEV_SHIFT              (0)
 307
 308/*IOCExceptions */
 309#define MPI2_IOCFACTS_EXCEPT_PARTIAL_MEMORY_FAILURE     (0x0200)
 310#define MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX      (0x0100)
 311
 312#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_MASK              (0x00E0)
 313#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_GOOD              (0x0000)
 314#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_BACKUP            (0x0020)
 315#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_RESTORED          (0x0040)
 316#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_CORRUPT_BACKUP    (0x0060)
 317
 318#define MPI2_IOCFACTS_EXCEPT_METADATA_UNSUPPORTED       (0x0010)
 319#define MPI2_IOCFACTS_EXCEPT_MANUFACT_CHECKSUM_FAIL     (0x0008)
 320#define MPI2_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL           (0x0004)
 321#define MPI2_IOCFACTS_EXCEPT_RAID_CONFIG_INVALID        (0x0002)
 322#define MPI2_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL       (0x0001)
 323
 324/*defines for WhoInit field are after the IOCInit Request */
 325
 326/*ProductID field uses MPI2_FW_HEADER_PID_ */
 327
 328/*IOCCapabilities */
 329#define MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE     (0x00040000)
 330#define MPI25_IOCFACTS_CAPABILITY_FAST_PATH_CAPABLE     (0x00020000)
 331#define MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY   (0x00010000)
 332#define MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX            (0x00008000)
 333#define MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR       (0x00004000)
 334#define MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY           (0x00002000)
 335#define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID        (0x00001000)
 336#define MPI2_IOCFACTS_CAPABILITY_TLR                    (0x00000800)
 337#define MPI2_IOCFACTS_CAPABILITY_MULTICAST              (0x00000100)
 338#define MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET   (0x00000080)
 339#define MPI2_IOCFACTS_CAPABILITY_EEDP                   (0x00000040)
 340#define MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER        (0x00000020)
 341#define MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER        (0x00000010)
 342#define MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER      (0x00000008)
 343#define MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING (0x00000004)
 344
 345/*ProtocolFlags */
 346#define MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET              (0x0001)
 347#define MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR           (0x0002)
 348
 349/****************************************************************************
 350* PortFacts message
 351****************************************************************************/
 352
 353/*PortFacts Request message */
 354typedef struct _MPI2_PORT_FACTS_REQUEST {
 355        U16 Reserved1;          /*0x00 */
 356        U8 ChainOffset;         /*0x02 */
 357        U8 Function;            /*0x03 */
 358        U16 Reserved2;          /*0x04 */
 359        U8 PortNumber;          /*0x06 */
 360        U8 MsgFlags;            /*0x07 */
 361        U8 VP_ID;               /*0x08 */
 362        U8 VF_ID;               /*0x09 */
 363        U16 Reserved3;          /*0x0A */
 364} MPI2_PORT_FACTS_REQUEST, *PTR_MPI2_PORT_FACTS_REQUEST,
 365        Mpi2PortFactsRequest_t, *pMpi2PortFactsRequest_t;
 366
 367/*PortFacts Reply message */
 368typedef struct _MPI2_PORT_FACTS_REPLY {
 369        U16 Reserved1;          /*0x00 */
 370        U8 MsgLength;           /*0x02 */
 371        U8 Function;            /*0x03 */
 372        U16 Reserved2;          /*0x04 */
 373        U8 PortNumber;          /*0x06 */
 374        U8 MsgFlags;            /*0x07 */
 375        U8 VP_ID;               /*0x08 */
 376        U8 VF_ID;               /*0x09 */
 377        U16 Reserved3;          /*0x0A */
 378        U16 Reserved4;          /*0x0C */
 379        U16 IOCStatus;          /*0x0E */
 380        U32 IOCLogInfo;         /*0x10 */
 381        U8 Reserved5;           /*0x14 */
 382        U8 PortType;            /*0x15 */
 383        U16 Reserved6;          /*0x16 */
 384        U16 MaxPostedCmdBuffers;        /*0x18 */
 385        U16 Reserved7;          /*0x1A */
 386} MPI2_PORT_FACTS_REPLY, *PTR_MPI2_PORT_FACTS_REPLY,
 387        Mpi2PortFactsReply_t, *pMpi2PortFactsReply_t;
 388
 389/*PortType values */
 390#define MPI2_PORTFACTS_PORTTYPE_INACTIVE            (0x00)
 391#define MPI2_PORTFACTS_PORTTYPE_FC                  (0x10)
 392#define MPI2_PORTFACTS_PORTTYPE_ISCSI               (0x20)
 393#define MPI2_PORTFACTS_PORTTYPE_SAS_PHYSICAL        (0x30)
 394#define MPI2_PORTFACTS_PORTTYPE_SAS_VIRTUAL         (0x31)
 395
 396/****************************************************************************
 397* PortEnable message
 398****************************************************************************/
 399
 400/*PortEnable Request message */
 401typedef struct _MPI2_PORT_ENABLE_REQUEST {
 402        U16 Reserved1;          /*0x00 */
 403        U8 ChainOffset;         /*0x02 */
 404        U8 Function;            /*0x03 */
 405        U8 Reserved2;           /*0x04 */
 406        U8 PortFlags;           /*0x05 */
 407        U8 Reserved3;           /*0x06 */
 408        U8 MsgFlags;            /*0x07 */
 409        U8 VP_ID;               /*0x08 */
 410        U8 VF_ID;               /*0x09 */
 411        U16 Reserved4;          /*0x0A */
 412} MPI2_PORT_ENABLE_REQUEST, *PTR_MPI2_PORT_ENABLE_REQUEST,
 413        Mpi2PortEnableRequest_t, *pMpi2PortEnableRequest_t;
 414
 415/*PortEnable Reply message */
 416typedef struct _MPI2_PORT_ENABLE_REPLY {
 417        U16 Reserved1;          /*0x00 */
 418        U8 MsgLength;           /*0x02 */
 419        U8 Function;            /*0x03 */
 420        U8 Reserved2;           /*0x04 */
 421        U8 PortFlags;           /*0x05 */
 422        U8 Reserved3;           /*0x06 */
 423        U8 MsgFlags;            /*0x07 */
 424        U8 VP_ID;               /*0x08 */
 425        U8 VF_ID;               /*0x09 */
 426        U16 Reserved4;          /*0x0A */
 427        U16 Reserved5;          /*0x0C */
 428        U16 IOCStatus;          /*0x0E */
 429        U32 IOCLogInfo;         /*0x10 */
 430} MPI2_PORT_ENABLE_REPLY, *PTR_MPI2_PORT_ENABLE_REPLY,
 431        Mpi2PortEnableReply_t, *pMpi2PortEnableReply_t;
 432
 433/****************************************************************************
 434* EventNotification message
 435****************************************************************************/
 436
 437/*EventNotification Request message */
 438#define MPI2_EVENT_NOTIFY_EVENTMASK_WORDS           (4)
 439
 440typedef struct _MPI2_EVENT_NOTIFICATION_REQUEST {
 441        U16 Reserved1;          /*0x00 */
 442        U8 ChainOffset;         /*0x02 */
 443        U8 Function;            /*0x03 */
 444        U16 Reserved2;          /*0x04 */
 445        U8 Reserved3;           /*0x06 */
 446        U8 MsgFlags;            /*0x07 */
 447        U8 VP_ID;               /*0x08 */
 448        U8 VF_ID;               /*0x09 */
 449        U16 Reserved4;          /*0x0A */
 450        U32 Reserved5;          /*0x0C */
 451        U32 Reserved6;          /*0x10 */
 452        U32 EventMasks[MPI2_EVENT_NOTIFY_EVENTMASK_WORDS];      /*0x14 */
 453        U16 SASBroadcastPrimitiveMasks; /*0x24 */
 454        U16 SASNotifyPrimitiveMasks;    /*0x26 */
 455        U32 Reserved8;          /*0x28 */
 456} MPI2_EVENT_NOTIFICATION_REQUEST,
 457        *PTR_MPI2_EVENT_NOTIFICATION_REQUEST,
 458        Mpi2EventNotificationRequest_t,
 459        *pMpi2EventNotificationRequest_t;
 460
 461/*EventNotification Reply message */
 462typedef struct _MPI2_EVENT_NOTIFICATION_REPLY {
 463        U16 EventDataLength;    /*0x00 */
 464        U8 MsgLength;           /*0x02 */
 465        U8 Function;            /*0x03 */
 466        U16 Reserved1;          /*0x04 */
 467        U8 AckRequired;         /*0x06 */
 468        U8 MsgFlags;            /*0x07 */
 469        U8 VP_ID;               /*0x08 */
 470        U8 VF_ID;               /*0x09 */
 471        U16 Reserved2;          /*0x0A */
 472        U16 Reserved3;          /*0x0C */
 473        U16 IOCStatus;          /*0x0E */
 474        U32 IOCLogInfo;         /*0x10 */
 475        U16 Event;              /*0x14 */
 476        U16 Reserved4;          /*0x16 */
 477        U32 EventContext;       /*0x18 */
 478        U32 EventData[1];       /*0x1C */
 479} MPI2_EVENT_NOTIFICATION_REPLY, *PTR_MPI2_EVENT_NOTIFICATION_REPLY,
 480        Mpi2EventNotificationReply_t,
 481        *pMpi2EventNotificationReply_t;
 482
 483/*AckRequired */
 484#define MPI2_EVENT_NOTIFICATION_ACK_NOT_REQUIRED    (0x00)
 485#define MPI2_EVENT_NOTIFICATION_ACK_REQUIRED        (0x01)
 486
 487/*Event */
 488#define MPI2_EVENT_LOG_DATA                         (0x0001)
 489#define MPI2_EVENT_STATE_CHANGE                     (0x0002)
 490#define MPI2_EVENT_HARD_RESET_RECEIVED              (0x0005)
 491#define MPI2_EVENT_EVENT_CHANGE                     (0x000A)
 492#define MPI2_EVENT_TASK_SET_FULL                    (0x000E)    /*obsolete */
 493#define MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE         (0x000F)
 494#define MPI2_EVENT_IR_OPERATION_STATUS              (0x0014)
 495#define MPI2_EVENT_SAS_DISCOVERY                    (0x0016)
 496#define MPI2_EVENT_SAS_BROADCAST_PRIMITIVE          (0x0017)
 497#define MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE    (0x0018)
 498#define MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW          (0x0019)
 499#define MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST         (0x001C)
 500#define MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE    (0x001D)
 501#define MPI2_EVENT_IR_VOLUME                        (0x001E)
 502#define MPI2_EVENT_IR_PHYSICAL_DISK                 (0x001F)
 503#define MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST     (0x0020)
 504#define MPI2_EVENT_LOG_ENTRY_ADDED                  (0x0021)
 505#define MPI2_EVENT_SAS_PHY_COUNTER                  (0x0022)
 506#define MPI2_EVENT_GPIO_INTERRUPT                   (0x0023)
 507#define MPI2_EVENT_HOST_BASED_DISCOVERY_PHY         (0x0024)
 508#define MPI2_EVENT_SAS_QUIESCE                      (0x0025)
 509#define MPI2_EVENT_SAS_NOTIFY_PRIMITIVE             (0x0026)
 510#define MPI2_EVENT_TEMP_THRESHOLD                   (0x0027)
 511#define MPI2_EVENT_HOST_MESSAGE                     (0x0028)
 512#define MPI2_EVENT_POWER_PERFORMANCE_CHANGE         (0x0029)
 513#define MPI2_EVENT_MIN_PRODUCT_SPECIFIC             (0x006E)
 514#define MPI2_EVENT_MAX_PRODUCT_SPECIFIC             (0x007F)
 515
 516/*Log Entry Added Event data */
 517
 518/*the following structure matches MPI2_LOG_0_ENTRY in mpi2_cnfg.h */
 519#define MPI2_EVENT_DATA_LOG_DATA_LENGTH             (0x1C)
 520
 521typedef struct _MPI2_EVENT_DATA_LOG_ENTRY_ADDED {
 522        U64 TimeStamp;          /*0x00 */
 523        U32 Reserved1;          /*0x08 */
 524        U16 LogSequence;        /*0x0C */
 525        U16 LogEntryQualifier;  /*0x0E */
 526        U8 VP_ID;               /*0x10 */
 527        U8 VF_ID;               /*0x11 */
 528        U16 Reserved2;          /*0x12 */
 529        U8 LogData[MPI2_EVENT_DATA_LOG_DATA_LENGTH];    /*0x14 */
 530} MPI2_EVENT_DATA_LOG_ENTRY_ADDED,
 531        *PTR_MPI2_EVENT_DATA_LOG_ENTRY_ADDED,
 532        Mpi2EventDataLogEntryAdded_t,
 533        *pMpi2EventDataLogEntryAdded_t;
 534
 535/*GPIO Interrupt Event data */
 536
 537typedef struct _MPI2_EVENT_DATA_GPIO_INTERRUPT {
 538        U8 GPIONum;             /*0x00 */
 539        U8 Reserved1;           /*0x01 */
 540        U16 Reserved2;          /*0x02 */
 541} MPI2_EVENT_DATA_GPIO_INTERRUPT,
 542        *PTR_MPI2_EVENT_DATA_GPIO_INTERRUPT,
 543        Mpi2EventDataGpioInterrupt_t,
 544        *pMpi2EventDataGpioInterrupt_t;
 545
 546/*Temperature Threshold Event data */
 547
 548typedef struct _MPI2_EVENT_DATA_TEMPERATURE {
 549        U16 Status;             /*0x00 */
 550        U8 SensorNum;           /*0x02 */
 551        U8 Reserved1;           /*0x03 */
 552        U16 CurrentTemperature; /*0x04 */
 553        U16 Reserved2;          /*0x06 */
 554        U32 Reserved3;          /*0x08 */
 555        U32 Reserved4;          /*0x0C */
 556} MPI2_EVENT_DATA_TEMPERATURE,
 557        *PTR_MPI2_EVENT_DATA_TEMPERATURE,
 558        Mpi2EventDataTemperature_t, *pMpi2EventDataTemperature_t;
 559
 560/*Temperature Threshold Event data Status bits */
 561#define MPI2_EVENT_TEMPERATURE3_EXCEEDED            (0x0008)
 562#define MPI2_EVENT_TEMPERATURE2_EXCEEDED            (0x0004)
 563#define MPI2_EVENT_TEMPERATURE1_EXCEEDED            (0x0002)
 564#define MPI2_EVENT_TEMPERATURE0_EXCEEDED            (0x0001)
 565
 566/*Host Message Event data */
 567
 568typedef struct _MPI2_EVENT_DATA_HOST_MESSAGE {
 569        U8 SourceVF_ID;         /*0x00 */
 570        U8 Reserved1;           /*0x01 */
 571        U16 Reserved2;          /*0x02 */
 572        U32 Reserved3;          /*0x04 */
 573        U32 HostData[1];        /*0x08 */
 574} MPI2_EVENT_DATA_HOST_MESSAGE, *PTR_MPI2_EVENT_DATA_HOST_MESSAGE,
 575        Mpi2EventDataHostMessage_t, *pMpi2EventDataHostMessage_t;
 576
 577/*Power Performance Change Event */
 578
 579typedef struct _MPI2_EVENT_DATA_POWER_PERF_CHANGE {
 580        U8 CurrentPowerMode;    /*0x00 */
 581        U8 PreviousPowerMode;   /*0x01 */
 582        U16 Reserved1;          /*0x02 */
 583} MPI2_EVENT_DATA_POWER_PERF_CHANGE,
 584        *PTR_MPI2_EVENT_DATA_POWER_PERF_CHANGE,
 585        Mpi2EventDataPowerPerfChange_t,
 586        *pMpi2EventDataPowerPerfChange_t;
 587
 588/*defines for CurrentPowerMode and PreviousPowerMode fields */
 589#define MPI2_EVENT_PM_INIT_MASK              (0xC0)
 590#define MPI2_EVENT_PM_INIT_UNAVAILABLE       (0x00)
 591#define MPI2_EVENT_PM_INIT_HOST              (0x40)
 592#define MPI2_EVENT_PM_INIT_IO_UNIT           (0x80)
 593#define MPI2_EVENT_PM_INIT_PCIE_DPA          (0xC0)
 594
 595#define MPI2_EVENT_PM_MODE_MASK              (0x07)
 596#define MPI2_EVENT_PM_MODE_UNAVAILABLE       (0x00)
 597#define MPI2_EVENT_PM_MODE_UNKNOWN           (0x01)
 598#define MPI2_EVENT_PM_MODE_FULL_POWER        (0x04)
 599#define MPI2_EVENT_PM_MODE_REDUCED_POWER     (0x05)
 600#define MPI2_EVENT_PM_MODE_STANDBY           (0x06)
 601
 602/*Hard Reset Received Event data */
 603
 604typedef struct _MPI2_EVENT_DATA_HARD_RESET_RECEIVED {
 605        U8 Reserved1;           /*0x00 */
 606        U8 Port;                /*0x01 */
 607        U16 Reserved2;          /*0x02 */
 608} MPI2_EVENT_DATA_HARD_RESET_RECEIVED,
 609        *PTR_MPI2_EVENT_DATA_HARD_RESET_RECEIVED,
 610        Mpi2EventDataHardResetReceived_t,
 611        *pMpi2EventDataHardResetReceived_t;
 612
 613/*Task Set Full Event data */
 614/*  this event is obsolete */
 615
 616typedef struct _MPI2_EVENT_DATA_TASK_SET_FULL {
 617        U16 DevHandle;          /*0x00 */
 618        U16 CurrentDepth;       /*0x02 */
 619} MPI2_EVENT_DATA_TASK_SET_FULL, *PTR_MPI2_EVENT_DATA_TASK_SET_FULL,
 620        Mpi2EventDataTaskSetFull_t, *pMpi2EventDataTaskSetFull_t;
 621
 622/*SAS Device Status Change Event data */
 623
 624typedef struct _MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE {
 625        U16 TaskTag;            /*0x00 */
 626        U8 ReasonCode;          /*0x02 */
 627        U8 PhysicalPort;        /*0x03 */
 628        U8 ASC;                 /*0x04 */
 629        U8 ASCQ;                /*0x05 */
 630        U16 DevHandle;          /*0x06 */
 631        U32 Reserved2;          /*0x08 */
 632        U64 SASAddress;         /*0x0C */
 633        U8 LUN[8];              /*0x14 */
 634} MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE,
 635        *PTR_MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE,
 636        Mpi2EventDataSasDeviceStatusChange_t,
 637        *pMpi2EventDataSasDeviceStatusChange_t;
 638
 639/*SAS Device Status Change Event data ReasonCode values */
 640#define MPI2_EVENT_SAS_DEV_STAT_RC_SMART_DATA                           (0x05)
 641#define MPI2_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED                          (0x07)
 642#define MPI2_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET                (0x08)
 643#define MPI2_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL                  (0x09)
 644#define MPI2_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL              (0x0A)
 645#define MPI2_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL              (0x0B)
 646#define MPI2_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL                  (0x0C)
 647#define MPI2_EVENT_SAS_DEV_STAT_RC_ASYNC_NOTIFICATION                   (0x0D)
 648#define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_INTERNAL_DEV_RESET               (0x0E)
 649#define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_TASK_ABORT_INTERNAL              (0x0F)
 650#define MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE                    (0x10)
 651#define MPI2_EVENT_SAS_DEV_STAT_RC_EXPANDER_REDUCED_FUNCTIONALITY       (0x11)
 652#define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_EXPANDER_REDUCED_FUNCTIONALITY   (0x12)
 653
 654/*Integrated RAID Operation Status Event data */
 655
 656typedef struct _MPI2_EVENT_DATA_IR_OPERATION_STATUS {
 657        U16 VolDevHandle;       /*0x00 */
 658        U16 Reserved1;          /*0x02 */
 659        U8 RAIDOperation;       /*0x04 */
 660        U8 PercentComplete;     /*0x05 */
 661        U16 Reserved2;          /*0x06 */
 662        U32 ElapsedSeconds;     /*0x08 */
 663} MPI2_EVENT_DATA_IR_OPERATION_STATUS,
 664        *PTR_MPI2_EVENT_DATA_IR_OPERATION_STATUS,
 665        Mpi2EventDataIrOperationStatus_t,
 666        *pMpi2EventDataIrOperationStatus_t;
 667
 668/*Integrated RAID Operation Status Event data RAIDOperation values */
 669#define MPI2_EVENT_IR_RAIDOP_RESYNC                     (0x00)
 670#define MPI2_EVENT_IR_RAIDOP_ONLINE_CAP_EXPANSION       (0x01)
 671#define MPI2_EVENT_IR_RAIDOP_CONSISTENCY_CHECK          (0x02)
 672#define MPI2_EVENT_IR_RAIDOP_BACKGROUND_INIT            (0x03)
 673#define MPI2_EVENT_IR_RAIDOP_MAKE_DATA_CONSISTENT       (0x04)
 674
 675/*Integrated RAID Volume Event data */
 676
 677typedef struct _MPI2_EVENT_DATA_IR_VOLUME {
 678        U16 VolDevHandle;       /*0x00 */
 679        U8 ReasonCode;          /*0x02 */
 680        U8 Reserved1;           /*0x03 */
 681        U32 NewValue;           /*0x04 */
 682        U32 PreviousValue;      /*0x08 */
 683} MPI2_EVENT_DATA_IR_VOLUME, *PTR_MPI2_EVENT_DATA_IR_VOLUME,
 684        Mpi2EventDataIrVolume_t, *pMpi2EventDataIrVolume_t;
 685
 686/*Integrated RAID Volume Event data ReasonCode values */
 687#define MPI2_EVENT_IR_VOLUME_RC_SETTINGS_CHANGED        (0x01)
 688#define MPI2_EVENT_IR_VOLUME_RC_STATUS_FLAGS_CHANGED    (0x02)
 689#define MPI2_EVENT_IR_VOLUME_RC_STATE_CHANGED           (0x03)
 690
 691/*Integrated RAID Physical Disk Event data */
 692
 693typedef struct _MPI2_EVENT_DATA_IR_PHYSICAL_DISK {
 694        U16 Reserved1;          /*0x00 */
 695        U8 ReasonCode;          /*0x02 */
 696        U8 PhysDiskNum;         /*0x03 */
 697        U16 PhysDiskDevHandle;  /*0x04 */
 698        U16 Reserved2;          /*0x06 */
 699        U16 Slot;               /*0x08 */
 700        U16 EnclosureHandle;    /*0x0A */
 701        U32 NewValue;           /*0x0C */
 702        U32 PreviousValue;      /*0x10 */
 703} MPI2_EVENT_DATA_IR_PHYSICAL_DISK,
 704        *PTR_MPI2_EVENT_DATA_IR_PHYSICAL_DISK,
 705        Mpi2EventDataIrPhysicalDisk_t,
 706        *pMpi2EventDataIrPhysicalDisk_t;
 707
 708/*Integrated RAID Physical Disk Event data ReasonCode values */
 709#define MPI2_EVENT_IR_PHYSDISK_RC_SETTINGS_CHANGED      (0x01)
 710#define MPI2_EVENT_IR_PHYSDISK_RC_STATUS_FLAGS_CHANGED  (0x02)
 711#define MPI2_EVENT_IR_PHYSDISK_RC_STATE_CHANGED         (0x03)
 712
 713/*Integrated RAID Configuration Change List Event data */
 714
 715/*
 716 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
 717 *one and check NumElements at runtime.
 718 */
 719#ifndef MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT
 720#define MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT          (1)
 721#endif
 722
 723typedef struct _MPI2_EVENT_IR_CONFIG_ELEMENT {
 724        U16 ElementFlags;       /*0x00 */
 725        U16 VolDevHandle;       /*0x02 */
 726        U8 ReasonCode;          /*0x04 */
 727        U8 PhysDiskNum;         /*0x05 */
 728        U16 PhysDiskDevHandle;  /*0x06 */
 729} MPI2_EVENT_IR_CONFIG_ELEMENT, *PTR_MPI2_EVENT_IR_CONFIG_ELEMENT,
 730        Mpi2EventIrConfigElement_t, *pMpi2EventIrConfigElement_t;
 731
 732/*IR Configuration Change List Event data ElementFlags values */
 733#define MPI2_EVENT_IR_CHANGE_EFLAGS_ELEMENT_TYPE_MASK   (0x000F)
 734#define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLUME_ELEMENT      (0x0000)
 735#define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLPHYSDISK_ELEMENT (0x0001)
 736#define MPI2_EVENT_IR_CHANGE_EFLAGS_HOTSPARE_ELEMENT    (0x0002)
 737
 738/*IR Configuration Change List Event data ReasonCode values */
 739#define MPI2_EVENT_IR_CHANGE_RC_ADDED                   (0x01)
 740#define MPI2_EVENT_IR_CHANGE_RC_REMOVED                 (0x02)
 741#define MPI2_EVENT_IR_CHANGE_RC_NO_CHANGE               (0x03)
 742#define MPI2_EVENT_IR_CHANGE_RC_HIDE                    (0x04)
 743#define MPI2_EVENT_IR_CHANGE_RC_UNHIDE                  (0x05)
 744#define MPI2_EVENT_IR_CHANGE_RC_VOLUME_CREATED          (0x06)
 745#define MPI2_EVENT_IR_CHANGE_RC_VOLUME_DELETED          (0x07)
 746#define MPI2_EVENT_IR_CHANGE_RC_PD_CREATED              (0x08)
 747#define MPI2_EVENT_IR_CHANGE_RC_PD_DELETED              (0x09)
 748
 749typedef struct _MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST {
 750        U8 NumElements;         /*0x00 */
 751        U8 Reserved1;           /*0x01 */
 752        U8 Reserved2;           /*0x02 */
 753        U8 ConfigNum;           /*0x03 */
 754        U32 Flags;              /*0x04 */
 755        MPI2_EVENT_IR_CONFIG_ELEMENT
 756                ConfigElement[MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT];/*0x08 */
 757} MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST,
 758        *PTR_MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST,
 759        Mpi2EventDataIrConfigChangeList_t,
 760        *pMpi2EventDataIrConfigChangeList_t;
 761
 762/*IR Configuration Change List Event data Flags values */
 763#define MPI2_EVENT_IR_CHANGE_FLAGS_FOREIGN_CONFIG   (0x00000001)
 764
 765/*SAS Discovery Event data */
 766
 767typedef struct _MPI2_EVENT_DATA_SAS_DISCOVERY {
 768        U8 Flags;               /*0x00 */
 769        U8 ReasonCode;          /*0x01 */
 770        U8 PhysicalPort;        /*0x02 */
 771        U8 Reserved1;           /*0x03 */
 772        U32 DiscoveryStatus;    /*0x04 */
 773} MPI2_EVENT_DATA_SAS_DISCOVERY,
 774        *PTR_MPI2_EVENT_DATA_SAS_DISCOVERY,
 775        Mpi2EventDataSasDiscovery_t, *pMpi2EventDataSasDiscovery_t;
 776
 777/*SAS Discovery Event data Flags values */
 778#define MPI2_EVENT_SAS_DISC_DEVICE_CHANGE                   (0x02)
 779#define MPI2_EVENT_SAS_DISC_IN_PROGRESS                     (0x01)
 780
 781/*SAS Discovery Event data ReasonCode values */
 782#define MPI2_EVENT_SAS_DISC_RC_STARTED                      (0x01)
 783#define MPI2_EVENT_SAS_DISC_RC_COMPLETED                    (0x02)
 784
 785/*SAS Discovery Event data DiscoveryStatus values */
 786#define MPI2_EVENT_SAS_DISC_DS_MAX_ENCLOSURES_EXCEED            (0x80000000)
 787#define MPI2_EVENT_SAS_DISC_DS_MAX_EXPANDERS_EXCEED             (0x40000000)
 788#define MPI2_EVENT_SAS_DISC_DS_MAX_DEVICES_EXCEED               (0x20000000)
 789#define MPI2_EVENT_SAS_DISC_DS_MAX_TOPO_PHYS_EXCEED             (0x10000000)
 790#define MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR             (0x08000000)
 791#define MPI2_EVENT_SAS_DISC_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE    (0x00008000)
 792#define MPI2_EVENT_SAS_DISC_DS_EXP_MULTI_SUBTRACTIVE            (0x00004000)
 793#define MPI2_EVENT_SAS_DISC_DS_MULTI_PORT_DOMAIN                (0x00002000)
 794#define MPI2_EVENT_SAS_DISC_DS_TABLE_TO_SUBTRACTIVE_LINK        (0x00001000)
 795#define MPI2_EVENT_SAS_DISC_DS_UNSUPPORTED_DEVICE               (0x00000800)
 796#define MPI2_EVENT_SAS_DISC_DS_TABLE_LINK                       (0x00000400)
 797#define MPI2_EVENT_SAS_DISC_DS_SUBTRACTIVE_LINK                 (0x00000200)
 798#define MPI2_EVENT_SAS_DISC_DS_SMP_CRC_ERROR                    (0x00000100)
 799#define MPI2_EVENT_SAS_DISC_DS_SMP_FUNCTION_FAILED              (0x00000080)
 800#define MPI2_EVENT_SAS_DISC_DS_INDEX_NOT_EXIST                  (0x00000040)
 801#define MPI2_EVENT_SAS_DISC_DS_OUT_ROUTE_ENTRIES                (0x00000020)
 802#define MPI2_EVENT_SAS_DISC_DS_SMP_TIMEOUT                      (0x00000010)
 803#define MPI2_EVENT_SAS_DISC_DS_MULTIPLE_PORTS                   (0x00000004)
 804#define MPI2_EVENT_SAS_DISC_DS_UNADDRESSABLE_DEVICE             (0x00000002)
 805#define MPI2_EVENT_SAS_DISC_DS_LOOP_DETECTED                    (0x00000001)
 806
 807/*SAS Broadcast Primitive Event data */
 808
 809typedef struct _MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE {
 810        U8 PhyNum;              /*0x00 */
 811        U8 Port;                /*0x01 */
 812        U8 PortWidth;           /*0x02 */
 813        U8 Primitive;           /*0x03 */
 814} MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE,
 815        *PTR_MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE,
 816        Mpi2EventDataSasBroadcastPrimitive_t,
 817        *pMpi2EventDataSasBroadcastPrimitive_t;
 818
 819/*defines for the Primitive field */
 820#define MPI2_EVENT_PRIMITIVE_CHANGE                         (0x01)
 821#define MPI2_EVENT_PRIMITIVE_SES                            (0x02)
 822#define MPI2_EVENT_PRIMITIVE_EXPANDER                       (0x03)
 823#define MPI2_EVENT_PRIMITIVE_ASYNCHRONOUS_EVENT             (0x04)
 824#define MPI2_EVENT_PRIMITIVE_RESERVED3                      (0x05)
 825#define MPI2_EVENT_PRIMITIVE_RESERVED4                      (0x06)
 826#define MPI2_EVENT_PRIMITIVE_CHANGE0_RESERVED               (0x07)
 827#define MPI2_EVENT_PRIMITIVE_CHANGE1_RESERVED               (0x08)
 828
 829/*SAS Notify Primitive Event data */
 830
 831typedef struct _MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE {
 832        U8 PhyNum;              /*0x00 */
 833        U8 Port;                /*0x01 */
 834        U8 Reserved1;           /*0x02 */
 835        U8 Primitive;           /*0x03 */
 836} MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE,
 837        *PTR_MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE,
 838        Mpi2EventDataSasNotifyPrimitive_t,
 839        *pMpi2EventDataSasNotifyPrimitive_t;
 840
 841/*defines for the Primitive field */
 842#define MPI2_EVENT_NOTIFY_ENABLE_SPINUP                     (0x01)
 843#define MPI2_EVENT_NOTIFY_POWER_LOSS_EXPECTED               (0x02)
 844#define MPI2_EVENT_NOTIFY_RESERVED1                         (0x03)
 845#define MPI2_EVENT_NOTIFY_RESERVED2                         (0x04)
 846
 847/*SAS Initiator Device Status Change Event data */
 848
 849typedef struct _MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE {
 850        U8 ReasonCode;          /*0x00 */
 851        U8 PhysicalPort;        /*0x01 */
 852        U16 DevHandle;          /*0x02 */
 853        U64 SASAddress;         /*0x04 */
 854} MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE,
 855        *PTR_MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE,
 856        Mpi2EventDataSasInitDevStatusChange_t,
 857        *pMpi2EventDataSasInitDevStatusChange_t;
 858
 859/*SAS Initiator Device Status Change event ReasonCode values */
 860#define MPI2_EVENT_SAS_INIT_RC_ADDED                (0x01)
 861#define MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING       (0x02)
 862
 863/*SAS Initiator Device Table Overflow Event data */
 864
 865typedef struct _MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW {
 866        U16 MaxInit;            /*0x00 */
 867        U16 CurrentInit;        /*0x02 */
 868        U64 SASAddress;         /*0x04 */
 869} MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW,
 870        *PTR_MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW,
 871        Mpi2EventDataSasInitTableOverflow_t,
 872        *pMpi2EventDataSasInitTableOverflow_t;
 873
 874/*SAS Topology Change List Event data */
 875
 876/*
 877 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
 878 *one and check NumEntries at runtime.
 879 */
 880#ifndef MPI2_EVENT_SAS_TOPO_PHY_COUNT
 881#define MPI2_EVENT_SAS_TOPO_PHY_COUNT           (1)
 882#endif
 883
 884typedef struct _MPI2_EVENT_SAS_TOPO_PHY_ENTRY {
 885        U16 AttachedDevHandle;  /*0x00 */
 886        U8 LinkRate;            /*0x02 */
 887        U8 PhyStatus;           /*0x03 */
 888} MPI2_EVENT_SAS_TOPO_PHY_ENTRY, *PTR_MPI2_EVENT_SAS_TOPO_PHY_ENTRY,
 889        Mpi2EventSasTopoPhyEntry_t, *pMpi2EventSasTopoPhyEntry_t;
 890
 891typedef struct _MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST {
 892        U16 EnclosureHandle;    /*0x00 */
 893        U16 ExpanderDevHandle;  /*0x02 */
 894        U8 NumPhys;             /*0x04 */
 895        U8 Reserved1;           /*0x05 */
 896        U16 Reserved2;          /*0x06 */
 897        U8 NumEntries;          /*0x08 */
 898        U8 StartPhyNum;         /*0x09 */
 899        U8 ExpStatus;           /*0x0A */
 900        U8 PhysicalPort;        /*0x0B */
 901        MPI2_EVENT_SAS_TOPO_PHY_ENTRY
 902        PHY[MPI2_EVENT_SAS_TOPO_PHY_COUNT];     /*0x0C */
 903} MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST,
 904        *PTR_MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST,
 905        Mpi2EventDataSasTopologyChangeList_t,
 906        *pMpi2EventDataSasTopologyChangeList_t;
 907
 908/*values for the ExpStatus field */
 909#define MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER                  (0x00)
 910#define MPI2_EVENT_SAS_TOPO_ES_ADDED                        (0x01)
 911#define MPI2_EVENT_SAS_TOPO_ES_NOT_RESPONDING               (0x02)
 912#define MPI2_EVENT_SAS_TOPO_ES_RESPONDING                   (0x03)
 913#define MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING         (0x04)
 914
 915/*defines for the LinkRate field */
 916#define MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK                 (0xF0)
 917#define MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT                (4)
 918#define MPI2_EVENT_SAS_TOPO_LR_PREV_MASK                    (0x0F)
 919#define MPI2_EVENT_SAS_TOPO_LR_PREV_SHIFT                   (0)
 920
 921#define MPI2_EVENT_SAS_TOPO_LR_UNKNOWN_LINK_RATE            (0x00)
 922#define MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED                 (0x01)
 923#define MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED           (0x02)
 924#define MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE            (0x03)
 925#define MPI2_EVENT_SAS_TOPO_LR_PORT_SELECTOR                (0x04)
 926#define MPI2_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS        (0x05)
 927#define MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY              (0x06)
 928#define MPI2_EVENT_SAS_TOPO_LR_RATE_1_5                     (0x08)
 929#define MPI2_EVENT_SAS_TOPO_LR_RATE_3_0                     (0x09)
 930#define MPI2_EVENT_SAS_TOPO_LR_RATE_6_0                     (0x0A)
 931#define MPI25_EVENT_SAS_TOPO_LR_RATE_12_0                   (0x0B)
 932
 933/*values for the PhyStatus field */
 934#define MPI2_EVENT_SAS_TOPO_PHYSTATUS_VACANT                (0x80)
 935#define MPI2_EVENT_SAS_TOPO_PS_MULTIPLEX_CHANGE             (0x10)
 936/*values for the PhyStatus ReasonCode sub-field */
 937#define MPI2_EVENT_SAS_TOPO_RC_MASK                         (0x0F)
 938#define MPI2_EVENT_SAS_TOPO_RC_TARG_ADDED                   (0x01)
 939#define MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING          (0x02)
 940#define MPI2_EVENT_SAS_TOPO_RC_PHY_CHANGED                  (0x03)
 941#define MPI2_EVENT_SAS_TOPO_RC_NO_CHANGE                    (0x04)
 942#define MPI2_EVENT_SAS_TOPO_RC_DELAY_NOT_RESPONDING         (0x05)
 943
 944/*SAS Enclosure Device Status Change Event data */
 945
 946typedef struct _MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE {
 947        U16 EnclosureHandle;    /*0x00 */
 948        U8 ReasonCode;          /*0x02 */
 949        U8 PhysicalPort;        /*0x03 */
 950        U64 EnclosureLogicalID; /*0x04 */
 951        U16 NumSlots;           /*0x0C */
 952        U16 StartSlot;          /*0x0E */
 953        U32 PhyBits;            /*0x10 */
 954} MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE,
 955        *PTR_MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE,
 956        Mpi2EventDataSasEnclDevStatusChange_t,
 957        *pMpi2EventDataSasEnclDevStatusChange_t;
 958
 959/*SAS Enclosure Device Status Change event ReasonCode values */
 960#define MPI2_EVENT_SAS_ENCL_RC_ADDED                (0x01)
 961#define MPI2_EVENT_SAS_ENCL_RC_NOT_RESPONDING       (0x02)
 962
 963/*SAS PHY Counter Event data */
 964
 965typedef struct _MPI2_EVENT_DATA_SAS_PHY_COUNTER {
 966        U64 TimeStamp;          /*0x00 */
 967        U32 Reserved1;          /*0x08 */
 968        U8 PhyEventCode;        /*0x0C */
 969        U8 PhyNum;              /*0x0D */
 970        U16 Reserved2;          /*0x0E */
 971        U32 PhyEventInfo;       /*0x10 */
 972        U8 CounterType;         /*0x14 */
 973        U8 ThresholdWindow;     /*0x15 */
 974        U8 TimeUnits;           /*0x16 */
 975        U8 Reserved3;           /*0x17 */
 976        U32 EventThreshold;     /*0x18 */
 977        U16 ThresholdFlags;     /*0x1C */
 978        U16 Reserved4;          /*0x1E */
 979} MPI2_EVENT_DATA_SAS_PHY_COUNTER,
 980        *PTR_MPI2_EVENT_DATA_SAS_PHY_COUNTER,
 981        Mpi2EventDataSasPhyCounter_t,
 982        *pMpi2EventDataSasPhyCounter_t;
 983
 984/*use MPI2_SASPHY3_EVENT_CODE_ values from mpi2_cnfg.h
 985 *for the PhyEventCode field */
 986
 987/*use MPI2_SASPHY3_COUNTER_TYPE_ values from mpi2_cnfg.h
 988 *for the CounterType field */
 989
 990/*use MPI2_SASPHY3_TIME_UNITS_ values from mpi2_cnfg.h
 991 *for the TimeUnits field */
 992
 993/*use MPI2_SASPHY3_TFLAGS_ values from mpi2_cnfg.h
 994 *for the ThresholdFlags field */
 995
 996/*SAS Quiesce Event data */
 997
 998typedef struct _MPI2_EVENT_DATA_SAS_QUIESCE {
 999        U8 ReasonCode;          /*0x00 */
1000        U8 Reserved1;           /*0x01 */

1001        U16 Reserved2;          /*0x02 */
1002        U32 Reserved3;          /*0x04 */
1003} MPI2_EVENT_DATA_SAS_QUIESCE,
1004        *PTR_MPI2_EVENT_DATA_SAS_QUIESCE,
1005        Mpi2EventDataSasQuiesce_t, *pMpi2EventDataSasQuiesce_t;
1006
1007/*SAS Quiesce Event data ReasonCode values */
1008#define MPI2_EVENT_SAS_QUIESCE_RC_STARTED                   (0x01)
1009#define MPI2_EVENT_SAS_QUIESCE_RC_COMPLETED                 (0x02)
1010
1011/*Host Based Discovery Phy Event data */
1012
1013typedef struct _MPI2_EVENT_HBD_PHY_SAS {
1014        U8 Flags;               /*0x00 */
1015        U8 NegotiatedLinkRate;  /*0x01 */
1016        U8 PhyNum;              /*0x02 */
1017        U8 PhysicalPort;        /*0x03 */
1018        U32 Reserved1;          /*0x04 */
1019        U8 InitialFrame[28];    /*0x08 */
1020} MPI2_EVENT_HBD_PHY_SAS, *PTR_MPI2_EVENT_HBD_PHY_SAS,
1021        Mpi2EventHbdPhySas_t, *pMpi2EventHbdPhySas_t;
1022
1023/*values for the Flags field */
1024#define MPI2_EVENT_HBD_SAS_FLAGS_FRAME_VALID        (0x02)
1025#define MPI2_EVENT_HBD_SAS_FLAGS_SATA_FRAME         (0x01)
1026
1027/*use MPI2_SAS_NEG_LINK_RATE_ defines from mpi2_cnfg.h
1028 *for the NegotiatedLinkRate field */
1029
1030typedef union _MPI2_EVENT_HBD_DESCRIPTOR {
1031        MPI2_EVENT_HBD_PHY_SAS Sas;
1032} MPI2_EVENT_HBD_DESCRIPTOR, *PTR_MPI2_EVENT_HBD_DESCRIPTOR,
1033        Mpi2EventHbdDescriptor_t, *pMpi2EventHbdDescriptor_t;
1034
1035typedef struct _MPI2_EVENT_DATA_HBD_PHY {
1036        U8 DescriptorType;      /*0x00 */
1037        U8 Reserved1;           /*0x01 */
1038        U16 Reserved2;          /*0x02 */
1039        U32 Reserved3;          /*0x04 */
1040        MPI2_EVENT_HBD_DESCRIPTOR Descriptor;   /*0x08 */
1041} MPI2_EVENT_DATA_HBD_PHY, *PTR_MPI2_EVENT_DATA_HBD_PHY,
1042        Mpi2EventDataHbdPhy_t,
1043        *pMpi2EventDataMpi2EventDataHbdPhy_t;
1044
1045/*values for the DescriptorType field */
1046#define MPI2_EVENT_HBD_DT_SAS               (0x01)
1047
1048/****************************************************************************
1049* EventAck message
1050****************************************************************************/
1051
1052/*EventAck Request message */
1053typedef struct _MPI2_EVENT_ACK_REQUEST {
1054        U16 Reserved1;          /*0x00 */
1055        U8 ChainOffset;         /*0x02 */
1056        U8 Function;            /*0x03 */
1057        U16 Reserved2;          /*0x04 */
1058        U8 Reserved3;           /*0x06 */
1059        U8 MsgFlags;            /*0x07 */
1060        U8 VP_ID;               /*0x08 */
1061        U8 VF_ID;               /*0x09 */
1062        U16 Reserved4;          /*0x0A */
1063        U16 Event;              /*0x0C */
1064        U16 Reserved5;          /*0x0E */
1065        U32 EventContext;       /*0x10 */
1066} MPI2_EVENT_ACK_REQUEST, *PTR_MPI2_EVENT_ACK_REQUEST,
1067        Mpi2EventAckRequest_t, *pMpi2EventAckRequest_t;
1068
1069/*EventAck Reply message */
1070typedef struct _MPI2_EVENT_ACK_REPLY {
1071        U16 Reserved1;          /*0x00 */
1072        U8 MsgLength;           /*0x02 */
1073        U8 Function;            /*0x03 */
1074        U16 Reserved2;          /*0x04 */
1075        U8 Reserved3;           /*0x06 */
1076        U8 MsgFlags;            /*0x07 */
1077        U8 VP_ID;               /*0x08 */
1078        U8 VF_ID;               /*0x09 */
1079        U16 Reserved4;          /*0x0A */
1080        U16 Reserved5;          /*0x0C */
1081        U16 IOCStatus;          /*0x0E */
1082        U32 IOCLogInfo;         /*0x10 */
1083} MPI2_EVENT_ACK_REPLY, *PTR_MPI2_EVENT_ACK_REPLY,
1084        Mpi2EventAckReply_t, *pMpi2EventAckReply_t;
1085
1086/****************************************************************************
1087* SendHostMessage message
1088****************************************************************************/
1089
1090/*SendHostMessage Request message */
1091typedef struct _MPI2_SEND_HOST_MESSAGE_REQUEST {
1092        U16 HostDataLength;     /*0x00 */
1093        U8 ChainOffset;         /*0x02 */
1094        U8 Function;            /*0x03 */
1095        U16 Reserved1;          /*0x04 */
1096        U8 Reserved2;           /*0x06 */
1097        U8 MsgFlags;            /*0x07 */
1098        U8 VP_ID;               /*0x08 */
1099        U8 VF_ID;               /*0x09 */
1100        U16 Reserved3;          /*0x0A */
1101        U8 Reserved4;           /*0x0C */
1102        U8 DestVF_ID;           /*0x0D */
1103        U16 Reserved5;          /*0x0E */
1104        U32 Reserved6;          /*0x10 */
1105        U32 Reserved7;          /*0x14 */
1106        U32 Reserved8;          /*0x18 */
1107        U32 Reserved9;          /*0x1C */
1108        U32 Reserved10;         /*0x20 */
1109        U32 HostData[1];        /*0x24 */
1110} MPI2_SEND_HOST_MESSAGE_REQUEST,
1111        *PTR_MPI2_SEND_HOST_MESSAGE_REQUEST,
1112        Mpi2SendHostMessageRequest_t,
1113        *pMpi2SendHostMessageRequest_t;
1114
1115/*SendHostMessage Reply message */
1116typedef struct _MPI2_SEND_HOST_MESSAGE_REPLY {
1117        U16 HostDataLength;     /*0x00 */
1118        U8 MsgLength;           /*0x02 */
1119        U8 Function;            /*0x03 */
1120        U16 Reserved1;          /*0x04 */
1121        U8 Reserved2;           /*0x06 */
1122        U8 MsgFlags;            /*0x07 */
1123        U8 VP_ID;               /*0x08 */
1124        U8 VF_ID;               /*0x09 */
1125        U16 Reserved3;          /*0x0A */
1126        U16 Reserved4;          /*0x0C */
1127        U16 IOCStatus;          /*0x0E */
1128        U32 IOCLogInfo;         /*0x10 */
1129} MPI2_SEND_HOST_MESSAGE_REPLY, *PTR_MPI2_SEND_HOST_MESSAGE_REPLY,
1130        Mpi2SendHostMessageReply_t, *pMpi2SendHostMessageReply_t;
1131
1132/****************************************************************************
1133* FWDownload message
1134****************************************************************************/
1135
1136/*MPI v2.0 FWDownload Request message */
1137typedef struct _MPI2_FW_DOWNLOAD_REQUEST {
1138        U8 ImageType;           /*0x00 */
1139        U8 Reserved1;           /*0x01 */
1140        U8 ChainOffset;         /*0x02 */
1141        U8 Function;            /*0x03 */
1142        U16 Reserved2;          /*0x04 */
1143        U8 Reserved3;           /*0x06 */
1144        U8 MsgFlags;            /*0x07 */
1145        U8 VP_ID;               /*0x08 */
1146        U8 VF_ID;               /*0x09 */
1147        U16 Reserved4;          /*0x0A */
1148        U32 TotalImageSize;     /*0x0C */
1149        U32 Reserved5;          /*0x10 */
1150        MPI2_MPI_SGE_UNION SGL; /*0x14 */
1151} MPI2_FW_DOWNLOAD_REQUEST, *PTR_MPI2_FW_DOWNLOAD_REQUEST,
1152        Mpi2FWDownloadRequest, *pMpi2FWDownloadRequest;
1153
1154#define MPI2_FW_DOWNLOAD_MSGFLGS_LAST_SEGMENT   (0x01)
1155
1156#define MPI2_FW_DOWNLOAD_ITYPE_FW                   (0x01)
1157#define MPI2_FW_DOWNLOAD_ITYPE_BIOS                 (0x02)
1158#define MPI2_FW_DOWNLOAD_ITYPE_MANUFACTURING        (0x06)
1159#define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_1             (0x07)
1160#define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_2             (0x08)
1161#define MPI2_FW_DOWNLOAD_ITYPE_MEGARAID             (0x09)
1162#define MPI2_FW_DOWNLOAD_ITYPE_COMPLETE             (0x0A)
1163#define MPI2_FW_DOWNLOAD_ITYPE_COMMON_BOOT_BLOCK    (0x0B)
1164#define MPI2_FW_DOWNLOAD_ITYPE_PUBLIC_KEY           (0x0C)
1165#define MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC (0xF0)
1166
1167/*MPI v2.0 FWDownload TransactionContext Element */
1168typedef struct _MPI2_FW_DOWNLOAD_TCSGE {
1169        U8 Reserved1;           /*0x00 */
1170        U8 ContextSize;         /*0x01 */
1171        U8 DetailsLength;       /*0x02 */
1172        U8 Flags;               /*0x03 */
1173        U32 Reserved2;          /*0x04 */
1174        U32 ImageOffset;        /*0x08 */
1175        U32 ImageSize;          /*0x0C */
1176} MPI2_FW_DOWNLOAD_TCSGE, *PTR_MPI2_FW_DOWNLOAD_TCSGE,
1177        Mpi2FWDownloadTCSGE_t, *pMpi2FWDownloadTCSGE_t;
1178
1179/*MPI v2.5 FWDownload Request message */
1180typedef struct _MPI25_FW_DOWNLOAD_REQUEST {
1181        U8 ImageType;           /*0x00 */
1182        U8 Reserved1;           /*0x01 */
1183        U8 ChainOffset;         /*0x02 */
1184        U8 Function;            /*0x03 */
1185        U16 Reserved2;          /*0x04 */
1186        U8 Reserved3;           /*0x06 */
1187        U8 MsgFlags;            /*0x07 */
1188        U8 VP_ID;               /*0x08 */
1189        U8 VF_ID;               /*0x09 */
1190        U16 Reserved4;          /*0x0A */
1191        U32 TotalImageSize;     /*0x0C */
1192        U32 Reserved5;          /*0x10 */
1193        U32 Reserved6;          /*0x14 */
1194        U32 ImageOffset;        /*0x18 */
1195        U32 ImageSize;          /*0x1C */
1196        MPI25_SGE_IO_UNION SGL; /*0x20 */
1197} MPI25_FW_DOWNLOAD_REQUEST, *PTR_MPI25_FW_DOWNLOAD_REQUEST,
1198        Mpi25FWDownloadRequest, *pMpi25FWDownloadRequest;
1199
1200/*FWDownload Reply message */
1201typedef struct _MPI2_FW_DOWNLOAD_REPLY {
1202        U8 ImageType;           /*0x00 */
1203        U8 Reserved1;           /*0x01 */
1204        U8 MsgLength;           /*0x02 */
1205        U8 Function;            /*0x03 */
1206        U16 Reserved2;          /*0x04 */
1207        U8 Reserved3;           /*0x06 */
1208        U8 MsgFlags;            /*0x07 */
1209        U8 VP_ID;               /*0x08 */
1210        U8 VF_ID;               /*0x09 */
1211        U16 Reserved4;          /*0x0A */
1212        U16 Reserved5;          /*0x0C */
1213        U16 IOCStatus;          /*0x0E */
1214        U32 IOCLogInfo;         /*0x10 */
1215} MPI2_FW_DOWNLOAD_REPLY, *PTR_MPI2_FW_DOWNLOAD_REPLY,
1216        Mpi2FWDownloadReply_t, *pMpi2FWDownloadReply_t;
1217
1218/****************************************************************************
1219* FWUpload message
1220****************************************************************************/
1221
1222/*MPI v2.0 FWUpload Request message */
1223typedef struct _MPI2_FW_UPLOAD_REQUEST {
1224        U8 ImageType;           /*0x00 */
1225        U8 Reserved1;           /*0x01 */
1226        U8 ChainOffset;         /*0x02 */
1227        U8 Function;            /*0x03 */
1228        U16 Reserved2;          /*0x04 */
1229        U8 Reserved3;           /*0x06 */
1230        U8 MsgFlags;            /*0x07 */
1231        U8 VP_ID;               /*0x08 */
1232        U8 VF_ID;               /*0x09 */
1233        U16 Reserved4;          /*0x0A */
1234        U32 Reserved5;          /*0x0C */
1235        U32 Reserved6;          /*0x10 */
1236        MPI2_MPI_SGE_UNION SGL; /*0x14 */
1237} MPI2_FW_UPLOAD_REQUEST, *PTR_MPI2_FW_UPLOAD_REQUEST,
1238        Mpi2FWUploadRequest_t, *pMpi2FWUploadRequest_t;
1239
1240#define MPI2_FW_UPLOAD_ITYPE_FW_CURRENT         (0x00)
1241#define MPI2_FW_UPLOAD_ITYPE_FW_FLASH           (0x01)
1242#define MPI2_FW_UPLOAD_ITYPE_BIOS_FLASH         (0x02)
1243#define MPI2_FW_UPLOAD_ITYPE_FW_BACKUP          (0x05)
1244#define MPI2_FW_UPLOAD_ITYPE_MANUFACTURING      (0x06)
1245#define MPI2_FW_UPLOAD_ITYPE_CONFIG_1           (0x07)
1246#define MPI2_FW_UPLOAD_ITYPE_CONFIG_2           (0x08)
1247#define MPI2_FW_UPLOAD_ITYPE_MEGARAID           (0x09)
1248#define MPI2_FW_UPLOAD_ITYPE_COMPLETE           (0x0A)
1249#define MPI2_FW_UPLOAD_ITYPE_COMMON_BOOT_BLOCK  (0x0B)
1250
1251/*MPI v2.0 FWUpload TransactionContext Element */
1252typedef struct _MPI2_FW_UPLOAD_TCSGE {
1253        U8 Reserved1;           /*0x00 */
1254        U8 ContextSize;         /*0x01 */
1255        U8 DetailsLength;       /*0x02 */
1256        U8 Flags;               /*0x03 */
1257        U32 Reserved2;          /*0x04 */
1258        U32 ImageOffset;        /*0x08 */
1259        U32 ImageSize;          /*0x0C */
1260} MPI2_FW_UPLOAD_TCSGE, *PTR_MPI2_FW_UPLOAD_TCSGE,
1261        Mpi2FWUploadTCSGE_t, *pMpi2FWUploadTCSGE_t;
1262
1263/*MPI v2.5 FWUpload Request message */
1264typedef struct _MPI25_FW_UPLOAD_REQUEST {
1265        U8 ImageType;           /*0x00 */
1266        U8 Reserved1;           /*0x01 */
1267        U8 ChainOffset;         /*0x02 */
1268        U8 Function;            /*0x03 */
1269        U16 Reserved2;          /*0x04 */
1270        U8 Reserved3;           /*0x06 */
1271        U8 MsgFlags;            /*0x07 */
1272        U8 VP_ID;               /*0x08 */
1273        U8 VF_ID;               /*0x09 */
1274        U16 Reserved4;          /*0x0A */
1275        U32 Reserved5;          /*0x0C */
1276        U32 Reserved6;          /*0x10 */
1277        U32 Reserved7;          /*0x14 */
1278        U32 ImageOffset;        /*0x18 */
1279        U32 ImageSize;          /*0x1C */
1280        MPI25_SGE_IO_UNION SGL; /*0x20 */
1281} MPI25_FW_UPLOAD_REQUEST, *PTR_MPI25_FW_UPLOAD_REQUEST,
1282        Mpi25FWUploadRequest_t, *pMpi25FWUploadRequest_t;
1283
1284/*FWUpload Reply message */
1285typedef struct _MPI2_FW_UPLOAD_REPLY {
1286        U8 ImageType;           /*0x00 */
1287        U8 Reserved1;           /*0x01 */
1288        U8 MsgLength;           /*0x02 */
1289        U8 Function;            /*0x03 */
1290        U16 Reserved2;          /*0x04 */
1291        U8 Reserved3;           /*0x06 */
1292        U8 MsgFlags;            /*0x07 */
1293        U8 VP_ID;               /*0x08 */
1294        U8 VF_ID;               /*0x09 */
1295        U16 Reserved4;          /*0x0A */
1296        U16 Reserved5;          /*0x0C */
1297        U16 IOCStatus;          /*0x0E */
1298        U32 IOCLogInfo;         /*0x10 */
1299        U32 ActualImageSize;    /*0x14 */
1300} MPI2_FW_UPLOAD_REPLY, *PTR_MPI2_FW_UPLOAD_REPLY,
1301        Mpi2FWUploadReply_t, *pMPi2FWUploadReply_t;
1302
1303/*FW Image Header */
1304typedef struct _MPI2_FW_IMAGE_HEADER {
1305        U32 Signature;          /*0x00 */
1306        U32 Signature0;         /*0x04 */
1307        U32 Signature1;         /*0x08 */
1308        U32 Signature2;         /*0x0C */
1309        MPI2_VERSION_UNION MPIVersion;  /*0x10 */
1310        MPI2_VERSION_UNION FWVersion;   /*0x14 */
1311        MPI2_VERSION_UNION NVDATAVersion;       /*0x18 */
1312        MPI2_VERSION_UNION PackageVersion;      /*0x1C */
1313        U16 VendorID;           /*0x20 */
1314        U16 ProductID;          /*0x22 */
1315        U16 ProtocolFlags;      /*0x24 */
1316        U16 Reserved26;         /*0x26 */
1317        U32 IOCCapabilities;    /*0x28 */
1318        U32 ImageSize;          /*0x2C */
1319        U32 NextImageHeaderOffset;      /*0x30 */
1320        U32 Checksum;           /*0x34 */
1321        U32 Reserved38;         /*0x38 */
1322        U32 Reserved3C;         /*0x3C */
1323        U32 Reserved40;         /*0x40 */
1324        U32 Reserved44;         /*0x44 */
1325        U32 Reserved48;         /*0x48 */
1326        U32 Reserved4C;         /*0x4C */
1327        U32 Reserved50;         /*0x50 */
1328        U32 Reserved54;         /*0x54 */
1329        U32 Reserved58;         /*0x58 */
1330        U32 Reserved5C;         /*0x5C */
1331        U32 Reserved60;         /*0x60 */
1332        U32 FirmwareVersionNameWhat;    /*0x64 */
1333        U8 FirmwareVersionName[32];     /*0x68 */
1334        U32 VendorNameWhat;     /*0x88 */
1335        U8 VendorName[32];      /*0x8C */
1336        U32 PackageNameWhat;    /*0x88 */
1337        U8 PackageName[32];     /*0x8C */
1338        U32 ReservedD0;         /*0xD0 */
1339        U32 ReservedD4;         /*0xD4 */
1340        U32 ReservedD8;         /*0xD8 */
1341        U32 ReservedDC;         /*0xDC */
1342        U32 ReservedE0;         /*0xE0 */
1343        U32 ReservedE4;         /*0xE4 */
1344        U32 ReservedE8;         /*0xE8 */
1345        U32 ReservedEC;         /*0xEC */
1346        U32 ReservedF0;         /*0xF0 */
1347        U32 ReservedF4;         /*0xF4 */
1348        U32 ReservedF8;         /*0xF8 */
1349        U32 ReservedFC;         /*0xFC */
1350} MPI2_FW_IMAGE_HEADER, *PTR_MPI2_FW_IMAGE_HEADER,
1351        Mpi2FWImageHeader_t, *pMpi2FWImageHeader_t;
1352
1353/*Signature field */
1354#define MPI2_FW_HEADER_SIGNATURE_OFFSET         (0x00)
1355#define MPI2_FW_HEADER_SIGNATURE_MASK           (0xFF000000)
1356#define MPI2_FW_HEADER_SIGNATURE                (0xEA000000)
1357
1358/*Signature0 field */
1359#define MPI2_FW_HEADER_SIGNATURE0_OFFSET        (0x04)
1360#define MPI2_FW_HEADER_SIGNATURE0               (0x5AFAA55A)
1361
1362/*Signature1 field */
1363#define MPI2_FW_HEADER_SIGNATURE1_OFFSET        (0x08)
1364#define MPI2_FW_HEADER_SIGNATURE1               (0xA55AFAA5)
1365
1366/*Signature2 field */
1367#define MPI2_FW_HEADER_SIGNATURE2_OFFSET        (0x0C)
1368#define MPI2_FW_HEADER_SIGNATURE2               (0x5AA55AFA)
1369
1370/*defines for using the ProductID field */
1371#define MPI2_FW_HEADER_PID_TYPE_MASK            (0xF000)
1372#define MPI2_FW_HEADER_PID_TYPE_SAS             (0x2000)
1373
1374#define MPI2_FW_HEADER_PID_PROD_MASK                    (0x0F00)
1375#define MPI2_FW_HEADER_PID_PROD_A                       (0x0000)
1376#define MPI2_FW_HEADER_PID_PROD_TARGET_INITIATOR_SCSI   (0x0200)
1377#define MPI2_FW_HEADER_PID_PROD_IR_SCSI                 (0x0700)
1378
1379#define MPI2_FW_HEADER_PID_FAMILY_MASK          (0x00FF)
1380/*SAS ProductID Family bits */
1381#define MPI2_FW_HEADER_PID_FAMILY_2108_SAS      (0x0013)
1382#define MPI2_FW_HEADER_PID_FAMILY_2208_SAS      (0x0014)
1383#define MPI25_FW_HEADER_PID_FAMILY_3108_SAS     (0x0021)
1384
1385/*use MPI2_IOCFACTS_PROTOCOL_ defines for ProtocolFlags field */
1386
1387/*use MPI2_IOCFACTS_CAPABILITY_ defines for IOCCapabilities field */
1388
1389#define MPI2_FW_HEADER_IMAGESIZE_OFFSET         (0x2C)
1390#define MPI2_FW_HEADER_NEXTIMAGE_OFFSET         (0x30)
1391#define MPI2_FW_HEADER_VERNMHWAT_OFFSET         (0x64)
1392
1393#define MPI2_FW_HEADER_WHAT_SIGNATURE           (0x29232840)
1394
1395#define MPI2_FW_HEADER_SIZE                     (0x100)
1396
1397/*Extended Image Header */
1398typedef struct _MPI2_EXT_IMAGE_HEADER {
1399        U8 ImageType;           /*0x00 */
1400        U8 Reserved1;           /*0x01 */
1401        U16 Reserved2;          /*0x02 */
1402        U32 Checksum;           /*0x04 */
1403        U32 ImageSize;          /*0x08 */
1404        U32 NextImageHeaderOffset;      /*0x0C */
1405        U32 PackageVersion;     /*0x10 */
1406        U32 Reserved3;          /*0x14 */
1407        U32 Reserved4;          /*0x18 */
1408        U32 Reserved5;          /*0x1C */
1409        U8 IdentifyString[32];  /*0x20 */
1410} MPI2_EXT_IMAGE_HEADER, *PTR_MPI2_EXT_IMAGE_HEADER,
1411        Mpi2ExtImageHeader_t, *pMpi2ExtImageHeader_t;
1412
1413/*useful offsets */
1414#define MPI2_EXT_IMAGE_IMAGETYPE_OFFSET         (0x00)
1415#define MPI2_EXT_IMAGE_IMAGESIZE_OFFSET         (0x08)
1416#define MPI2_EXT_IMAGE_NEXTIMAGE_OFFSET         (0x0C)
1417
1418#define MPI2_EXT_IMAGE_HEADER_SIZE              (0x40)
1419
1420/*defines for the ImageType field */
1421#define MPI2_EXT_IMAGE_TYPE_UNSPECIFIED             (0x00)
1422#define MPI2_EXT_IMAGE_TYPE_FW                      (0x01)
1423#define MPI2_EXT_IMAGE_TYPE_NVDATA                  (0x03)
1424#define MPI2_EXT_IMAGE_TYPE_BOOTLOADER              (0x04)
1425#define MPI2_EXT_IMAGE_TYPE_INITIALIZATION          (0x05)
1426#define MPI2_EXT_IMAGE_TYPE_FLASH_LAYOUT            (0x06)
1427#define MPI2_EXT_IMAGE_TYPE_SUPPORTED_DEVICES       (0x07)
1428#define MPI2_EXT_IMAGE_TYPE_MEGARAID                (0x08)
1429#define MPI2_EXT_IMAGE_TYPE_ENCRYPTED_HASH          (0x09)
1430#define MPI2_EXT_IMAGE_TYPE_MIN_PRODUCT_SPECIFIC    (0x80)
1431#define MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC    (0xFF)
1432
1433#define MPI2_EXT_IMAGE_TYPE_MAX (MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC)
1434
1435/*FLASH Layout Extended Image Data */
1436
1437/*
1438 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1439 *one and check RegionsPerLayout at runtime.
1440 */
1441#ifndef MPI2_FLASH_NUMBER_OF_REGIONS
1442#define MPI2_FLASH_NUMBER_OF_REGIONS        (1)
1443#endif
1444
1445/*
1446 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1447 *one and check NumberOfLayouts at runtime.
1448 */
1449#ifndef MPI2_FLASH_NUMBER_OF_LAYOUTS
1450#define MPI2_FLASH_NUMBER_OF_LAYOUTS        (1)
1451#endif
1452
1453typedef struct _MPI2_FLASH_REGION {
1454        U8 RegionType;          /*0x00 */
1455        U8 Reserved1;           /*0x01 */
1456        U16 Reserved2;          /*0x02 */
1457        U32 RegionOffset;       /*0x04 */
1458        U32 RegionSize;         /*0x08 */
1459        U32 Reserved3;          /*0x0C */
1460} MPI2_FLASH_REGION, *PTR_MPI2_FLASH_REGION,
1461        Mpi2FlashRegion_t, *pMpi2FlashRegion_t;
1462
1463typedef struct _MPI2_FLASH_LAYOUT {
1464        U32 FlashSize;          /*0x00 */
1465        U32 Reserved1;          /*0x04 */
1466        U32 Reserved2;          /*0x08 */
1467        U32 Reserved3;          /*0x0C */
1468        MPI2_FLASH_REGION Region[MPI2_FLASH_NUMBER_OF_REGIONS]; /*0x10 */
1469} MPI2_FLASH_LAYOUT, *PTR_MPI2_FLASH_LAYOUT,
1470        Mpi2FlashLayout_t, *pMpi2FlashLayout_t;
1471
1472typedef struct _MPI2_FLASH_LAYOUT_DATA {
1473        U8 ImageRevision;       /*0x00 */
1474        U8 Reserved1;           /*0x01 */
1475        U8 SizeOfRegion;        /*0x02 */
1476        U8 Reserved2;           /*0x03 */
1477        U16 NumberOfLayouts;    /*0x04 */
1478        U16 RegionsPerLayout;   /*0x06 */
1479        U16 MinimumSectorAlignment;     /*0x08 */
1480        U16 Reserved3;          /*0x0A */
1481        U32 Reserved4;          /*0x0C */
1482        MPI2_FLASH_LAYOUT Layout[MPI2_FLASH_NUMBER_OF_LAYOUTS]; /*0x10 */
1483} MPI2_FLASH_LAYOUT_DATA, *PTR_MPI2_FLASH_LAYOUT_DATA,
1484        Mpi2FlashLayoutData_t, *pMpi2FlashLayoutData_t;
1485
1486/*defines for the RegionType field */
1487#define MPI2_FLASH_REGION_UNUSED                (0x00)
1488#define MPI2_FLASH_REGION_FIRMWARE              (0x01)
1489#define MPI2_FLASH_REGION_BIOS                  (0x02)
1490#define MPI2_FLASH_REGION_NVDATA                (0x03)
1491#define MPI2_FLASH_REGION_FIRMWARE_BACKUP       (0x05)
1492#define MPI2_FLASH_REGION_MFG_INFORMATION       (0x06)
1493#define MPI2_FLASH_REGION_CONFIG_1              (0x07)
1494#define MPI2_FLASH_REGION_CONFIG_2              (0x08)
1495#define MPI2_FLASH_REGION_MEGARAID              (0x09)
1496#define MPI2_FLASH_REGION_INIT                  (0x0A)
1497
1498/*ImageRevision */
1499#define MPI2_FLASH_LAYOUT_IMAGE_REVISION        (0x00)
1500
1501/*Supported Devices Extended Image Data */
1502
1503/*
1504 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1505 *one and check NumberOfDevices at runtime.
1506 */
1507#ifndef MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES
1508#define MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES    (1)
1509#endif
1510
1511typedef struct _MPI2_SUPPORTED_DEVICE {
1512        U16 DeviceID;           /*0x00 */
1513        U16 VendorID;           /*0x02 */
1514        U16 DeviceIDMask;       /*0x04 */
1515        U16 Reserved1;          /*0x06 */
1516        U8 LowPCIRev;           /*0x08 */
1517        U8 HighPCIRev;          /*0x09 */
1518        U16 Reserved2;          /*0x0A */
1519        U32 Reserved3;          /*0x0C */
1520} MPI2_SUPPORTED_DEVICE, *PTR_MPI2_SUPPORTED_DEVICE,
1521        Mpi2SupportedDevice_t, *pMpi2SupportedDevice_t;
1522
1523typedef struct _MPI2_SUPPORTED_DEVICES_DATA {
1524        U8 ImageRevision;       /*0x00 */
1525        U8 Reserved1;           /*0x01 */
1526        U8 NumberOfDevices;     /*0x02 */
1527        U8 Reserved2;           /*0x03 */
1528        U32 Reserved3;          /*0x04 */
1529        MPI2_SUPPORTED_DEVICE
1530        SupportedDevice[MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES];/*0x08 */
1531} MPI2_SUPPORTED_DEVICES_DATA, *PTR_MPI2_SUPPORTED_DEVICES_DATA,
1532        Mpi2SupportedDevicesData_t, *pMpi2SupportedDevicesData_t;
1533
1534/*ImageRevision */
1535#define MPI2_SUPPORTED_DEVICES_IMAGE_REVISION   (0x00)
1536
1537/*Init Extended Image Data */
1538
1539typedef struct _MPI2_INIT_IMAGE_FOOTER {
1540        U32 BootFlags;          /*0x00 */
1541        U32 ImageSize;          /*0x04 */
1542        U32 Signature0;         /*0x08 */
1543        U32 Signature1;         /*0x0C */
1544        U32 Signature2;         /*0x10 */
1545        U32 ResetVector;        /*0x14 */
1546} MPI2_INIT_IMAGE_FOOTER, *PTR_MPI2_INIT_IMAGE_FOOTER,
1547        Mpi2InitImageFooter_t, *pMpi2InitImageFooter_t;
1548
1549/*defines for the BootFlags field */
1550#define MPI2_INIT_IMAGE_BOOTFLAGS_OFFSET        (0x00)
1551
1552/*defines for the ImageSize field */
1553#define MPI2_INIT_IMAGE_IMAGESIZE_OFFSET        (0x04)
1554
1555/*defines for the Signature0 field */
1556#define MPI2_INIT_IMAGE_SIGNATURE0_OFFSET       (0x08)
1557#define MPI2_INIT_IMAGE_SIGNATURE0              (0x5AA55AEA)
1558
1559/*defines for the Signature1 field */
1560#define MPI2_INIT_IMAGE_SIGNATURE1_OFFSET       (0x0C)
1561#define MPI2_INIT_IMAGE_SIGNATURE1              (0xA55AEAA5)
1562
1563/*defines for the Signature2 field */
1564#define MPI2_INIT_IMAGE_SIGNATURE2_OFFSET       (0x10)
1565#define MPI2_INIT_IMAGE_SIGNATURE2              (0x5AEAA55A)
1566
1567/*Signature fields as individual bytes */
1568#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_0        (0xEA)
1569#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_1        (0x5A)
1570#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_2        (0xA5)
1571#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_3        (0x5A)
1572
1573#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_4        (0xA5)
1574#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_5        (0xEA)
1575#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_6        (0x5A)
1576#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_7        (0xA5)
1577
1578#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_8        (0x5A)
1579#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_9        (0xA5)
1580#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_A        (0xEA)
1581#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_B        (0x5A)
1582
1583/*defines for the ResetVector field */
1584#define MPI2_INIT_IMAGE_RESETVECTOR_OFFSET      (0x14)
1585
1586
1587/* Encrypted Hash Extended Image Data */
1588
1589typedef struct _MPI25_ENCRYPTED_HASH_ENTRY {
1590        U8              HashImageType;          /* 0x00 */
1591        U8              HashAlgorithm;          /* 0x01 */
1592        U8              EncryptionAlgorithm;    /* 0x02 */
1593        U8              Reserved1;              /* 0x03 */
1594        U32             Reserved2;              /* 0x04 */
1595        U32             EncryptedHash[1];       /* 0x08 */ /* variable length */
1596} MPI25_ENCRYPTED_HASH_ENTRY, *PTR_MPI25_ENCRYPTED_HASH_ENTRY,
1597Mpi25EncryptedHashEntry_t, *pMpi25EncryptedHashEntry_t;
1598
1599/* values for HashImageType */
1600#define MPI25_HASH_IMAGE_TYPE_UNUSED            (0x00)
1601#define MPI25_HASH_IMAGE_TYPE_FIRMWARE          (0x01)
1602#define MPI25_HASH_IMAGE_TYPE_BIOS              (0x02)
1603
1604/* values for HashAlgorithm */
1605#define MPI25_HASH_ALGORITHM_UNUSED             (0x00)
1606#define MPI25_HASH_ALGORITHM_SHA256             (0x01)
1607
1608/* values for EncryptionAlgorithm */
1609#define MPI25_ENCRYPTION_ALG_UNUSED             (0x00)
1610#define MPI25_ENCRYPTION_ALG_RSA256             (0x01)
1611
1612typedef struct _MPI25_ENCRYPTED_HASH_DATA {
1613        U8                              ImageVersion;           /* 0x00 */
1614        U8                              NumHash;                /* 0x01 */
1615        U16                             Reserved1;              /* 0x02 */
1616        U32                             Reserved2;              /* 0x04 */
1617        MPI25_ENCRYPTED_HASH_ENTRY      EncryptedHashEntry[1];  /* 0x08 */
1618} MPI25_ENCRYPTED_HASH_DATA, *PTR_MPI25_ENCRYPTED_HASH_DATA,
1619Mpi25EncryptedHashData_t, *pMpi25EncryptedHashData_t;
1620
1621
1622
1623/****************************************************************************
1624* PowerManagementControl message
1625****************************************************************************/
1626
1627/*PowerManagementControl Request message */
1628typedef struct _MPI2_PWR_MGMT_CONTROL_REQUEST {
1629        U8 Feature;             /*0x00 */
1630        U8 Reserved1;           /*0x01 */
1631        U8 ChainOffset;         /*0x02 */
1632        U8 Function;            /*0x03 */
1633        U16 Reserved2;          /*0x04 */
1634        U8 Reserved3;           /*0x06 */
1635        U8 MsgFlags;            /*0x07 */
1636        U8 VP_ID;               /*0x08 */
1637        U8 VF_ID;               /*0x09 */
1638        U16 Reserved4;          /*0x0A */
1639        U8 Parameter1;          /*0x0C */
1640        U8 Parameter2;          /*0x0D */
1641        U8 Parameter3;          /*0x0E */
1642        U8 Parameter4;          /*0x0F */
1643        U32 Reserved5;          /*0x10 */
1644        U32 Reserved6;          /*0x14 */
1645} MPI2_PWR_MGMT_CONTROL_REQUEST, *PTR_MPI2_PWR_MGMT_CONTROL_REQUEST,
1646        Mpi2PwrMgmtControlRequest_t, *pMpi2PwrMgmtControlRequest_t;
1647
1648/*defines for the Feature field */
1649#define MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND       (0x01)
1650#define MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION   (0x02)
1651#define MPI2_PM_CONTROL_FEATURE_PCIE_LINK               (0x03)  /*obsolete */
1652#define MPI2_PM_CONTROL_FEATURE_IOC_SPEED               (0x04)
1653#define MPI2_PM_CONTROL_FEATURE_GLOBAL_PWR_MGMT_MODE    (0x05)
1654#define MPI2_PM_CONTROL_FEATURE_MIN_PRODUCT_SPECIFIC    (0x80)
1655#define MPI2_PM_CONTROL_FEATURE_MAX_PRODUCT_SPECIFIC    (0xFF)
1656
1657/*parameter usage for the MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND Feature */
1658/*Parameter1 contains a PHY number */
1659/*Parameter2 indicates power condition action using these defines */
1660#define MPI2_PM_CONTROL_PARAM2_PARTIAL                  (0x01)
1661#define MPI2_PM_CONTROL_PARAM2_SLUMBER                  (0x02)
1662#define MPI2_PM_CONTROL_PARAM2_EXIT_PWR_MGMT            (0x03)
1663/*Parameter3 and Parameter4 are reserved */
1664
1665/*parameter usage for the MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION
1666 * Feature */
1667/*Parameter1 contains SAS port width modulation group number */
1668/*Parameter2 indicates IOC action using these defines */
1669#define MPI2_PM_CONTROL_PARAM2_REQUEST_OWNERSHIP        (0x01)
1670#define MPI2_PM_CONTROL_PARAM2_CHANGE_MODULATION        (0x02)
1671#define MPI2_PM_CONTROL_PARAM2_RELINQUISH_OWNERSHIP     (0x03)
1672/*Parameter3 indicates desired modulation level using these defines */
1673#define MPI2_PM_CONTROL_PARAM3_25_PERCENT               (0x00)
1674#define MPI2_PM_CONTROL_PARAM3_50_PERCENT               (0x01)
1675#define MPI2_PM_CONTROL_PARAM3_75_PERCENT               (0x02)
1676#define MPI2_PM_CONTROL_PARAM3_100_PERCENT              (0x03)
1677/*Parameter4 is reserved */
1678
1679/*this next set (_PCIE_LINK) is obsolete */
1680/*parameter usage for the MPI2_PM_CONTROL_FEATURE_PCIE_LINK Feature */
1681/*Parameter1 indicates desired PCIe link speed using these defines */
1682#define MPI2_PM_CONTROL_PARAM1_PCIE_2_5_GBPS            (0x00)  /*obsolete */
1683#define MPI2_PM_CONTROL_PARAM1_PCIE_5_0_GBPS            (0x01)  /*obsolete */
1684#define MPI2_PM_CONTROL_PARAM1_PCIE_8_0_GBPS            (0x02)  /*obsolete */
1685/*Parameter2 indicates desired PCIe link width using these defines */
1686#define MPI2_PM_CONTROL_PARAM2_WIDTH_X1                 (0x01)  /*obsolete */
1687#define MPI2_PM_CONTROL_PARAM2_WIDTH_X2                 (0x02)  /*obsolete */
1688#define MPI2_PM_CONTROL_PARAM2_WIDTH_X4                 (0x04)  /*obsolete */
1689#define MPI2_PM_CONTROL_PARAM2_WIDTH_X8                 (0x08)  /*obsolete */
1690/*Parameter3 and Parameter4 are reserved */
1691
1692/*parameter usage for the MPI2_PM_CONTROL_FEATURE_IOC_SPEED Feature */
1693/*Parameter1 indicates desired IOC hardware clock speed using these defines */
1694#define MPI2_PM_CONTROL_PARAM1_FULL_IOC_SPEED           (0x01)
1695#define MPI2_PM_CONTROL_PARAM1_HALF_IOC_SPEED           (0x02)
1696#define MPI2_PM_CONTROL_PARAM1_QUARTER_IOC_SPEED        (0x04)
1697#define MPI2_PM_CONTROL_PARAM1_EIGHTH_IOC_SPEED         (0x08)
1698/*Parameter2, Parameter3, and Parameter4 are reserved */
1699
1700/*parameter usage for the MPI2_PM_CONTROL_FEATURE_GLOBAL_PWR_MGMT_MODE Feature*/
1701/*Parameter1 indicates host action regarding global power management mode */
1702#define MPI2_PM_CONTROL_PARAM1_TAKE_CONTROL             (0x01)
1703#define MPI2_PM_CONTROL_PARAM1_CHANGE_GLOBAL_MODE       (0x02)
1704#define MPI2_PM_CONTROL_PARAM1_RELEASE_CONTROL          (0x03)
1705/*Parameter2 indicates the requested global power management mode */
1706#define MPI2_PM_CONTROL_PARAM2_FULL_PWR_PERF            (0x01)
1707#define MPI2_PM_CONTROL_PARAM2_REDUCED_PWR_PERF         (0x08)
1708#define MPI2_PM_CONTROL_PARAM2_STANDBY                  (0x40)
1709/*Parameter3 and Parameter4 are reserved */
1710
1711/*PowerManagementControl Reply message */
1712typedef struct _MPI2_PWR_MGMT_CONTROL_REPLY {
1713        U8 Feature;             /*0x00 */
1714        U8 Reserved1;           /*0x01 */
1715        U8 MsgLength;           /*0x02 */
1716        U8 Function;            /*0x03 */
1717        U16 Reserved2;          /*0x04 */
1718        U8 Reserved3;           /*0x06 */
1719        U8 MsgFlags;            /*0x07 */
1720        U8 VP_ID;               /*0x08 */
1721        U8 VF_ID;               /*0x09 */
1722        U16 Reserved4;          /*0x0A */
1723        U16 Reserved5;          /*0x0C */
1724        U16 IOCStatus;          /*0x0E */
1725        U32 IOCLogInfo;         /*0x10 */
1726} MPI2_PWR_MGMT_CONTROL_REPLY, *PTR_MPI2_PWR_MGMT_CONTROL_REPLY,
1727        Mpi2PwrMgmtControlReply_t, *pMpi2PwrMgmtControlReply_t;
1728
1729#endif
1730