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7#include "qla_def.h"
8#include "qla_target.h"
9
10#include <linux/delay.h>
11#include <linux/slab.h>
12#include <scsi/scsi_tcq.h>
13#include <scsi/scsi_bsg_fc.h>
14#include <scsi/scsi_eh.h>
15
16static void qla2x00_mbx_completion(scsi_qla_host_t *, uint16_t);
17static void qla2x00_status_entry(scsi_qla_host_t *, struct rsp_que *, void *);
18static void qla2x00_status_cont_entry(struct rsp_que *, sts_cont_entry_t *);
19static void qla2x00_error_entry(scsi_qla_host_t *, struct rsp_que *,
20 sts_entry_t *);
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22
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30
31irqreturn_t
32qla2100_intr_handler(int irq, void *dev_id)
33{
34 scsi_qla_host_t *vha;
35 struct qla_hw_data *ha;
36 struct device_reg_2xxx __iomem *reg;
37 int status;
38 unsigned long iter;
39 uint16_t hccr;
40 uint16_t mb[4];
41 struct rsp_que *rsp;
42 unsigned long flags;
43
44 rsp = (struct rsp_que *) dev_id;
45 if (!rsp) {
46 ql_log(ql_log_info, NULL, 0x505d,
47 "%s: NULL response queue pointer.\n", __func__);
48 return (IRQ_NONE);
49 }
50
51 ha = rsp->hw;
52 reg = &ha->iobase->isp;
53 status = 0;
54
55 spin_lock_irqsave(&ha->hardware_lock, flags);
56 vha = pci_get_drvdata(ha->pdev);
57 for (iter = 50; iter--; ) {
58 hccr = RD_REG_WORD(®->hccr);
59 if (qla2x00_check_reg16_for_disconnect(vha, hccr))
60 break;
61 if (hccr & HCCR_RISC_PAUSE) {
62 if (pci_channel_offline(ha->pdev))
63 break;
64
65
66
67
68
69
70 WRT_REG_WORD(®->hccr, HCCR_RESET_RISC);
71 RD_REG_WORD(®->hccr);
72
73 ha->isp_ops->fw_dump(vha, 1);
74 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
75 break;
76 } else if ((RD_REG_WORD(®->istatus) & ISR_RISC_INT) == 0)
77 break;
78
79 if (RD_REG_WORD(®->semaphore) & BIT_0) {
80 WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT);
81 RD_REG_WORD(®->hccr);
82
83
84 mb[0] = RD_MAILBOX_REG(ha, reg, 0);
85 if (mb[0] > 0x3fff && mb[0] < 0x8000) {
86 qla2x00_mbx_completion(vha, mb[0]);
87 status |= MBX_INTERRUPT;
88 } else if (mb[0] > 0x7fff && mb[0] < 0xc000) {
89 mb[1] = RD_MAILBOX_REG(ha, reg, 1);
90 mb[2] = RD_MAILBOX_REG(ha, reg, 2);
91 mb[3] = RD_MAILBOX_REG(ha, reg, 3);
92 qla2x00_async_event(vha, rsp, mb);
93 } else {
94
95 ql_dbg(ql_dbg_async, vha, 0x5025,
96 "Unrecognized interrupt type (%d).\n",
97 mb[0]);
98 }
99
100 WRT_REG_WORD(®->semaphore, 0);
101 RD_REG_WORD(®->semaphore);
102 } else {
103 qla2x00_process_response_queue(rsp);
104
105 WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT);
106 RD_REG_WORD(®->hccr);
107 }
108 }
109 qla2x00_handle_mbx_completion(ha, status);
110 spin_unlock_irqrestore(&ha->hardware_lock, flags);
111
112 return (IRQ_HANDLED);
113}
114
115bool
116qla2x00_check_reg32_for_disconnect(scsi_qla_host_t *vha, uint32_t reg)
117{
118
119 if (reg == 0xffffffff && !pci_channel_offline(vha->hw->pdev)) {
120 if (!test_and_set_bit(PFLG_DISCONNECTED, &vha->pci_flags) &&
121 !test_bit(PFLG_DRIVER_REMOVING, &vha->pci_flags) &&
122 !test_bit(PFLG_DRIVER_PROBING, &vha->pci_flags)) {
123
124
125
126
127
128 schedule_work(&vha->hw->board_disable);
129 }
130 return true;
131 } else
132 return false;
133}
134
135bool
136qla2x00_check_reg16_for_disconnect(scsi_qla_host_t *vha, uint16_t reg)
137{
138 return qla2x00_check_reg32_for_disconnect(vha, 0xffff0000 | reg);
139}
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149
150irqreturn_t
151qla2300_intr_handler(int irq, void *dev_id)
152{
153 scsi_qla_host_t *vha;
154 struct device_reg_2xxx __iomem *reg;
155 int status;
156 unsigned long iter;
157 uint32_t stat;
158 uint16_t hccr;
159 uint16_t mb[4];
160 struct rsp_que *rsp;
161 struct qla_hw_data *ha;
162 unsigned long flags;
163
164 rsp = (struct rsp_que *) dev_id;
165 if (!rsp) {
166 ql_log(ql_log_info, NULL, 0x5058,
167 "%s: NULL response queue pointer.\n", __func__);
168 return (IRQ_NONE);
169 }
170
171 ha = rsp->hw;
172 reg = &ha->iobase->isp;
173 status = 0;
174
175 spin_lock_irqsave(&ha->hardware_lock, flags);
176 vha = pci_get_drvdata(ha->pdev);
177 for (iter = 50; iter--; ) {
178 stat = RD_REG_DWORD(®->u.isp2300.host_status);
179 if (qla2x00_check_reg32_for_disconnect(vha, stat))
180 break;
181 if (stat & HSR_RISC_PAUSED) {
182 if (unlikely(pci_channel_offline(ha->pdev)))
183 break;
184
185 hccr = RD_REG_WORD(®->hccr);
186
187 if (hccr & (BIT_15 | BIT_13 | BIT_11 | BIT_8))
188 ql_log(ql_log_warn, vha, 0x5026,
189 "Parity error -- HCCR=%x, Dumping "
190 "firmware.\n", hccr);
191 else
192 ql_log(ql_log_warn, vha, 0x5027,
193 "RISC paused -- HCCR=%x, Dumping "
194 "firmware.\n", hccr);
195
196
197
198
199
200
201 WRT_REG_WORD(®->hccr, HCCR_RESET_RISC);
202 RD_REG_WORD(®->hccr);
203
204 ha->isp_ops->fw_dump(vha, 1);
205 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
206 break;
207 } else if ((stat & HSR_RISC_INT) == 0)
208 break;
209
210 switch (stat & 0xff) {
211 case 0x1:
212 case 0x2:
213 case 0x10:
214 case 0x11:
215 qla2x00_mbx_completion(vha, MSW(stat));
216 status |= MBX_INTERRUPT;
217
218
219 WRT_REG_WORD(®->semaphore, 0);
220 break;
221 case 0x12:
222 mb[0] = MSW(stat);
223 mb[1] = RD_MAILBOX_REG(ha, reg, 1);
224 mb[2] = RD_MAILBOX_REG(ha, reg, 2);
225 mb[3] = RD_MAILBOX_REG(ha, reg, 3);
226 qla2x00_async_event(vha, rsp, mb);
227 break;
228 case 0x13:
229 qla2x00_process_response_queue(rsp);
230 break;
231 case 0x15:
232 mb[0] = MBA_CMPLT_1_16BIT;
233 mb[1] = MSW(stat);
234 qla2x00_async_event(vha, rsp, mb);
235 break;
236 case 0x16:
237 mb[0] = MBA_SCSI_COMPLETION;
238 mb[1] = MSW(stat);
239 mb[2] = RD_MAILBOX_REG(ha, reg, 2);
240 qla2x00_async_event(vha, rsp, mb);
241 break;
242 default:
243 ql_dbg(ql_dbg_async, vha, 0x5028,
244 "Unrecognized interrupt type (%d).\n", stat & 0xff);
245 break;
246 }
247 WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT);
248 RD_REG_WORD_RELAXED(®->hccr);
249 }
250 qla2x00_handle_mbx_completion(ha, status);
251 spin_unlock_irqrestore(&ha->hardware_lock, flags);
252
253 return (IRQ_HANDLED);
254}
255
256
257
258
259
260
261static void
262qla2x00_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0)
263{
264 uint16_t cnt;
265 uint32_t mboxes;
266 uint16_t __iomem *wptr;
267 struct qla_hw_data *ha = vha->hw;
268 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
269
270
271 mboxes = (1 << ha->mbx_count) - 1;
272 if (!ha->mcp)
273 ql_dbg(ql_dbg_async, vha, 0x5001, "MBX pointer ERROR.\n");
274 else
275 mboxes = ha->mcp->in_mb;
276
277
278 ha->flags.mbox_int = 1;
279 ha->mailbox_out[0] = mb0;
280 mboxes >>= 1;
281 wptr = (uint16_t __iomem *)MAILBOX_REG(ha, reg, 1);
282
283 for (cnt = 1; cnt < ha->mbx_count; cnt++) {
284 if (IS_QLA2200(ha) && cnt == 8)
285 wptr = (uint16_t __iomem *)MAILBOX_REG(ha, reg, 8);
286 if ((cnt == 4 || cnt == 5) && (mboxes & BIT_0))
287 ha->mailbox_out[cnt] = qla2x00_debounce_register(wptr);
288 else if (mboxes & BIT_0)
289 ha->mailbox_out[cnt] = RD_REG_WORD(wptr);
290
291 wptr++;
292 mboxes >>= 1;
293 }
294}
295
296static void
297qla81xx_idc_event(scsi_qla_host_t *vha, uint16_t aen, uint16_t descr)
298{
299 static char *event[] =
300 { "Complete", "Request Notification", "Time Extension" };
301 int rval;
302 struct device_reg_24xx __iomem *reg24 = &vha->hw->iobase->isp24;
303 struct device_reg_82xx __iomem *reg82 = &vha->hw->iobase->isp82;
304 uint16_t __iomem *wptr;
305 uint16_t cnt, timeout, mb[QLA_IDC_ACK_REGS];
306
307
308 if (IS_QLA81XX(vha->hw) || IS_QLA83XX(vha->hw))
309 wptr = (uint16_t __iomem *)®24->mailbox1;
310 else if (IS_QLA8044(vha->hw))
311 wptr = (uint16_t __iomem *)®82->mailbox_out[1];
312 else
313 return;
314
315 for (cnt = 0; cnt < QLA_IDC_ACK_REGS; cnt++, wptr++)
316 mb[cnt] = RD_REG_WORD(wptr);
317
318 ql_dbg(ql_dbg_async, vha, 0x5021,
319 "Inter-Driver Communication %s -- "
320 "%04x %04x %04x %04x %04x %04x %04x.\n",
321 event[aen & 0xff], mb[0], mb[1], mb[2], mb[3],
322 mb[4], mb[5], mb[6]);
323 switch (aen) {
324
325 case MBA_IDC_COMPLETE:
326 if (mb[1] >> 15) {
327 vha->hw->flags.idc_compl_status = 1;
328 if (vha->hw->notify_dcbx_comp && !vha->vp_idx)
329 complete(&vha->hw->dcbx_comp);
330 }
331 break;
332
333 case MBA_IDC_NOTIFY:
334
335 timeout = (descr >> 8) & 0xf;
336 ql_dbg(ql_dbg_async, vha, 0x5022,
337 "%lu Inter-Driver Communication %s -- ACK timeout=%d.\n",
338 vha->host_no, event[aen & 0xff], timeout);
339
340 if (!timeout)
341 return;
342 rval = qla2x00_post_idc_ack_work(vha, mb);
343 if (rval != QLA_SUCCESS)
344 ql_log(ql_log_warn, vha, 0x5023,
345 "IDC failed to post ACK.\n");
346 break;
347 case MBA_IDC_TIME_EXT:
348 vha->hw->idc_extend_tmo = descr;
349 ql_dbg(ql_dbg_async, vha, 0x5087,
350 "%lu Inter-Driver Communication %s -- "
351 "Extend timeout by=%d.\n",
352 vha->host_no, event[aen & 0xff], vha->hw->idc_extend_tmo);
353 break;
354 }
355}
356
357#define LS_UNKNOWN 2
358const char *
359qla2x00_get_link_speed_str(struct qla_hw_data *ha, uint16_t speed)
360{
361 static const char *const link_speeds[] = {
362 "1", "2", "?", "4", "8", "16", "32", "10"
363 };
364#define QLA_LAST_SPEED 7
365
366 if (IS_QLA2100(ha) || IS_QLA2200(ha))
367 return link_speeds[0];
368 else if (speed == 0x13)
369 return link_speeds[QLA_LAST_SPEED];
370 else if (speed < QLA_LAST_SPEED)
371 return link_speeds[speed];
372 else
373 return link_speeds[LS_UNKNOWN];
374}
375
376static void
377qla83xx_handle_8200_aen(scsi_qla_host_t *vha, uint16_t *mb)
378{
379 struct qla_hw_data *ha = vha->hw;
380
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391
392 ql_dbg(ql_dbg_async, vha, 0x506b, "AEN Code: mb[0] = 0x%x AEN reason: "
393 "mb[1] = 0x%x PH-status1: mb[2] = 0x%x PH-status1: mb[6] = 0x%x.\n",
394 mb[0], mb[1], mb[2], mb[6]);
395 ql_dbg(ql_dbg_async, vha, 0x506c, "PH-status2: mb[3] = 0x%x "
396 "PH-status2: mb[7] = 0x%x Device-State: mb[4] = 0x%x "
397 "Drv-Presence: mb[5] = 0x%x.\n", mb[3], mb[7], mb[4], mb[5]);
398
399 if (mb[1] & (IDC_PEG_HALT_STATUS_CHANGE | IDC_NIC_FW_REPORTED_FAILURE |
400 IDC_HEARTBEAT_FAILURE)) {
401 ha->flags.nic_core_hung = 1;
402 ql_log(ql_log_warn, vha, 0x5060,
403 "83XX: F/W Error Reported: Check if reset required.\n");
404
405 if (mb[1] & IDC_PEG_HALT_STATUS_CHANGE) {
406 uint32_t protocol_engine_id, fw_err_code, err_level;
407
408
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421 protocol_engine_id = (mb[2] & 0xff);
422 fw_err_code = (((mb[2] & 0xff00) >> 8) |
423 ((mb[6] & 0x1fff) << 8));
424 err_level = ((mb[6] & 0xe000) >> 13);
425 ql_log(ql_log_warn, vha, 0x5061, "PegHalt Status-1 "
426 "Register: protocol_engine_id=0x%x "
427 "fw_err_code=0x%x err_level=0x%x.\n",
428 protocol_engine_id, fw_err_code, err_level);
429 ql_log(ql_log_warn, vha, 0x5062, "PegHalt Status-2 "
430 "Register: 0x%x%x.\n", mb[7], mb[3]);
431 if (err_level == ERR_LEVEL_NON_FATAL) {
432 ql_log(ql_log_warn, vha, 0x5063,
433 "Not a fatal error, f/w has recovered "
434 "iteself.\n");
435 } else if (err_level == ERR_LEVEL_RECOVERABLE_FATAL) {
436 ql_log(ql_log_fatal, vha, 0x5064,
437 "Recoverable Fatal error: Chip reset "
438 "required.\n");
439 qla83xx_schedule_work(vha,
440 QLA83XX_NIC_CORE_RESET);
441 } else if (err_level == ERR_LEVEL_UNRECOVERABLE_FATAL) {
442 ql_log(ql_log_fatal, vha, 0x5065,
443 "Unrecoverable Fatal error: Set FAILED "
444 "state, reboot required.\n");
445 qla83xx_schedule_work(vha,
446 QLA83XX_NIC_CORE_UNRECOVERABLE);
447 }
448 }
449
450 if (mb[1] & IDC_NIC_FW_REPORTED_FAILURE) {
451 uint16_t peg_fw_state, nw_interface_link_up;
452 uint16_t nw_interface_signal_detect, sfp_status;
453 uint16_t htbt_counter, htbt_monitor_enable;
454 uint16_t sfp_additonal_info, sfp_multirate;
455 uint16_t sfp_tx_fault, link_speed, dcbx_status;
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488 peg_fw_state = (mb[2] & 0x00ff);
489 nw_interface_link_up = ((mb[2] & 0x0100) >> 8);
490 nw_interface_signal_detect = ((mb[2] & 0x0200) >> 9);
491 sfp_status = ((mb[2] & 0x0c00) >> 10);
492 htbt_counter = ((mb[2] & 0x7000) >> 12);
493 htbt_monitor_enable = ((mb[2] & 0x8000) >> 15);
494 sfp_additonal_info = (mb[6] & 0x0003);
495 sfp_multirate = ((mb[6] & 0x0004) >> 2);
496 sfp_tx_fault = ((mb[6] & 0x0008) >> 3);
497 link_speed = ((mb[6] & 0x0070) >> 4);
498 dcbx_status = ((mb[6] & 0x7000) >> 12);
499
500 ql_log(ql_log_warn, vha, 0x5066,
501 "Peg-to-Fc Status Register:\n"
502 "peg_fw_state=0x%x, nw_interface_link_up=0x%x, "
503 "nw_interface_signal_detect=0x%x"
504 "\nsfp_statis=0x%x.\n ", peg_fw_state,
505 nw_interface_link_up, nw_interface_signal_detect,
506 sfp_status);
507 ql_log(ql_log_warn, vha, 0x5067,
508 "htbt_counter=0x%x, htbt_monitor_enable=0x%x, "
509 "sfp_additonal_info=0x%x, sfp_multirate=0x%x.\n ",
510 htbt_counter, htbt_monitor_enable,
511 sfp_additonal_info, sfp_multirate);
512 ql_log(ql_log_warn, vha, 0x5068,
513 "sfp_tx_fault=0x%x, link_state=0x%x, "
514 "dcbx_status=0x%x.\n", sfp_tx_fault, link_speed,
515 dcbx_status);
516
517 qla83xx_schedule_work(vha, QLA83XX_NIC_CORE_RESET);
518 }
519
520 if (mb[1] & IDC_HEARTBEAT_FAILURE) {
521 ql_log(ql_log_warn, vha, 0x5069,
522 "Heartbeat Failure encountered, chip reset "
523 "required.\n");
524
525 qla83xx_schedule_work(vha, QLA83XX_NIC_CORE_RESET);
526 }
527 }
528
529 if (mb[1] & IDC_DEVICE_STATE_CHANGE) {
530 ql_log(ql_log_info, vha, 0x506a,
531 "IDC Device-State changed = 0x%x.\n", mb[4]);
532 if (ha->flags.nic_core_reset_owner)
533 return;
534 qla83xx_schedule_work(vha, MBA_IDC_AEN);
535 }
536}
537
538int
539qla2x00_is_a_vp_did(scsi_qla_host_t *vha, uint32_t rscn_entry)
540{
541 struct qla_hw_data *ha = vha->hw;
542 scsi_qla_host_t *vp;
543 uint32_t vp_did;
544 unsigned long flags;
545 int ret = 0;
546
547 if (!ha->num_vhosts)
548 return ret;
549
550 spin_lock_irqsave(&ha->vport_slock, flags);
551 list_for_each_entry(vp, &ha->vp_list, list) {
552 vp_did = vp->d_id.b24;
553 if (vp_did == rscn_entry) {
554 ret = 1;
555 break;
556 }
557 }
558 spin_unlock_irqrestore(&ha->vport_slock, flags);
559
560 return ret;
561}
562
563static inline fc_port_t *
564qla2x00_find_fcport_by_loopid(scsi_qla_host_t *vha, uint16_t loop_id)
565{
566 fc_port_t *fcport;
567
568 list_for_each_entry(fcport, &vha->vp_fcports, list)
569 if (fcport->loop_id == loop_id)
570 return fcport;
571 return NULL;
572}
573
574
575
576
577
578
579void
580qla2x00_async_event(scsi_qla_host_t *vha, struct rsp_que *rsp, uint16_t *mb)
581{
582 uint16_t handle_cnt;
583 uint16_t cnt, mbx;
584 uint32_t handles[5];
585 struct qla_hw_data *ha = vha->hw;
586 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
587 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
588 struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82;
589 uint32_t rscn_entry, host_pid;
590 unsigned long flags;
591 fc_port_t *fcport = NULL;
592
593
594 handle_cnt = 0;
595 if (IS_CNA_CAPABLE(ha))
596 goto skip_rio;
597 switch (mb[0]) {
598 case MBA_SCSI_COMPLETION:
599 handles[0] = le32_to_cpu((uint32_t)((mb[2] << 16) | mb[1]));
600 handle_cnt = 1;
601 break;
602 case MBA_CMPLT_1_16BIT:
603 handles[0] = mb[1];
604 handle_cnt = 1;
605 mb[0] = MBA_SCSI_COMPLETION;
606 break;
607 case MBA_CMPLT_2_16BIT:
608 handles[0] = mb[1];
609 handles[1] = mb[2];
610 handle_cnt = 2;
611 mb[0] = MBA_SCSI_COMPLETION;
612 break;
613 case MBA_CMPLT_3_16BIT:
614 handles[0] = mb[1];
615 handles[1] = mb[2];
616 handles[2] = mb[3];
617 handle_cnt = 3;
618 mb[0] = MBA_SCSI_COMPLETION;
619 break;
620 case MBA_CMPLT_4_16BIT:
621 handles[0] = mb[1];
622 handles[1] = mb[2];
623 handles[2] = mb[3];
624 handles[3] = (uint32_t)RD_MAILBOX_REG(ha, reg, 6);
625 handle_cnt = 4;
626 mb[0] = MBA_SCSI_COMPLETION;
627 break;
628 case MBA_CMPLT_5_16BIT:
629 handles[0] = mb[1];
630 handles[1] = mb[2];
631 handles[2] = mb[3];
632 handles[3] = (uint32_t)RD_MAILBOX_REG(ha, reg, 6);
633 handles[4] = (uint32_t)RD_MAILBOX_REG(ha, reg, 7);
634 handle_cnt = 5;
635 mb[0] = MBA_SCSI_COMPLETION;
636 break;
637 case MBA_CMPLT_2_32BIT:
638 handles[0] = le32_to_cpu((uint32_t)((mb[2] << 16) | mb[1]));
639 handles[1] = le32_to_cpu(
640 ((uint32_t)(RD_MAILBOX_REG(ha, reg, 7) << 16)) |
641 RD_MAILBOX_REG(ha, reg, 6));
642 handle_cnt = 2;
643 mb[0] = MBA_SCSI_COMPLETION;
644 break;
645 default:
646 break;
647 }
648skip_rio:
649 switch (mb[0]) {
650 case MBA_SCSI_COMPLETION:
651 if (!vha->flags.online)
652 break;
653
654 for (cnt = 0; cnt < handle_cnt; cnt++)
655 qla2x00_process_completed_request(vha, rsp->req,
656 handles[cnt]);
657 break;
658
659 case MBA_RESET:
660 ql_dbg(ql_dbg_async, vha, 0x5002,
661 "Asynchronous RESET.\n");
662
663 set_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
664 break;
665
666 case MBA_SYSTEM_ERR:
667 mbx = (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha)) ?
668 RD_REG_WORD(®24->mailbox7) : 0;
669 ql_log(ql_log_warn, vha, 0x5003,
670 "ISP System Error - mbx1=%xh mbx2=%xh mbx3=%xh "
671 "mbx7=%xh.\n", mb[1], mb[2], mb[3], mbx);
672
673 ha->isp_ops->fw_dump(vha, 1);
674
675 if (IS_FWI2_CAPABLE(ha)) {
676 if (mb[1] == 0 && mb[2] == 0) {
677 ql_log(ql_log_fatal, vha, 0x5004,
678 "Unrecoverable Hardware Error: adapter "
679 "marked OFFLINE!\n");
680 vha->flags.online = 0;
681 vha->device_flags |= DFLG_DEV_FAILED;
682 } else {
683
684 if ((mbx & MBX_3) && (ha->port_no == 0))
685 set_bit(MPI_RESET_NEEDED,
686 &vha->dpc_flags);
687
688 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
689 }
690 } else if (mb[1] == 0) {
691 ql_log(ql_log_fatal, vha, 0x5005,
692 "Unrecoverable Hardware Error: adapter marked "
693 "OFFLINE!\n");
694 vha->flags.online = 0;
695 vha->device_flags |= DFLG_DEV_FAILED;
696 } else
697 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
698 break;
699
700 case MBA_REQ_TRANSFER_ERR:
701 ql_log(ql_log_warn, vha, 0x5006,
702 "ISP Request Transfer Error (%x).\n", mb[1]);
703
704 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
705 break;
706
707 case MBA_RSP_TRANSFER_ERR:
708 ql_log(ql_log_warn, vha, 0x5007,
709 "ISP Response Transfer Error.\n");
710
711 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
712 break;
713
714 case MBA_WAKEUP_THRES:
715 ql_dbg(ql_dbg_async, vha, 0x5008,
716 "Asynchronous WAKEUP_THRES.\n");
717
718 break;
719 case MBA_LIP_OCCURRED:
720 ql_dbg(ql_dbg_async, vha, 0x5009,
721 "LIP occurred (%x).\n", mb[1]);
722
723 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
724 atomic_set(&vha->loop_state, LOOP_DOWN);
725 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
726 qla2x00_mark_all_devices_lost(vha, 1);
727 }
728
729 if (vha->vp_idx) {
730 atomic_set(&vha->vp_state, VP_FAILED);
731 fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
732 }
733
734 set_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags);
735 set_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags);
736
737 vha->flags.management_server_logged_in = 0;
738 qla2x00_post_aen_work(vha, FCH_EVT_LIP, mb[1]);
739 break;
740
741 case MBA_LOOP_UP:
742 if (IS_QLA2100(ha) || IS_QLA2200(ha))
743 ha->link_data_rate = PORT_SPEED_1GB;
744 else
745 ha->link_data_rate = mb[1];
746
747 ql_log(ql_log_info, vha, 0x500a,
748 "LOOP UP detected (%s Gbps).\n",
749 qla2x00_get_link_speed_str(ha, ha->link_data_rate));
750
751 vha->flags.management_server_logged_in = 0;
752 qla2x00_post_aen_work(vha, FCH_EVT_LINKUP, ha->link_data_rate);
753 break;
754
755 case MBA_LOOP_DOWN:
756 mbx = (IS_QLA81XX(ha) || IS_QLA8031(ha))
757 ? RD_REG_WORD(®24->mailbox4) : 0;
758 mbx = (IS_P3P_TYPE(ha)) ? RD_REG_WORD(®82->mailbox_out[4])
759 : mbx;
760 ql_log(ql_log_info, vha, 0x500b,
761 "LOOP DOWN detected (%x %x %x %x).\n",
762 mb[1], mb[2], mb[3], mbx);
763
764 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
765 atomic_set(&vha->loop_state, LOOP_DOWN);
766 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
767
768
769
770
771
772 if (!vha->vp_idx) {
773 if (ha->flags.fawwpn_enabled) {
774 void *wwpn = ha->init_cb->port_name;
775 memcpy(vha->port_name, wwpn, WWN_SIZE);
776 fc_host_port_name(vha->host) =
777 wwn_to_u64(vha->port_name);
778 ql_dbg(ql_dbg_init + ql_dbg_verbose,
779 vha, 0x0144, "LOOP DOWN detected,"
780 "restore WWPN %016llx\n",
781 wwn_to_u64(vha->port_name));
782 }
783
784 clear_bit(VP_CONFIG_OK, &vha->vp_flags);
785 }
786
787 vha->device_flags |= DFLG_NO_CABLE;
788 qla2x00_mark_all_devices_lost(vha, 1);
789 }
790
791 if (vha->vp_idx) {
792 atomic_set(&vha->vp_state, VP_FAILED);
793 fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
794 }
795
796 vha->flags.management_server_logged_in = 0;
797 ha->link_data_rate = PORT_SPEED_UNKNOWN;
798 qla2x00_post_aen_work(vha, FCH_EVT_LINKDOWN, 0);
799 break;
800
801 case MBA_LIP_RESET:
802 ql_dbg(ql_dbg_async, vha, 0x500c,
803 "LIP reset occurred (%x).\n", mb[1]);
804
805 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
806 atomic_set(&vha->loop_state, LOOP_DOWN);
807 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
808 qla2x00_mark_all_devices_lost(vha, 1);
809 }
810
811 if (vha->vp_idx) {
812 atomic_set(&vha->vp_state, VP_FAILED);
813 fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
814 }
815
816 set_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
817
818 ha->operating_mode = LOOP;
819 vha->flags.management_server_logged_in = 0;
820 qla2x00_post_aen_work(vha, FCH_EVT_LIPRESET, mb[1]);
821 break;
822
823
824 case MBA_POINT_TO_POINT:
825 if (IS_QLA2100(ha))
826 break;
827
828 if (IS_CNA_CAPABLE(ha)) {
829 ql_dbg(ql_dbg_async, vha, 0x500d,
830 "DCBX Completed -- %04x %04x %04x.\n",
831 mb[1], mb[2], mb[3]);
832 if (ha->notify_dcbx_comp && !vha->vp_idx)
833 complete(&ha->dcbx_comp);
834
835 } else
836 ql_dbg(ql_dbg_async, vha, 0x500e,
837 "Asynchronous P2P MODE received.\n");
838
839
840
841
842
843 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
844 atomic_set(&vha->loop_state, LOOP_DOWN);
845 if (!atomic_read(&vha->loop_down_timer))
846 atomic_set(&vha->loop_down_timer,
847 LOOP_DOWN_TIME);
848 qla2x00_mark_all_devices_lost(vha, 1);
849 }
850
851 if (vha->vp_idx) {
852 atomic_set(&vha->vp_state, VP_FAILED);
853 fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
854 }
855
856 if (!(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)))
857 set_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
858
859 set_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags);
860 set_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags);
861
862 ha->flags.gpsc_supported = 1;
863 vha->flags.management_server_logged_in = 0;
864 break;
865
866 case MBA_CHG_IN_CONNECTION:
867 if (IS_QLA2100(ha))
868 break;
869
870 ql_dbg(ql_dbg_async, vha, 0x500f,
871 "Configuration change detected: value=%x.\n", mb[1]);
872
873 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
874 atomic_set(&vha->loop_state, LOOP_DOWN);
875 if (!atomic_read(&vha->loop_down_timer))
876 atomic_set(&vha->loop_down_timer,
877 LOOP_DOWN_TIME);
878 qla2x00_mark_all_devices_lost(vha, 1);
879 }
880
881 if (vha->vp_idx) {
882 atomic_set(&vha->vp_state, VP_FAILED);
883 fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
884 }
885
886 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
887 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
888 break;
889
890 case MBA_PORT_UPDATE:
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906 if (IS_QLA2XXX_MIDTYPE(ha) &&
907 ((mb[1] == 0xffff && (mb[3] & 0xff) != 0xff) ||
908 (mb[1] != 0xffff)) && vha->vp_idx != (mb[3] & 0xff))
909 break;
910
911 if (mb[2] == 0x7) {
912 ql_dbg(ql_dbg_async, vha, 0x5010,
913 "Port %s %04x %04x %04x.\n",
914 mb[1] == 0xffff ? "unavailable" : "logout",
915 mb[1], mb[2], mb[3]);
916
917 if (mb[1] == 0xffff)
918 goto global_port_update;
919
920
921 fcport = qla2x00_find_fcport_by_loopid(vha, mb[1]);
922 if (!fcport)
923 break;
924 if (atomic_read(&fcport->state) != FCS_ONLINE)
925 break;
926 ql_dbg(ql_dbg_async, vha, 0x508a,
927 "Marking port lost loopid=%04x portid=%06x.\n",
928 fcport->loop_id, fcport->d_id.b24);
929 qla2x00_mark_device_lost(fcport->vha, fcport, 1, 1);
930 break;
931
932global_port_update:
933
934 ql_log(ql_log_warn, vha, 0x505e,
935 "Link is offline.\n");
936
937 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
938 atomic_set(&vha->loop_state, LOOP_DOWN);
939 atomic_set(&vha->loop_down_timer,
940 LOOP_DOWN_TIME);
941 vha->device_flags |= DFLG_NO_CABLE;
942 qla2x00_mark_all_devices_lost(vha, 1);
943 }
944
945 if (vha->vp_idx) {
946 atomic_set(&vha->vp_state, VP_FAILED);
947 fc_vport_set_state(vha->fc_vport,
948 FC_VPORT_FAILED);
949 qla2x00_mark_all_devices_lost(vha, 1);
950 }
951
952 vha->flags.management_server_logged_in = 0;
953 ha->link_data_rate = PORT_SPEED_UNKNOWN;
954 break;
955 }
956
957
958
959
960
961
962 atomic_set(&vha->loop_down_timer, 0);
963 if (atomic_read(&vha->loop_state) != LOOP_DOWN &&
964 atomic_read(&vha->loop_state) != LOOP_DEAD) {
965 ql_dbg(ql_dbg_async, vha, 0x5011,
966 "Asynchronous PORT UPDATE ignored %04x/%04x/%04x.\n",
967 mb[1], mb[2], mb[3]);
968
969 qlt_async_event(mb[0], vha, mb);
970 break;
971 }
972
973 ql_dbg(ql_dbg_async, vha, 0x5012,
974 "Port database changed %04x %04x %04x.\n",
975 mb[1], mb[2], mb[3]);
976
977
978
979
980 atomic_set(&vha->loop_state, LOOP_UP);
981
982 qla2x00_mark_all_devices_lost(vha, 1);
983
984 if (vha->vp_idx == 0 && !qla_ini_mode_enabled(vha))
985 set_bit(SCR_PENDING, &vha->dpc_flags);
986
987 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
988 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
989 set_bit(VP_CONFIG_OK, &vha->vp_flags);
990
991 qlt_async_event(mb[0], vha, mb);
992 break;
993
994 case MBA_RSCN_UPDATE:
995
996 if (vha->vp_idx && test_bit(VP_SCR_NEEDED, &vha->vp_flags))
997 break;
998
999 if (ha->flags.npiv_supported && vha->vp_idx != (mb[3] & 0xff))
1000 break;
1001
1002 ql_dbg(ql_dbg_async, vha, 0x5013,
1003 "RSCN database changed -- %04x %04x %04x.\n",
1004 mb[1], mb[2], mb[3]);
1005
1006 rscn_entry = ((mb[1] & 0xff) << 16) | mb[2];
1007 host_pid = (vha->d_id.b.domain << 16) | (vha->d_id.b.area << 8)
1008 | vha->d_id.b.al_pa;
1009 if (rscn_entry == host_pid) {
1010 ql_dbg(ql_dbg_async, vha, 0x5014,
1011 "Ignoring RSCN update to local host "
1012 "port ID (%06x).\n", host_pid);
1013 break;
1014 }
1015
1016
1017 rscn_entry = ((mb[1] & 0x3ff) << 16) | mb[2];
1018
1019
1020 if (qla2x00_is_a_vp_did(vha, rscn_entry))
1021 break;
1022
1023
1024
1025
1026
1027 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1028 if (atomic_read(&fcport->state) != FCS_ONLINE)
1029 continue;
1030 if (fcport->d_id.b24 == rscn_entry) {
1031 qla2x00_mark_device_lost(vha, fcport, 0, 0);
1032 break;
1033 }
1034 }
1035
1036 atomic_set(&vha->loop_down_timer, 0);
1037 vha->flags.management_server_logged_in = 0;
1038
1039 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1040 set_bit(RSCN_UPDATE, &vha->dpc_flags);
1041 qla2x00_post_aen_work(vha, FCH_EVT_RSCN, rscn_entry);
1042 break;
1043
1044
1045 case MBA_ZIO_RESPONSE:
1046 ql_dbg(ql_dbg_async, vha, 0x5015,
1047 "[R|Z]IO update completion.\n");
1048
1049 if (IS_FWI2_CAPABLE(ha))
1050 qla24xx_process_response_queue(vha, rsp);
1051 else
1052 qla2x00_process_response_queue(rsp);
1053 break;
1054
1055 case MBA_DISCARD_RND_FRAME:
1056 ql_dbg(ql_dbg_async, vha, 0x5016,
1057 "Discard RND Frame -- %04x %04x %04x.\n",
1058 mb[1], mb[2], mb[3]);
1059 break;
1060
1061 case MBA_TRACE_NOTIFICATION:
1062 ql_dbg(ql_dbg_async, vha, 0x5017,
1063 "Trace Notification -- %04x %04x.\n", mb[1], mb[2]);
1064 break;
1065
1066 case MBA_ISP84XX_ALERT:
1067 ql_dbg(ql_dbg_async, vha, 0x5018,
1068 "ISP84XX Alert Notification -- %04x %04x %04x.\n",
1069 mb[1], mb[2], mb[3]);
1070
1071 spin_lock_irqsave(&ha->cs84xx->access_lock, flags);
1072 switch (mb[1]) {
1073 case A84_PANIC_RECOVERY:
1074 ql_log(ql_log_info, vha, 0x5019,
1075 "Alert 84XX: panic recovery %04x %04x.\n",
1076 mb[2], mb[3]);
1077 break;
1078 case A84_OP_LOGIN_COMPLETE:
1079 ha->cs84xx->op_fw_version = mb[3] << 16 | mb[2];
1080 ql_log(ql_log_info, vha, 0x501a,
1081 "Alert 84XX: firmware version %x.\n",
1082 ha->cs84xx->op_fw_version);
1083 break;
1084 case A84_DIAG_LOGIN_COMPLETE:
1085 ha->cs84xx->diag_fw_version = mb[3] << 16 | mb[2];
1086 ql_log(ql_log_info, vha, 0x501b,
1087 "Alert 84XX: diagnostic firmware version %x.\n",
1088 ha->cs84xx->diag_fw_version);
1089 break;
1090 case A84_GOLD_LOGIN_COMPLETE:
1091 ha->cs84xx->diag_fw_version = mb[3] << 16 | mb[2];
1092 ha->cs84xx->fw_update = 1;
1093 ql_log(ql_log_info, vha, 0x501c,
1094 "Alert 84XX: gold firmware version %x.\n",
1095 ha->cs84xx->gold_fw_version);
1096 break;
1097 default:
1098 ql_log(ql_log_warn, vha, 0x501d,
1099 "Alert 84xx: Invalid Alert %04x %04x %04x.\n",
1100 mb[1], mb[2], mb[3]);
1101 }
1102 spin_unlock_irqrestore(&ha->cs84xx->access_lock, flags);
1103 break;
1104 case MBA_DCBX_START:
1105 ql_dbg(ql_dbg_async, vha, 0x501e,
1106 "DCBX Started -- %04x %04x %04x.\n",
1107 mb[1], mb[2], mb[3]);
1108 break;
1109 case MBA_DCBX_PARAM_UPDATE:
1110 ql_dbg(ql_dbg_async, vha, 0x501f,
1111 "DCBX Parameters Updated -- %04x %04x %04x.\n",
1112 mb[1], mb[2], mb[3]);
1113 break;
1114 case MBA_FCF_CONF_ERR:
1115 ql_dbg(ql_dbg_async, vha, 0x5020,
1116 "FCF Configuration Error -- %04x %04x %04x.\n",
1117 mb[1], mb[2], mb[3]);
1118 break;
1119 case MBA_IDC_NOTIFY:
1120 if (IS_QLA8031(vha->hw) || IS_QLA8044(ha)) {
1121 mb[4] = RD_REG_WORD(®24->mailbox4);
1122 if (((mb[2] & 0x7fff) == MBC_PORT_RESET ||
1123 (mb[2] & 0x7fff) == MBC_SET_PORT_CONFIG) &&
1124 (mb[4] & INTERNAL_LOOPBACK_MASK) != 0) {
1125 set_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags);
1126
1127
1128
1129 if (atomic_read(&vha->loop_state) == LOOP_DOWN)
1130 atomic_set(&vha->loop_down_timer,
1131 LOOP_DOWN_TIME);
1132 qla2xxx_wake_dpc(vha);
1133 }
1134 }
1135 case MBA_IDC_COMPLETE:
1136 if (ha->notify_lb_portup_comp && !vha->vp_idx)
1137 complete(&ha->lb_portup_comp);
1138
1139 case MBA_IDC_TIME_EXT:
1140 if (IS_QLA81XX(vha->hw) || IS_QLA8031(vha->hw) ||
1141 IS_QLA8044(ha))
1142 qla81xx_idc_event(vha, mb[0], mb[1]);
1143 break;
1144
1145 case MBA_IDC_AEN:
1146 mb[4] = RD_REG_WORD(®24->mailbox4);
1147 mb[5] = RD_REG_WORD(®24->mailbox5);
1148 mb[6] = RD_REG_WORD(®24->mailbox6);
1149 mb[7] = RD_REG_WORD(®24->mailbox7);
1150 qla83xx_handle_8200_aen(vha, mb);
1151 break;
1152
1153 case MBA_DPORT_DIAGNOSTICS:
1154 ql_dbg(ql_dbg_async, vha, 0x5052,
1155 "D-Port Diagnostics: %04x %04x=%s\n", mb[0], mb[1],
1156 mb[1] == 0 ? "start" :
1157 mb[1] == 1 ? "done (ok)" :
1158 mb[1] == 2 ? "done (error)" : "other");
1159 break;
1160
1161 default:
1162 ql_dbg(ql_dbg_async, vha, 0x5057,
1163 "Unknown AEN:%04x %04x %04x %04x\n",
1164 mb[0], mb[1], mb[2], mb[3]);
1165 }
1166
1167 qlt_async_event(mb[0], vha, mb);
1168
1169 if (!vha->vp_idx && ha->num_vhosts)
1170 qla2x00_alert_all_vps(rsp, mb);
1171}
1172
1173
1174
1175
1176
1177
1178void
1179qla2x00_process_completed_request(struct scsi_qla_host *vha,
1180 struct req_que *req, uint32_t index)
1181{
1182 srb_t *sp;
1183 struct qla_hw_data *ha = vha->hw;
1184
1185
1186 if (index >= req->num_outstanding_cmds) {
1187 ql_log(ql_log_warn, vha, 0x3014,
1188 "Invalid SCSI command index (%x).\n", index);
1189
1190 if (IS_P3P_TYPE(ha))
1191 set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
1192 else
1193 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
1194 return;
1195 }
1196
1197 sp = req->outstanding_cmds[index];
1198 if (sp) {
1199
1200 req->outstanding_cmds[index] = NULL;
1201
1202
1203 sp->done(ha, sp, DID_OK << 16);
1204 } else {
1205 ql_log(ql_log_warn, vha, 0x3016, "Invalid SCSI SRB.\n");
1206
1207 if (IS_P3P_TYPE(ha))
1208 set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
1209 else
1210 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
1211 }
1212}
1213
1214srb_t *
1215qla2x00_get_sp_from_handle(scsi_qla_host_t *vha, const char *func,
1216 struct req_que *req, void *iocb)
1217{
1218 struct qla_hw_data *ha = vha->hw;
1219 sts_entry_t *pkt = iocb;
1220 srb_t *sp = NULL;
1221 uint16_t index;
1222
1223 index = LSW(pkt->handle);
1224 if (index >= req->num_outstanding_cmds) {
1225 ql_log(ql_log_warn, vha, 0x5031,
1226 "Invalid command index (%x).\n", index);
1227 if (IS_P3P_TYPE(ha))
1228 set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
1229 else
1230 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
1231 goto done;
1232 }
1233 sp = req->outstanding_cmds[index];
1234 if (!sp) {
1235 ql_log(ql_log_warn, vha, 0x5032,
1236 "Invalid completion handle (%x) -- timed-out.\n", index);
1237 return sp;
1238 }
1239 if (sp->handle != index) {
1240 ql_log(ql_log_warn, vha, 0x5033,
1241 "SRB handle (%x) mismatch %x.\n", sp->handle, index);
1242 return NULL;
1243 }
1244
1245 req->outstanding_cmds[index] = NULL;
1246
1247done:
1248 return sp;
1249}
1250
1251static void
1252qla2x00_mbx_iocb_entry(scsi_qla_host_t *vha, struct req_que *req,
1253 struct mbx_entry *mbx)
1254{
1255 const char func[] = "MBX-IOCB";
1256 const char *type;
1257 fc_port_t *fcport;
1258 srb_t *sp;
1259 struct srb_iocb *lio;
1260 uint16_t *data;
1261 uint16_t status;
1262
1263 sp = qla2x00_get_sp_from_handle(vha, func, req, mbx);
1264 if (!sp)
1265 return;
1266
1267 lio = &sp->u.iocb_cmd;
1268 type = sp->name;
1269 fcport = sp->fcport;
1270 data = lio->u.logio.data;
1271
1272 data[0] = MBS_COMMAND_ERROR;
1273 data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ?
1274 QLA_LOGIO_LOGIN_RETRIED : 0;
1275 if (mbx->entry_status) {
1276 ql_dbg(ql_dbg_async, vha, 0x5043,
1277 "Async-%s error entry - hdl=%x portid=%02x%02x%02x "
1278 "entry-status=%x status=%x state-flag=%x "
1279 "status-flags=%x.\n", type, sp->handle,
1280 fcport->d_id.b.domain, fcport->d_id.b.area,
1281 fcport->d_id.b.al_pa, mbx->entry_status,
1282 le16_to_cpu(mbx->status), le16_to_cpu(mbx->state_flags),
1283 le16_to_cpu(mbx->status_flags));
1284
1285 ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, vha, 0x5029,
1286 (uint8_t *)mbx, sizeof(*mbx));
1287
1288 goto logio_done;
1289 }
1290
1291 status = le16_to_cpu(mbx->status);
1292 if (status == 0x30 && sp->type == SRB_LOGIN_CMD &&
1293 le16_to_cpu(mbx->mb0) == MBS_COMMAND_COMPLETE)
1294 status = 0;
1295 if (!status && le16_to_cpu(mbx->mb0) == MBS_COMMAND_COMPLETE) {
1296 ql_dbg(ql_dbg_async, vha, 0x5045,
1297 "Async-%s complete - hdl=%x portid=%02x%02x%02x mbx1=%x.\n",
1298 type, sp->handle, fcport->d_id.b.domain,
1299 fcport->d_id.b.area, fcport->d_id.b.al_pa,
1300 le16_to_cpu(mbx->mb1));
1301
1302 data[0] = MBS_COMMAND_COMPLETE;
1303 if (sp->type == SRB_LOGIN_CMD) {
1304 fcport->port_type = FCT_TARGET;
1305 if (le16_to_cpu(mbx->mb1) & BIT_0)
1306 fcport->port_type = FCT_INITIATOR;
1307 else if (le16_to_cpu(mbx->mb1) & BIT_1)
1308 fcport->flags |= FCF_FCP2_DEVICE;
1309 }
1310 goto logio_done;
1311 }
1312
1313 data[0] = le16_to_cpu(mbx->mb0);
1314 switch (data[0]) {
1315 case MBS_PORT_ID_USED:
1316 data[1] = le16_to_cpu(mbx->mb1);
1317 break;
1318 case MBS_LOOP_ID_USED:
1319 break;
1320 default:
1321 data[0] = MBS_COMMAND_ERROR;
1322 break;
1323 }
1324
1325 ql_log(ql_log_warn, vha, 0x5046,
1326 "Async-%s failed - hdl=%x portid=%02x%02x%02x status=%x "
1327 "mb0=%x mb1=%x mb2=%x mb6=%x mb7=%x.\n", type, sp->handle,
1328 fcport->d_id.b.domain, fcport->d_id.b.area, fcport->d_id.b.al_pa,
1329 status, le16_to_cpu(mbx->mb0), le16_to_cpu(mbx->mb1),
1330 le16_to_cpu(mbx->mb2), le16_to_cpu(mbx->mb6),
1331 le16_to_cpu(mbx->mb7));
1332
1333logio_done:
1334 sp->done(vha, sp, 0);
1335}
1336
1337static void
1338qla2x00_ct_entry(scsi_qla_host_t *vha, struct req_que *req,
1339 sts_entry_t *pkt, int iocb_type)
1340{
1341 const char func[] = "CT_IOCB";
1342 const char *type;
1343 srb_t *sp;
1344 struct fc_bsg_job *bsg_job;
1345 uint16_t comp_status;
1346 int res;
1347
1348 sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
1349 if (!sp)
1350 return;
1351
1352 bsg_job = sp->u.bsg_job;
1353
1354 type = "ct pass-through";
1355
1356 comp_status = le16_to_cpu(pkt->comp_status);
1357
1358
1359
1360
1361 bsg_job->reply->reply_data.ctels_reply.status = FC_CTELS_STATUS_OK;
1362 bsg_job->reply_len = sizeof(struct fc_bsg_reply);
1363
1364 if (comp_status != CS_COMPLETE) {
1365 if (comp_status == CS_DATA_UNDERRUN) {
1366 res = DID_OK << 16;
1367 bsg_job->reply->reply_payload_rcv_len =
1368 le16_to_cpu(((sts_entry_t *)pkt)->rsp_info_len);
1369
1370 ql_log(ql_log_warn, vha, 0x5048,
1371 "CT pass-through-%s error "
1372 "comp_status-status=0x%x total_byte = 0x%x.\n",
1373 type, comp_status,
1374 bsg_job->reply->reply_payload_rcv_len);
1375 } else {
1376 ql_log(ql_log_warn, vha, 0x5049,
1377 "CT pass-through-%s error "
1378 "comp_status-status=0x%x.\n", type, comp_status);
1379 res = DID_ERROR << 16;
1380 bsg_job->reply->reply_payload_rcv_len = 0;
1381 }
1382 ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, vha, 0x5035,
1383 (uint8_t *)pkt, sizeof(*pkt));
1384 } else {
1385 res = DID_OK << 16;
1386 bsg_job->reply->reply_payload_rcv_len =
1387 bsg_job->reply_payload.payload_len;
1388 bsg_job->reply_len = 0;
1389 }
1390
1391 sp->done(vha, sp, res);
1392}
1393
1394static void
1395qla24xx_els_ct_entry(scsi_qla_host_t *vha, struct req_que *req,
1396 struct sts_entry_24xx *pkt, int iocb_type)
1397{
1398 const char func[] = "ELS_CT_IOCB";
1399 const char *type;
1400 srb_t *sp;
1401 struct fc_bsg_job *bsg_job;
1402 uint16_t comp_status;
1403 uint32_t fw_status[3];
1404 uint8_t* fw_sts_ptr;
1405 int res;
1406
1407 sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
1408 if (!sp)
1409 return;
1410 bsg_job = sp->u.bsg_job;
1411
1412 type = NULL;
1413 switch (sp->type) {
1414 case SRB_ELS_CMD_RPT:
1415 case SRB_ELS_CMD_HST:
1416 type = "els";
1417 break;
1418 case SRB_CT_CMD:
1419 type = "ct pass-through";
1420 break;
1421 default:
1422 ql_dbg(ql_dbg_user, vha, 0x503e,
1423 "Unrecognized SRB: (%p) type=%d.\n", sp, sp->type);
1424 return;
1425 }
1426
1427 comp_status = fw_status[0] = le16_to_cpu(pkt->comp_status);
1428 fw_status[1] = le16_to_cpu(((struct els_sts_entry_24xx*)pkt)->error_subcode_1);
1429 fw_status[2] = le16_to_cpu(((struct els_sts_entry_24xx*)pkt)->error_subcode_2);
1430
1431
1432
1433
1434 bsg_job->reply->reply_data.ctels_reply.status = FC_CTELS_STATUS_OK;
1435 bsg_job->reply_len = sizeof(struct fc_bsg_reply) + sizeof(fw_status);
1436
1437 if (comp_status != CS_COMPLETE) {
1438 if (comp_status == CS_DATA_UNDERRUN) {
1439 res = DID_OK << 16;
1440 bsg_job->reply->reply_payload_rcv_len =
1441 le16_to_cpu(((struct els_sts_entry_24xx *)pkt)->total_byte_count);
1442
1443 ql_dbg(ql_dbg_user, vha, 0x503f,
1444 "ELS-CT pass-through-%s error hdl=%x comp_status-status=0x%x "
1445 "error subcode 1=0x%x error subcode 2=0x%x total_byte = 0x%x.\n",
1446 type, sp->handle, comp_status, fw_status[1], fw_status[2],
1447 le16_to_cpu(((struct els_sts_entry_24xx *)
1448 pkt)->total_byte_count));
1449 fw_sts_ptr = ((uint8_t*)bsg_job->req->sense) + sizeof(struct fc_bsg_reply);
1450 memcpy( fw_sts_ptr, fw_status, sizeof(fw_status));
1451 }
1452 else {
1453 ql_dbg(ql_dbg_user, vha, 0x5040,
1454 "ELS-CT pass-through-%s error hdl=%x comp_status-status=0x%x "
1455 "error subcode 1=0x%x error subcode 2=0x%x.\n",
1456 type, sp->handle, comp_status,
1457 le16_to_cpu(((struct els_sts_entry_24xx *)
1458 pkt)->error_subcode_1),
1459 le16_to_cpu(((struct els_sts_entry_24xx *)
1460 pkt)->error_subcode_2));
1461 res = DID_ERROR << 16;
1462 bsg_job->reply->reply_payload_rcv_len = 0;
1463 fw_sts_ptr = ((uint8_t*)bsg_job->req->sense) + sizeof(struct fc_bsg_reply);
1464 memcpy( fw_sts_ptr, fw_status, sizeof(fw_status));
1465 }
1466 ql_dump_buffer(ql_dbg_user + ql_dbg_buffer, vha, 0x5056,
1467 (uint8_t *)pkt, sizeof(*pkt));
1468 }
1469 else {
1470 res = DID_OK << 16;
1471 bsg_job->reply->reply_payload_rcv_len = bsg_job->reply_payload.payload_len;
1472 bsg_job->reply_len = 0;
1473 }
1474
1475 sp->done(vha, sp, res);
1476}
1477
1478static void
1479qla24xx_logio_entry(scsi_qla_host_t *vha, struct req_que *req,
1480 struct logio_entry_24xx *logio)
1481{
1482 const char func[] = "LOGIO-IOCB";
1483 const char *type;
1484 fc_port_t *fcport;
1485 srb_t *sp;
1486 struct srb_iocb *lio;
1487 uint16_t *data;
1488 uint32_t iop[2];
1489
1490 sp = qla2x00_get_sp_from_handle(vha, func, req, logio);
1491 if (!sp)
1492 return;
1493
1494 lio = &sp->u.iocb_cmd;
1495 type = sp->name;
1496 fcport = sp->fcport;
1497 data = lio->u.logio.data;
1498
1499 data[0] = MBS_COMMAND_ERROR;
1500 data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ?
1501 QLA_LOGIO_LOGIN_RETRIED : 0;
1502 if (logio->entry_status) {
1503 ql_log(ql_log_warn, fcport->vha, 0x5034,
1504 "Async-%s error entry - hdl=%x"
1505 "portid=%02x%02x%02x entry-status=%x.\n",
1506 type, sp->handle, fcport->d_id.b.domain,
1507 fcport->d_id.b.area, fcport->d_id.b.al_pa,
1508 logio->entry_status);
1509 ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, vha, 0x504d,
1510 (uint8_t *)logio, sizeof(*logio));
1511
1512 goto logio_done;
1513 }
1514
1515 if (le16_to_cpu(logio->comp_status) == CS_COMPLETE) {
1516 ql_dbg(ql_dbg_async, fcport->vha, 0x5036,
1517 "Async-%s complete - hdl=%x portid=%02x%02x%02x "
1518 "iop0=%x.\n", type, sp->handle, fcport->d_id.b.domain,
1519 fcport->d_id.b.area, fcport->d_id.b.al_pa,
1520 le32_to_cpu(logio->io_parameter[0]));
1521
1522 data[0] = MBS_COMMAND_COMPLETE;
1523 if (sp->type != SRB_LOGIN_CMD)
1524 goto logio_done;
1525
1526 iop[0] = le32_to_cpu(logio->io_parameter[0]);
1527 if (iop[0] & BIT_4) {
1528 fcport->port_type = FCT_TARGET;
1529 if (iop[0] & BIT_8)
1530 fcport->flags |= FCF_FCP2_DEVICE;
1531 } else if (iop[0] & BIT_5)
1532 fcport->port_type = FCT_INITIATOR;
1533
1534 if (iop[0] & BIT_7)
1535 fcport->flags |= FCF_CONF_COMP_SUPPORTED;
1536
1537 if (logio->io_parameter[7] || logio->io_parameter[8])
1538 fcport->supported_classes |= FC_COS_CLASS2;
1539 if (logio->io_parameter[9] || logio->io_parameter[10])
1540 fcport->supported_classes |= FC_COS_CLASS3;
1541
1542 goto logio_done;
1543 }
1544
1545 iop[0] = le32_to_cpu(logio->io_parameter[0]);
1546 iop[1] = le32_to_cpu(logio->io_parameter[1]);
1547 switch (iop[0]) {
1548 case LSC_SCODE_PORTID_USED:
1549 data[0] = MBS_PORT_ID_USED;
1550 data[1] = LSW(iop[1]);
1551 break;
1552 case LSC_SCODE_NPORT_USED:
1553 data[0] = MBS_LOOP_ID_USED;
1554 break;
1555 default:
1556 data[0] = MBS_COMMAND_ERROR;
1557 break;
1558 }
1559
1560 ql_dbg(ql_dbg_async, fcport->vha, 0x5037,
1561 "Async-%s failed - hdl=%x portid=%02x%02x%02x comp=%x "
1562 "iop0=%x iop1=%x.\n", type, sp->handle, fcport->d_id.b.domain,
1563 fcport->d_id.b.area, fcport->d_id.b.al_pa,
1564 le16_to_cpu(logio->comp_status),
1565 le32_to_cpu(logio->io_parameter[0]),
1566 le32_to_cpu(logio->io_parameter[1]));
1567
1568logio_done:
1569 sp->done(vha, sp, 0);
1570}
1571
1572static void
1573qla24xx_tm_iocb_entry(scsi_qla_host_t *vha, struct req_que *req, void *tsk)
1574{
1575 const char func[] = "TMF-IOCB";
1576 const char *type;
1577 fc_port_t *fcport;
1578 srb_t *sp;
1579 struct srb_iocb *iocb;
1580 struct sts_entry_24xx *sts = (struct sts_entry_24xx *)tsk;
1581
1582 sp = qla2x00_get_sp_from_handle(vha, func, req, tsk);
1583 if (!sp)
1584 return;
1585
1586 iocb = &sp->u.iocb_cmd;
1587 type = sp->name;
1588 fcport = sp->fcport;
1589 iocb->u.tmf.data = QLA_SUCCESS;
1590
1591 if (sts->entry_status) {
1592 ql_log(ql_log_warn, fcport->vha, 0x5038,
1593 "Async-%s error - hdl=%x entry-status(%x).\n",
1594 type, sp->handle, sts->entry_status);
1595 iocb->u.tmf.data = QLA_FUNCTION_FAILED;
1596 } else if (sts->comp_status != cpu_to_le16(CS_COMPLETE)) {
1597 ql_log(ql_log_warn, fcport->vha, 0x5039,
1598 "Async-%s error - hdl=%x completion status(%x).\n",
1599 type, sp->handle, sts->comp_status);
1600 iocb->u.tmf.data = QLA_FUNCTION_FAILED;
1601 } else if ((le16_to_cpu(sts->scsi_status) &
1602 SS_RESPONSE_INFO_LEN_VALID)) {
1603 if (le32_to_cpu(sts->rsp_data_len) < 4) {
1604 ql_log(ql_log_warn, fcport->vha, 0x503b,
1605 "Async-%s error - hdl=%x not enough response(%d).\n",
1606 type, sp->handle, sts->rsp_data_len);
1607 } else if (sts->data[3]) {
1608 ql_log(ql_log_warn, fcport->vha, 0x503c,
1609 "Async-%s error - hdl=%x response(%x).\n",
1610 type, sp->handle, sts->data[3]);
1611 iocb->u.tmf.data = QLA_FUNCTION_FAILED;
1612 }
1613 }
1614
1615 if (iocb->u.tmf.data != QLA_SUCCESS)
1616 ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, vha, 0x5055,
1617 (uint8_t *)sts, sizeof(*sts));
1618
1619 sp->done(vha, sp, 0);
1620}
1621
1622
1623
1624
1625
1626void
1627qla2x00_process_response_queue(struct rsp_que *rsp)
1628{
1629 struct scsi_qla_host *vha;
1630 struct qla_hw_data *ha = rsp->hw;
1631 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1632 sts_entry_t *pkt;
1633 uint16_t handle_cnt;
1634 uint16_t cnt;
1635
1636 vha = pci_get_drvdata(ha->pdev);
1637
1638 if (!vha->flags.online)
1639 return;
1640
1641 while (rsp->ring_ptr->signature != RESPONSE_PROCESSED) {
1642 pkt = (sts_entry_t *)rsp->ring_ptr;
1643
1644 rsp->ring_index++;
1645 if (rsp->ring_index == rsp->length) {
1646 rsp->ring_index = 0;
1647 rsp->ring_ptr = rsp->ring;
1648 } else {
1649 rsp->ring_ptr++;
1650 }
1651
1652 if (pkt->entry_status != 0) {
1653 qla2x00_error_entry(vha, rsp, pkt);
1654 ((response_t *)pkt)->signature = RESPONSE_PROCESSED;
1655 wmb();
1656 continue;
1657 }
1658
1659 switch (pkt->entry_type) {
1660 case STATUS_TYPE:
1661 qla2x00_status_entry(vha, rsp, pkt);
1662 break;
1663 case STATUS_TYPE_21:
1664 handle_cnt = ((sts21_entry_t *)pkt)->handle_count;
1665 for (cnt = 0; cnt < handle_cnt; cnt++) {
1666 qla2x00_process_completed_request(vha, rsp->req,
1667 ((sts21_entry_t *)pkt)->handle[cnt]);
1668 }
1669 break;
1670 case STATUS_TYPE_22:
1671 handle_cnt = ((sts22_entry_t *)pkt)->handle_count;
1672 for (cnt = 0; cnt < handle_cnt; cnt++) {
1673 qla2x00_process_completed_request(vha, rsp->req,
1674 ((sts22_entry_t *)pkt)->handle[cnt]);
1675 }
1676 break;
1677 case STATUS_CONT_TYPE:
1678 qla2x00_status_cont_entry(rsp, (sts_cont_entry_t *)pkt);
1679 break;
1680 case MBX_IOCB_TYPE:
1681 qla2x00_mbx_iocb_entry(vha, rsp->req,
1682 (struct mbx_entry *)pkt);
1683 break;
1684 case CT_IOCB_TYPE:
1685 qla2x00_ct_entry(vha, rsp->req, pkt, CT_IOCB_TYPE);
1686 break;
1687 default:
1688
1689 ql_log(ql_log_warn, vha, 0x504a,
1690 "Received unknown response pkt type %x "
1691 "entry status=%x.\n",
1692 pkt->entry_type, pkt->entry_status);
1693 break;
1694 }
1695 ((response_t *)pkt)->signature = RESPONSE_PROCESSED;
1696 wmb();
1697 }
1698
1699
1700 WRT_REG_WORD(ISP_RSP_Q_OUT(ha, reg), rsp->ring_index);
1701}
1702
1703static inline void
1704qla2x00_handle_sense(srb_t *sp, uint8_t *sense_data, uint32_t par_sense_len,
1705 uint32_t sense_len, struct rsp_que *rsp, int res)
1706{
1707 struct scsi_qla_host *vha = sp->fcport->vha;
1708 struct scsi_cmnd *cp = GET_CMD_SP(sp);
1709 uint32_t track_sense_len;
1710
1711 if (sense_len >= SCSI_SENSE_BUFFERSIZE)
1712 sense_len = SCSI_SENSE_BUFFERSIZE;
1713
1714 SET_CMD_SENSE_LEN(sp, sense_len);
1715 SET_CMD_SENSE_PTR(sp, cp->sense_buffer);
1716 track_sense_len = sense_len;
1717
1718 if (sense_len > par_sense_len)
1719 sense_len = par_sense_len;
1720
1721 memcpy(cp->sense_buffer, sense_data, sense_len);
1722
1723 SET_CMD_SENSE_PTR(sp, cp->sense_buffer + sense_len);
1724 track_sense_len -= sense_len;
1725 SET_CMD_SENSE_LEN(sp, track_sense_len);
1726
1727 if (track_sense_len != 0) {
1728 rsp->status_srb = sp;
1729 cp->result = res;
1730 }
1731
1732 if (sense_len) {
1733 ql_dbg(ql_dbg_io + ql_dbg_buffer, vha, 0x301c,
1734 "Check condition Sense data, nexus%ld:%d:%llu cmd=%p.\n",
1735 sp->fcport->vha->host_no, cp->device->id, cp->device->lun,
1736 cp);
1737 ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x302b,
1738 cp->sense_buffer, sense_len);
1739 }
1740}
1741
1742struct scsi_dif_tuple {
1743 __be16 guard;
1744 __be16 app_tag;
1745 __be32 ref_tag;
1746};
1747
1748
1749
1750
1751
1752
1753
1754static inline int
1755qla2x00_handle_dif_error(srb_t *sp, struct sts_entry_24xx *sts24)
1756{
1757 struct scsi_qla_host *vha = sp->fcport->vha;
1758 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
1759 uint8_t *ap = &sts24->data[12];
1760 uint8_t *ep = &sts24->data[20];
1761 uint32_t e_ref_tag, a_ref_tag;
1762 uint16_t e_app_tag, a_app_tag;
1763 uint16_t e_guard, a_guard;
1764
1765
1766
1767
1768
1769 a_guard = le16_to_cpu(*(uint16_t *)(ap + 2));
1770 a_app_tag = le16_to_cpu(*(uint16_t *)(ap + 0));
1771 a_ref_tag = le32_to_cpu(*(uint32_t *)(ap + 4));
1772 e_guard = le16_to_cpu(*(uint16_t *)(ep + 2));
1773 e_app_tag = le16_to_cpu(*(uint16_t *)(ep + 0));
1774 e_ref_tag = le32_to_cpu(*(uint32_t *)(ep + 4));
1775
1776 ql_dbg(ql_dbg_io, vha, 0x3023,
1777 "iocb(s) %p Returned STATUS.\n", sts24);
1778
1779 ql_dbg(ql_dbg_io, vha, 0x3024,
1780 "DIF ERROR in cmd 0x%x lba 0x%llx act ref"
1781 " tag=0x%x, exp ref_tag=0x%x, act app tag=0x%x, exp app"
1782 " tag=0x%x, act guard=0x%x, exp guard=0x%x.\n",
1783 cmd->cmnd[0], (u64)scsi_get_lba(cmd), a_ref_tag, e_ref_tag,
1784 a_app_tag, e_app_tag, a_guard, e_guard);
1785
1786
1787
1788
1789
1790
1791 if ((a_app_tag == 0xffff) &&
1792 ((scsi_get_prot_type(cmd) != SCSI_PROT_DIF_TYPE3) ||
1793 (a_ref_tag == 0xffffffff))) {
1794 uint32_t blocks_done, resid;
1795 sector_t lba_s = scsi_get_lba(cmd);
1796
1797
1798 blocks_done = e_ref_tag - (uint32_t)lba_s + 1;
1799
1800 resid = scsi_bufflen(cmd) - (blocks_done *
1801 cmd->device->sector_size);
1802
1803 scsi_set_resid(cmd, resid);
1804 cmd->result = DID_OK << 16;
1805
1806
1807 if (scsi_prot_sg_count(cmd)) {
1808 uint32_t i, j = 0, k = 0, num_ent;
1809 struct scatterlist *sg;
1810 struct sd_dif_tuple *spt;
1811
1812
1813 scsi_for_each_prot_sg(cmd, sg,
1814 scsi_prot_sg_count(cmd), i) {
1815 num_ent = sg_dma_len(sg) / 8;
1816 if (k + num_ent < blocks_done) {
1817 k += num_ent;
1818 continue;
1819 }
1820 j = blocks_done - k - 1;
1821 k = blocks_done;
1822 break;
1823 }
1824
1825 if (k != blocks_done) {
1826 ql_log(ql_log_warn, vha, 0x302f,
1827 "unexpected tag values tag:lba=%x:%llx)\n",
1828 e_ref_tag, (unsigned long long)lba_s);
1829 return 1;
1830 }
1831
1832 spt = page_address(sg_page(sg)) + sg->offset;
1833 spt += j;
1834
1835 spt->app_tag = 0xffff;
1836 if (scsi_get_prot_type(cmd) == SCSI_PROT_DIF_TYPE3)
1837 spt->ref_tag = 0xffffffff;
1838 }
1839
1840 return 0;
1841 }
1842
1843
1844 if (e_guard != a_guard) {
1845 scsi_build_sense_buffer(1, cmd->sense_buffer, ILLEGAL_REQUEST,
1846 0x10, 0x1);
1847 set_driver_byte(cmd, DRIVER_SENSE);
1848 set_host_byte(cmd, DID_ABORT);
1849 cmd->result |= SAM_STAT_CHECK_CONDITION << 1;
1850 return 1;
1851 }
1852
1853
1854 if (e_ref_tag != a_ref_tag) {
1855 scsi_build_sense_buffer(1, cmd->sense_buffer, ILLEGAL_REQUEST,
1856 0x10, 0x3);
1857 set_driver_byte(cmd, DRIVER_SENSE);
1858 set_host_byte(cmd, DID_ABORT);
1859 cmd->result |= SAM_STAT_CHECK_CONDITION << 1;
1860 return 1;
1861 }
1862
1863
1864 if (e_app_tag != a_app_tag) {
1865 scsi_build_sense_buffer(1, cmd->sense_buffer, ILLEGAL_REQUEST,
1866 0x10, 0x2);
1867 set_driver_byte(cmd, DRIVER_SENSE);
1868 set_host_byte(cmd, DID_ABORT);
1869 cmd->result |= SAM_STAT_CHECK_CONDITION << 1;
1870 return 1;
1871 }
1872
1873 return 1;
1874}
1875
1876static void
1877qla25xx_process_bidir_status_iocb(scsi_qla_host_t *vha, void *pkt,
1878 struct req_que *req, uint32_t index)
1879{
1880 struct qla_hw_data *ha = vha->hw;
1881 srb_t *sp;
1882 uint16_t comp_status;
1883 uint16_t scsi_status;
1884 uint16_t thread_id;
1885 uint32_t rval = EXT_STATUS_OK;
1886 struct fc_bsg_job *bsg_job = NULL;
1887 sts_entry_t *sts;
1888 struct sts_entry_24xx *sts24;
1889 sts = (sts_entry_t *) pkt;
1890 sts24 = (struct sts_entry_24xx *) pkt;
1891
1892
1893 if (index >= req->num_outstanding_cmds) {
1894 ql_log(ql_log_warn, vha, 0x70af,
1895 "Invalid SCSI completion handle 0x%x.\n", index);
1896 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
1897 return;
1898 }
1899
1900 sp = req->outstanding_cmds[index];
1901 if (sp) {
1902
1903 req->outstanding_cmds[index] = NULL;
1904 bsg_job = sp->u.bsg_job;
1905 } else {
1906 ql_log(ql_log_warn, vha, 0x70b0,
1907 "Req:%d: Invalid ISP SCSI completion handle(0x%x)\n",
1908 req->id, index);
1909
1910 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
1911 return;
1912 }
1913
1914 if (IS_FWI2_CAPABLE(ha)) {
1915 comp_status = le16_to_cpu(sts24->comp_status);
1916 scsi_status = le16_to_cpu(sts24->scsi_status) & SS_MASK;
1917 } else {
1918 comp_status = le16_to_cpu(sts->comp_status);
1919 scsi_status = le16_to_cpu(sts->scsi_status) & SS_MASK;
1920 }
1921
1922 thread_id = bsg_job->request->rqst_data.h_vendor.vendor_cmd[1];
1923 switch (comp_status) {
1924 case CS_COMPLETE:
1925 if (scsi_status == 0) {
1926 bsg_job->reply->reply_payload_rcv_len =
1927 bsg_job->reply_payload.payload_len;
1928 vha->qla_stats.input_bytes +=
1929 bsg_job->reply->reply_payload_rcv_len;
1930 vha->qla_stats.input_requests++;
1931 rval = EXT_STATUS_OK;
1932 }
1933 goto done;
1934
1935 case CS_DATA_OVERRUN:
1936 ql_dbg(ql_dbg_user, vha, 0x70b1,
1937 "Command completed with date overrun thread_id=%d\n",
1938 thread_id);
1939 rval = EXT_STATUS_DATA_OVERRUN;
1940 break;
1941
1942 case CS_DATA_UNDERRUN:
1943 ql_dbg(ql_dbg_user, vha, 0x70b2,
1944 "Command completed with date underrun thread_id=%d\n",
1945 thread_id);
1946 rval = EXT_STATUS_DATA_UNDERRUN;
1947 break;
1948 case CS_BIDIR_RD_OVERRUN:
1949 ql_dbg(ql_dbg_user, vha, 0x70b3,
1950 "Command completed with read data overrun thread_id=%d\n",
1951 thread_id);
1952 rval = EXT_STATUS_DATA_OVERRUN;
1953 break;
1954
1955 case CS_BIDIR_RD_WR_OVERRUN:
1956 ql_dbg(ql_dbg_user, vha, 0x70b4,
1957 "Command completed with read and write data overrun "
1958 "thread_id=%d\n", thread_id);
1959 rval = EXT_STATUS_DATA_OVERRUN;
1960 break;
1961
1962 case CS_BIDIR_RD_OVERRUN_WR_UNDERRUN:
1963 ql_dbg(ql_dbg_user, vha, 0x70b5,
1964 "Command completed with read data over and write data "
1965 "underrun thread_id=%d\n", thread_id);
1966 rval = EXT_STATUS_DATA_OVERRUN;
1967 break;
1968
1969 case CS_BIDIR_RD_UNDERRUN:
1970 ql_dbg(ql_dbg_user, vha, 0x70b6,
1971 "Command completed with read data data underrun "
1972 "thread_id=%d\n", thread_id);
1973 rval = EXT_STATUS_DATA_UNDERRUN;
1974 break;
1975
1976 case CS_BIDIR_RD_UNDERRUN_WR_OVERRUN:
1977 ql_dbg(ql_dbg_user, vha, 0x70b7,
1978 "Command completed with read data under and write data "
1979 "overrun thread_id=%d\n", thread_id);
1980 rval = EXT_STATUS_DATA_UNDERRUN;
1981 break;
1982
1983 case CS_BIDIR_RD_WR_UNDERRUN:
1984 ql_dbg(ql_dbg_user, vha, 0x70b8,
1985 "Command completed with read and write data underrun "
1986 "thread_id=%d\n", thread_id);
1987 rval = EXT_STATUS_DATA_UNDERRUN;
1988 break;
1989
1990 case CS_BIDIR_DMA:
1991 ql_dbg(ql_dbg_user, vha, 0x70b9,
1992 "Command completed with data DMA error thread_id=%d\n",
1993 thread_id);
1994 rval = EXT_STATUS_DMA_ERR;
1995 break;
1996
1997 case CS_TIMEOUT:
1998 ql_dbg(ql_dbg_user, vha, 0x70ba,
1999 "Command completed with timeout thread_id=%d\n",
2000 thread_id);
2001 rval = EXT_STATUS_TIMEOUT;
2002 break;
2003 default:
2004 ql_dbg(ql_dbg_user, vha, 0x70bb,
2005 "Command completed with completion status=0x%x "
2006 "thread_id=%d\n", comp_status, thread_id);
2007 rval = EXT_STATUS_ERR;
2008 break;
2009 }
2010 bsg_job->reply->reply_payload_rcv_len = 0;
2011
2012done:
2013
2014 bsg_job->reply->reply_data.vendor_reply.vendor_rsp[0] = rval;
2015 bsg_job->reply_len = sizeof(struct fc_bsg_reply);
2016
2017
2018 sp->done(vha, sp, (DID_OK << 6));
2019
2020}
2021
2022
2023
2024
2025
2026
2027static void
2028qla2x00_status_entry(scsi_qla_host_t *vha, struct rsp_que *rsp, void *pkt)
2029{
2030 srb_t *sp;
2031 fc_port_t *fcport;
2032 struct scsi_cmnd *cp;
2033 sts_entry_t *sts;
2034 struct sts_entry_24xx *sts24;
2035 uint16_t comp_status;
2036 uint16_t scsi_status;
2037 uint16_t ox_id;
2038 uint8_t lscsi_status;
2039 int32_t resid;
2040 uint32_t sense_len, par_sense_len, rsp_info_len, resid_len,
2041 fw_resid_len;
2042 uint8_t *rsp_info, *sense_data;
2043 struct qla_hw_data *ha = vha->hw;
2044 uint32_t handle;
2045 uint16_t que;
2046 struct req_que *req;
2047 int logit = 1;
2048 int res = 0;
2049 uint16_t state_flags = 0;
2050 uint16_t retry_delay = 0;
2051
2052 sts = (sts_entry_t *) pkt;
2053 sts24 = (struct sts_entry_24xx *) pkt;
2054 if (IS_FWI2_CAPABLE(ha)) {
2055 comp_status = le16_to_cpu(sts24->comp_status);
2056 scsi_status = le16_to_cpu(sts24->scsi_status) & SS_MASK;
2057 state_flags = le16_to_cpu(sts24->state_flags);
2058 } else {
2059 comp_status = le16_to_cpu(sts->comp_status);
2060 scsi_status = le16_to_cpu(sts->scsi_status) & SS_MASK;
2061 }
2062 handle = (uint32_t) LSW(sts->handle);
2063 que = MSW(sts->handle);
2064 req = ha->req_q_map[que];
2065
2066
2067 if (req == NULL ||
2068 que >= find_first_zero_bit(ha->req_qid_map, ha->max_req_queues)) {
2069 ql_dbg(ql_dbg_io, vha, 0x3059,
2070 "Invalid status handle (0x%x): Bad req pointer. req=%p, "
2071 "que=%u.\n", sts->handle, req, que);
2072 return;
2073 }
2074
2075
2076 if (handle < req->num_outstanding_cmds) {
2077 sp = req->outstanding_cmds[handle];
2078 if (!sp) {
2079 ql_dbg(ql_dbg_io, vha, 0x3075,
2080 "%s(%ld): Already returned command for status handle (0x%x).\n",
2081 __func__, vha->host_no, sts->handle);
2082 return;
2083 }
2084 } else {
2085 ql_dbg(ql_dbg_io, vha, 0x3017,
2086 "Invalid status handle, out of range (0x%x).\n",
2087 sts->handle);
2088
2089 if (!test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) {
2090 if (IS_P3P_TYPE(ha))
2091 set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
2092 else
2093 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2094 qla2xxx_wake_dpc(vha);
2095 }
2096 return;
2097 }
2098
2099 if (unlikely((state_flags & BIT_1) && (sp->type == SRB_BIDI_CMD))) {
2100 qla25xx_process_bidir_status_iocb(vha, pkt, req, handle);
2101 return;
2102 }
2103
2104
2105 if (sp->type == SRB_TM_CMD) {
2106 qla24xx_tm_iocb_entry(vha, req, pkt);
2107 return;
2108 }
2109
2110
2111 if (comp_status == CS_COMPLETE && scsi_status == 0) {
2112 qla2x00_process_completed_request(vha, req, handle);
2113
2114 return;
2115 }
2116
2117 req->outstanding_cmds[handle] = NULL;
2118 cp = GET_CMD_SP(sp);
2119 if (cp == NULL) {
2120 ql_dbg(ql_dbg_io, vha, 0x3018,
2121 "Command already returned (0x%x/%p).\n",
2122 sts->handle, sp);
2123
2124 return;
2125 }
2126
2127 lscsi_status = scsi_status & STATUS_MASK;
2128
2129 fcport = sp->fcport;
2130
2131 ox_id = 0;
2132 sense_len = par_sense_len = rsp_info_len = resid_len =
2133 fw_resid_len = 0;
2134 if (IS_FWI2_CAPABLE(ha)) {
2135 if (scsi_status & SS_SENSE_LEN_VALID)
2136 sense_len = le32_to_cpu(sts24->sense_len);
2137 if (scsi_status & SS_RESPONSE_INFO_LEN_VALID)
2138 rsp_info_len = le32_to_cpu(sts24->rsp_data_len);
2139 if (scsi_status & (SS_RESIDUAL_UNDER | SS_RESIDUAL_OVER))
2140 resid_len = le32_to_cpu(sts24->rsp_residual_count);
2141 if (comp_status == CS_DATA_UNDERRUN)
2142 fw_resid_len = le32_to_cpu(sts24->residual_len);
2143 rsp_info = sts24->data;
2144 sense_data = sts24->data;
2145 host_to_fcp_swap(sts24->data, sizeof(sts24->data));
2146 ox_id = le16_to_cpu(sts24->ox_id);
2147 par_sense_len = sizeof(sts24->data);
2148
2149 if (sts24->retry_delay > 0 && sts24->retry_delay < 0xfff1)
2150 retry_delay = sts24->retry_delay;
2151 } else {
2152 if (scsi_status & SS_SENSE_LEN_VALID)
2153 sense_len = le16_to_cpu(sts->req_sense_length);
2154 if (scsi_status & SS_RESPONSE_INFO_LEN_VALID)
2155 rsp_info_len = le16_to_cpu(sts->rsp_info_len);
2156 resid_len = le32_to_cpu(sts->residual_length);
2157 rsp_info = sts->rsp_info;
2158 sense_data = sts->req_sense_data;
2159 par_sense_len = sizeof(sts->req_sense_data);
2160 }
2161
2162
2163 if (scsi_status & SS_RESPONSE_INFO_LEN_VALID) {
2164
2165 if (IS_FWI2_CAPABLE(ha)) {
2166 sense_data += rsp_info_len;
2167 par_sense_len -= rsp_info_len;
2168 }
2169 if (rsp_info_len > 3 && rsp_info[3]) {
2170 ql_dbg(ql_dbg_io, fcport->vha, 0x3019,
2171 "FCP I/O protocol failure (0x%x/0x%x).\n",
2172 rsp_info_len, rsp_info[3]);
2173
2174 res = DID_BUS_BUSY << 16;
2175 goto out;
2176 }
2177 }
2178
2179
2180 if (IS_FWI2_CAPABLE(ha) && comp_status == CS_COMPLETE &&
2181 scsi_status & SS_RESIDUAL_OVER)
2182 comp_status = CS_DATA_OVERRUN;
2183
2184
2185
2186
2187
2188 if (lscsi_status == SAM_STAT_TASK_SET_FULL ||
2189 lscsi_status == SAM_STAT_BUSY)
2190 qla2x00_set_retry_delay_timestamp(fcport, retry_delay);
2191
2192
2193
2194
2195 switch (comp_status) {
2196 case CS_COMPLETE:
2197 case CS_QUEUE_FULL:
2198 if (scsi_status == 0) {
2199 res = DID_OK << 16;
2200 break;
2201 }
2202 if (scsi_status & (SS_RESIDUAL_UNDER | SS_RESIDUAL_OVER)) {
2203 resid = resid_len;
2204 scsi_set_resid(cp, resid);
2205
2206 if (!lscsi_status &&
2207 ((unsigned)(scsi_bufflen(cp) - resid) <
2208 cp->underflow)) {
2209 ql_dbg(ql_dbg_io, fcport->vha, 0x301a,
2210 "Mid-layer underflow "
2211 "detected (0x%x of 0x%x bytes).\n",
2212 resid, scsi_bufflen(cp));
2213
2214 res = DID_ERROR << 16;
2215 break;
2216 }
2217 }
2218 res = DID_OK << 16 | lscsi_status;
2219
2220 if (lscsi_status == SAM_STAT_TASK_SET_FULL) {
2221 ql_dbg(ql_dbg_io, fcport->vha, 0x301b,
2222 "QUEUE FULL detected.\n");
2223 break;
2224 }
2225 logit = 0;
2226 if (lscsi_status != SS_CHECK_CONDITION)
2227 break;
2228
2229 memset(cp->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE);
2230 if (!(scsi_status & SS_SENSE_LEN_VALID))
2231 break;
2232
2233 qla2x00_handle_sense(sp, sense_data, par_sense_len, sense_len,
2234 rsp, res);
2235 break;
2236
2237 case CS_DATA_UNDERRUN:
2238
2239 resid = IS_FWI2_CAPABLE(ha) ? fw_resid_len : resid_len;
2240 scsi_set_resid(cp, resid);
2241 if (scsi_status & SS_RESIDUAL_UNDER) {
2242 if (IS_FWI2_CAPABLE(ha) && fw_resid_len != resid_len) {
2243 ql_dbg(ql_dbg_io, fcport->vha, 0x301d,
2244 "Dropped frame(s) detected "
2245 "(0x%x of 0x%x bytes).\n",
2246 resid, scsi_bufflen(cp));
2247
2248 res = DID_ERROR << 16 | lscsi_status;
2249 goto check_scsi_status;
2250 }
2251
2252 if (!lscsi_status &&
2253 ((unsigned)(scsi_bufflen(cp) - resid) <
2254 cp->underflow)) {
2255 ql_dbg(ql_dbg_io, fcport->vha, 0x301e,
2256 "Mid-layer underflow "
2257 "detected (0x%x of 0x%x bytes).\n",
2258 resid, scsi_bufflen(cp));
2259
2260 res = DID_ERROR << 16;
2261 break;
2262 }
2263 } else if (lscsi_status != SAM_STAT_TASK_SET_FULL &&
2264 lscsi_status != SAM_STAT_BUSY) {
2265
2266
2267
2268
2269
2270 ql_dbg(ql_dbg_io, fcport->vha, 0x301f,
2271 "Dropped frame(s) detected (0x%x "
2272 "of 0x%x bytes).\n", resid,
2273 scsi_bufflen(cp));
2274
2275 res = DID_ERROR << 16 | lscsi_status;
2276 goto check_scsi_status;
2277 } else {
2278 ql_dbg(ql_dbg_io, fcport->vha, 0x3030,
2279 "scsi_status: 0x%x, lscsi_status: 0x%x\n",
2280 scsi_status, lscsi_status);
2281 }
2282
2283 res = DID_OK << 16 | lscsi_status;
2284 logit = 0;
2285
2286check_scsi_status:
2287
2288
2289
2290
2291 if (lscsi_status != 0) {
2292 if (lscsi_status == SAM_STAT_TASK_SET_FULL) {
2293 ql_dbg(ql_dbg_io, fcport->vha, 0x3020,
2294 "QUEUE FULL detected.\n");
2295 logit = 1;
2296 break;
2297 }
2298 if (lscsi_status != SS_CHECK_CONDITION)
2299 break;
2300
2301 memset(cp->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE);
2302 if (!(scsi_status & SS_SENSE_LEN_VALID))
2303 break;
2304
2305 qla2x00_handle_sense(sp, sense_data, par_sense_len,
2306 sense_len, rsp, res);
2307 }
2308 break;
2309
2310 case CS_PORT_LOGGED_OUT:
2311 case CS_PORT_CONFIG_CHG:
2312 case CS_PORT_BUSY:
2313 case CS_INCOMPLETE:
2314 case CS_PORT_UNAVAILABLE:
2315 case CS_TIMEOUT:
2316 case CS_RESET:
2317
2318
2319
2320
2321
2322
2323 res = DID_TRANSPORT_DISRUPTED << 16;
2324
2325 if (comp_status == CS_TIMEOUT) {
2326 if (IS_FWI2_CAPABLE(ha))
2327 break;
2328 else if ((le16_to_cpu(sts->status_flags) &
2329 SF_LOGOUT_SENT) == 0)
2330 break;
2331 }
2332
2333 ql_dbg(ql_dbg_io, fcport->vha, 0x3021,
2334 "Port to be marked lost on fcport=%02x%02x%02x, current "
2335 "port state= %s.\n", fcport->d_id.b.domain,
2336 fcport->d_id.b.area, fcport->d_id.b.al_pa,
2337 port_state_str[atomic_read(&fcport->state)]);
2338
2339 if (atomic_read(&fcport->state) == FCS_ONLINE)
2340 qla2x00_mark_device_lost(fcport->vha, fcport, 1, 1);
2341 break;
2342
2343 case CS_ABORTED:
2344 res = DID_RESET << 16;
2345 break;
2346
2347 case CS_DIF_ERROR:
2348 logit = qla2x00_handle_dif_error(sp, sts24);
2349 res = cp->result;
2350 break;
2351
2352 case CS_TRANSPORT:
2353 res = DID_ERROR << 16;
2354
2355 if (!IS_PI_SPLIT_DET_CAPABLE(ha))
2356 break;
2357
2358 if (state_flags & BIT_4)
2359 scmd_printk(KERN_WARNING, cp,
2360 "Unsupported device '%s' found.\n",
2361 cp->device->vendor);
2362 break;
2363
2364 default:
2365 res = DID_ERROR << 16;
2366 break;
2367 }
2368
2369out:
2370 if (logit)
2371 ql_dbg(ql_dbg_io, fcport->vha, 0x3022,
2372 "FCP command status: 0x%x-0x%x (0x%x) nexus=%ld:%d:%llu "
2373 "portid=%02x%02x%02x oxid=0x%x cdb=%10phN len=0x%x "
2374 "rsp_info=0x%x resid=0x%x fw_resid=0x%x sp=%p cp=%p.\n",
2375 comp_status, scsi_status, res, vha->host_no,
2376 cp->device->id, cp->device->lun, fcport->d_id.b.domain,
2377 fcport->d_id.b.area, fcport->d_id.b.al_pa, ox_id,
2378 cp->cmnd, scsi_bufflen(cp), rsp_info_len,
2379 resid_len, fw_resid_len, sp, cp);
2380
2381 if (rsp->status_srb == NULL)
2382 sp->done(ha, sp, res);
2383}
2384
2385
2386
2387
2388
2389
2390
2391
2392static void
2393qla2x00_status_cont_entry(struct rsp_que *rsp, sts_cont_entry_t *pkt)
2394{
2395 uint8_t sense_sz = 0;
2396 struct qla_hw_data *ha = rsp->hw;
2397 struct scsi_qla_host *vha = pci_get_drvdata(ha->pdev);
2398 srb_t *sp = rsp->status_srb;
2399 struct scsi_cmnd *cp;
2400 uint32_t sense_len;
2401 uint8_t *sense_ptr;
2402
2403 if (!sp || !GET_CMD_SENSE_LEN(sp))
2404 return;
2405
2406 sense_len = GET_CMD_SENSE_LEN(sp);
2407 sense_ptr = GET_CMD_SENSE_PTR(sp);
2408
2409 cp = GET_CMD_SP(sp);
2410 if (cp == NULL) {
2411 ql_log(ql_log_warn, vha, 0x3025,
2412 "cmd is NULL: already returned to OS (sp=%p).\n", sp);
2413
2414 rsp->status_srb = NULL;
2415 return;
2416 }
2417
2418 if (sense_len > sizeof(pkt->data))
2419 sense_sz = sizeof(pkt->data);
2420 else
2421 sense_sz = sense_len;
2422
2423
2424 if (IS_FWI2_CAPABLE(ha))
2425 host_to_fcp_swap(pkt->data, sizeof(pkt->data));
2426 memcpy(sense_ptr, pkt->data, sense_sz);
2427 ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x302c,
2428 sense_ptr, sense_sz);
2429
2430 sense_len -= sense_sz;
2431 sense_ptr += sense_sz;
2432
2433 SET_CMD_SENSE_PTR(sp, sense_ptr);
2434 SET_CMD_SENSE_LEN(sp, sense_len);
2435
2436
2437 if (sense_len == 0) {
2438 rsp->status_srb = NULL;
2439 sp->done(ha, sp, cp->result);
2440 }
2441}
2442
2443
2444
2445
2446
2447
2448static void
2449qla2x00_error_entry(scsi_qla_host_t *vha, struct rsp_que *rsp, sts_entry_t *pkt)
2450{
2451 srb_t *sp;
2452 struct qla_hw_data *ha = vha->hw;
2453 const char func[] = "ERROR-IOCB";
2454 uint16_t que = MSW(pkt->handle);
2455 struct req_que *req = NULL;
2456 int res = DID_ERROR << 16;
2457
2458 ql_dbg(ql_dbg_async, vha, 0x502a,
2459 "type of error status in response: 0x%x\n", pkt->entry_status);
2460
2461 if (que >= ha->max_req_queues || !ha->req_q_map[que])
2462 goto fatal;
2463
2464 req = ha->req_q_map[que];
2465
2466 if (pkt->entry_status & RF_BUSY)
2467 res = DID_BUS_BUSY << 16;
2468
2469 sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
2470 if (sp) {
2471 sp->done(ha, sp, res);
2472 return;
2473 }
2474fatal:
2475 ql_log(ql_log_warn, vha, 0x5030,
2476 "Error entry - invalid handle/queue (%04x).\n", que);
2477}
2478
2479
2480
2481
2482
2483
2484static void
2485qla24xx_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0)
2486{
2487 uint16_t cnt;
2488 uint32_t mboxes;
2489 uint16_t __iomem *wptr;
2490 struct qla_hw_data *ha = vha->hw;
2491 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
2492
2493
2494 mboxes = (1 << ha->mbx_count) - 1;
2495 if (!ha->mcp)
2496 ql_dbg(ql_dbg_async, vha, 0x504e, "MBX pointer ERROR.\n");
2497 else
2498 mboxes = ha->mcp->in_mb;
2499
2500
2501 ha->flags.mbox_int = 1;
2502 ha->mailbox_out[0] = mb0;
2503 mboxes >>= 1;
2504 wptr = (uint16_t __iomem *)®->mailbox1;
2505
2506 for (cnt = 1; cnt < ha->mbx_count; cnt++) {
2507 if (mboxes & BIT_0)
2508 ha->mailbox_out[cnt] = RD_REG_WORD(wptr);
2509
2510 mboxes >>= 1;
2511 wptr++;
2512 }
2513}
2514
2515static void
2516qla24xx_abort_iocb_entry(scsi_qla_host_t *vha, struct req_que *req,
2517 struct abort_entry_24xx *pkt)
2518{
2519 const char func[] = "ABT_IOCB";
2520 srb_t *sp;
2521 struct srb_iocb *abt;
2522
2523 sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
2524 if (!sp)
2525 return;
2526
2527 abt = &sp->u.iocb_cmd;
2528 abt->u.abt.comp_status = le32_to_cpu(pkt->nport_handle);
2529 sp->done(vha, sp, 0);
2530}
2531
2532
2533
2534
2535
2536void qla24xx_process_response_queue(struct scsi_qla_host *vha,
2537 struct rsp_que *rsp)
2538{
2539 struct sts_entry_24xx *pkt;
2540 struct qla_hw_data *ha = vha->hw;
2541
2542 if (!vha->flags.online)
2543 return;
2544
2545 while (rsp->ring_ptr->signature != RESPONSE_PROCESSED) {
2546 pkt = (struct sts_entry_24xx *)rsp->ring_ptr;
2547
2548 rsp->ring_index++;
2549 if (rsp->ring_index == rsp->length) {
2550 rsp->ring_index = 0;
2551 rsp->ring_ptr = rsp->ring;
2552 } else {
2553 rsp->ring_ptr++;
2554 }
2555
2556 if (pkt->entry_status != 0) {
2557 qla2x00_error_entry(vha, rsp, (sts_entry_t *) pkt);
2558
2559 if (qlt_24xx_process_response_error(vha, pkt))
2560 goto process_err;
2561
2562 ((response_t *)pkt)->signature = RESPONSE_PROCESSED;
2563 wmb();
2564 continue;
2565 }
2566process_err:
2567
2568 switch (pkt->entry_type) {
2569 case STATUS_TYPE:
2570 qla2x00_status_entry(vha, rsp, pkt);
2571 break;
2572 case STATUS_CONT_TYPE:
2573 qla2x00_status_cont_entry(rsp, (sts_cont_entry_t *)pkt);
2574 break;
2575 case VP_RPT_ID_IOCB_TYPE:
2576 qla24xx_report_id_acquisition(vha,
2577 (struct vp_rpt_id_entry_24xx *)pkt);
2578 break;
2579 case LOGINOUT_PORT_IOCB_TYPE:
2580 qla24xx_logio_entry(vha, rsp->req,
2581 (struct logio_entry_24xx *)pkt);
2582 break;
2583 case CT_IOCB_TYPE:
2584 qla24xx_els_ct_entry(vha, rsp->req, pkt, CT_IOCB_TYPE);
2585 break;
2586 case ELS_IOCB_TYPE:
2587 qla24xx_els_ct_entry(vha, rsp->req, pkt, ELS_IOCB_TYPE);
2588 break;
2589 case ABTS_RECV_24XX:
2590
2591 qlt_24xx_process_atio_queue(vha);
2592 case ABTS_RESP_24XX:
2593 case CTIO_TYPE7:
2594 case NOTIFY_ACK_TYPE:
2595 case CTIO_CRC2:
2596 qlt_response_pkt_all_vps(vha, (response_t *)pkt);
2597 break;
2598 case MARKER_TYPE:
2599
2600
2601
2602 break;
2603 case ABORT_IOCB_TYPE:
2604 qla24xx_abort_iocb_entry(vha, rsp->req,
2605 (struct abort_entry_24xx *)pkt);
2606 break;
2607 default:
2608
2609 ql_dbg(ql_dbg_async, vha, 0x5042,
2610 "Received unknown response pkt type %x "
2611 "entry status=%x.\n",
2612 pkt->entry_type, pkt->entry_status);
2613 break;
2614 }
2615 ((response_t *)pkt)->signature = RESPONSE_PROCESSED;
2616 wmb();
2617 }
2618
2619
2620 if (IS_P3P_TYPE(ha)) {
2621 struct device_reg_82xx __iomem *reg = &ha->iobase->isp82;
2622 WRT_REG_DWORD(®->rsp_q_out[0], rsp->ring_index);
2623 } else
2624 WRT_REG_DWORD(rsp->rsp_q_out, rsp->ring_index);
2625}
2626
2627static void
2628qla2xxx_check_risc_status(scsi_qla_host_t *vha)
2629{
2630 int rval;
2631 uint32_t cnt;
2632 struct qla_hw_data *ha = vha->hw;
2633 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
2634
2635 if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha) &&
2636 !IS_QLA27XX(ha))
2637 return;
2638
2639 rval = QLA_SUCCESS;
2640 WRT_REG_DWORD(®->iobase_addr, 0x7C00);
2641 RD_REG_DWORD(®->iobase_addr);
2642 WRT_REG_DWORD(®->iobase_window, 0x0001);
2643 for (cnt = 10000; (RD_REG_DWORD(®->iobase_window) & BIT_0) == 0 &&
2644 rval == QLA_SUCCESS; cnt--) {
2645 if (cnt) {
2646 WRT_REG_DWORD(®->iobase_window, 0x0001);
2647 udelay(10);
2648 } else
2649 rval = QLA_FUNCTION_TIMEOUT;
2650 }
2651 if (rval == QLA_SUCCESS)
2652 goto next_test;
2653
2654 rval = QLA_SUCCESS;
2655 WRT_REG_DWORD(®->iobase_window, 0x0003);
2656 for (cnt = 100; (RD_REG_DWORD(®->iobase_window) & BIT_0) == 0 &&
2657 rval == QLA_SUCCESS; cnt--) {
2658 if (cnt) {
2659 WRT_REG_DWORD(®->iobase_window, 0x0003);
2660 udelay(10);
2661 } else
2662 rval = QLA_FUNCTION_TIMEOUT;
2663 }
2664 if (rval != QLA_SUCCESS)
2665 goto done;
2666
2667next_test:
2668 if (RD_REG_DWORD(®->iobase_c8) & BIT_3)
2669 ql_log(ql_log_info, vha, 0x504c,
2670 "Additional code -- 0x55AA.\n");
2671
2672done:
2673 WRT_REG_DWORD(®->iobase_window, 0x0000);
2674 RD_REG_DWORD(®->iobase_window);
2675}
2676
2677
2678
2679
2680
2681
2682
2683
2684
2685
2686irqreturn_t
2687qla24xx_intr_handler(int irq, void *dev_id)
2688{
2689 scsi_qla_host_t *vha;
2690 struct qla_hw_data *ha;
2691 struct device_reg_24xx __iomem *reg;
2692 int status;
2693 unsigned long iter;
2694 uint32_t stat;
2695 uint32_t hccr;
2696 uint16_t mb[8];
2697 struct rsp_que *rsp;
2698 unsigned long flags;
2699
2700 rsp = (struct rsp_que *) dev_id;
2701 if (!rsp) {
2702 ql_log(ql_log_info, NULL, 0x5059,
2703 "%s: NULL response queue pointer.\n", __func__);
2704 return IRQ_NONE;
2705 }
2706
2707 ha = rsp->hw;
2708 reg = &ha->iobase->isp24;
2709 status = 0;
2710
2711 if (unlikely(pci_channel_offline(ha->pdev)))
2712 return IRQ_HANDLED;
2713
2714 spin_lock_irqsave(&ha->hardware_lock, flags);
2715 vha = pci_get_drvdata(ha->pdev);
2716 for (iter = 50; iter--; ) {
2717 stat = RD_REG_DWORD(®->host_status);
2718 if (qla2x00_check_reg32_for_disconnect(vha, stat))
2719 break;
2720 if (stat & HSRX_RISC_PAUSED) {
2721 if (unlikely(pci_channel_offline(ha->pdev)))
2722 break;
2723
2724 hccr = RD_REG_DWORD(®->hccr);
2725
2726 ql_log(ql_log_warn, vha, 0x504b,
2727 "RISC paused -- HCCR=%x, Dumping firmware.\n",
2728 hccr);
2729
2730 qla2xxx_check_risc_status(vha);
2731
2732 ha->isp_ops->fw_dump(vha, 1);
2733 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2734 break;
2735 } else if ((stat & HSRX_RISC_INT) == 0)
2736 break;
2737
2738 switch (stat & 0xff) {
2739 case INTR_ROM_MB_SUCCESS:
2740 case INTR_ROM_MB_FAILED:
2741 case INTR_MB_SUCCESS:
2742 case INTR_MB_FAILED:
2743 qla24xx_mbx_completion(vha, MSW(stat));
2744 status |= MBX_INTERRUPT;
2745
2746 break;
2747 case INTR_ASYNC_EVENT:
2748 mb[0] = MSW(stat);
2749 mb[1] = RD_REG_WORD(®->mailbox1);
2750 mb[2] = RD_REG_WORD(®->mailbox2);
2751 mb[3] = RD_REG_WORD(®->mailbox3);
2752 qla2x00_async_event(vha, rsp, mb);
2753 break;
2754 case INTR_RSP_QUE_UPDATE:
2755 case INTR_RSP_QUE_UPDATE_83XX:
2756 qla24xx_process_response_queue(vha, rsp);
2757 break;
2758 case INTR_ATIO_QUE_UPDATE:
2759 qlt_24xx_process_atio_queue(vha);
2760 break;
2761 case INTR_ATIO_RSP_QUE_UPDATE:
2762 qlt_24xx_process_atio_queue(vha);
2763 qla24xx_process_response_queue(vha, rsp);
2764 break;
2765 default:
2766 ql_dbg(ql_dbg_async, vha, 0x504f,
2767 "Unrecognized interrupt type (%d).\n", stat * 0xff);
2768 break;
2769 }
2770 WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_INT);
2771 RD_REG_DWORD_RELAXED(®->hccr);
2772 if (unlikely(IS_QLA83XX(ha) && (ha->pdev->revision == 1)))
2773 ndelay(3500);
2774 }
2775 qla2x00_handle_mbx_completion(ha, status);
2776 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2777
2778 return IRQ_HANDLED;
2779}
2780
2781static irqreturn_t
2782qla24xx_msix_rsp_q(int irq, void *dev_id)
2783{
2784 struct qla_hw_data *ha;
2785 struct rsp_que *rsp;
2786 struct device_reg_24xx __iomem *reg;
2787 struct scsi_qla_host *vha;
2788 unsigned long flags;
2789 uint32_t stat = 0;
2790
2791 rsp = (struct rsp_que *) dev_id;
2792 if (!rsp) {
2793 ql_log(ql_log_info, NULL, 0x505a,
2794 "%s: NULL response queue pointer.\n", __func__);
2795 return IRQ_NONE;
2796 }
2797 ha = rsp->hw;
2798 reg = &ha->iobase->isp24;
2799
2800 spin_lock_irqsave(&ha->hardware_lock, flags);
2801
2802 vha = pci_get_drvdata(ha->pdev);
2803
2804
2805
2806
2807 stat = RD_REG_DWORD(®->host_status);
2808 if (qla2x00_check_reg32_for_disconnect(vha, stat))
2809 goto out;
2810 qla24xx_process_response_queue(vha, rsp);
2811 if (!ha->flags.disable_msix_handshake) {
2812 WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_INT);
2813 RD_REG_DWORD_RELAXED(®->hccr);
2814 }
2815out:
2816 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2817
2818 return IRQ_HANDLED;
2819}
2820
2821static irqreturn_t
2822qla25xx_msix_rsp_q(int irq, void *dev_id)
2823{
2824 struct qla_hw_data *ha;
2825 scsi_qla_host_t *vha;
2826 struct rsp_que *rsp;
2827 struct device_reg_24xx __iomem *reg;
2828 unsigned long flags;
2829 uint32_t hccr = 0;
2830
2831 rsp = (struct rsp_que *) dev_id;
2832 if (!rsp) {
2833 ql_log(ql_log_info, NULL, 0x505b,
2834 "%s: NULL response queue pointer.\n", __func__);
2835 return IRQ_NONE;
2836 }
2837 ha = rsp->hw;
2838 vha = pci_get_drvdata(ha->pdev);
2839
2840
2841 if (!ha->flags.disable_msix_handshake) {
2842 reg = &ha->iobase->isp24;
2843 spin_lock_irqsave(&ha->hardware_lock, flags);
2844 WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_INT);
2845 hccr = RD_REG_DWORD_RELAXED(®->hccr);
2846 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2847 }
2848 if (qla2x00_check_reg32_for_disconnect(vha, hccr))
2849 goto out;
2850 queue_work_on((int) (rsp->id - 1), ha->wq, &rsp->q_work);
2851
2852out:
2853 return IRQ_HANDLED;
2854}
2855
2856static irqreturn_t
2857qla24xx_msix_default(int irq, void *dev_id)
2858{
2859 scsi_qla_host_t *vha;
2860 struct qla_hw_data *ha;
2861 struct rsp_que *rsp;
2862 struct device_reg_24xx __iomem *reg;
2863 int status;
2864 uint32_t stat;
2865 uint32_t hccr;
2866 uint16_t mb[8];
2867 unsigned long flags;
2868
2869 rsp = (struct rsp_que *) dev_id;
2870 if (!rsp) {
2871 ql_log(ql_log_info, NULL, 0x505c,
2872 "%s: NULL response queue pointer.\n", __func__);
2873 return IRQ_NONE;
2874 }
2875 ha = rsp->hw;
2876 reg = &ha->iobase->isp24;
2877 status = 0;
2878
2879 spin_lock_irqsave(&ha->hardware_lock, flags);
2880 vha = pci_get_drvdata(ha->pdev);
2881 do {
2882 stat = RD_REG_DWORD(®->host_status);
2883 if (qla2x00_check_reg32_for_disconnect(vha, stat))
2884 break;
2885 if (stat & HSRX_RISC_PAUSED) {
2886 if (unlikely(pci_channel_offline(ha->pdev)))
2887 break;
2888
2889 hccr = RD_REG_DWORD(®->hccr);
2890
2891 ql_log(ql_log_info, vha, 0x5050,
2892 "RISC paused -- HCCR=%x, Dumping firmware.\n",
2893 hccr);
2894
2895 qla2xxx_check_risc_status(vha);
2896
2897 ha->isp_ops->fw_dump(vha, 1);
2898 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2899 break;
2900 } else if ((stat & HSRX_RISC_INT) == 0)
2901 break;
2902
2903 switch (stat & 0xff) {
2904 case INTR_ROM_MB_SUCCESS:
2905 case INTR_ROM_MB_FAILED:
2906 case INTR_MB_SUCCESS:
2907 case INTR_MB_FAILED:
2908 qla24xx_mbx_completion(vha, MSW(stat));
2909 status |= MBX_INTERRUPT;
2910
2911 break;
2912 case INTR_ASYNC_EVENT:
2913 mb[0] = MSW(stat);
2914 mb[1] = RD_REG_WORD(®->mailbox1);
2915 mb[2] = RD_REG_WORD(®->mailbox2);
2916 mb[3] = RD_REG_WORD(®->mailbox3);
2917 qla2x00_async_event(vha, rsp, mb);
2918 break;
2919 case INTR_RSP_QUE_UPDATE:
2920 case INTR_RSP_QUE_UPDATE_83XX:
2921 qla24xx_process_response_queue(vha, rsp);
2922 break;
2923 case INTR_ATIO_QUE_UPDATE:
2924 qlt_24xx_process_atio_queue(vha);
2925 break;
2926 case INTR_ATIO_RSP_QUE_UPDATE:
2927 qlt_24xx_process_atio_queue(vha);
2928 qla24xx_process_response_queue(vha, rsp);
2929 break;
2930 default:
2931 ql_dbg(ql_dbg_async, vha, 0x5051,
2932 "Unrecognized interrupt type (%d).\n", stat & 0xff);
2933 break;
2934 }
2935 WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_INT);
2936 } while (0);
2937 qla2x00_handle_mbx_completion(ha, status);
2938 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2939
2940 return IRQ_HANDLED;
2941}
2942
2943
2944
2945struct qla_init_msix_entry {
2946 const char *name;
2947 irq_handler_t handler;
2948};
2949
2950static struct qla_init_msix_entry msix_entries[3] = {
2951 { "qla2xxx (default)", qla24xx_msix_default },
2952 { "qla2xxx (rsp_q)", qla24xx_msix_rsp_q },
2953 { "qla2xxx (multiq)", qla25xx_msix_rsp_q },
2954};
2955
2956static struct qla_init_msix_entry qla82xx_msix_entries[2] = {
2957 { "qla2xxx (default)", qla82xx_msix_default },
2958 { "qla2xxx (rsp_q)", qla82xx_msix_rsp_q },
2959};
2960
2961static struct qla_init_msix_entry qla83xx_msix_entries[3] = {
2962 { "qla2xxx (default)", qla24xx_msix_default },
2963 { "qla2xxx (rsp_q)", qla24xx_msix_rsp_q },
2964 { "qla2xxx (atio_q)", qla83xx_msix_atio_q },
2965};
2966
2967static void
2968qla24xx_disable_msix(struct qla_hw_data *ha)
2969{
2970 int i;
2971 struct qla_msix_entry *qentry;
2972 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2973
2974 for (i = 0; i < ha->msix_count; i++) {
2975 qentry = &ha->msix_entries[i];
2976 if (qentry->have_irq)
2977 free_irq(qentry->vector, qentry->rsp);
2978 }
2979 pci_disable_msix(ha->pdev);
2980 kfree(ha->msix_entries);
2981 ha->msix_entries = NULL;
2982 ha->flags.msix_enabled = 0;
2983 ql_dbg(ql_dbg_init, vha, 0x0042,
2984 "Disabled the MSI.\n");
2985}
2986
2987static int
2988qla24xx_enable_msix(struct qla_hw_data *ha, struct rsp_que *rsp)
2989{
2990#define MIN_MSIX_COUNT 2
2991#define ATIO_VECTOR 2
2992 int i, ret;
2993 struct msix_entry *entries;
2994 struct qla_msix_entry *qentry;
2995 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2996
2997 entries = kzalloc(sizeof(struct msix_entry) * ha->msix_count,
2998 GFP_KERNEL);
2999 if (!entries) {
3000 ql_log(ql_log_warn, vha, 0x00bc,
3001 "Failed to allocate memory for msix_entry.\n");
3002 return -ENOMEM;
3003 }
3004
3005 for (i = 0; i < ha->msix_count; i++)
3006 entries[i].entry = i;
3007
3008 ret = pci_enable_msix_range(ha->pdev,
3009 entries, MIN_MSIX_COUNT, ha->msix_count);
3010 if (ret < 0) {
3011 ql_log(ql_log_fatal, vha, 0x00c7,
3012 "MSI-X: Failed to enable support, "
3013 "giving up -- %d/%d.\n",
3014 ha->msix_count, ret);
3015 goto msix_out;
3016 } else if (ret < ha->msix_count) {
3017 ql_log(ql_log_warn, vha, 0x00c6,
3018 "MSI-X: Failed to enable support "
3019 "-- %d/%d\n Retry with %d vectors.\n",
3020 ha->msix_count, ret, ret);
3021 }
3022 ha->msix_count = ret;
3023 ha->max_rsp_queues = ha->msix_count - 1;
3024 ha->msix_entries = kzalloc(sizeof(struct qla_msix_entry) *
3025 ha->msix_count, GFP_KERNEL);
3026 if (!ha->msix_entries) {
3027 ql_log(ql_log_fatal, vha, 0x00c8,
3028 "Failed to allocate memory for ha->msix_entries.\n");
3029 ret = -ENOMEM;
3030 goto msix_out;
3031 }
3032 ha->flags.msix_enabled = 1;
3033
3034 for (i = 0; i < ha->msix_count; i++) {
3035 qentry = &ha->msix_entries[i];
3036 qentry->vector = entries[i].vector;
3037 qentry->entry = entries[i].entry;
3038 qentry->have_irq = 0;
3039 qentry->rsp = NULL;
3040 }
3041
3042
3043 for (i = 0; i < 2; i++) {
3044 qentry = &ha->msix_entries[i];
3045 if (IS_P3P_TYPE(ha))
3046 ret = request_irq(qentry->vector,
3047 qla82xx_msix_entries[i].handler,
3048 0, qla82xx_msix_entries[i].name, rsp);
3049 else
3050 ret = request_irq(qentry->vector,
3051 msix_entries[i].handler,
3052 0, msix_entries[i].name, rsp);
3053 if (ret)
3054 goto msix_register_fail;
3055 qentry->have_irq = 1;
3056 qentry->rsp = rsp;
3057 rsp->msix = qentry;
3058 }
3059
3060
3061
3062
3063
3064 if (QLA_TGT_MODE_ENABLED() && IS_ATIO_MSIX_CAPABLE(ha)) {
3065 qentry = &ha->msix_entries[ATIO_VECTOR];
3066 ret = request_irq(qentry->vector,
3067 qla83xx_msix_entries[ATIO_VECTOR].handler,
3068 0, qla83xx_msix_entries[ATIO_VECTOR].name, rsp);
3069 qentry->have_irq = 1;
3070 qentry->rsp = rsp;
3071 rsp->msix = qentry;
3072 }
3073
3074msix_register_fail:
3075 if (ret) {
3076 ql_log(ql_log_fatal, vha, 0x00cb,
3077 "MSI-X: unable to register handler -- %x/%d.\n",
3078 qentry->vector, ret);
3079 qla24xx_disable_msix(ha);
3080 ha->mqenable = 0;
3081 goto msix_out;
3082 }
3083
3084
3085 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
3086 if (ha->msixbase && ha->mqiobase &&
3087 (ha->max_rsp_queues > 1 || ha->max_req_queues > 1))
3088 ha->mqenable = 1;
3089 } else
3090 if (ha->mqiobase
3091 && (ha->max_rsp_queues > 1 || ha->max_req_queues > 1))
3092 ha->mqenable = 1;
3093 ql_dbg(ql_dbg_multiq, vha, 0xc005,
3094 "mqiobase=%p, max_rsp_queues=%d, max_req_queues=%d.\n",
3095 ha->mqiobase, ha->max_rsp_queues, ha->max_req_queues);
3096 ql_dbg(ql_dbg_init, vha, 0x0055,
3097 "mqiobase=%p, max_rsp_queues=%d, max_req_queues=%d.\n",
3098 ha->mqiobase, ha->max_rsp_queues, ha->max_req_queues);
3099
3100msix_out:
3101 kfree(entries);
3102 return ret;
3103}
3104
3105int
3106qla2x00_request_irqs(struct qla_hw_data *ha, struct rsp_que *rsp)
3107{
3108 int ret = QLA_FUNCTION_FAILED;
3109 device_reg_t *reg = ha->iobase;
3110 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
3111
3112
3113 if (!IS_QLA2432(ha) && !IS_QLA2532(ha) && !IS_QLA8432(ha) &&
3114 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha) && !IS_QLAFX00(ha) &&
3115 !IS_QLA27XX(ha))
3116 goto skip_msi;
3117
3118 if (ha->pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
3119 (ha->pdev->subsystem_device == 0x7040 ||
3120 ha->pdev->subsystem_device == 0x7041 ||
3121 ha->pdev->subsystem_device == 0x1705)) {
3122 ql_log(ql_log_warn, vha, 0x0034,
3123 "MSI-X: Unsupported ISP 2432 SSVID/SSDID (0x%X,0x%X).\n",
3124 ha->pdev->subsystem_vendor,
3125 ha->pdev->subsystem_device);
3126 goto skip_msi;
3127 }
3128
3129 if (IS_QLA2432(ha) && (ha->pdev->revision < QLA_MSIX_CHIP_REV_24XX)) {
3130 ql_log(ql_log_warn, vha, 0x0035,
3131 "MSI-X; Unsupported ISP2432 (0x%X, 0x%X).\n",
3132 ha->pdev->revision, QLA_MSIX_CHIP_REV_24XX);
3133 goto skip_msix;
3134 }
3135
3136 ret = qla24xx_enable_msix(ha, rsp);
3137 if (!ret) {
3138 ql_dbg(ql_dbg_init, vha, 0x0036,
3139 "MSI-X: Enabled (0x%X, 0x%X).\n",
3140 ha->chip_revision, ha->fw_attributes);
3141 goto clear_risc_ints;
3142 }
3143
3144skip_msix:
3145
3146 ql_log(ql_log_info, vha, 0x0037,
3147 "Falling back-to MSI mode -%d.\n", ret);
3148
3149 if (!IS_QLA24XX(ha) && !IS_QLA2532(ha) && !IS_QLA8432(ha) &&
3150 !IS_QLA8001(ha) && !IS_P3P_TYPE(ha) && !IS_QLAFX00(ha) &&
3151 !IS_QLA27XX(ha))
3152 goto skip_msi;
3153
3154 ret = pci_enable_msi(ha->pdev);
3155 if (!ret) {
3156 ql_dbg(ql_dbg_init, vha, 0x0038,
3157 "MSI: Enabled.\n");
3158 ha->flags.msi_enabled = 1;
3159 } else
3160 ql_log(ql_log_warn, vha, 0x0039,
3161 "Falling back-to INTa mode -- %d.\n", ret);
3162skip_msi:
3163
3164
3165 if (!ha->flags.msi_enabled && IS_QLA82XX(ha))
3166 return QLA_FUNCTION_FAILED;
3167
3168 ret = request_irq(ha->pdev->irq, ha->isp_ops->intr_handler,
3169 ha->flags.msi_enabled ? 0 : IRQF_SHARED,
3170 QLA2XXX_DRIVER_NAME, rsp);
3171 if (ret) {
3172 ql_log(ql_log_warn, vha, 0x003a,
3173 "Failed to reserve interrupt %d already in use.\n",
3174 ha->pdev->irq);
3175 goto fail;
3176 } else if (!ha->flags.msi_enabled) {
3177 ql_dbg(ql_dbg_init, vha, 0x0125,
3178 "INTa mode: Enabled.\n");
3179 ha->flags.mr_intr_valid = 1;
3180 }
3181
3182clear_risc_ints:
3183 if (IS_FWI2_CAPABLE(ha) || IS_QLAFX00(ha))
3184 goto fail;
3185
3186 spin_lock_irq(&ha->hardware_lock);
3187 WRT_REG_WORD(®->isp.semaphore, 0);
3188 spin_unlock_irq(&ha->hardware_lock);
3189
3190fail:
3191 return ret;
3192}
3193
3194void
3195qla2x00_free_irqs(scsi_qla_host_t *vha)
3196{
3197 struct qla_hw_data *ha = vha->hw;
3198 struct rsp_que *rsp;
3199
3200
3201
3202
3203
3204 if (!ha->rsp_q_map || !ha->rsp_q_map[0])
3205 return;
3206 rsp = ha->rsp_q_map[0];
3207
3208 if (ha->flags.msix_enabled)
3209 qla24xx_disable_msix(ha);
3210 else if (ha->flags.msi_enabled) {
3211 free_irq(ha->pdev->irq, rsp);
3212 pci_disable_msi(ha->pdev);
3213 } else
3214 free_irq(ha->pdev->irq, rsp);
3215}
3216
3217
3218int qla25xx_request_irq(struct rsp_que *rsp)
3219{
3220 struct qla_hw_data *ha = rsp->hw;
3221 struct qla_init_msix_entry *intr = &msix_entries[2];
3222 struct qla_msix_entry *msix = rsp->msix;
3223 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
3224 int ret;
3225
3226 ret = request_irq(msix->vector, intr->handler, 0, intr->name, rsp);
3227 if (ret) {
3228 ql_log(ql_log_fatal, vha, 0x00e6,
3229 "MSI-X: Unable to register handler -- %x/%d.\n",
3230 msix->vector, ret);
3231 return ret;
3232 }
3233 msix->have_irq = 1;
3234 msix->rsp = rsp;
3235 return ret;
3236}
3237
