LXR linux/drivers/spi/spi-xlp.c

   1/*
   2 * Copyright (C) 2003-2015 Broadcom Corporation
   3 * All Rights Reserved
   4 *
   5 * This program is free software; you can redistribute it and/or modify
   6 * it under the terms of the GNU General Public License version 2 (GPL v2)
   7 * as published by the Free Software Foundation.
   8 *
   9 * This program is distributed in the hope that it will be useful,
  10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12 * GNU General Public License for more details.
  13 */
  14#include <linux/clk.h>
  15#include <linux/kernel.h>
  16#include <linux/module.h>
  17#include <linux/platform_device.h>
  18#include <linux/spi/spi.h>
  19#include <linux/of.h>
  20#include <linux/interrupt.h>
  21
  22/* SPI Configuration Register */
  23#define XLP_SPI_CONFIG                  0x00
  24#define XLP_SPI_CPHA                    BIT(0)
  25#define XLP_SPI_CPOL                    BIT(1)
  26#define XLP_SPI_CS_POL                  BIT(2)
  27#define XLP_SPI_TXMISO_EN               BIT(3)
  28#define XLP_SPI_TXMOSI_EN               BIT(4)
  29#define XLP_SPI_RXMISO_EN               BIT(5)
  30#define XLP_SPI_CS_LSBFE                BIT(10)
  31#define XLP_SPI_RXCAP_EN                BIT(11)
  32
  33/* SPI Frequency Divider Register */
  34#define XLP_SPI_FDIV                    0x04
  35
  36/* SPI Command Register */
  37#define XLP_SPI_CMD                     0x08
  38#define XLP_SPI_CMD_IDLE_MASK           0x0
  39#define XLP_SPI_CMD_TX_MASK             0x1
  40#define XLP_SPI_CMD_RX_MASK             0x2
  41#define XLP_SPI_CMD_TXRX_MASK           0x3
  42#define XLP_SPI_CMD_CONT                BIT(4)
  43#define XLP_SPI_XFR_BITCNT_SHIFT        16
  44
  45/* SPI Status Register */
  46#define XLP_SPI_STATUS                  0x0c
  47#define XLP_SPI_XFR_PENDING             BIT(0)
  48#define XLP_SPI_XFR_DONE                BIT(1)
  49#define XLP_SPI_TX_INT                  BIT(2)
  50#define XLP_SPI_RX_INT                  BIT(3)
  51#define XLP_SPI_TX_UF                   BIT(4)
  52#define XLP_SPI_RX_OF                   BIT(5)
  53#define XLP_SPI_STAT_MASK               0x3f
  54
  55/* SPI Interrupt Enable Register */
  56#define XLP_SPI_INTR_EN                 0x10
  57#define XLP_SPI_INTR_DONE               BIT(0)
  58#define XLP_SPI_INTR_TXTH               BIT(1)
  59#define XLP_SPI_INTR_RXTH               BIT(2)
  60#define XLP_SPI_INTR_TXUF               BIT(3)
  61#define XLP_SPI_INTR_RXOF               BIT(4)
  62
  63/* SPI FIFO Threshold Register */
  64#define XLP_SPI_FIFO_THRESH             0x14
  65
  66/* SPI FIFO Word Count Register */
  67#define XLP_SPI_FIFO_WCNT               0x18
  68#define XLP_SPI_RXFIFO_WCNT_MASK        0xf
  69#define XLP_SPI_TXFIFO_WCNT_MASK        0xf0
  70#define XLP_SPI_TXFIFO_WCNT_SHIFT       4
  71
  72/* SPI Transmit Data FIFO Register */
  73#define XLP_SPI_TXDATA_FIFO             0x1c
  74
  75/* SPI Receive Data FIFO Register */
  76#define XLP_SPI_RXDATA_FIFO             0x20
  77
  78/* SPI System Control Register */
  79#define XLP_SPI_SYSCTRL                 0x100
  80#define XLP_SPI_SYS_RESET               BIT(0)
  81#define XLP_SPI_SYS_CLKDIS              BIT(1)
  82#define XLP_SPI_SYS_PMEN                BIT(8)
  83
  84#define SPI_CS_OFFSET                   0x40
  85#define XLP_SPI_TXRXTH                  0x80
  86#define XLP_SPI_FIFO_SIZE               8
  87#define XLP_SPI_MAX_CS                  4
  88#define XLP_SPI_DEFAULT_FREQ            133333333
  89#define XLP_SPI_FDIV_MIN                4
  90#define XLP_SPI_FDIV_MAX                65535
  91/*
  92 * SPI can transfer only 28 bytes properly at a time. So split the
  93 * transfer into 28 bytes size.
  94 */
  95#define XLP_SPI_XFER_SIZE               28
  96
  97struct xlp_spi_priv {
  98        struct device           dev;            /* device structure */
  99        void __iomem            *base;          /* spi registers base address */
 100        const u8                *tx_buf;        /* tx data buffer */
 101        u8                      *rx_buf;        /* rx data buffer */
 102        int                     tx_len;         /* tx xfer length */
 103        int                     rx_len;         /* rx xfer length */
 104        int                     txerrors;       /* TXFIFO underflow count */
 105        int                     rxerrors;       /* RXFIFO overflow count */
 106        int                     cs;             /* slave device chip select */
 107        u32                     spi_clk;        /* spi clock frequency */
 108        bool                    cmd_cont;       /* cs active */
 109        struct completion       done;           /* completion notification */
 110};
 111
 112static inline u32 xlp_spi_reg_read(struct xlp_spi_priv *priv,
 113                                int cs, int regoff)
 114{
 115        return readl(priv->base + regoff + cs * SPI_CS_OFFSET);
 116}
 117
 118static inline void xlp_spi_reg_write(struct xlp_spi_priv *priv, int cs,
 119                                int regoff, u32 val)
 120{
 121        writel(val, priv->base + regoff + cs * SPI_CS_OFFSET);
 122}
 123
 124static inline void xlp_spi_sysctl_write(struct xlp_spi_priv *priv,
 125                                int regoff, u32 val)
 126{
 127        writel(val, priv->base + regoff);
 128}
 129
 130/*
 131 * Setup global SPI_SYSCTRL register for all SPI channels.
 132 */
 133static void xlp_spi_sysctl_setup(struct xlp_spi_priv *xspi)
 134{
 135        int cs;
 136
 137        for (cs = 0; cs < XLP_SPI_MAX_CS; cs++)
 138                xlp_spi_sysctl_write(xspi, XLP_SPI_SYSCTRL,
 139                                XLP_SPI_SYS_RESET << cs);
 140        xlp_spi_sysctl_write(xspi, XLP_SPI_SYSCTRL, XLP_SPI_SYS_PMEN);
 141}
 142
 143static int xlp_spi_setup(struct spi_device *spi)
 144{
 145        struct xlp_spi_priv *xspi;
 146        u32 fdiv, cfg;
 147        int cs;
 148
 149        xspi = spi_master_get_devdata(spi->master);
 150        cs = spi->chip_select;
 151        /*
 152         * The value of fdiv must be between 4 and 65535.
 153         */
 154        fdiv = DIV_ROUND_UP(xspi->spi_clk, spi->max_speed_hz);
 155        if (fdiv > XLP_SPI_FDIV_MAX)
 156                fdiv = XLP_SPI_FDIV_MAX;
 157        else if (fdiv < XLP_SPI_FDIV_MIN)
 158                fdiv = XLP_SPI_FDIV_MIN;
 159
 160        xlp_spi_reg_write(xspi, cs, XLP_SPI_FDIV, fdiv);
 161        xlp_spi_reg_write(xspi, cs, XLP_SPI_FIFO_THRESH, XLP_SPI_TXRXTH);
 162        cfg = xlp_spi_reg_read(xspi, cs, XLP_SPI_CONFIG);
 163        if (spi->mode & SPI_CPHA)
 164                cfg |= XLP_SPI_CPHA;
 165        else
 166                cfg &= ~XLP_SPI_CPHA;
 167        if (spi->mode & SPI_CPOL)
 168                cfg |= XLP_SPI_CPOL;
 169        else
 170                cfg &= ~XLP_SPI_CPOL;
 171        if (!(spi->mode & SPI_CS_HIGH))
 172                cfg |= XLP_SPI_CS_POL;
 173        else
 174                cfg &= ~XLP_SPI_CS_POL;
 175        if (spi->mode & SPI_LSB_FIRST)
 176                cfg |= XLP_SPI_CS_LSBFE;
 177        else
 178                cfg &= ~XLP_SPI_CS_LSBFE;
 179
 180        cfg |= XLP_SPI_TXMOSI_EN | XLP_SPI_RXMISO_EN;
 181        if (fdiv == 4)
 182                cfg |= XLP_SPI_RXCAP_EN;
 183        xlp_spi_reg_write(xspi, cs, XLP_SPI_CONFIG, cfg);
 184
 185        return 0;
 186}
 187
 188static void xlp_spi_read_rxfifo(struct xlp_spi_priv *xspi)
 189{
 190        u32 rx_data, rxfifo_cnt;
 191        int i, j, nbytes;
 192
 193        rxfifo_cnt = xlp_spi_reg_read(xspi, xspi->cs, XLP_SPI_FIFO_WCNT);
 194        rxfifo_cnt &= XLP_SPI_RXFIFO_WCNT_MASK;
 195        while (rxfifo_cnt) {
 196                rx_data = xlp_spi_reg_read(xspi, xspi->cs, XLP_SPI_RXDATA_FIFO);
 197                j = 0;
 198                nbytes = min(xspi->rx_len, 4);
 199                for (i = nbytes - 1; i >= 0; i--, j++)
 200                        xspi->rx_buf[i] = (rx_data >> (j * 8)) & 0xff;
 201
 202                xspi->rx_len -= nbytes;
 203                xspi->rx_buf += nbytes;
 204                rxfifo_cnt--;
 205        }
 206}
 207
 208static void xlp_spi_fill_txfifo(struct xlp_spi_priv *xspi)
 209{
 210        u32 tx_data, txfifo_cnt;
 211        int i, j, nbytes;
 212
 213        txfifo_cnt = xlp_spi_reg_read(xspi, xspi->cs, XLP_SPI_FIFO_WCNT);
 214        txfifo_cnt &= XLP_SPI_TXFIFO_WCNT_MASK;
 215        txfifo_cnt >>= XLP_SPI_TXFIFO_WCNT_SHIFT;
 216        while (xspi->tx_len && (txfifo_cnt < XLP_SPI_FIFO_SIZE)) {
 217                j = 0;
 218                tx_data = 0;
 219                nbytes = min(xspi->tx_len, 4);
 220                for (i = nbytes - 1; i >= 0; i--, j++)
 221                        tx_data |= xspi->tx_buf[i] << (j * 8);
 222
 223                xlp_spi_reg_write(xspi, xspi->cs, XLP_SPI_TXDATA_FIFO, tx_data);
 224                xspi->tx_len -= nbytes;
 225                xspi->tx_buf += nbytes;
 226                txfifo_cnt++;
 227        }
 228}
 229
 230static irqreturn_t xlp_spi_interrupt(int irq, void *dev_id)
 231{
 232        struct xlp_spi_priv *xspi = dev_id;
 233        u32 stat;
 234
 235        stat = xlp_spi_reg_read(xspi, xspi->cs, XLP_SPI_STATUS) &
 236                XLP_SPI_STAT_MASK;
 237        if (!stat)
 238                return IRQ_NONE;
 239
 240        if (stat & XLP_SPI_TX_INT) {
 241                if (xspi->tx_len)
 242                        xlp_spi_fill_txfifo(xspi);
 243                if (stat & XLP_SPI_TX_UF)
 244                        xspi->txerrors++;
 245        }
 246
 247        if (stat & XLP_SPI_RX_INT) {
 248                if (xspi->rx_len)
 249                        xlp_spi_read_rxfifo(xspi);
 250                if (stat & XLP_SPI_RX_OF)
 251                        xspi->rxerrors++;
 252        }
 253
 254        /* write status back to clear interrupts */
 255        xlp_spi_reg_write(xspi, xspi->cs, XLP_SPI_STATUS, stat);
 256        if (stat & XLP_SPI_XFR_DONE)
 257                complete(&xspi->done);
 258
 259        return IRQ_HANDLED;
 260}
 261
 262static void xlp_spi_send_cmd(struct xlp_spi_priv *xspi, int xfer_len,
 263                        int cmd_cont)
 264{
 265        u32 cmd = 0;
 266
 267        if (xspi->tx_buf)
 268                cmd |= XLP_SPI_CMD_TX_MASK;
 269        if (xspi->rx_buf)
 270                cmd |= XLP_SPI_CMD_RX_MASK;
 271        if (cmd_cont)
 272                cmd |= XLP_SPI_CMD_CONT;
 273        cmd |= ((xfer_len * 8 - 1) << XLP_SPI_XFR_BITCNT_SHIFT);
 274        xlp_spi_reg_write(xspi, xspi->cs, XLP_SPI_CMD, cmd);
 275}
 276
 277static int xlp_spi_xfer_block(struct  xlp_spi_priv *xs,
 278                const unsigned char *tx_buf,
 279                unsigned char *rx_buf, int xfer_len, int cmd_cont)
 280{
 281        int timeout;
 282        u32 intr_mask = 0;
 283
 284        xs->tx_buf = tx_buf;
 285        xs->rx_buf = rx_buf;
 286        xs->tx_len = (xs->tx_buf == NULL) ? 0 : xfer_len;
 287        xs->rx_len = (xs->rx_buf == NULL) ? 0 : xfer_len;
 288        xs->txerrors = xs->rxerrors = 0;
 289
 290        /* fill TXDATA_FIFO, then send the CMD */
 291        if (xs->tx_len)
 292                xlp_spi_fill_txfifo(xs);
 293
 294        xlp_spi_send_cmd(xs, xfer_len, cmd_cont);
 295
 296        /*
 297         * We are getting some spurious tx interrupts, so avoid enabling
 298         * tx interrupts when only rx is in process.
 299         * Enable all the interrupts in tx case.
 300         */
 301        if (xs->tx_len)
 302                intr_mask |= XLP_SPI_INTR_TXTH | XLP_SPI_INTR_TXUF |
 303                                XLP_SPI_INTR_RXTH | XLP_SPI_INTR_RXOF;
 304        else
 305                intr_mask |= XLP_SPI_INTR_RXTH | XLP_SPI_INTR_RXOF;
 306
 307        intr_mask |= XLP_SPI_INTR_DONE;
 308        xlp_spi_reg_write(xs, xs->cs, XLP_SPI_INTR_EN, intr_mask);
 309
 310        timeout = wait_for_completion_timeout(&xs->done,
 311                                msecs_to_jiffies(1000));
 312        /* Disable interrupts */
 313        xlp_spi_reg_write(xs, xs->cs, XLP_SPI_INTR_EN, 0x0);
 314        if (!timeout) {
 315                dev_err(&xs->dev, "xfer timedout!\n");
 316                goto out;
 317        }
 318        if (xs->txerrors || xs->rxerrors)
 319                dev_err(&xs->dev, "Over/Underflow rx %d tx %d xfer %d!\n",
 320                                xs->rxerrors, xs->txerrors, xfer_len);
 321
 322        return xfer_len;
 323out:
 324        return -ETIMEDOUT;
 325}
 326
 327static int xlp_spi_txrx_bufs(struct xlp_spi_priv *xs, struct spi_transfer *t)
 328{
 329        int bytesleft, sz;
 330        unsigned char *rx_buf;
 331        const unsigned char *tx_buf;
 332
 333        tx_buf = t->tx_buf;
 334        rx_buf = t->rx_buf;
 335        bytesleft = t->len;
 336        while (bytesleft) {
 337                if (bytesleft > XLP_SPI_XFER_SIZE)
 338                        sz = xlp_spi_xfer_block(xs, tx_buf, rx_buf,
 339                                        XLP_SPI_XFER_SIZE, 1);
 340                else
 341                        sz = xlp_spi_xfer_block(xs, tx_buf, rx_buf,
 342                                        bytesleft, xs->cmd_cont);
 343                if (sz < 0)
 344                        return sz;
 345                bytesleft -= sz;
 346                if (tx_buf)
 347                        tx_buf += sz;
 348                if (rx_buf)
 349                        rx_buf += sz;
 350        }
 351        return bytesleft;
 352}
 353
 354static int xlp_spi_transfer_one(struct spi_master *master,
 355                                        struct spi_device *spi,
 356                                        struct spi_transfer *t)
 357{
 358        struct xlp_spi_priv *xspi = spi_master_get_devdata(master);
 359        int ret = 0;
 360
 361        xspi->cs = spi->chip_select;
 362        xspi->dev = spi->dev;
 363
 364        if (spi_transfer_is_last(master, t))
 365                xspi->cmd_cont = 0;
 366        else
 367                xspi->cmd_cont = 1;
 368
 369        if (xlp_spi_txrx_bufs(xspi, t))
 370                ret = -EIO;
 371
 372        spi_finalize_current_transfer(master);
 373        return ret;
 374}
 375
 376static int xlp_spi_probe(struct platform_device *pdev)
 377{
 378        struct spi_master *master;
 379        struct xlp_spi_priv *xspi;
 380        struct resource *res;
 381        struct clk *clk;
 382        int irq, err;
 383
 384        xspi = devm_kzalloc(&pdev->dev, sizeof(*xspi), GFP_KERNEL);
 385        if (!xspi)
 386                return -ENOMEM;
 387
 388        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 389        xspi->base = devm_ioremap_resource(&pdev->dev, res);
 390        if (IS_ERR(xspi->base))
 391                return PTR_ERR(xspi->base);
 392
 393        irq = platform_get_irq(pdev, 0);
 394        if (irq < 0) {
 395                dev_err(&pdev->dev, "no IRQ resource found\n");
 396                return -EINVAL;
 397        }
 398        err = devm_request_irq(&pdev->dev, irq, xlp_spi_interrupt, 0,
 399                        pdev->name, xspi);
 400        if (err) {
 401                dev_err(&pdev->dev, "unable to request irq %d\n", irq);
 402                return err;
 403        }
 404
 405        clk = devm_clk_get(&pdev->dev, NULL);
 406        if (IS_ERR(clk)) {
 407                dev_err(&pdev->dev, "could not get spi clock\n");
 408                return -ENODEV;
 409        }
 410        xspi->spi_clk = clk_get_rate(clk);
 411
 412        master = spi_alloc_master(&pdev->dev, 0);
 413        if (!master) {
 414                dev_err(&pdev->dev, "could not alloc master\n");
 415                return -ENOMEM;
 416        }
 417
 418        master->bus_num = 0;
 419        master->num_chipselect = XLP_SPI_MAX_CS;
 420        master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
 421        master->setup = xlp_spi_setup;
 422        master->transfer_one = xlp_spi_transfer_one;
 423        master->dev.of_node = pdev->dev.of_node;
 424
 425        init_completion(&xspi->done);
 426        spi_master_set_devdata(master, xspi);
 427        xlp_spi_sysctl_setup(xspi);
 428
 429        /* register spi controller */
 430        err = devm_spi_register_master(&pdev->dev, master);
 431        if (err) {
 432                dev_err(&pdev->dev, "spi register master failed!\n");
 433                spi_master_put(master);
 434                return err;
 435        }
 436
 437        return 0;
 438}
 439
 440static const struct of_device_id xlp_spi_dt_id[] = {
 441        { .compatible = "netlogic,xlp832-spi" },
 442        { },
 443};
 444
 445static struct platform_driver xlp_spi_driver = {
 446        .probe  = xlp_spi_probe,
 447        .driver = {
 448                .name   = "xlp-spi",
 449                .of_match_table = xlp_spi_dt_id,
 450        },
 451};
 452module_platform_driver(xlp_spi_driver);
 453
 454MODULE_AUTHOR("Kamlakant Patel <kamlakant.patel@broadcom.com>");
 455MODULE_DESCRIPTION("Netlogic XLP SPI controller driver");
 456MODULE_LICENSE("GPL v2");
 457