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24#ifndef _COMEDI_NI_STC_H
25#define _COMEDI_NI_STC_H
26
27#include "ni_tio.h"
28
29
30
31
32
33#define NISTC_INTA_ACK_REG 2
34#define NISTC_INTA_ACK_G0_GATE BIT(15)
35#define NISTC_INTA_ACK_G0_TC BIT(14)
36#define NISTC_INTA_ACK_AI_ERR BIT(13)
37#define NISTC_INTA_ACK_AI_STOP BIT(12)
38#define NISTC_INTA_ACK_AI_START BIT(11)
39#define NISTC_INTA_ACK_AI_START2 BIT(10)
40#define NISTC_INTA_ACK_AI_START1 BIT(9)
41#define NISTC_INTA_ACK_AI_SC_TC BIT(8)
42#define NISTC_INTA_ACK_AI_SC_TC_ERR BIT(7)
43#define NISTC_INTA_ACK_G0_TC_ERR BIT(6)
44#define NISTC_INTA_ACK_G0_GATE_ERR BIT(5)
45#define NISTC_INTA_ACK_AI_ALL (NISTC_INTA_ACK_AI_ERR | \
46 NISTC_INTA_ACK_AI_STOP | \
47 NISTC_INTA_ACK_AI_START | \
48 NISTC_INTA_ACK_AI_START2 | \
49 NISTC_INTA_ACK_AI_START1 | \
50 NISTC_INTA_ACK_AI_SC_TC | \
51 NISTC_INTA_ACK_AI_SC_TC_ERR)
52
53#define NISTC_INTB_ACK_REG 3
54#define NISTC_INTB_ACK_G1_GATE BIT(15)
55#define NISTC_INTB_ACK_G1_TC BIT(14)
56#define NISTC_INTB_ACK_AO_ERR BIT(13)
57#define NISTC_INTB_ACK_AO_STOP BIT(12)
58#define NISTC_INTB_ACK_AO_START BIT(11)
59#define NISTC_INTB_ACK_AO_UPDATE BIT(10)
60#define NISTC_INTB_ACK_AO_START1 BIT(9)
61#define NISTC_INTB_ACK_AO_BC_TC BIT(8)
62#define NISTC_INTB_ACK_AO_UC_TC BIT(7)
63#define NISTC_INTB_ACK_AO_UI2_TC BIT(6)
64#define NISTC_INTB_ACK_AO_UI2_TC_ERR BIT(5)
65#define NISTC_INTB_ACK_AO_BC_TC_ERR BIT(4)
66#define NISTC_INTB_ACK_AO_BC_TC_TRIG_ERR BIT(3)
67#define NISTC_INTB_ACK_G1_TC_ERR BIT(2)
68#define NISTC_INTB_ACK_G1_GATE_ERR BIT(1)
69#define NISTC_INTB_ACK_AO_ALL (NISTC_INTB_ACK_AO_ERR | \
70 NISTC_INTB_ACK_AO_STOP | \
71 NISTC_INTB_ACK_AO_START | \
72 NISTC_INTB_ACK_AO_UPDATE | \
73 NISTC_INTB_ACK_AO_START1 | \
74 NISTC_INTB_ACK_AO_BC_TC | \
75 NISTC_INTB_ACK_AO_UC_TC | \
76 NISTC_INTB_ACK_AO_BC_TC_ERR | \
77 NISTC_INTB_ACK_AO_BC_TC_TRIG_ERR)
78
79#define NISTC_AI_CMD2_REG 4
80#define NISTC_AI_CMD2_END_ON_SC_TC BIT(15)
81#define NISTC_AI_CMD2_END_ON_EOS BIT(14)
82#define NISTC_AI_CMD2_START1_DISABLE BIT(11)
83#define NISTC_AI_CMD2_SC_SAVE_TRACE BIT(10)
84#define NISTC_AI_CMD2_SI_SW_ON_SC_TC BIT(9)
85#define NISTC_AI_CMD2_SI_SW_ON_STOP BIT(8)
86#define NISTC_AI_CMD2_SI_SW_ON_TC BIT(7)
87#define NISTC_AI_CMD2_SC_SW_ON_TC BIT(4)
88#define NISTC_AI_CMD2_STOP_PULSE BIT(3)
89#define NISTC_AI_CMD2_START_PULSE BIT(2)
90#define NISTC_AI_CMD2_START2_PULSE BIT(1)
91#define NISTC_AI_CMD2_START1_PULSE BIT(0)
92
93#define NISTC_AO_CMD2_REG 5
94#define NISTC_AO_CMD2_END_ON_BC_TC(x) (((x) & 0x3) << 14)
95#define NISTC_AO_CMD2_START_STOP_GATE_ENA BIT(13)
96#define NISTC_AO_CMD2_UC_SAVE_TRACE BIT(12)
97#define NISTC_AO_CMD2_BC_GATE_ENA BIT(11)
98#define NISTC_AO_CMD2_BC_SAVE_TRACE BIT(10)
99#define NISTC_AO_CMD2_UI_SW_ON_BC_TC BIT(9)
100#define NISTC_AO_CMD2_UI_SW_ON_STOP BIT(8)
101#define NISTC_AO_CMD2_UI_SW_ON_TC BIT(7)
102#define NISTC_AO_CMD2_UC_SW_ON_BC_TC BIT(6)
103#define NISTC_AO_CMD2_UC_SW_ON_TC BIT(5)
104#define NISTC_AO_CMD2_BC_SW_ON_TC BIT(4)
105#define NISTC_AO_CMD2_MUTE_B BIT(3)
106#define NISTC_AO_CMD2_MUTE_A BIT(2)
107#define NISTC_AO_CMD2_UPDATE2_PULSE BIT(1)
108#define NISTC_AO_CMD2_START1_PULSE BIT(0)
109
110#define NISTC_G0_CMD_REG 6
111#define NISTC_G1_CMD_REG 7
112
113#define NISTC_AI_CMD1_REG 8
114#define NISTC_AI_CMD1_ATRIG_RESET BIT(14)
115#define NISTC_AI_CMD1_DISARM BIT(13)
116#define NISTC_AI_CMD1_SI2_ARM BIT(12)
117#define NISTC_AI_CMD1_SI2_LOAD BIT(11)
118#define NISTC_AI_CMD1_SI_ARM BIT(10)
119#define NISTC_AI_CMD1_SI_LOAD BIT(9)
120#define NISTC_AI_CMD1_DIV_ARM BIT(8)
121#define NISTC_AI_CMD1_DIV_LOAD BIT(7)
122#define NISTC_AI_CMD1_SC_ARM BIT(6)
123#define NISTC_AI_CMD1_SC_LOAD BIT(5)
124#define NISTC_AI_CMD1_SCAN_IN_PROG_PULSE BIT(4)
125#define NISTC_AI_CMD1_EXTMUX_CLK_PULSE BIT(3)
126#define NISTC_AI_CMD1_LOCALMUX_CLK_PULSE BIT(2)
127#define NISTC_AI_CMD1_SC_TC_PULSE BIT(1)
128#define NISTC_AI_CMD1_CONVERT_PULSE BIT(0)
129
130#define NISTC_AO_CMD1_REG 9
131#define NISTC_AO_CMD1_ATRIG_RESET BIT(15)
132#define NISTC_AO_CMD1_START_PULSE BIT(14)
133#define NISTC_AO_CMD1_DISARM BIT(13)
134#define NISTC_AO_CMD1_UI2_ARM_DISARM BIT(12)
135#define NISTC_AO_CMD1_UI2_LOAD BIT(11)
136#define NISTC_AO_CMD1_UI_ARM BIT(10)
137#define NISTC_AO_CMD1_UI_LOAD BIT(9)
138#define NISTC_AO_CMD1_UC_ARM BIT(8)
139#define NISTC_AO_CMD1_UC_LOAD BIT(7)
140#define NISTC_AO_CMD1_BC_ARM BIT(6)
141#define NISTC_AO_CMD1_BC_LOAD BIT(5)
142#define NISTC_AO_CMD1_DAC1_UPDATE_MODE BIT(4)
143#define NISTC_AO_CMD1_LDAC1_SRC_SEL BIT(3)
144#define NISTC_AO_CMD1_DAC0_UPDATE_MODE BIT(2)
145#define NISTC_AO_CMD1_LDAC0_SRC_SEL BIT(1)
146#define NISTC_AO_CMD1_UPDATE_PULSE BIT(0)
147
148#define NISTC_DIO_OUT_REG 10
149#define NISTC_DIO_OUT_SERIAL(x) (((x) & 0xff) << 8)
150#define NISTC_DIO_OUT_SERIAL_MASK NISTC_DIO_OUT_SERIAL(0xff)
151#define NISTC_DIO_OUT_PARALLEL(x) ((x) & 0xff)
152#define NISTC_DIO_OUT_PARALLEL_MASK NISTC_DIO_OUT_PARALLEL(0xff)
153#define NISTC_DIO_SDIN BIT(4)
154#define NISTC_DIO_SDOUT BIT(0)
155
156#define NISTC_DIO_CTRL_REG 11
157#define NISTC_DIO_SDCLK BIT(11)
158#define NISTC_DIO_CTRL_HW_SER_TIMEBASE BIT(10)
159#define NISTC_DIO_CTRL_HW_SER_ENA BIT(9)
160#define NISTC_DIO_CTRL_HW_SER_START BIT(8)
161#define NISTC_DIO_CTRL_DIR(x) ((x) & 0xff)
162#define NISTC_DIO_CTRL_DIR_MASK NISTC_DIO_CTRL_DIR(0xff)
163
164#define NISTC_AI_MODE1_REG 12
165#define NISTC_AI_MODE1_CONVERT_SRC(x) (((x) & 0x1f) << 11)
166#define NISTC_AI_MODE1_SI_SRC(x) (((x) & 0x1f) << 6)
167#define NISTC_AI_MODE1_CONVERT_POLARITY BIT(5)
168#define NISTC_AI_MODE1_SI_POLARITY BIT(4)
169#define NISTC_AI_MODE1_START_STOP BIT(3)
170#define NISTC_AI_MODE1_RSVD BIT(2)
171#define NISTC_AI_MODE1_CONTINUOUS BIT(1)
172#define NISTC_AI_MODE1_TRIGGER_ONCE BIT(0)
173
174#define NISTC_AI_MODE2_REG 13
175#define NISTC_AI_MODE2_SC_GATE_ENA BIT(15)
176#define NISTC_AI_MODE2_START_STOP_GATE_ENA BIT(14)
177#define NISTC_AI_MODE2_PRE_TRIGGER BIT(13)
178#define NISTC_AI_MODE2_EXTMUX_PRESENT BIT(12)
179#define NISTC_AI_MODE2_SI2_INIT_LOAD_SRC BIT(9)
180#define NISTC_AI_MODE2_SI2_RELOAD_MODE BIT(8)
181#define NISTC_AI_MODE2_SI_INIT_LOAD_SRC BIT(7)
182#define NISTC_AI_MODE2_SI_RELOAD_MODE(x) (((x) & 0x7) << 4)
183#define NISTC_AI_MODE2_SI_WR_SWITCH BIT(3)
184#define NISTC_AI_MODE2_SC_INIT_LOAD_SRC BIT(2)
185#define NISTC_AI_MODE2_SC_RELOAD_MODE BIT(1)
186#define NISTC_AI_MODE2_SC_WR_SWITCH BIT(0)
187
188#define NISTC_AI_SI_LOADA_REG 14
189#define NISTC_AI_SI_LOADB_REG 16
190#define NISTC_AI_SC_LOADA_REG 18
191#define NISTC_AI_SC_LOADB_REG 20
192#define NISTC_AI_SI2_LOADA_REG 23
193#define NISTC_AI_SI2_LOADB_REG 25
194
195#define NISTC_G0_MODE_REG 26
196#define NISTC_G1_MODE_REG 27
197#define NISTC_G0_LOADA_REG 28
198#define NISTC_G0_LOADB_REG 30
199#define NISTC_G1_LOADA_REG 32
200#define NISTC_G1_LOADB_REG 34
201#define NISTC_G0_INPUT_SEL_REG 36
202#define NISTC_G1_INPUT_SEL_REG 37
203
204#define NISTC_AO_MODE1_REG 38
205#define NISTC_AO_MODE1_UPDATE_SRC(x) (((x) & 0x1f) << 11)
206#define NISTC_AO_MODE1_UPDATE_SRC_MASK NISTC_AO_MODE1_UPDATE_SRC(0x1f)
207#define NISTC_AO_MODE1_UI_SRC(x) (((x) & 0x1f) << 6)
208#define NISTC_AO_MODE1_UI_SRC_MASK NISTC_AO_MODE1_UI_SRC(0x1f)
209#define NISTC_AO_MODE1_MULTI_CHAN BIT(5)
210#define NISTC_AO_MODE1_UPDATE_SRC_POLARITY BIT(4)
211#define NISTC_AO_MODE1_UI_SRC_POLARITY BIT(3)
212#define NISTC_AO_MODE1_UC_SW_EVERY_TC BIT(2)
213#define NISTC_AO_MODE1_CONTINUOUS BIT(1)
214#define NISTC_AO_MODE1_TRIGGER_ONCE BIT(0)
215
216#define NISTC_AO_MODE2_REG 39
217#define NISTC_AO_MODE2_FIFO_MODE(x) (((x) & 0x3) << 14)
218#define NISTC_AO_MODE2_FIFO_MODE_MASK NISTC_AO_MODE2_FIFO_MODE(3)
219#define NISTC_AO_MODE2_FIFO_MODE_E NISTC_AO_MODE2_FIFO_MODE(0)
220#define NISTC_AO_MODE2_FIFO_MODE_HF NISTC_AO_MODE2_FIFO_MODE(1)
221#define NISTC_AO_MODE2_FIFO_MODE_F NISTC_AO_MODE2_FIFO_MODE(2)
222#define NISTC_AO_MODE2_FIFO_MODE_HF_F NISTC_AO_MODE2_FIFO_MODE(3)
223#define NISTC_AO_MODE2_FIFO_REXMIT_ENA BIT(13)
224#define NISTC_AO_MODE2_START1_DISABLE BIT(12)
225#define NISTC_AO_MODE2_UC_INIT_LOAD_SRC BIT(11)
226#define NISTC_AO_MODE2_UC_WR_SWITCH BIT(10)
227#define NISTC_AO_MODE2_UI2_INIT_LOAD_SRC BIT(9)
228#define NISTC_AO_MODE2_UI2_RELOAD_MODE BIT(8)
229#define NISTC_AO_MODE2_UI_INIT_LOAD_SRC BIT(7)
230#define NISTC_AO_MODE2_UI_RELOAD_MODE(x) (((x) & 0x7) << 4)
231#define NISTC_AO_MODE2_UI_WR_SWITCH BIT(3)
232#define NISTC_AO_MODE2_BC_INIT_LOAD_SRC BIT(2)
233#define NISTC_AO_MODE2_BC_RELOAD_MODE BIT(1)
234#define NISTC_AO_MODE2_BC_WR_SWITCH BIT(0)
235
236#define NISTC_AO_UI_LOADA_REG 40
237#define NISTC_AO_UI_LOADB_REG 42
238#define NISTC_AO_BC_LOADA_REG 44
239#define NISTC_AO_BC_LOADB_REG 46
240#define NISTC_AO_UC_LOADA_REG 48
241#define NISTC_AO_UC_LOADB_REG 50
242
243#define NISTC_CLK_FOUT_REG 56
244#define NISTC_CLK_FOUT_ENA BIT(15)
245#define NISTC_CLK_FOUT_TIMEBASE_SEL BIT(14)
246#define NISTC_CLK_FOUT_DIO_SER_OUT_DIV2 BIT(13)
247#define NISTC_CLK_FOUT_SLOW_DIV2 BIT(12)
248#define NISTC_CLK_FOUT_SLOW_TIMEBASE BIT(11)
249#define NISTC_CLK_FOUT_G_SRC_DIV2 BIT(10)
250#define NISTC_CLK_FOUT_TO_BOARD_DIV2 BIT(9)
251#define NISTC_CLK_FOUT_TO_BOARD BIT(8)
252#define NISTC_CLK_FOUT_AI_OUT_DIV2 BIT(7)
253#define NISTC_CLK_FOUT_AI_SRC_DIV2 BIT(6)
254#define NISTC_CLK_FOUT_AO_OUT_DIV2 BIT(5)
255#define NISTC_CLK_FOUT_AO_SRC_DIV2 BIT(4)
256#define NISTC_CLK_FOUT_DIVIDER(x) (((x) & 0xf) << 0)
257#define NISTC_CLK_FOUT_TO_DIVIDER(x) (((x) >> 0) & 0xf)
258#define NISTC_CLK_FOUT_DIVIDER_MASK NISTC_CLK_FOUT_DIVIDER(0xf)
259
260#define NISTC_IO_BIDIR_PIN_REG 57
261
262#define NISTC_RTSI_TRIG_DIR_REG 58
263#define NISTC_RTSI_TRIG_OLD_CLK_CHAN 7
264#define NISTC_RTSI_TRIG_NUM_CHAN(_m) ((_m) ? 8 : 7)
265#define NISTC_RTSI_TRIG_DIR(_c, _m) ((_m) ? BIT(8 + (_c)) : BIT(7 + (_c)))
266#define NISTC_RTSI_TRIG_USE_CLK BIT(1)
267#define NISTC_RTSI_TRIG_DRV_CLK BIT(0)
268
269#define NISTC_INT_CTRL_REG 59
270#define NISTC_INT_CTRL_INTB_ENA BIT(15)
271#define NISTC_INT_CTRL_INTB_SEL(x) (((x) & 0x7) << 12)
272#define NISTC_INT_CTRL_INTA_ENA BIT(11)
273#define NISTC_INT_CTRL_INTA_SEL(x) (((x) & 0x7) << 8)
274#define NISTC_INT_CTRL_PASSTHRU0_POL BIT(3)
275#define NISTC_INT_CTRL_PASSTHRU1_POL BIT(2)
276#define NISTC_INT_CTRL_3PIN_INT BIT(1)
277#define NISTC_INT_CTRL_INT_POL BIT(0)
278
279#define NISTC_AI_OUT_CTRL_REG 60
280#define NISTC_AI_OUT_CTRL_START_SEL BIT(10)
281#define NISTC_AI_OUT_CTRL_SCAN_IN_PROG_SEL(x) (((x) & 0x3) << 8)
282#define NISTC_AI_OUT_CTRL_EXTMUX_CLK_SEL(x) (((x) & 0x3) << 6)
283#define NISTC_AI_OUT_CTRL_LOCALMUX_CLK_SEL(x) (((x) & 0x3) << 4)
284#define NISTC_AI_OUT_CTRL_SC_TC_SEL(x) (((x) & 0x3) << 2)
285#define NISTC_AI_OUT_CTRL_CONVERT_SEL(x) (((x) & 0x3) << 0)
286#define NISTC_AI_OUT_CTRL_CONVERT_HIGH_Z NISTC_AI_OUT_CTRL_CONVERT_SEL(0)
287#define NISTC_AI_OUT_CTRL_CONVERT_GND NISTC_AI_OUT_CTRL_CONVERT_SEL(1)
288#define NISTC_AI_OUT_CTRL_CONVERT_LOW NISTC_AI_OUT_CTRL_CONVERT_SEL(2)
289#define NISTC_AI_OUT_CTRL_CONVERT_HIGH NISTC_AI_OUT_CTRL_CONVERT_SEL(3)
290
291#define NISTC_ATRIG_ETC_REG 61
292#define NISTC_ATRIG_ETC_GPFO_1_ENA BIT(15)
293#define NISTC_ATRIG_ETC_GPFO_0_ENA BIT(14)
294#define NISTC_ATRIG_ETC_GPFO_0_SEL(x) (((x) & 0x3) << 11)
295#define NISTC_ATRIG_ETC_GPFO_1_SEL BIT(7)
296#define NISTC_ATRIG_ETC_DRV BIT(4)
297#define NISTC_ATRIG_ETC_ENA BIT(3)
298#define NISTC_ATRIG_ETC_MODE(x) (((x) & 0x7) << 0)
299
300#define NISTC_AI_START_STOP_REG 62
301#define NISTC_AI_START_POLARITY BIT(15)
302#define NISTC_AI_STOP_POLARITY BIT(14)
303#define NISTC_AI_STOP_SYNC BIT(13)
304#define NISTC_AI_STOP_EDGE BIT(12)
305#define NISTC_AI_STOP_SEL(x) (((x) & 0x1f) << 7)
306#define NISTC_AI_START_SYNC BIT(6)
307#define NISTC_AI_START_EDGE BIT(5)
308#define NISTC_AI_START_SEL(x) (((x) & 0x1f) << 0)
309
310#define NISTC_AI_TRIG_SEL_REG 63
311#define NISTC_AI_TRIG_START1_POLARITY BIT(15)
312#define NISTC_AI_TRIG_START2_POLARITY BIT(14)
313#define NISTC_AI_TRIG_START2_SYNC BIT(13)
314#define NISTC_AI_TRIG_START2_EDGE BIT(12)
315#define NISTC_AI_TRIG_START2_SEL(x) (((x) & 0x1f) << 7)
316#define NISTC_AI_TRIG_START1_SYNC BIT(6)
317#define NISTC_AI_TRIG_START1_EDGE BIT(5)
318#define NISTC_AI_TRIG_START1_SEL(x) (((x) & 0x1f) << 0)
319
320#define NISTC_AI_DIV_LOADA_REG 64
321
322#define NISTC_AO_START_SEL_REG 66
323#define NISTC_AO_START_UI2_SW_GATE BIT(15)
324#define NISTC_AO_START_UI2_EXT_GATE_POL BIT(14)
325#define NISTC_AO_START_POLARITY BIT(13)
326#define NISTC_AO_START_AOFREQ_ENA BIT(12)
327#define NISTC_AO_START_UI2_EXT_GATE_SEL(x) (((x) & 0x1f) << 7)
328#define NISTC_AO_START_SYNC BIT(6)
329#define NISTC_AO_START_EDGE BIT(5)
330#define NISTC_AO_START_SEL(x) (((x) & 0x1f) << 0)
331
332#define NISTC_AO_TRIG_SEL_REG 67
333#define NISTC_AO_TRIG_UI2_EXT_GATE_ENA BIT(15)
334#define NISTC_AO_TRIG_DELAYED_START1 BIT(14)
335#define NISTC_AO_TRIG_START1_POLARITY BIT(13)
336#define NISTC_AO_TRIG_UI2_SRC_POLARITY BIT(12)
337#define NISTC_AO_TRIG_UI2_SRC_SEL(x) (((x) & 0x1f) << 7)
338#define NISTC_AO_TRIG_START1_SYNC BIT(6)
339#define NISTC_AO_TRIG_START1_EDGE BIT(5)
340#define NISTC_AO_TRIG_START1_SEL(x) (((x) & 0x1f) << 0)
341#define NISTC_AO_TRIG_START1_SEL_MASK NISTC_AO_TRIG_START1_SEL(0x1f)
342
343#define NISTC_G0_AUTOINC_REG 68
344#define NISTC_G1_AUTOINC_REG 69
345
346#define NISTC_AO_MODE3_REG 70
347#define NISTC_AO_MODE3_UI2_SW_NEXT_TC BIT(13)
348#define NISTC_AO_MODE3_UC_SW_EVERY_BC_TC BIT(12)
349#define NISTC_AO_MODE3_TRIG_LEN BIT(11)
350#define NISTC_AO_MODE3_STOP_ON_OVERRUN_ERR BIT(5)
351#define NISTC_AO_MODE3_STOP_ON_BC_TC_TRIG_ERR BIT(4)
352#define NISTC_AO_MODE3_STOP_ON_BC_TC_ERR BIT(3)
353#define NISTC_AO_MODE3_NOT_AN_UPDATE BIT(2)
354#define NISTC_AO_MODE3_SW_GATE BIT(1)
355#define NISTC_AO_MODE3_LAST_GATE_DISABLE BIT(0)
356
357#define NISTC_RESET_REG 72
358#define NISTC_RESET_SOFTWARE BIT(11)
359#define NISTC_RESET_AO_CFG_END BIT(9)
360#define NISTC_RESET_AI_CFG_END BIT(8)
361#define NISTC_RESET_AO_CFG_START BIT(5)
362#define NISTC_RESET_AI_CFG_START BIT(4)
363#define NISTC_RESET_G1 BIT(3)
364#define NISTC_RESET_G0 BIT(2)
365#define NISTC_RESET_AO BIT(1)
366#define NISTC_RESET_AI BIT(0)
367
368#define NISTC_INTA_ENA_REG 73
369#define NISTC_INTA2_ENA_REG 74
370#define NISTC_INTA_ENA_PASSTHRU0 BIT(9)
371#define NISTC_INTA_ENA_G0_GATE BIT(8)
372#define NISTC_INTA_ENA_AI_FIFO BIT(7)
373#define NISTC_INTA_ENA_G0_TC BIT(6)
374#define NISTC_INTA_ENA_AI_ERR BIT(5)
375#define NISTC_INTA_ENA_AI_STOP BIT(4)
376#define NISTC_INTA_ENA_AI_START BIT(3)
377#define NISTC_INTA_ENA_AI_START2 BIT(2)
378#define NISTC_INTA_ENA_AI_START1 BIT(1)
379#define NISTC_INTA_ENA_AI_SC_TC BIT(0)
380#define NISTC_INTA_ENA_AI_MASK (NISTC_INTA_ENA_AI_FIFO | \
381 NISTC_INTA_ENA_AI_ERR | \
382 NISTC_INTA_ENA_AI_STOP | \
383 NISTC_INTA_ENA_AI_START | \
384 NISTC_INTA_ENA_AI_START2 | \
385 NISTC_INTA_ENA_AI_START1 | \
386 NISTC_INTA_ENA_AI_SC_TC)
387
388#define NISTC_INTB_ENA_REG 75
389#define NISTC_INTB2_ENA_REG 76
390#define NISTC_INTB_ENA_PASSTHRU1 BIT(11)
391#define NISTC_INTB_ENA_G1_GATE BIT(10)
392#define NISTC_INTB_ENA_G1_TC BIT(9)
393#define NISTC_INTB_ENA_AO_FIFO BIT(8)
394#define NISTC_INTB_ENA_AO_UI2_TC BIT(7)
395#define NISTC_INTB_ENA_AO_UC_TC BIT(6)
396#define NISTC_INTB_ENA_AO_ERR BIT(5)
397#define NISTC_INTB_ENA_AO_STOP BIT(4)
398#define NISTC_INTB_ENA_AO_START BIT(3)
399#define NISTC_INTB_ENA_AO_UPDATE BIT(2)
400#define NISTC_INTB_ENA_AO_START1 BIT(1)
401#define NISTC_INTB_ENA_AO_BC_TC BIT(0)
402
403#define NISTC_AI_PERSONAL_REG 77
404#define NISTC_AI_PERSONAL_SHIFTIN_PW BIT(15)
405#define NISTC_AI_PERSONAL_EOC_POLARITY BIT(14)
406#define NISTC_AI_PERSONAL_SOC_POLARITY BIT(13)
407#define NISTC_AI_PERSONAL_SHIFTIN_POL BIT(12)
408#define NISTC_AI_PERSONAL_CONVERT_TIMEBASE BIT(11)
409#define NISTC_AI_PERSONAL_CONVERT_PW BIT(10)
410#define NISTC_AI_PERSONAL_CONVERT_ORIG_PULSE BIT(9)
411#define NISTC_AI_PERSONAL_FIFO_FLAGS_POL BIT(8)
412#define NISTC_AI_PERSONAL_OVERRUN_MODE BIT(7)
413#define NISTC_AI_PERSONAL_EXTMUX_CLK_PW BIT(6)
414#define NISTC_AI_PERSONAL_LOCALMUX_CLK_PW BIT(5)
415#define NISTC_AI_PERSONAL_AIFREQ_POL BIT(4)
416
417#define NISTC_AO_PERSONAL_REG 78
418#define NISTC_AO_PERSONAL_MULTI_DACS BIT(15)
419#define NISTC_AO_PERSONAL_NUM_DAC BIT(14)
420#define NISTC_AO_PERSONAL_FAST_CPU BIT(13)
421#define NISTC_AO_PERSONAL_TMRDACWR_PW BIT(12)
422#define NISTC_AO_PERSONAL_FIFO_FLAGS_POL BIT(11)
423#define NISTC_AO_PERSONAL_FIFO_ENA BIT(10)
424#define NISTC_AO_PERSONAL_AOFREQ_POL BIT(9)
425#define NISTC_AO_PERSONAL_DMA_PIO_CTRL BIT(8)
426#define NISTC_AO_PERSONAL_UPDATE_ORIG_PULSE BIT(7)
427#define NISTC_AO_PERSONAL_UPDATE_TIMEBASE BIT(6)
428#define NISTC_AO_PERSONAL_UPDATE_PW BIT(5)
429#define NISTC_AO_PERSONAL_BC_SRC_SEL BIT(4)
430#define NISTC_AO_PERSONAL_INTERVAL_BUFFER_MODE BIT(3)
431
432#define NISTC_RTSI_TRIGA_OUT_REG 79
433#define NISTC_RTSI_TRIGB_OUT_REG 80
434#define NISTC_RTSI_TRIGB_SUB_SEL1 BIT(15)
435#define NISTC_RTSI_TRIG(_c, _s) (((_s) & 0xf) << (((_c) % 4) * 4))
436#define NISTC_RTSI_TRIG_MASK(_c) NISTC_RTSI_TRIG((_c), 0xf)
437#define NISTC_RTSI_TRIG_TO_SRC(_c, _b) (((_b) >> (((_c) % 4) * 4)) & 0xf)
438
439#define NISTC_RTSI_BOARD_REG 81
440
441#define NISTC_CFG_MEM_CLR_REG 82
442#define NISTC_ADC_FIFO_CLR_REG 83
443#define NISTC_DAC_FIFO_CLR_REG 84
444#define NISTC_WR_STROBE3_REG 85
445
446#define NISTC_AO_OUT_CTRL_REG 86
447#define NISTC_AO_OUT_CTRL_EXT_GATE_ENA BIT(15)
448#define NISTC_AO_OUT_CTRL_EXT_GATE_SEL(x) (((x) & 0x1f) << 10)
449#define NISTC_AO_OUT_CTRL_CHANS(x) (((x) & 0xf) << 6)
450#define NISTC_AO_OUT_CTRL_UPDATE2_SEL(x) (((x) & 0x3) << 4)
451#define NISTC_AO_OUT_CTRL_EXT_GATE_POL BIT(3)
452#define NISTC_AO_OUT_CTRL_UPDATE2_TOGGLE BIT(2)
453#define NISTC_AO_OUT_CTRL_UPDATE_SEL(x) (((x) & 0x3) << 0)
454#define NISTC_AO_OUT_CTRL_UPDATE_SEL_HIGHZ NISTC_AO_OUT_CTRL_UPDATE_SEL(0)
455#define NISTC_AO_OUT_CTRL_UPDATE_SEL_GND NISTC_AO_OUT_CTRL_UPDATE_SEL(1)
456#define NISTC_AO_OUT_CTRL_UPDATE_SEL_LOW NISTC_AO_OUT_CTRL_UPDATE_SEL(2)
457#define NISTC_AO_OUT_CTRL_UPDATE_SEL_HIGH NISTC_AO_OUT_CTRL_UPDATE_SEL(3)
458
459#define NISTC_AI_MODE3_REG 87
460#define NISTC_AI_MODE3_TRIG_LEN BIT(15)
461#define NISTC_AI_MODE3_DELAY_START BIT(14)
462#define NISTC_AI_MODE3_SOFTWARE_GATE BIT(13)
463#define NISTC_AI_MODE3_SI_TRIG_DELAY BIT(12)
464#define NISTC_AI_MODE3_SI2_SRC_SEL BIT(11)
465#define NISTC_AI_MODE3_DELAYED_START2 BIT(10)
466#define NISTC_AI_MODE3_DELAYED_START1 BIT(9)
467#define NISTC_AI_MODE3_EXT_GATE_MODE BIT(8)
468#define NISTC_AI_MODE3_FIFO_MODE(x) (((x) & 0x3) << 6)
469#define NISTC_AI_MODE3_FIFO_MODE_NE NISTC_AI_MODE3_FIFO_MODE(0)
470#define NISTC_AI_MODE3_FIFO_MODE_HF NISTC_AI_MODE3_FIFO_MODE(1)
471#define NISTC_AI_MODE3_FIFO_MODE_F NISTC_AI_MODE3_FIFO_MODE(2)
472#define NISTC_AI_MODE3_FIFO_MODE_HF_E NISTC_AI_MODE3_FIFO_MODE(3)
473#define NISTC_AI_MODE3_EXT_GATE_POL BIT(5)
474#define NISTC_AI_MODE3_EXT_GATE_SEL(x) (((x) & 0x1f) << 0)
475
476#define NISTC_AI_STATUS1_REG 2
477#define NISTC_AI_STATUS1_INTA BIT(15)
478#define NISTC_AI_STATUS1_FIFO_F BIT(14)
479#define NISTC_AI_STATUS1_FIFO_HF BIT(13)
480#define NISTC_AI_STATUS1_FIFO_E BIT(12)
481#define NISTC_AI_STATUS1_OVERRUN BIT(11)
482#define NISTC_AI_STATUS1_OVERFLOW BIT(10)
483#define NISTC_AI_STATUS1_SC_TC_ERR BIT(9)
484#define NISTC_AI_STATUS1_OVER (NISTC_AI_STATUS1_OVERRUN | \
485 NISTC_AI_STATUS1_OVERFLOW)
486#define NISTC_AI_STATUS1_ERR (NISTC_AI_STATUS1_OVER | \
487 NISTC_AI_STATUS1_SC_TC_ERR)
488#define NISTC_AI_STATUS1_START2 BIT(8)
489#define NISTC_AI_STATUS1_START1 BIT(7)
490#define NISTC_AI_STATUS1_SC_TC BIT(6)
491#define NISTC_AI_STATUS1_START BIT(5)
492#define NISTC_AI_STATUS1_STOP BIT(4)
493#define NISTC_AI_STATUS1_G0_TC BIT(3)
494#define NISTC_AI_STATUS1_G0_GATE BIT(2)
495#define NISTC_AI_STATUS1_FIFO_REQ BIT(1)
496#define NISTC_AI_STATUS1_PASSTHRU0 BIT(0)
497
498#define NISTC_AO_STATUS1_REG 3
499#define NISTC_AO_STATUS1_INTB BIT(15)
500#define NISTC_AO_STATUS1_FIFO_F BIT(14)
501#define NISTC_AO_STATUS1_FIFO_HF BIT(13)
502#define NISTC_AO_STATUS1_FIFO_E BIT(12)
503#define NISTC_AO_STATUS1_BC_TC_ERR BIT(11)
504#define NISTC_AO_STATUS1_START BIT(10)
505#define NISTC_AO_STATUS1_OVERRUN BIT(9)
506#define NISTC_AO_STATUS1_START1 BIT(8)
507#define NISTC_AO_STATUS1_BC_TC BIT(7)
508#define NISTC_AO_STATUS1_UC_TC BIT(6)
509#define NISTC_AO_STATUS1_UPDATE BIT(5)
510#define NISTC_AO_STATUS1_UI2_TC BIT(4)
511#define NISTC_AO_STATUS1_G1_TC BIT(3)
512#define NISTC_AO_STATUS1_G1_GATE BIT(2)
513#define NISTC_AO_STATUS1_FIFO_REQ BIT(1)
514#define NISTC_AO_STATUS1_PASSTHRU1 BIT(0)
515
516#define NISTC_G01_STATUS_REG 4
517
518#define NISTC_AI_STATUS2_REG 5
519
520#define NISTC_AO_STATUS2_REG 6
521
522#define NISTC_DIO_IN_REG 7
523
524#define NISTC_G0_HW_SAVE_REG 8
525#define NISTC_G1_HW_SAVE_REG 10
526
527#define NISTC_G0_SAVE_REG 12
528#define NISTC_G1_SAVE_REG 14
529
530#define NISTC_AO_UI_SAVE_REG 16
531#define NISTC_AO_BC_SAVE_REG 18
532#define NISTC_AO_UC_SAVE_REG 20
533
534#define NISTC_STATUS1_REG 27
535#define NISTC_STATUS1_SERIO_IN_PROG BIT(12)
536
537#define NISTC_DIO_SERIAL_IN_REG 28
538
539#define NISTC_STATUS2_REG 29
540#define NISTC_STATUS2_AO_TMRDACWRS_IN_PROGRESS BIT(5)
541
542#define NISTC_AI_SI_SAVE_REG 64
543#define NISTC_AI_SC_SAVE_REG 66
544
545
546
547
548#define NI_E_STC_WINDOW_ADDR_REG 0x00
549#define NI_E_STC_WINDOW_DATA_REG 0x02
550
551#define NI_E_STATUS_REG 0x01
552#define NI_E_STATUS_AI_FIFO_LOWER_NE BIT(3)
553#define NI_E_STATUS_PROMOUT BIT(0)
554
555#define NI_E_DMA_AI_AO_SEL_REG 0x09
556#define NI_E_DMA_AI_SEL(x) (((x) & 0xf) << 0)
557#define NI_E_DMA_AI_SEL_MASK NI_E_DMA_AI_SEL(0xf)
558#define NI_E_DMA_AO_SEL(x) (((x) & 0xf) << 4)
559#define NI_E_DMA_AO_SEL_MASK NI_E_DMA_AO_SEL(0xf)
560
561#define NI_E_DMA_G0_G1_SEL_REG 0x0b
562#define NI_E_DMA_G0_G1_SEL(_g, _c) (((_c) & 0xf) << ((_g) * 4))
563#define NI_E_DMA_G0_G1_SEL_MASK(_g) NI_E_DMA_G0_G1_SEL((_g), 0xf)
564
565#define NI_E_SERIAL_CMD_REG 0x0d
566#define NI_E_SERIAL_CMD_DAC_LD(x) BIT(3 + (x))
567#define NI_E_SERIAL_CMD_EEPROM_CS BIT(2)
568#define NI_E_SERIAL_CMD_SDATA BIT(1)
569#define NI_E_SERIAL_CMD_SCLK BIT(0)
570
571#define NI_E_MISC_CMD_REG 0x0f
572#define NI_E_MISC_CMD_INTEXT_ATRIG(x) (((x) & 0x1) << 7)
573#define NI_E_MISC_CMD_EXT_ATRIG NI_E_MISC_CMD_INTEXT_ATRIG(0)
574#define NI_E_MISC_CMD_INT_ATRIG NI_E_MISC_CMD_INTEXT_ATRIG(1)
575
576#define NI_E_AI_CFG_LO_REG 0x10
577#define NI_E_AI_CFG_LO_LAST_CHAN BIT(15)
578#define NI_E_AI_CFG_LO_GEN_TRIG BIT(12)
579#define NI_E_AI_CFG_LO_DITHER BIT(9)
580#define NI_E_AI_CFG_LO_UNI BIT(8)
581#define NI_E_AI_CFG_LO_GAIN(x) ((x) << 0)
582
583#define NI_E_AI_CFG_HI_REG 0x12
584#define NI_E_AI_CFG_HI_TYPE(x) (((x) & 0x7) << 12)
585#define NI_E_AI_CFG_HI_TYPE_DIFF NI_E_AI_CFG_HI_TYPE(1)
586#define NI_E_AI_CFG_HI_TYPE_COMMON NI_E_AI_CFG_HI_TYPE(2)
587#define NI_E_AI_CFG_HI_TYPE_GROUND NI_E_AI_CFG_HI_TYPE(3)
588#define NI_E_AI_CFG_HI_AC_COUPLE BIT(11)
589#define NI_E_AI_CFG_HI_CHAN(x) (((x) & 0x3f) << 0)
590
591#define NI_E_AO_CFG_REG 0x16
592#define NI_E_AO_DACSEL(x) ((x) << 8)
593#define NI_E_AO_GROUND_REF BIT(3)
594#define NI_E_AO_EXT_REF BIT(2)
595#define NI_E_AO_DEGLITCH BIT(1)
596#define NI_E_AO_CFG_BIP BIT(0)
597
598#define NI_E_DAC_DIRECT_DATA_REG(x) (0x18 + ((x) * 2))
599
600#define NI_E_8255_BASE 0x19
601
602#define NI_E_AI_FIFO_DATA_REG 0x1c
603
604#define NI_E_AO_FIFO_DATA_REG 0x1e
605
606
607
608
609#define NI611X_MAGIC_REG 0x19
610#define NI611X_CALIB_CHAN_SEL_REG 0x1a
611#define NI611X_AI_FIFO_DATA_REG 0x1c
612#define NI611X_AI_FIFO_OFFSET_LOAD_REG 0x05
613#define NI611X_AO_FIFO_DATA_REG 0x14
614#define NI611X_CAL_GAIN_SEL_REG 0x05
615
616#define NI611X_AO_WINDOW_ADDR_REG 0x18
617#define NI611X_AO_WINDOW_DATA_REG 0x1e
618
619
620
621
622#define NI6143_MAGIC_REG 0x19
623#define NI6143_DMA_G0_G1_SEL_REG 0x0b
624#define NI6143_PIPELINE_DELAY_REG 0x1f
625#define NI6143_EOC_SET_REG 0x1d
626#define NI6143_DMA_AI_SEL_REG 0x09
627#define NI6143_AI_FIFO_DATA_REG 0x8c
628#define NI6143_AI_FIFO_FLAG_REG 0x84
629#define NI6143_AI_FIFO_CTRL_REG 0x88
630#define NI6143_AI_FIFO_STATUS_REG 0x88
631#define NI6143_AI_FIFO_DMA_THRESH_REG 0x90
632#define NI6143_AI_FIFO_WORDS_AVAIL_REG 0x94
633
634#define NI6143_CALIB_CHAN_REG 0x42
635#define NI6143_CALIB_CHAN_RELAY_ON BIT(15)
636#define NI6143_CALIB_CHAN_RELAY_OFF BIT(14)
637#define NI6143_CALIB_CHAN(x) (((x) & 0xf) << 0)
638#define NI6143_CALIB_CHAN_GND_GND NI6143_CALIB_CHAN(0)
639#define NI6143_CALIB_CHAN_2V5_GND NI6143_CALIB_CHAN(2)
640#define NI6143_CALIB_CHAN_PWM_GND NI6143_CALIB_CHAN(5)
641#define NI6143_CALIB_CHAN_2V5_PWM NI6143_CALIB_CHAN(10)
642#define NI6143_CALIB_CHAN_PWM_PWM NI6143_CALIB_CHAN(13)
643#define NI6143_CALIB_CHAN_GND_PWM NI6143_CALIB_CHAN(14)
644#define NI6143_CALIB_LO_TIME_REG 0x20
645#define NI6143_CALIB_HI_TIME_REG 0x22
646#define NI6143_RELAY_COUNTER_LOAD_REG 0x4c
647#define NI6143_SIGNATURE_REG 0x50
648#define NI6143_RELEASE_DATE_REG 0x54
649#define NI6143_RELEASE_OLDEST_DATE_REG 0x58
650
651
652
653
654#define NI671X_DAC_DIRECT_DATA_REG(x) (0x00 + (x))
655#define NI611X_AO_TIMED_REG 0x10
656#define NI671X_AO_IMMEDIATE_REG 0x11
657#define NI611X_AO_FIFO_OFFSET_LOAD_REG 0x13
658#define NI67XX_AO_SP_UPDATES_REG 0x14
659#define NI611X_AO_WAVEFORM_GEN_REG 0x15
660#define NI611X_AO_MISC_REG 0x16
661#define NI611X_AO_MISC_CLEAR_WG BIT(0)
662#define NI67XX_AO_CAL_CHAN_SEL_REG 0x17
663#define NI67XX_AO_CFG2_REG 0x18
664#define NI67XX_CAL_CMD_REG 0x19
665#define NI67XX_CAL_STATUS_REG 0x1a
666#define NI67XX_CAL_STATUS_BUSY BIT(0)
667#define NI67XX_CAL_STATUS_OSC_DETECT BIT(1)
668#define NI67XX_CAL_STATUS_OVERRANGE BIT(2)
669#define NI67XX_CAL_DATA_REG 0x1b
670#define NI67XX_CAL_CFG_HI_REG 0x1c
671#define NI67XX_CAL_CFG_LO_REG 0x1d
672
673#define CS5529_CMD_CB BIT(7)
674#define CS5529_CMD_SINGLE_CONV BIT(6)
675#define CS5529_CMD_CONT_CONV BIT(5)
676#define CS5529_CMD_READ BIT(4)
677#define CS5529_CMD_REG(x) (((x) & 0x7) << 1)
678#define CS5529_CMD_REG_MASK CS5529_CMD_REG(7)
679#define CS5529_CMD_PWR_SAVE BIT(0)
680
681#define CS5529_OFFSET_REG CS5529_CMD_REG(0)
682#define CS5529_GAIN_REG CS5529_CMD_REG(1)
683#define CS5529_CONV_DATA_REG CS5529_CMD_REG(3)
684#define CS5529_SETUP_REG CS5529_CMD_REG(4)
685
686#define CS5529_CFG_REG CS5529_CMD_REG(2)
687#define CS5529_CFG_AOUT(x) BIT(22 + (x))
688#define CS5529_CFG_DOUT(x) BIT(18 + (x))
689#define CS5529_CFG_LOW_PWR_MODE BIT(16)
690#define CS5529_CFG_WORD_RATE(x) (((x) & 0x7) << 13)
691#define CS5529_CFG_WORD_RATE_MASK CS5529_CFG_WORD_RATE(0x7)
692#define CS5529_CFG_WORD_RATE_2180 CS5529_CFG_WORD_RATE(0)
693#define CS5529_CFG_WORD_RATE_1092 CS5529_CFG_WORD_RATE(1)
694#define CS5529_CFG_WORD_RATE_532 CS5529_CFG_WORD_RATE(2)
695#define CS5529_CFG_WORD_RATE_388 CS5529_CFG_WORD_RATE(3)
696#define CS5529_CFG_WORD_RATE_324 CS5529_CFG_WORD_RATE(4)
697#define CS5529_CFG_WORD_RATE_17444 CS5529_CFG_WORD_RATE(5)
698#define CS5529_CFG_WORD_RATE_8724 CS5529_CFG_WORD_RATE(6)
699#define CS5529_CFG_WORD_RATE_4364 CS5529_CFG_WORD_RATE(7)
700#define CS5529_CFG_UNIPOLAR BIT(12)
701#define CS5529_CFG_RESET BIT(7)
702#define CS5529_CFG_RESET_VALID BIT(6)
703#define CS5529_CFG_PORT_FLAG BIT(5)
704#define CS5529_CFG_PWR_SAVE_SEL BIT(4)
705#define CS5529_CFG_DONE_FLAG BIT(3)
706#define CS5529_CFG_CALIB(x) (((x) & 0x7) << 0)
707#define CS5529_CFG_CALIB_NONE CS5529_CFG_CALIB(0)
708#define CS5529_CFG_CALIB_OFFSET_SELF CS5529_CFG_CALIB(1)
709#define CS5529_CFG_CALIB_GAIN_SELF CS5529_CFG_CALIB(2)
710#define CS5529_CFG_CALIB_BOTH_SELF CS5529_CFG_CALIB(3)
711#define CS5529_CFG_CALIB_OFFSET_SYS CS5529_CFG_CALIB(5)
712#define CS5529_CFG_CALIB_GAIN_SYS CS5529_CFG_CALIB(6)
713
714
715
716
717
718#define NI_M_CDIO_DMA_SEL_REG 0x007
719#define NI_M_CDIO_DMA_SEL_CDO(x) (((x) & 0xf) << 4)
720#define NI_M_CDIO_DMA_SEL_CDO_MASK NI_M_CDIO_DMA_SEL_CDO(0xf)
721#define NI_M_CDIO_DMA_SEL_CDI(x) (((x) & 0xf) << 0)
722#define NI_M_CDIO_DMA_SEL_CDI_MASK NI_M_CDIO_DMA_SEL_CDI(0xf)
723#define NI_M_SCXI_STATUS_REG 0x007
724#define NI_M_AI_AO_SEL_REG 0x009
725#define NI_M_G0_G1_SEL_REG 0x00b
726#define NI_M_MISC_CMD_REG 0x00f
727#define NI_M_SCXI_SER_DO_REG 0x011
728#define NI_M_SCXI_CTRL_REG 0x013
729#define NI_M_SCXI_OUT_ENA_REG 0x015
730#define NI_M_AI_FIFO_DATA_REG 0x01c
731#define NI_M_DIO_REG 0x024
732#define NI_M_DIO_DIR_REG 0x028
733#define NI_M_CAL_PWM_REG 0x040
734#define NI_M_CAL_PWM_HIGH_TIME(x) (((x) & 0xffff) << 16)
735#define NI_M_CAL_PWM_LOW_TIME(x) (((x) & 0xffff) << 0)
736#define NI_M_GEN_PWM_REG(x) (0x044 + ((x) * 2))
737#define NI_M_AI_CFG_FIFO_DATA_REG 0x05e
738#define NI_M_AI_CFG_LAST_CHAN BIT(14)
739#define NI_M_AI_CFG_DITHER BIT(13)
740#define NI_M_AI_CFG_POLARITY BIT(12)
741#define NI_M_AI_CFG_GAIN(x) (((x) & 0x7) << 9)
742#define NI_M_AI_CFG_CHAN_TYPE(x) (((x) & 0x7) << 6)
743#define NI_M_AI_CFG_CHAN_TYPE_MASK NI_M_AI_CFG_CHAN_TYPE(7)
744#define NI_M_AI_CFG_CHAN_TYPE_CALIB NI_M_AI_CFG_CHAN_TYPE(0)
745#define NI_M_AI_CFG_CHAN_TYPE_DIFF NI_M_AI_CFG_CHAN_TYPE(1)
746#define NI_M_AI_CFG_CHAN_TYPE_COMMON NI_M_AI_CFG_CHAN_TYPE(2)
747#define NI_M_AI_CFG_CHAN_TYPE_GROUND NI_M_AI_CFG_CHAN_TYPE(3)
748#define NI_M_AI_CFG_CHAN_TYPE_AUX NI_M_AI_CFG_CHAN_TYPE(5)
749#define NI_M_AI_CFG_CHAN_TYPE_GHOST NI_M_AI_CFG_CHAN_TYPE(7)
750#define NI_M_AI_CFG_BANK_SEL(x) ((((x) & 0x40) << 4) | ((x) & 0x30))
751#define NI_M_AI_CFG_CHAN_SEL(x) (((x) & 0xf) << 0)
752#define NI_M_INTC_ENA_REG 0x088
753#define NI_M_INTC_ENA BIT(0)
754#define NI_M_INTC_STATUS_REG 0x088
755#define NI_M_INTC_STATUS BIT(0)
756#define NI_M_ATRIG_CTRL_REG 0x08c
757#define NI_M_AO_SER_INT_ENA_REG 0x0a0
758#define NI_M_AO_SER_INT_ACK_REG 0x0a1
759#define NI_M_AO_SER_INT_STATUS_REG 0x0a1
760#define NI_M_AO_CALIB_REG 0x0a3
761#define NI_M_AO_FIFO_DATA_REG 0x0a4
762#define NI_M_PFI_FILTER_REG 0x0b0
763#define NI_M_PFI_FILTER_SEL(_c, _f) (((_f) & 0x3) << ((_c) * 2))
764#define NI_M_PFI_FILTER_SEL_MASK(_c) NI_M_PFI_FILTER_SEL((_c), 0x3)
765#define NI_M_RTSI_FILTER_REG 0x0b4
766#define NI_M_SCXI_LEGACY_COMPAT_REG 0x0bc
767#define NI_M_DAC_DIRECT_DATA_REG(x) (0x0c0 + ((x) * 4))
768#define NI_M_AO_WAVEFORM_ORDER_REG(x) (0x0c2 + ((x) * 4))
769#define NI_M_AO_CFG_BANK_REG(x) (0x0c3 + ((x) * 4))
770#define NI_M_AO_CFG_BANK_BIPOLAR BIT(7)
771#define NI_M_AO_CFG_BANK_UPDATE_TIMED BIT(6)
772#define NI_M_AO_CFG_BANK_REF(x) (((x) & 0x7) << 3)
773#define NI_M_AO_CFG_BANK_REF_MASK NI_M_AO_CFG_BANK_REF(7)
774#define NI_M_AO_CFG_BANK_REF_INT_10V NI_M_AO_CFG_BANK_REF(0)
775#define NI_M_AO_CFG_BANK_REF_INT_5V NI_M_AO_CFG_BANK_REF(1)
776#define NI_M_AO_CFG_BANK_OFFSET(x) (((x) & 0x7) << 0)
777#define NI_M_AO_CFG_BANK_OFFSET_MASK NI_M_AO_CFG_BANK_OFFSET(7)
778#define NI_M_AO_CFG_BANK_OFFSET_0V NI_M_AO_CFG_BANK_OFFSET(0)
779#define NI_M_AO_CFG_BANK_OFFSET_5V NI_M_AO_CFG_BANK_OFFSET(1)
780#define NI_M_RTSI_SHARED_MUX_REG 0x1a2
781#define NI_M_CLK_FOUT2_REG 0x1c4
782#define NI_M_CLK_FOUT2_RTSI_10MHZ BIT(7)
783#define NI_M_CLK_FOUT2_TIMEBASE3_PLL BIT(6)
784#define NI_M_CLK_FOUT2_TIMEBASE1_PLL BIT(5)
785#define NI_M_CLK_FOUT2_PLL_SRC(x) (((x) & 0x1f) << 0)
786#define NI_M_CLK_FOUT2_PLL_SRC_MASK NI_M_CLK_FOUT2_PLL_SRC(0x1f)
787#define NI_M_MAX_RTSI_CHAN 7
788#define NI_M_CLK_FOUT2_PLL_SRC_RTSI(x) (((x) == NI_M_MAX_RTSI_CHAN) \
789 ? NI_M_CLK_FOUT2_PLL_SRC(0x1b) \
790 : NI_M_CLK_FOUT2_PLL_SRC(0xb + (x)))
791#define NI_M_CLK_FOUT2_PLL_SRC_STAR NI_M_CLK_FOUT2_PLL_SRC(0x14)
792#define NI_M_CLK_FOUT2_PLL_SRC_PXI10 NI_M_CLK_FOUT2_PLL_SRC(0x1d)
793#define NI_M_PLL_CTRL_REG 0x1c6
794#define NI_M_PLL_CTRL_VCO_MODE(x) (((x) & 0x3) << 13)
795#define NI_M_PLL_CTRL_VCO_MODE_200_325MHZ NI_M_PLL_CTRL_VCO_MODE(0)
796#define NI_M_PLL_CTRL_VCO_MODE_175_225MHZ NI_M_PLL_CTRL_VCO_MODE(1)
797#define NI_M_PLL_CTRL_VCO_MODE_100_225MHZ NI_M_PLL_CTRL_VCO_MODE(2)
798#define NI_M_PLL_CTRL_VCO_MODE_75_150MHZ NI_M_PLL_CTRL_VCO_MODE(3)
799#define NI_M_PLL_CTRL_ENA BIT(12)
800#define NI_M_PLL_MAX_DIVISOR 0x10
801#define NI_M_PLL_CTRL_DIVISOR(x) (((x) & 0xf) << 8)
802#define NI_M_PLL_MAX_MULTIPLIER 0x100
803#define NI_M_PLL_CTRL_MULTIPLIER(x) (((x) & 0xff) << 0)
804#define NI_M_PLL_STATUS_REG 0x1c8
805#define NI_M_PLL_STATUS_LOCKED BIT(0)
806#define NI_M_PFI_OUT_SEL_REG(x) (0x1d0 + ((x) * 2))
807#define NI_M_PFI_CHAN(_c) (((_c) % 3) * 5)
808#define NI_M_PFI_OUT_SEL(_c, _s) (((_s) & 0x1f) << NI_M_PFI_CHAN(_c))
809#define NI_M_PFI_OUT_SEL_MASK(_c) (0x1f << NI_M_PFI_CHAN(_c))
810#define NI_M_PFI_OUT_SEL_TO_SRC(_c, _b) (((_b) >> NI_M_PFI_CHAN(_c)) & 0x1f)
811#define NI_M_PFI_DI_REG 0x1dc
812#define NI_M_PFI_DO_REG 0x1de
813#define NI_M_CFG_BYPASS_FIFO_REG 0x218
814#define NI_M_CFG_BYPASS_FIFO BIT(31)
815#define NI_M_CFG_BYPASS_AI_POLARITY BIT(22)
816#define NI_M_CFG_BYPASS_AI_DITHER BIT(21)
817#define NI_M_CFG_BYPASS_AI_GAIN(x) (((x) & 0x7) << 18)
818#define NI_M_CFG_BYPASS_AO_CAL(x) (((x) & 0xf) << 15)
819#define NI_M_CFG_BYPASS_AO_CAL_MASK NI_M_CFG_BYPASS_AO_CAL(0xf)
820#define NI_M_CFG_BYPASS_AI_MODE_MUX(x) (((x) & 0x3) << 13)
821#define NI_M_CFG_BYPASS_AI_MODE_MUX_MASK NI_M_CFG_BYPASS_AI_MODE_MUX(3)
822#define NI_M_CFG_BYPASS_AI_CAL_NEG(x) (((x) & 0x7) << 10)
823#define NI_M_CFG_BYPASS_AI_CAL_NEG_MASK NI_M_CFG_BYPASS_AI_CAL_NEG(7)
824#define NI_M_CFG_BYPASS_AI_CAL_POS(x) (((x) & 0x7) << 7)
825#define NI_M_CFG_BYPASS_AI_CAL_POS_MASK NI_M_CFG_BYPASS_AI_CAL_POS(7)
826#define NI_M_CFG_BYPASS_AI_CAL_MASK (NI_M_CFG_BYPASS_AI_CAL_POS_MASK | \
827 NI_M_CFG_BYPASS_AI_CAL_NEG_MASK | \
828 NI_M_CFG_BYPASS_AI_MODE_MUX_MASK | \
829 NI_M_CFG_BYPASS_AO_CAL_MASK)
830#define NI_M_CFG_BYPASS_AI_BANK(x) (((x) & 0xf) << 3)
831#define NI_M_CFG_BYPASS_AI_BANK_MASK NI_M_CFG_BYPASS_AI_BANK(0xf)
832#define NI_M_CFG_BYPASS_AI_CHAN(x) (((x) & 0x7) << 0)
833#define NI_M_CFG_BYPASS_AI_CHAN_MASK NI_M_CFG_BYPASS_AI_CHAN(7)
834#define NI_M_SCXI_DIO_ENA_REG 0x21c
835#define NI_M_CDI_FIFO_DATA_REG 0x220
836#define NI_M_CDO_FIFO_DATA_REG 0x220
837#define NI_M_CDIO_STATUS_REG 0x224
838#define NI_M_CDIO_STATUS_CDI_OVERFLOW BIT(20)
839#define NI_M_CDIO_STATUS_CDI_OVERRUN BIT(19)
840#define NI_M_CDIO_STATUS_CDI_ERROR (NI_M_CDIO_STATUS_CDI_OVERFLOW | \
841 NI_M_CDIO_STATUS_CDI_OVERRUN)
842#define NI_M_CDIO_STATUS_CDI_FIFO_REQ BIT(18)
843#define NI_M_CDIO_STATUS_CDI_FIFO_FULL BIT(17)
844#define NI_M_CDIO_STATUS_CDI_FIFO_EMPTY BIT(16)
845#define NI_M_CDIO_STATUS_CDO_UNDERFLOW BIT(4)
846#define NI_M_CDIO_STATUS_CDO_OVERRUN BIT(3)
847#define NI_M_CDIO_STATUS_CDO_ERROR (NI_M_CDIO_STATUS_CDO_UNDERFLOW | \
848 NI_M_CDIO_STATUS_CDO_OVERRUN)
849#define NI_M_CDIO_STATUS_CDO_FIFO_REQ BIT(2)
850#define NI_M_CDIO_STATUS_CDO_FIFO_FULL BIT(1)
851#define NI_M_CDIO_STATUS_CDO_FIFO_EMPTY BIT(0)
852#define NI_M_CDIO_CMD_REG 0x224
853#define NI_M_CDI_CMD_SW_UPDATE BIT(20)
854#define NI_M_CDO_CMD_SW_UPDATE BIT(19)
855#define NI_M_CDO_CMD_F_E_INT_ENA_CLR BIT(17)
856#define NI_M_CDO_CMD_F_E_INT_ENA_SET BIT(16)
857#define NI_M_CDI_CMD_ERR_INT_CONFIRM BIT(15)
858#define NI_M_CDO_CMD_ERR_INT_CONFIRM BIT(14)
859#define NI_M_CDI_CMD_F_REQ_INT_ENA_CLR BIT(13)
860#define NI_M_CDI_CMD_F_REQ_INT_ENA_SET BIT(12)
861#define NI_M_CDO_CMD_F_REQ_INT_ENA_CLR BIT(11)
862#define NI_M_CDO_CMD_F_REQ_INT_ENA_SET BIT(10)
863#define NI_M_CDI_CMD_ERR_INT_ENA_CLR BIT(9)
864#define NI_M_CDI_CMD_ERR_INT_ENA_SET BIT(8)
865#define NI_M_CDO_CMD_ERR_INT_ENA_CLR BIT(7)
866#define NI_M_CDO_CMD_ERR_INT_ENA_SET BIT(6)
867#define NI_M_CDI_CMD_RESET BIT(5)
868#define NI_M_CDO_CMD_RESET BIT(4)
869#define NI_M_CDI_CMD_ARM BIT(3)
870#define NI_M_CDI_CMD_DISARM BIT(2)
871#define NI_M_CDO_CMD_ARM BIT(1)
872#define NI_M_CDO_CMD_DISARM BIT(0)
873#define NI_M_CDI_MODE_REG 0x228
874#define NI_M_CDI_MODE_DATA_LANE(x) (((x) & 0x3) << 12)
875#define NI_M_CDI_MODE_DATA_LANE_MASK NI_M_CDI_MODE_DATA_LANE(3)
876#define NI_M_CDI_MODE_DATA_LANE_0_15 NI_M_CDI_MODE_DATA_LANE(0)
877#define NI_M_CDI_MODE_DATA_LANE_16_31 NI_M_CDI_MODE_DATA_LANE(1)
878#define NI_M_CDI_MODE_DATA_LANE_0_7 NI_M_CDI_MODE_DATA_LANE(0)
879#define NI_M_CDI_MODE_DATA_LANE_8_15 NI_M_CDI_MODE_DATA_LANE(1)
880#define NI_M_CDI_MODE_DATA_LANE_16_23 NI_M_CDI_MODE_DATA_LANE(2)
881#define NI_M_CDI_MODE_DATA_LANE_24_31 NI_M_CDI_MODE_DATA_LANE(3)
882#define NI_M_CDI_MODE_FIFO_MODE BIT(11)
883#define NI_M_CDI_MODE_POLARITY BIT(10)
884#define NI_M_CDI_MODE_HALT_ON_ERROR BIT(9)
885#define NI_M_CDI_MODE_SAMPLE_SRC(x) (((x) & 0x3f) << 0)
886#define NI_M_CDI_MODE_SAMPLE_SRC_MASK NI_M_CDI_MODE_SAMPLE_SRC(0x3f)
887#define NI_M_CDO_MODE_REG 0x22c
888#define NI_M_CDO_MODE_DATA_LANE(x) (((x) & 0x3) << 12)
889#define NI_M_CDO_MODE_DATA_LANE_MASK NI_M_CDO_MODE_DATA_LANE(3)
890#define NI_M_CDO_MODE_DATA_LANE_0_15 NI_M_CDO_MODE_DATA_LANE(0)
891#define NI_M_CDO_MODE_DATA_LANE_16_31 NI_M_CDO_MODE_DATA_LANE(1)
892#define NI_M_CDO_MODE_DATA_LANE_0_7 NI_M_CDO_MODE_DATA_LANE(0)
893#define NI_M_CDO_MODE_DATA_LANE_8_15 NI_M_CDO_MODE_DATA_LANE(1)
894#define NI_M_CDO_MODE_DATA_LANE_16_23 NI_M_CDO_MODE_DATA_LANE(2)
895#define NI_M_CDO_MODE_DATA_LANE_24_31 NI_M_CDO_MODE_DATA_LANE(3)
896#define NI_M_CDO_MODE_FIFO_MODE BIT(11)
897#define NI_M_CDO_MODE_POLARITY BIT(10)
898#define NI_M_CDO_MODE_HALT_ON_ERROR BIT(9)
899#define NI_M_CDO_MODE_RETRANSMIT BIT(8)
900#define NI_M_CDO_MODE_SAMPLE_SRC(x) (((x) & 0x3f) << 0)
901#define NI_M_CDO_MODE_SAMPLE_SRC_MASK NI_M_CDO_MODE_SAMPLE_SRC(0x3f)
902#define NI_M_CDI_MASK_ENA_REG 0x230
903#define NI_M_CDO_MASK_ENA_REG 0x234
904#define NI_M_STATIC_AI_CTRL_REG(x) ((x) ? (0x260 + (x)) : 0x064)
905#define NI_M_AO_REF_ATTENUATION_REG(x) (0x264 + (x))
906#define NI_M_AO_REF_ATTENUATION_X5 BIT(0)
907
908enum {
909 ai_gain_16 = 0,
910 ai_gain_8,
911 ai_gain_14,
912 ai_gain_4,
913 ai_gain_611x,
914 ai_gain_622x,
915 ai_gain_628x,
916 ai_gain_6143
917};
918
919enum caldac_enum {
920 caldac_none = 0,
921 mb88341,
922 dac8800,
923 dac8043,
924 ad8522,
925 ad8804,
926 ad8842,
927 ad8804_debug
928};
929
930enum ni_reg_type {
931 ni_reg_normal = 0x0,
932 ni_reg_611x = 0x1,
933 ni_reg_6711 = 0x2,
934 ni_reg_6713 = 0x4,
935 ni_reg_67xx_mask = 0x6,
936 ni_reg_6xxx_mask = 0x7,
937 ni_reg_622x = 0x8,
938 ni_reg_625x = 0x10,
939 ni_reg_628x = 0x18,
940 ni_reg_m_series_mask = 0x18,
941 ni_reg_6143 = 0x20
942};
943
944struct ni_board_struct {
945 const char *name;
946 int device_id;
947 int isapnp_id;
948
949 int n_adchan;
950 unsigned int ai_maxdata;
951
952 int ai_fifo_depth;
953 unsigned int alwaysdither:1;
954 int gainlkup;
955 int ai_speed;
956
957 int n_aochan;
958 unsigned int ao_maxdata;
959 int ao_fifo_depth;
960 const struct comedi_lrange *ao_range_table;
961 unsigned ao_speed;
962
963 int reg_type;
964 unsigned int has_8255:1;
965 unsigned int has_32dio_chan:1;
966
967 enum caldac_enum caldac[3];
968};
969
970#define MAX_N_CALDACS 34
971#define MAX_N_AO_CHAN 8
972#define NUM_GPCT 2
973
974#define NUM_PFI_OUTPUT_SELECT_REGS 6
975
976#define M_SERIES_EEPROM_SIZE 1024
977
978struct ni_private {
979 unsigned short dio_output;
980 unsigned short dio_control;
981 int aimode;
982 unsigned int ai_calib_source;
983 unsigned int ai_calib_source_enabled;
984
985 spinlock_t window_lock;
986
987 spinlock_t soft_reg_copy_lock;
988
989 spinlock_t mite_channel_lock;
990
991 int changain_state;
992 unsigned int changain_spec;
993
994 unsigned int caldac_maxdata_list[MAX_N_CALDACS];
995 unsigned short caldacs[MAX_N_CALDACS];
996
997 unsigned short ai_cmd2;
998
999 unsigned short ao_conf[MAX_N_AO_CHAN];
1000 unsigned short ao_mode1;
1001 unsigned short ao_mode2;
1002 unsigned short ao_mode3;
1003 unsigned short ao_cmd1;
1004 unsigned short ao_cmd2;
1005 unsigned short ao_trigger_select;
1006
1007 struct ni_gpct_device *counter_dev;
1008 unsigned short an_trig_etc_reg;
1009
1010 unsigned ai_offset[512];
1011
1012 unsigned long serial_interval_ns;
1013 unsigned char serial_hw_mode;
1014 unsigned short clock_and_fout;
1015 unsigned short clock_and_fout2;
1016
1017 unsigned short int_a_enable_reg;
1018 unsigned short int_b_enable_reg;
1019 unsigned short io_bidirection_pin_reg;
1020 unsigned short rtsi_trig_direction_reg;
1021 unsigned short rtsi_trig_a_output_reg;
1022 unsigned short rtsi_trig_b_output_reg;
1023 unsigned short pfi_output_select_reg[NUM_PFI_OUTPUT_SELECT_REGS];
1024 unsigned short ai_ao_select_reg;
1025 unsigned short g0_g1_select_reg;
1026 unsigned short cdio_dma_select_reg;
1027
1028 unsigned clock_ns;
1029 unsigned clock_source;
1030
1031 unsigned short pwm_up_count;
1032 unsigned short pwm_down_count;
1033
1034 unsigned short ai_fifo_buffer[0x2000];
1035 uint8_t eeprom_buffer[M_SERIES_EEPROM_SIZE];
1036 __be32 serial_number;
1037
1038 struct mite_struct *mite;
1039 struct mite_channel *ai_mite_chan;
1040 struct mite_channel *ao_mite_chan;
1041 struct mite_channel *cdo_mite_chan;
1042 struct mite_dma_descriptor_ring *ai_mite_ring;
1043 struct mite_dma_descriptor_ring *ao_mite_ring;
1044 struct mite_dma_descriptor_ring *cdo_mite_ring;
1045 struct mite_dma_descriptor_ring *gpct_mite_ring[NUM_GPCT];
1046
1047
1048 unsigned int is_m_series:1;
1049 unsigned int is_6xxx:1;
1050 unsigned int is_611x:1;
1051 unsigned int is_6143:1;
1052 unsigned int is_622x:1;
1053 unsigned int is_625x:1;
1054 unsigned int is_628x:1;
1055 unsigned int is_67xx:1;
1056 unsigned int is_6711:1;
1057 unsigned int is_6713:1;
1058};
1059
1060static const struct comedi_lrange range_ni_E_ao_ext;
1061
1062#endif
1063