linux/drivers/usb/host/ehci-pci.c
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   1/*
   2 * EHCI HCD (Host Controller Driver) PCI Bus Glue.
   3 *
   4 * Copyright (c) 2000-2004 by David Brownell
   5 *
   6 * This program is free software; you can redistribute it and/or modify it
   7 * under the terms of the GNU General Public License as published by the
   8 * Free Software Foundation; either version 2 of the License, or (at your
   9 * option) any later version.
  10 *
  11 * This program is distributed in the hope that it will be useful, but
  12 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13 * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  14 * for more details.
  15 *
  16 * You should have received a copy of the GNU General Public License
  17 * along with this program; if not, write to the Free Software Foundation,
  18 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19 */
  20
  21#include <linux/kernel.h>
  22#include <linux/module.h>
  23#include <linux/pci.h>
  24#include <linux/usb.h>
  25#include <linux/usb/hcd.h>
  26
  27#include "ehci.h"
  28#include "pci-quirks.h"
  29
  30#define DRIVER_DESC "EHCI PCI platform driver"
  31
  32static const char hcd_name[] = "ehci-pci";
  33
  34/* defined here to avoid adding to pci_ids.h for single instance use */
  35#define PCI_DEVICE_ID_INTEL_CE4100_USB  0x2e70
  36
  37/*-------------------------------------------------------------------------*/
  38#define PCI_DEVICE_ID_INTEL_QUARK_X1000_SOC             0x0939
  39static inline bool is_intel_quark_x1000(struct pci_dev *pdev)
  40{
  41        return pdev->vendor == PCI_VENDOR_ID_INTEL &&
  42                pdev->device == PCI_DEVICE_ID_INTEL_QUARK_X1000_SOC;
  43}
  44
  45/*
  46 * This is the list of PCI IDs for the devices that have EHCI USB class and
  47 * specific drivers for that. One of the example is a ChipIdea device installed
  48 * on some Intel MID platforms.
  49 */
  50static const struct pci_device_id bypass_pci_id_table[] = {
  51        /* ChipIdea on Intel MID platform */
  52        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0811), },
  53        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0829), },
  54        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe006), },
  55        {}
  56};
  57
  58static inline bool is_bypassed_id(struct pci_dev *pdev)
  59{
  60        return !!pci_match_id(bypass_pci_id_table, pdev);
  61}
  62
  63/*
  64 * 0x84 is the offset of in/out threshold register,
  65 * and it is the same offset as the register of 'hostpc'.
  66 */
  67#define intel_quark_x1000_insnreg01     hostpc
  68
  69/* Maximum usable threshold value is 0x7f dwords for both IN and OUT */
  70#define INTEL_QUARK_X1000_EHCI_MAX_THRESHOLD    0x007f007f
  71
  72/* called after powerup, by probe or system-pm "wakeup" */
  73static int ehci_pci_reinit(struct ehci_hcd *ehci, struct pci_dev *pdev)
  74{
  75        int                     retval;
  76
  77        /* we expect static quirk code to handle the "extended capabilities"
  78         * (currently just BIOS handoff) allowed starting with EHCI 0.96
  79         */
  80
  81        /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
  82        retval = pci_set_mwi(pdev);
  83        if (!retval)
  84                ehci_dbg(ehci, "MWI active\n");
  85
  86        /* Reset the threshold limit */
  87        if (is_intel_quark_x1000(pdev)) {
  88                /*
  89                 * For the Intel QUARK X1000, raise the I/O threshold to the
  90                 * maximum usable value in order to improve performance.
  91                 */
  92                ehci_writel(ehci, INTEL_QUARK_X1000_EHCI_MAX_THRESHOLD,
  93                        ehci->regs->intel_quark_x1000_insnreg01);
  94        }
  95
  96        return 0;
  97}
  98
  99/* called during probe() after chip reset completes */
 100static int ehci_pci_setup(struct usb_hcd *hcd)
 101{
 102        struct ehci_hcd         *ehci = hcd_to_ehci(hcd);
 103        struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 104        u32                     temp;
 105        int                     retval;
 106
 107        ehci->caps = hcd->regs;
 108
 109        /*
 110         * ehci_init() causes memory for DMA transfers to be
 111         * allocated.  Thus, any vendor-specific workarounds based on
 112         * limiting the type of memory used for DMA transfers must
 113         * happen before ehci_setup() is called.
 114         *
 115         * Most other workarounds can be done either before or after
 116         * init and reset; they are located here too.
 117         */
 118        switch (pdev->vendor) {
 119        case PCI_VENDOR_ID_TOSHIBA_2:
 120                /* celleb's companion chip */
 121                if (pdev->device == 0x01b5) {
 122#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
 123                        ehci->big_endian_mmio = 1;
 124#else
 125                        ehci_warn(ehci,
 126                                  "unsupported big endian Toshiba quirk\n");
 127#endif
 128                }
 129                break;
 130        case PCI_VENDOR_ID_NVIDIA:
 131                /* NVidia reports that certain chips don't handle
 132                 * QH, ITD, or SITD addresses above 2GB.  (But TD,
 133                 * data buffer, and periodic schedule are normal.)
 134                 */
 135                switch (pdev->device) {
 136                case 0x003c:    /* MCP04 */
 137                case 0x005b:    /* CK804 */
 138                case 0x00d8:    /* CK8 */
 139                case 0x00e8:    /* CK8S */
 140                        if (pci_set_consistent_dma_mask(pdev,
 141                                                DMA_BIT_MASK(31)) < 0)
 142                                ehci_warn(ehci, "can't enable NVidia "
 143                                        "workaround for >2GB RAM\n");
 144                        break;
 145
 146                /* Some NForce2 chips have problems with selective suspend;
 147                 * fixed in newer silicon.
 148                 */
 149                case 0x0068:
 150                        if (pdev->revision < 0xa4)
 151                                ehci->no_selective_suspend = 1;
 152                        break;
 153                }
 154                break;
 155        case PCI_VENDOR_ID_INTEL:
 156                if (pdev->device == PCI_DEVICE_ID_INTEL_CE4100_USB)
 157                        hcd->has_tt = 1;
 158                break;
 159        case PCI_VENDOR_ID_TDI:
 160                if (pdev->device == PCI_DEVICE_ID_TDI_EHCI)
 161                        hcd->has_tt = 1;
 162                break;
 163        case PCI_VENDOR_ID_AMD:
 164                /* AMD PLL quirk */
 165                if (usb_amd_find_chipset_info())
 166                        ehci->amd_pll_fix = 1;
 167                /* AMD8111 EHCI doesn't work, according to AMD errata */
 168                if (pdev->device == 0x7463) {
 169                        ehci_info(ehci, "ignoring AMD8111 (errata)\n");
 170                        retval = -EIO;
 171                        goto done;
 172                }
 173
 174                /*
 175                 * EHCI controller on AMD SB700/SB800/Hudson-2/3 platforms may
 176                 * read/write memory space which does not belong to it when
 177                 * there is NULL pointer with T-bit set to 1 in the frame list
 178                 * table. To avoid the issue, the frame list link pointer
 179                 * should always contain a valid pointer to a inactive qh.
 180                 */
 181                if (pdev->device == 0x7808) {
 182                        ehci->use_dummy_qh = 1;
 183                        ehci_info(ehci, "applying AMD SB700/SB800/Hudson-2/3 EHCI dummy qh workaround\n");
 184                }
 185                break;
 186        case PCI_VENDOR_ID_VIA:
 187                if (pdev->device == 0x3104 && (pdev->revision & 0xf0) == 0x60) {
 188                        u8 tmp;
 189
 190                        /* The VT6212 defaults to a 1 usec EHCI sleep time which
 191                         * hogs the PCI bus *badly*. Setting bit 5 of 0x4B makes
 192                         * that sleep time use the conventional 10 usec.
 193                         */
 194                        pci_read_config_byte(pdev, 0x4b, &tmp);
 195                        if (tmp & 0x20)
 196                                break;
 197                        pci_write_config_byte(pdev, 0x4b, tmp | 0x20);
 198                }
 199                break;
 200        case PCI_VENDOR_ID_ATI:
 201                /* AMD PLL quirk */
 202                if (usb_amd_find_chipset_info())
 203                        ehci->amd_pll_fix = 1;
 204
 205                /*
 206                 * EHCI controller on AMD SB700/SB800/Hudson-2/3 platforms may
 207                 * read/write memory space which does not belong to it when
 208                 * there is NULL pointer with T-bit set to 1 in the frame list
 209                 * table. To avoid the issue, the frame list link pointer
 210                 * should always contain a valid pointer to a inactive qh.
 211                 */
 212                if (pdev->device == 0x4396) {
 213                        ehci->use_dummy_qh = 1;
 214                        ehci_info(ehci, "applying AMD SB700/SB800/Hudson-2/3 EHCI dummy qh workaround\n");
 215                }
 216                /* SB600 and old version of SB700 have a bug in EHCI controller,
 217                 * which causes usb devices lose response in some cases.
 218                 */
 219                if ((pdev->device == 0x4386 || pdev->device == 0x4396) &&
 220                                usb_amd_hang_symptom_quirk()) {
 221                        u8 tmp;
 222                        ehci_info(ehci, "applying AMD SB600/SB700 USB freeze workaround\n");
 223                        pci_read_config_byte(pdev, 0x53, &tmp);
 224                        pci_write_config_byte(pdev, 0x53, tmp | (1<<3));
 225                }
 226                break;
 227        case PCI_VENDOR_ID_NETMOS:
 228                /* MosChip frame-index-register bug */
 229                ehci_info(ehci, "applying MosChip frame-index workaround\n");
 230                ehci->frame_index_bug = 1;
 231                break;
 232        }
 233
 234        /* optional debug port, normally in the first BAR */
 235        temp = pci_find_capability(pdev, PCI_CAP_ID_DBG);
 236        if (temp) {
 237                pci_read_config_dword(pdev, temp, &temp);
 238                temp >>= 16;
 239                if (((temp >> 13) & 7) == 1) {
 240                        u32 hcs_params = ehci_readl(ehci,
 241                                                    &ehci->caps->hcs_params);
 242
 243                        temp &= 0x1fff;
 244                        ehci->debug = hcd->regs + temp;
 245                        temp = ehci_readl(ehci, &ehci->debug->control);
 246                        ehci_info(ehci, "debug port %d%s\n",
 247                                  HCS_DEBUG_PORT(hcs_params),
 248                                  (temp & DBGP_ENABLED) ? " IN USE" : "");
 249                        if (!(temp & DBGP_ENABLED))
 250                                ehci->debug = NULL;
 251                }
 252        }
 253
 254        retval = ehci_setup(hcd);
 255        if (retval)
 256                return retval;
 257
 258        /* These workarounds need to be applied after ehci_setup() */
 259        switch (pdev->vendor) {
 260        case PCI_VENDOR_ID_NEC:
 261                ehci->need_io_watchdog = 0;
 262                break;
 263        case PCI_VENDOR_ID_INTEL:
 264                ehci->need_io_watchdog = 0;
 265                break;
 266        case PCI_VENDOR_ID_NVIDIA:
 267                switch (pdev->device) {
 268                /* MCP89 chips on the MacBookAir3,1 give EPROTO when
 269                 * fetching device descriptors unless LPM is disabled.
 270                 * There are also intermittent problems enumerating
 271                 * devices with PPCD enabled.
 272                 */
 273                case 0x0d9d:
 274                        ehci_info(ehci, "disable ppcd for nvidia mcp89\n");
 275                        ehci->has_ppcd = 0;
 276                        ehci->command &= ~CMD_PPCEE;
 277                        break;
 278                }
 279                break;
 280        }
 281
 282        /* at least the Genesys GL880S needs fixup here */
 283        temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params);
 284        temp &= 0x0f;
 285        if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) {
 286                ehci_dbg(ehci, "bogus port configuration: "
 287                        "cc=%d x pcc=%d < ports=%d\n",
 288                        HCS_N_CC(ehci->hcs_params),
 289                        HCS_N_PCC(ehci->hcs_params),
 290                        HCS_N_PORTS(ehci->hcs_params));
 291
 292                switch (pdev->vendor) {
 293                case 0x17a0:            /* GENESYS */
 294                        /* GL880S: should be PORTS=2 */
 295                        temp |= (ehci->hcs_params & ~0xf);
 296                        ehci->hcs_params = temp;
 297                        break;
 298                case PCI_VENDOR_ID_NVIDIA:
 299                        /* NF4: should be PCC=10 */
 300                        break;
 301                }
 302        }
 303
 304        /* Serial Bus Release Number is at PCI 0x60 offset */
 305        if (pdev->vendor == PCI_VENDOR_ID_STMICRO
 306            && pdev->device == PCI_DEVICE_ID_STMICRO_USB_HOST)
 307                ;       /* ConneXT has no sbrn register */
 308        else
 309                pci_read_config_byte(pdev, 0x60, &ehci->sbrn);
 310
 311        /* Keep this around for a while just in case some EHCI
 312         * implementation uses legacy PCI PM support.  This test
 313         * can be removed on 17 Dec 2009 if the dev_warn() hasn't
 314         * been triggered by then.
 315         */
 316        if (!device_can_wakeup(&pdev->dev)) {
 317                u16     port_wake;
 318
 319                pci_read_config_word(pdev, 0x62, &port_wake);
 320                if (port_wake & 0x0001) {
 321                        dev_warn(&pdev->dev, "Enabling legacy PCI PM\n");
 322                        device_set_wakeup_capable(&pdev->dev, 1);
 323                }
 324        }
 325
 326#ifdef  CONFIG_PM
 327        if (ehci->no_selective_suspend && device_can_wakeup(&pdev->dev))
 328                ehci_warn(ehci, "selective suspend/wakeup unavailable\n");
 329#endif
 330
 331        retval = ehci_pci_reinit(ehci, pdev);
 332done:
 333        return retval;
 334}
 335
 336/*-------------------------------------------------------------------------*/
 337
 338#ifdef  CONFIG_PM
 339
 340/* suspend/resume, section 4.3 */
 341
 342/* These routines rely on the PCI bus glue
 343 * to handle powerdown and wakeup, and currently also on
 344 * transceivers that don't need any software attention to set up
 345 * the right sort of wakeup.
 346 * Also they depend on separate root hub suspend/resume.
 347 */
 348
 349static int ehci_pci_resume(struct usb_hcd *hcd, bool hibernated)
 350{
 351        struct ehci_hcd         *ehci = hcd_to_ehci(hcd);
 352        struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 353
 354        if (ehci_resume(hcd, hibernated) != 0)
 355                (void) ehci_pci_reinit(ehci, pdev);
 356        return 0;
 357}
 358
 359#else
 360
 361#define ehci_suspend            NULL
 362#define ehci_pci_resume         NULL
 363#endif  /* CONFIG_PM */
 364
 365static struct hc_driver __read_mostly ehci_pci_hc_driver;
 366
 367static const struct ehci_driver_overrides pci_overrides __initconst = {
 368        .reset =                ehci_pci_setup,
 369};
 370
 371/*-------------------------------------------------------------------------*/
 372
 373static int ehci_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 374{
 375        if (is_bypassed_id(pdev))
 376                return -ENODEV;
 377        return usb_hcd_pci_probe(pdev, id);
 378}
 379
 380/* PCI driver selection metadata; PCI hotplugging uses this */
 381static const struct pci_device_id pci_ids [] = { {
 382        /* handle any USB 2.0 EHCI controller */
 383        PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_EHCI, ~0),
 384        .driver_data =  (unsigned long) &ehci_pci_hc_driver,
 385        }, {
 386        PCI_VDEVICE(STMICRO, PCI_DEVICE_ID_STMICRO_USB_HOST),
 387        .driver_data = (unsigned long) &ehci_pci_hc_driver,
 388        },
 389        { /* end: all zeroes */ }
 390};
 391MODULE_DEVICE_TABLE(pci, pci_ids);
 392
 393/* pci driver glue; this is a "new style" PCI driver module */
 394static struct pci_driver ehci_pci_driver = {
 395        .name =         (char *) hcd_name,
 396        .id_table =     pci_ids,
 397
 398        .probe =        ehci_pci_probe,
 399        .remove =       usb_hcd_pci_remove,
 400        .shutdown =     usb_hcd_pci_shutdown,
 401
 402#ifdef CONFIG_PM
 403        .driver =       {
 404                .pm =   &usb_hcd_pci_pm_ops
 405        },
 406#endif
 407};
 408
 409static int __init ehci_pci_init(void)
 410{
 411        if (usb_disabled())
 412                return -ENODEV;
 413
 414        pr_info("%s: " DRIVER_DESC "\n", hcd_name);
 415
 416        ehci_init_driver(&ehci_pci_hc_driver, &pci_overrides);
 417
 418        /* Entries for the PCI suspend/resume callbacks are special */
 419        ehci_pci_hc_driver.pci_suspend = ehci_suspend;
 420        ehci_pci_hc_driver.pci_resume = ehci_pci_resume;
 421
 422        return pci_register_driver(&ehci_pci_driver);
 423}
 424module_init(ehci_pci_init);
 425
 426static void __exit ehci_pci_cleanup(void)
 427{
 428        pci_unregister_driver(&ehci_pci_driver);
 429}
 430module_exit(ehci_pci_cleanup);
 431
 432MODULE_DESCRIPTION(DRIVER_DESC);
 433MODULE_AUTHOR("David Brownell");
 434MODULE_AUTHOR("Alan Stern");
 435MODULE_LICENSE("GPL");
 436