1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32#ifndef __AMDGPU_DRM_H__
33#define __AMDGPU_DRM_H__
34
35#include "drm.h"
36
37#define DRM_AMDGPU_GEM_CREATE 0x00
38#define DRM_AMDGPU_GEM_MMAP 0x01
39#define DRM_AMDGPU_CTX 0x02
40#define DRM_AMDGPU_BO_LIST 0x03
41#define DRM_AMDGPU_CS 0x04
42#define DRM_AMDGPU_INFO 0x05
43#define DRM_AMDGPU_GEM_METADATA 0x06
44#define DRM_AMDGPU_GEM_WAIT_IDLE 0x07
45#define DRM_AMDGPU_GEM_VA 0x08
46#define DRM_AMDGPU_WAIT_CS 0x09
47#define DRM_AMDGPU_GEM_OP 0x10
48#define DRM_AMDGPU_GEM_USERPTR 0x11
49
50#define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
51#define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
52#define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx)
53#define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list)
54#define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs)
55#define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info)
56#define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata)
57#define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle)
58#define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va)
59#define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs)
60#define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op)
61#define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr)
62
63#define AMDGPU_GEM_DOMAIN_CPU 0x1
64#define AMDGPU_GEM_DOMAIN_GTT 0x2
65#define AMDGPU_GEM_DOMAIN_VRAM 0x4
66#define AMDGPU_GEM_DOMAIN_GDS 0x8
67#define AMDGPU_GEM_DOMAIN_GWS 0x10
68#define AMDGPU_GEM_DOMAIN_OA 0x20
69
70
71#define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0)
72
73#define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1)
74
75#define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2)
76
77struct drm_amdgpu_gem_create_in {
78
79 uint64_t bo_size;
80
81 uint64_t alignment;
82
83 uint64_t domains;
84
85 uint64_t domain_flags;
86};
87
88struct drm_amdgpu_gem_create_out {
89
90 uint32_t handle;
91 uint32_t _pad;
92};
93
94union drm_amdgpu_gem_create {
95 struct drm_amdgpu_gem_create_in in;
96 struct drm_amdgpu_gem_create_out out;
97};
98
99
100#define AMDGPU_BO_LIST_OP_CREATE 0
101
102#define AMDGPU_BO_LIST_OP_DESTROY 1
103
104#define AMDGPU_BO_LIST_OP_UPDATE 2
105
106struct drm_amdgpu_bo_list_in {
107
108 uint32_t operation;
109
110 uint32_t list_handle;
111
112 uint32_t bo_number;
113
114 uint32_t bo_info_size;
115
116 uint64_t bo_info_ptr;
117};
118
119struct drm_amdgpu_bo_list_entry {
120
121 uint32_t bo_handle;
122
123 uint32_t bo_priority;
124};
125
126struct drm_amdgpu_bo_list_out {
127
128 uint32_t list_handle;
129 uint32_t _pad;
130};
131
132union drm_amdgpu_bo_list {
133 struct drm_amdgpu_bo_list_in in;
134 struct drm_amdgpu_bo_list_out out;
135};
136
137
138#define AMDGPU_CTX_OP_ALLOC_CTX 1
139#define AMDGPU_CTX_OP_FREE_CTX 2
140#define AMDGPU_CTX_OP_QUERY_STATE 3
141
142
143#define AMDGPU_CTX_NO_RESET 0
144
145#define AMDGPU_CTX_GUILTY_RESET 1
146
147#define AMDGPU_CTX_INNOCENT_RESET 2
148
149#define AMDGPU_CTX_UNKNOWN_RESET 3
150
151struct drm_amdgpu_ctx_in {
152
153 uint32_t op;
154
155 uint32_t flags;
156 uint32_t ctx_id;
157 uint32_t _pad;
158};
159
160union drm_amdgpu_ctx_out {
161 struct {
162 uint32_t ctx_id;
163 uint32_t _pad;
164 } alloc;
165
166 struct {
167
168 uint64_t flags;
169
170 uint32_t hangs;
171
172 uint32_t reset_status;
173 } state;
174};
175
176union drm_amdgpu_ctx {
177 struct drm_amdgpu_ctx_in in;
178 union drm_amdgpu_ctx_out out;
179};
180
181
182
183
184
185
186#define AMDGPU_GEM_USERPTR_READONLY (1 << 0)
187#define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1)
188#define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2)
189#define AMDGPU_GEM_USERPTR_REGISTER (1 << 3)
190
191struct drm_amdgpu_gem_userptr {
192 uint64_t addr;
193 uint64_t size;
194
195 uint32_t flags;
196
197 uint32_t handle;
198};
199
200
201#define AMDGPU_TILING_ARRAY_MODE_SHIFT 0
202#define AMDGPU_TILING_ARRAY_MODE_MASK 0xf
203#define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4
204#define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f
205#define AMDGPU_TILING_TILE_SPLIT_SHIFT 9
206#define AMDGPU_TILING_TILE_SPLIT_MASK 0x7
207#define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12
208#define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7
209#define AMDGPU_TILING_BANK_WIDTH_SHIFT 15
210#define AMDGPU_TILING_BANK_WIDTH_MASK 0x3
211#define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17
212#define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3
213#define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19
214#define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3
215#define AMDGPU_TILING_NUM_BANKS_SHIFT 21
216#define AMDGPU_TILING_NUM_BANKS_MASK 0x3
217
218#define AMDGPU_TILING_SET(field, value) \
219 (((value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT)
220#define AMDGPU_TILING_GET(value, field) \
221 (((value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK)
222
223#define AMDGPU_GEM_METADATA_OP_SET_METADATA 1
224#define AMDGPU_GEM_METADATA_OP_GET_METADATA 2
225
226
227struct drm_amdgpu_gem_metadata {
228
229 uint32_t handle;
230
231 uint32_t op;
232 struct {
233
234 uint64_t flags;
235
236 uint64_t tiling_info;
237 uint32_t data_size_bytes;
238 uint32_t data[64];
239 } data;
240};
241
242struct drm_amdgpu_gem_mmap_in {
243
244 uint32_t handle;
245 uint32_t _pad;
246};
247
248struct drm_amdgpu_gem_mmap_out {
249
250 uint64_t addr_ptr;
251};
252
253union drm_amdgpu_gem_mmap {
254 struct drm_amdgpu_gem_mmap_in in;
255 struct drm_amdgpu_gem_mmap_out out;
256};
257
258struct drm_amdgpu_gem_wait_idle_in {
259
260 uint32_t handle;
261
262 uint32_t flags;
263
264 uint64_t timeout;
265};
266
267struct drm_amdgpu_gem_wait_idle_out {
268
269 uint32_t status;
270
271 uint32_t domain;
272};
273
274union drm_amdgpu_gem_wait_idle {
275 struct drm_amdgpu_gem_wait_idle_in in;
276 struct drm_amdgpu_gem_wait_idle_out out;
277};
278
279struct drm_amdgpu_wait_cs_in {
280
281 uint64_t handle;
282
283 uint64_t timeout;
284 uint32_t ip_type;
285 uint32_t ip_instance;
286 uint32_t ring;
287 uint32_t ctx_id;
288};
289
290struct drm_amdgpu_wait_cs_out {
291
292 uint64_t status;
293};
294
295union drm_amdgpu_wait_cs {
296 struct drm_amdgpu_wait_cs_in in;
297 struct drm_amdgpu_wait_cs_out out;
298};
299
300#define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0
301#define AMDGPU_GEM_OP_SET_PLACEMENT 1
302
303
304struct drm_amdgpu_gem_op {
305
306 uint32_t handle;
307
308 uint32_t op;
309
310 uint64_t value;
311};
312
313#define AMDGPU_VA_OP_MAP 1
314#define AMDGPU_VA_OP_UNMAP 2
315
316
317#define AMDGPU_VM_DELAY_UPDATE (1 << 0)
318
319
320
321#define AMDGPU_VM_PAGE_READABLE (1 << 1)
322
323#define AMDGPU_VM_PAGE_WRITEABLE (1 << 2)
324
325#define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3)
326
327struct drm_amdgpu_gem_va {
328
329 uint32_t handle;
330 uint32_t _pad;
331
332 uint32_t operation;
333
334 uint32_t flags;
335
336 uint64_t va_address;
337
338 uint64_t offset_in_bo;
339
340 uint64_t map_size;
341};
342
343#define AMDGPU_HW_IP_GFX 0
344#define AMDGPU_HW_IP_COMPUTE 1
345#define AMDGPU_HW_IP_DMA 2
346#define AMDGPU_HW_IP_UVD 3
347#define AMDGPU_HW_IP_VCE 4
348#define AMDGPU_HW_IP_NUM 5
349
350#define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1
351
352#define AMDGPU_CHUNK_ID_IB 0x01
353#define AMDGPU_CHUNK_ID_FENCE 0x02
354#define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03
355
356struct drm_amdgpu_cs_chunk {
357 uint32_t chunk_id;
358 uint32_t length_dw;
359 uint64_t chunk_data;
360};
361
362struct drm_amdgpu_cs_in {
363
364 uint32_t ctx_id;
365
366 uint32_t bo_list_handle;
367 uint32_t num_chunks;
368 uint32_t _pad;
369
370 uint64_t chunks;
371};
372
373struct drm_amdgpu_cs_out {
374 uint64_t handle;
375};
376
377union drm_amdgpu_cs {
378 struct drm_amdgpu_cs_in in;
379 struct drm_amdgpu_cs_out out;
380};
381
382
383
384
385#define AMDGPU_IB_FLAG_CE (1<<0)
386
387
388#define AMDGPU_IB_FLAG_PREAMBLE (1<<1)
389
390struct drm_amdgpu_cs_chunk_ib {
391 uint32_t _pad;
392
393 uint32_t flags;
394
395 uint64_t va_start;
396
397 uint32_t ib_bytes;
398
399 uint32_t ip_type;
400
401 uint32_t ip_instance;
402
403 uint32_t ring;
404};
405
406struct drm_amdgpu_cs_chunk_dep {
407 uint32_t ip_type;
408 uint32_t ip_instance;
409 uint32_t ring;
410 uint32_t ctx_id;
411 uint64_t handle;
412};
413
414struct drm_amdgpu_cs_chunk_fence {
415 uint32_t handle;
416 uint32_t offset;
417};
418
419struct drm_amdgpu_cs_chunk_data {
420 union {
421 struct drm_amdgpu_cs_chunk_ib ib_data;
422 struct drm_amdgpu_cs_chunk_fence fence_data;
423 };
424};
425
426
427
428
429
430#define AMDGPU_IDS_FLAGS_FUSION 0x1
431
432
433#define AMDGPU_INFO_ACCEL_WORKING 0x00
434
435#define AMDGPU_INFO_CRTC_FROM_ID 0x01
436
437#define AMDGPU_INFO_HW_IP_INFO 0x02
438
439#define AMDGPU_INFO_HW_IP_COUNT 0x03
440
441#define AMDGPU_INFO_TIMESTAMP 0x05
442
443#define AMDGPU_INFO_FW_VERSION 0x0e
444
445 #define AMDGPU_INFO_FW_VCE 0x1
446
447 #define AMDGPU_INFO_FW_UVD 0x2
448
449 #define AMDGPU_INFO_FW_GMC 0x03
450
451 #define AMDGPU_INFO_FW_GFX_ME 0x04
452
453 #define AMDGPU_INFO_FW_GFX_PFP 0x05
454
455 #define AMDGPU_INFO_FW_GFX_CE 0x06
456
457 #define AMDGPU_INFO_FW_GFX_RLC 0x07
458
459 #define AMDGPU_INFO_FW_GFX_MEC 0x08
460
461 #define AMDGPU_INFO_FW_SMC 0x0a
462
463 #define AMDGPU_INFO_FW_SDMA 0x0b
464
465#define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f
466
467#define AMDGPU_INFO_VRAM_USAGE 0x10
468
469#define AMDGPU_INFO_GTT_USAGE 0x11
470
471#define AMDGPU_INFO_GDS_CONFIG 0x13
472
473#define AMDGPU_INFO_VRAM_GTT 0x14
474
475#define AMDGPU_INFO_READ_MMR_REG 0x15
476
477#define AMDGPU_INFO_DEV_INFO 0x16
478
479#define AMDGPU_INFO_VIS_VRAM_USAGE 0x17
480
481#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
482#define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
483#define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8
484#define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff
485
486
487struct drm_amdgpu_info {
488
489 uint64_t return_pointer;
490
491
492 uint32_t return_size;
493
494 uint32_t query;
495
496 union {
497 struct {
498 uint32_t id;
499 uint32_t _pad;
500 } mode_crtc;
501
502 struct {
503
504 uint32_t type;
505
506
507
508
509 uint32_t ip_instance;
510 } query_hw_ip;
511
512 struct {
513 uint32_t dword_offset;
514
515 uint32_t count;
516 uint32_t instance;
517
518 uint32_t flags;
519 } read_mmr_reg;
520
521 struct {
522
523 uint32_t fw_type;
524
525
526
527
528 uint32_t ip_instance;
529
530
531
532
533 uint32_t index;
534 uint32_t _pad;
535 } query_fw;
536 };
537};
538
539struct drm_amdgpu_info_gds {
540
541 uint32_t gds_gfx_partition_size;
542
543 uint32_t compute_partition_size;
544
545 uint32_t gds_total_size;
546
547 uint32_t gws_per_gfx_partition;
548
549 uint32_t gws_per_compute_partition;
550
551 uint32_t oa_per_gfx_partition;
552
553 uint32_t oa_per_compute_partition;
554 uint32_t _pad;
555};
556
557struct drm_amdgpu_info_vram_gtt {
558 uint64_t vram_size;
559 uint64_t vram_cpu_accessible_size;
560 uint64_t gtt_size;
561};
562
563struct drm_amdgpu_info_firmware {
564 uint32_t ver;
565 uint32_t feature;
566};
567
568#define AMDGPU_VRAM_TYPE_UNKNOWN 0
569#define AMDGPU_VRAM_TYPE_GDDR1 1
570#define AMDGPU_VRAM_TYPE_DDR2 2
571#define AMDGPU_VRAM_TYPE_GDDR3 3
572#define AMDGPU_VRAM_TYPE_GDDR4 4
573#define AMDGPU_VRAM_TYPE_GDDR5 5
574#define AMDGPU_VRAM_TYPE_HBM 6
575#define AMDGPU_VRAM_TYPE_DDR3 7
576
577struct drm_amdgpu_info_device {
578
579 uint32_t device_id;
580
581 uint32_t chip_rev;
582 uint32_t external_rev;
583
584 uint32_t pci_rev;
585 uint32_t family;
586 uint32_t num_shader_engines;
587 uint32_t num_shader_arrays_per_engine;
588
589 uint32_t gpu_counter_freq;
590 uint64_t max_engine_clock;
591 uint64_t max_memory_clock;
592
593 uint32_t cu_active_number;
594 uint32_t cu_ao_mask;
595 uint32_t cu_bitmap[4][4];
596
597 uint32_t enabled_rb_pipes_mask;
598 uint32_t num_rb_pipes;
599 uint32_t num_hw_gfx_contexts;
600 uint32_t _pad;
601 uint64_t ids_flags;
602
603 uint64_t virtual_address_offset;
604
605 uint64_t virtual_address_max;
606
607 uint32_t virtual_address_alignment;
608
609 uint32_t pte_fragment_size;
610 uint32_t gart_page_size;
611
612 uint32_t ce_ram_size;
613
614 uint32_t vram_type;
615
616 uint32_t vram_bit_width;
617
618 uint32_t vce_harvest_config;
619};
620
621struct drm_amdgpu_info_hw_ip {
622
623 uint32_t hw_ip_version_major;
624 uint32_t hw_ip_version_minor;
625
626 uint64_t capabilities_flags;
627
628 uint32_t ib_start_alignment;
629
630 uint32_t ib_size_alignment;
631
632 uint32_t available_rings;
633 uint32_t _pad;
634};
635
636
637
638
639#define AMDGPU_FAMILY_UNKNOWN 0
640#define AMDGPU_FAMILY_CI 120
641#define AMDGPU_FAMILY_KV 125
642#define AMDGPU_FAMILY_VI 130
643#define AMDGPU_FAMILY_CZ 135
644
645#endif
646