linux/sound/pci/au88x0/au8810.h
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   1/*
   2    Aureal Advantage Soundcard driver.
   3 */
   4
   5#define CHIP_AU8810
   6
   7#define CARD_NAME "Aureal Advantage"
   8#define CARD_NAME_SHORT "au8810"
   9
  10#define NR_ADB          0x10
  11#define NR_WT           0x00
  12#define NR_SRC          0x10
  13#define NR_A3D          0x10
  14#define NR_MIXIN        0x20
  15#define NR_MIXOUT       0x10
  16
  17
  18/* ADBDMA */
  19#define VORTEX_ADBDMA_STAT 0x27e00      /* read only, subbuffer, DMA pos */
  20#define         POS_MASK 0x00000fff
  21#define     POS_SHIFT 0x0
  22#define         ADB_SUBBUF_MASK 0x00003000      /* ADB only. */
  23#define     ADB_SUBBUF_SHIFT 0xc        /* ADB only. */
  24#define VORTEX_ADBDMA_CTRL 0x27180      /* write only; format, flags, DMA pos */
  25#define         OFFSET_MASK 0x00000fff
  26#define     OFFSET_SHIFT 0x0
  27#define         IE_MASK 0x00001000      /* interrupt enable. */
  28#define     IE_SHIFT 0xc
  29#define     DIR_MASK 0x00002000 /* Direction */
  30#define     DIR_SHIFT 0xd
  31#define         FMT_MASK 0x0003c000
  32#define         FMT_SHIFT 0xe
  33// The ADB masks and shift also are valid for the wtdma, except if specified otherwise.
  34#define VORTEX_ADBDMA_BUFCFG0 0x27100
  35#define VORTEX_ADBDMA_BUFCFG1 0x27104
  36#define VORTEX_ADBDMA_BUFBASE 0x27000
  37#define VORTEX_ADBDMA_START 0x27c00     /* Which subbuffer starts */
  38
  39#define VORTEX_ADBDMA_STATUS 0x27A90    /* stored at AdbDma->this_10 / 2 DWORD in size. */
  40
  41/* WTDMA */
  42#define VORTEX_WTDMA_CTRL 0x27fd8       /* format, DMA pos */
  43#define VORTEX_WTDMA_STAT 0x27fe8       /* DMA subbuf, DMA pos */
  44#define     WT_SUBBUF_MASK 0x3
  45#define     WT_SUBBUF_SHIFT 0xc
  46#define VORTEX_WTDMA_BUFBASE 0x27fc0
  47#define VORTEX_WTDMA_BUFCFG0 0x27fd0
  48#define VORTEX_WTDMA_BUFCFG1 0x27fd4
  49#define VORTEX_WTDMA_START 0x27fe4      /* which subbuffer is first */
  50
  51/* ADB */
  52#define VORTEX_ADB_SR 0x28400   /* Samplerates enable/disable */
  53#define VORTEX_ADB_RTBASE 0x28000
  54#define VORTEX_ADB_RTBASE_COUNT 173
  55#define VORTEX_ADB_CHNBASE 0x282b4
  56#define VORTEX_ADB_CHNBASE_COUNT 24
  57#define         ROUTE_MASK      0xffff
  58#define         SOURCE_MASK     0xff00
  59#define     ADB_MASK   0xff
  60#define         ADB_SHIFT 0x8
  61
  62/* ADB address */
  63#define         OFFSET_ADBDMA   0x00
  64#define         OFFSET_SRCIN    0x40
  65#define         OFFSET_SRCOUT   0x20
  66#define         OFFSET_MIXIN    0x50
  67#define         OFFSET_MIXOUT   0x30
  68#define         OFFSET_CODECIN  0x70
  69#define         OFFSET_CODECOUT 0x88
  70#define         OFFSET_SPORTIN  0x78    /* ch 0x13 */
  71#define         OFFSET_SPORTOUT 0x90
  72#define         OFFSET_SPDIFOUT 0x92    /* ch 0x14 check this! */
  73#define         OFFSET_EQIN     0xa0
  74#define         OFFSET_EQOUT    0x7e    /* 2 routes on ch 0x11 */
  75#define         OFFSET_XTALKOUT 0x66    /* crosstalk canceller (source) */
  76#define         OFFSET_XTALKIN  0x96    /* crosstalk canceller (sink) */
  77#define         OFFSET_A3DIN    0x70    /* ADB sink. */
  78#define         OFFSET_A3DOUT   0xA6    /* ADB source. 2 routes per slice = 8 */
  79#define         OFFSET_EFXIN    0x80    /* ADB sink. */
  80#define         OFFSET_EFXOUT   0x68    /* ADB source. */
  81
  82/* ADB route translate helper */
  83#define ADB_DMA(x) (x)
  84#define ADB_SRCOUT(x) (x + OFFSET_SRCOUT)
  85#define ADB_SRCIN(x) (x + OFFSET_SRCIN)
  86#define ADB_MIXOUT(x) (x + OFFSET_MIXOUT)
  87#define ADB_MIXIN(x) (x + OFFSET_MIXIN)
  88#define ADB_CODECIN(x) (x + OFFSET_CODECIN)
  89#define ADB_CODECOUT(x) (x + OFFSET_CODECOUT)
  90#define ADB_SPORTIN(x) (x + OFFSET_SPORTIN)
  91#define ADB_SPORTOUT(x) (x + OFFSET_SPORTOUT)
  92#define ADB_SPDIFOUT(x) (x + OFFSET_SPDIFOUT)
  93#define ADB_EQIN(x) (x + OFFSET_EQIN)
  94#define ADB_EQOUT(x) (x + OFFSET_EQOUT)
  95#define ADB_A3DOUT(x) (x + OFFSET_A3DOUT)       /* 0x10 A3D blocks */
  96#define ADB_A3DIN(x) (x + OFFSET_A3DIN)
  97#define ADB_XTALKIN(x) (x + OFFSET_XTALKIN)
  98#define ADB_XTALKOUT(x) (x + OFFSET_XTALKOUT)
  99
 100#define MIX_OUTL    0xe
 101#define MIX_OUTR    0xf
 102#define MIX_INL     0x1e
 103#define MIX_INR     0x1f
 104#define MIX_DEFIGAIN 0x08       /* 0x8 => 6dB */
 105#define MIX_DEFOGAIN 0x08
 106
 107/* MIXER */
 108#define VORTEX_MIXER_SR 0x21f00
 109#define VORTEX_MIXER_CLIP 0x21f80
 110#define VORTEX_MIXER_CHNBASE 0x21e40
 111#define VORTEX_MIXER_RTBASE 0x21e00
 112#define         MIXER_RTBASE_SIZE 0x38
 113#define VORTEX_MIX_ENIN 0x21a00 /* Input enable bits. 4 bits wide. */
 114#define VORTEX_MIX_SMP 0x21c00  /* AU8820: 0x9c00 */
 115
 116/* MIX */
 117#define VORTEX_MIX_INVOL_A 0x21000      /* in? */
 118#define VORTEX_MIX_INVOL_B 0x20000      /* out? */
 119#define VORTEX_MIX_VOL_A 0x21800
 120#define VORTEX_MIX_VOL_B 0x20800
 121
 122#define         VOL_MIN 0x80    /* Input volume when muted. */
 123#define         VOL_MAX 0x7f    /* FIXME: Not confirmed! Just guessed. */
 124
 125/* SRC */
 126#define VORTEX_SRC_CHNBASE              0x26c40
 127#define VORTEX_SRC_RTBASE               0x26c00
 128#define VORTEX_SRCBLOCK_SR              0x26cc0
 129#define VORTEX_SRC_SOURCE               0x26cc4
 130#define VORTEX_SRC_SOURCESIZE   0x26cc8
 131/* Params
 132        0x26e00 : 1 U0
 133        0x26e40 : 2 CR
 134        0x26e80 : 3 U3
 135        0x26ec0 : 4 DRIFT1
 136        0x26f00 : 5 U1
 137        0x26f40 : 6 DRIFT2
 138        0x26f80 : 7 U2 : Target rate, direction
 139*/
 140
 141#define VORTEX_SRC_CONVRATIO    0x26e40
 142#define VORTEX_SRC_DRIFT0               0x26e80
 143#define VORTEX_SRC_DRIFT1               0x26ec0
 144#define VORTEX_SRC_DRIFT2               0x26f40
 145#define VORTEX_SRC_U0                   0x26e00
 146#define         U0_SLOWLOCK             0x200
 147#define VORTEX_SRC_U1                   0x26f00
 148#define VORTEX_SRC_U2                   0x26f80
 149#define VORTEX_SRC_DATA                 0x26800 /* 0xc800 */
 150#define VORTEX_SRC_DATA0                0x26000
 151
 152/* FIFO */
 153#define VORTEX_FIFO_ADBCTRL 0x16100     /* Control bits. */
 154#define VORTEX_FIFO_WTCTRL 0x16000
 155#define         FIFO_RDONLY     0x00000001
 156#define         FIFO_CTRL       0x00000002      /* Allow ctrl. ? */
 157#define         FIFO_VALID      0x00000010
 158#define         FIFO_EMPTY      0x00000020
 159#define         FIFO_U0         0x00001000      /* Unknown. */
 160#define         FIFO_U1         0x00010000
 161#define         FIFO_SIZE_BITS 5
 162#define         FIFO_SIZE       (1<<FIFO_SIZE_BITS)     // 0x20
 163#define         FIFO_MASK       (FIFO_SIZE-1)   //0x1f    /* at shift left 0xc */
 164//#define       FIFO_MASK       0x1f    /* at shift left 0xb */
 165//#define               FIFO_SIZE       0x20
 166#define         FIFO_BITS       0x03880000
 167#define VORTEX_FIFO_ADBDATA     0x14000
 168#define VORTEX_FIFO_WTDATA      0x10000
 169
 170/* CODEC */
 171#define VORTEX_CODEC_CTRL       0x29184
 172#define VORTEX_CODEC_EN         0x29190
 173#define         EN_CODEC0       0x00000300
 174#define         EN_AC98         0x00000c00 /* Modem AC98 slots. */
 175#define         EN_CODEC1       0x00003000
 176#define         EN_CODEC        (EN_CODEC0 | EN_CODEC1)
 177#define         EN_SPORT        0x00030000
 178#define         EN_SPDIF        0x000c0000
 179
 180#define VORTEX_CODEC_CHN        0x29080
 181#define VORTEX_CODEC_IO         0x29188
 182
 183/* SPDIF */
 184#define VORTEX_SPDIF_FLAGS      0x2205c
 185#define VORTEX_SPDIF_CFG0       0x291D0
 186#define VORTEX_SPDIF_CFG1       0x291D4
 187#define VORTEX_SPDIF_SMPRATE    0x29194
 188
 189/* Sample timer */
 190#define VORTEX_SMP_TIME         0x29198
 191
 192#define VORTEX_MODEM_CTRL       0x291ac
 193
 194/* IRQ */
 195#define VORTEX_IRQ_SOURCE 0x2a000       /* Interrupt source flags. */
 196#define VORTEX_IRQ_CTRL 0x2a004 /* Interrupt source mask. */
 197
 198#define VORTEX_STAT     0x2a008 /* Status */
 199
 200#define VORTEX_CTRL             0x2a00c
 201#define         CTRL_MIDI_EN    0x00000001
 202#define         CTRL_MIDI_PORT  0x00000060
 203#define         CTRL_GAME_EN    0x00000008
 204#define         CTRL_GAME_PORT  0x00000e00
 205//#define       CTRL_IRQ_ENABLE 0x01004000
 206#define         CTRL_IRQ_ENABLE 0x00004000
 207
 208/* write: Timer period config / read: TIMER IRQ ack. */
 209#define VORTEX_IRQ_STAT         0x2919c
 210
 211/* DMA */
 212#define VORTEX_ENGINE_CTRL      0x27ae8
 213#define         ENGINE_INIT     0x1380000
 214
 215/* MIDI *//* GAME. */
 216#define VORTEX_MIDI_DATA        0x28800
 217#define VORTEX_MIDI_CMD         0x28804 /* Write command / Read status */
 218
 219#define VORTEX_CTRL2            0x2880c
 220#define         CTRL2_GAME_ADCMODE 0x40
 221#define VORTEX_GAME_LEGACY      0x28808
 222#define VORTEX_GAME_AXIS        0x28810
 223#define         AXIS_SIZE 4
 224#define         AXIS_RANGE 0x1fff
 225