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8
9#ifndef _DEF_LPBLACKFIN_H
10#define _DEF_LPBLACKFIN_H
11
12#include <mach/anomaly.h>
13
14#define MK_BMSK_(x) (1<<x)
15#define BFIN_DEPOSIT(mask, x) (((x) << __ffs(mask)) & (mask))
16#define BFIN_EXTRACT(mask, x) (((x) & (mask)) >> __ffs(mask))
17
18#ifndef __ASSEMBLY__
19
20#include <linux/types.h>
21
22#if ANOMALY_05000198
23# define NOP_PAD_ANOMALY_05000198 "nop;"
24#else
25# define NOP_PAD_ANOMALY_05000198
26#endif
27
28#define _bfin_readX(addr, size, asm_size, asm_ext) ({ \
29 u32 __v; \
30 __asm__ __volatile__( \
31 NOP_PAD_ANOMALY_05000198 \
32 "%0 = " #asm_size "[%1]" #asm_ext ";" \
33 : "=d" (__v) \
34 : "a" (addr) \
35 ); \
36 __v; })
37#define _bfin_writeX(addr, val, size, asm_size) \
38 __asm__ __volatile__( \
39 NOP_PAD_ANOMALY_05000198 \
40 #asm_size "[%0] = %1;" \
41 : \
42 : "a" (addr), "d" ((u##size)(val)) \
43 : "memory" \
44 )
45
46#define bfin_read8(addr) _bfin_readX(addr, 8, b, (z))
47#define bfin_read16(addr) _bfin_readX(addr, 16, w, (z))
48#define bfin_read32(addr) _bfin_readX(addr, 32, , )
49#define bfin_write8(addr, val) _bfin_writeX(addr, val, 8, b)
50#define bfin_write16(addr, val) _bfin_writeX(addr, val, 16, w)
51#define bfin_write32(addr, val) _bfin_writeX(addr, val, 32, )
52
53#define bfin_read(addr) \
54({ \
55 sizeof(*(addr)) == 1 ? bfin_read8(addr) : \
56 sizeof(*(addr)) == 2 ? bfin_read16(addr) : \
57 sizeof(*(addr)) == 4 ? bfin_read32(addr) : \
58 ({ BUG(); 0; }); \
59})
60#define bfin_write(addr, val) \
61do { \
62 switch (sizeof(*(addr))) { \
63 case 1: bfin_write8(addr, val); break; \
64 case 2: bfin_write16(addr, val); break; \
65 case 4: bfin_write32(addr, val); break; \
66 default: BUG(); \
67 } \
68} while (0)
69
70#define bfin_write_or(addr, bits) \
71do { \
72 typeof(addr) __addr = (addr); \
73 bfin_write(__addr, bfin_read(__addr) | (bits)); \
74} while (0)
75
76#define bfin_write_and(addr, bits) \
77do { \
78 typeof(addr) __addr = (addr); \
79 bfin_write(__addr, bfin_read(__addr) & (bits)); \
80} while (0)
81
82#endif
83
84
85
86
87
88
89
90
91
92
93
94
95#define ASTAT_AZ_P 0x00000000
96
97#define ASTAT_AN_P 0x00000001
98
99#define ASTAT_CC_P 0x00000005
100
101#define ASTAT_AQ_P 0x00000006
102
103#define ASTAT_RND_MOD_P 0x00000008
104
105#define ASTAT_AC0_P 0x0000000C
106
107#define ASTAT_AC0_COPY_P 0x00000002
108
109#define ASTAT_AC1_P 0x0000000D
110
111#define ASTAT_AV0_P 0x00000010
112
113#define ASTAT_AV0S_P 0x00000011
114
115#define ASTAT_AV1_P 0x00000012
116
117#define ASTAT_AV1S_P 0x00000013
118
119#define ASTAT_V_P 0x00000018
120
121#define ASTAT_V_COPY_P 0x00000003
122
123#define ASTAT_VS_P 0x00000019
124
125
126
127
128#define ASTAT_AZ MK_BMSK_(ASTAT_AZ_P)
129
130#define ASTAT_AN MK_BMSK_(ASTAT_AN_P)
131
132#define ASTAT_AC0 MK_BMSK_(ASTAT_AC0_P)
133
134#define ASTAT_AC0_COPY MK_BMSK_(ASTAT_AC0_COPY_P)
135
136#define ASTAT_AC1 MK_BMSK_(ASTAT_AC1_P)
137
138#define ASTAT_AV0 MK_BMSK_(ASTAT_AV0_P)
139
140#define ASTAT_AV1 MK_BMSK_(ASTAT_AV1_P)
141
142#define ASTAT_CC MK_BMSK_(ASTAT_CC_P)
143
144#define ASTAT_AQ MK_BMSK_(ASTAT_AQ_P)
145
146#define ASTAT_RND_MOD MK_BMSK_(ASTAT_RND_MOD_P)
147
148#define ASTAT_V MK_BMSK_(ASTAT_V_P)
149
150#define ASTAT_V_COPY MK_BMSK_(ASTAT_V_COPY_P)
151
152
153
154
155
156
157#define SEQSTAT_EXCAUSE0_P 0x00000000
158#define SEQSTAT_EXCAUSE1_P 0x00000001
159#define SEQSTAT_EXCAUSE2_P 0x00000002
160#define SEQSTAT_EXCAUSE3_P 0x00000003
161#define SEQSTAT_EXCAUSE4_P 0x00000004
162#define SEQSTAT_EXCAUSE5_P 0x00000005
163#define SEQSTAT_IDLE_REQ_P 0x0000000C
164
165
166#define SEQSTAT_SFTRESET_P 0x0000000D
167
168
169
170#define SEQSTAT_HWERRCAUSE0_P 0x0000000E
171#define SEQSTAT_HWERRCAUSE1_P 0x0000000F
172#define SEQSTAT_HWERRCAUSE2_P 0x00000010
173#define SEQSTAT_HWERRCAUSE3_P 0x00000011
174#define SEQSTAT_HWERRCAUSE4_P 0x00000012
175
176
177#define SEQSTAT_EXCAUSE (MK_BMSK_(SEQSTAT_EXCAUSE0_P) | \
178 MK_BMSK_(SEQSTAT_EXCAUSE1_P) | \
179 MK_BMSK_(SEQSTAT_EXCAUSE2_P) | \
180 MK_BMSK_(SEQSTAT_EXCAUSE3_P) | \
181 MK_BMSK_(SEQSTAT_EXCAUSE4_P) | \
182 MK_BMSK_(SEQSTAT_EXCAUSE5_P) | \
183 0)
184
185
186#define SEQSTAT_SFTRESET (MK_BMSK_(SEQSTAT_SFTRESET_P))
187
188
189#define SEQSTAT_HWERRCAUSE (MK_BMSK_(SEQSTAT_HWERRCAUSE0_P) | \
190 MK_BMSK_(SEQSTAT_HWERRCAUSE1_P) | \
191 MK_BMSK_(SEQSTAT_HWERRCAUSE2_P) | \
192 MK_BMSK_(SEQSTAT_HWERRCAUSE3_P) | \
193 MK_BMSK_(SEQSTAT_HWERRCAUSE4_P) | \
194 0)
195
196
197
198
199#define SEQSTAT_HWERRCAUSE_SHIFT (14)
200#define SEQSTAT_HWERRCAUSE_SYSTEM_MMR (0x02 << SEQSTAT_HWERRCAUSE_SHIFT)
201#define SEQSTAT_HWERRCAUSE_EXTERN_ADDR (0x03 << SEQSTAT_HWERRCAUSE_SHIFT)
202#define SEQSTAT_HWERRCAUSE_PERF_FLOW (0x12 << SEQSTAT_HWERRCAUSE_SHIFT)
203#define SEQSTAT_HWERRCAUSE_RAISE_5 (0x18 << SEQSTAT_HWERRCAUSE_SHIFT)
204
205
206
207
208
209
210#define SYSCFG_SSSTEP_P 0x00000000
211
212
213
214#define SYSCFG_CCEN_P 0x00000001
215#define SYSCFG_SNEN_P 0x00000002
216
217
218
219
220
221
222#define SYSCFG_SSSTEP MK_BMSK_(SYSCFG_SSSTEP_P )
223
224#define SYSCFG_CCEN MK_BMSK_(SYSCFG_CCEN_P )
225
226#define SYSCFG_SNEN MK_BMSK_(SYSCFG_SNEN_P)
227
228#define SYSCFG_SSSSTEP SYSCFG_SSSTEP
229#define SYSCFG_CCCEN SYSCFG_CCEN
230
231
232
233
234
235
236
237#define SRAM_BASE_ADDRESS 0xFFE00000
238#define DMEM_CONTROL 0xFFE00004
239#define DCPLB_STATUS 0xFFE00008
240
241
242#define DCPLB_FAULT_STATUS 0xFFE00008
243#define DCPLB_FAULT_ADDR 0xFFE0000C
244
245
246#define DCPLB_ADDR0 0xFFE00100
247
248
249#define DCPLB_ADDR1 0xFFE00104
250
251
252#define DCPLB_ADDR2 0xFFE00108
253
254
255#define DCPLB_ADDR3 0xFFE0010C
256
257
258#define DCPLB_ADDR4 0xFFE00110
259
260
261#define DCPLB_ADDR5 0xFFE00114
262
263
264#define DCPLB_ADDR6 0xFFE00118
265
266
267#define DCPLB_ADDR7 0xFFE0011C
268
269
270#define DCPLB_ADDR8 0xFFE00120
271
272
273#define DCPLB_ADDR9 0xFFE00124
274
275
276#define DCPLB_ADDR10 0xFFE00128
277
278
279#define DCPLB_ADDR11 0xFFE0012C
280
281
282#define DCPLB_ADDR12 0xFFE00130
283
284
285#define DCPLB_ADDR13 0xFFE00134
286
287
288#define DCPLB_ADDR14 0xFFE00138
289
290
291#define DCPLB_ADDR15 0xFFE0013C
292
293
294#define DCPLB_DATA0 0xFFE00200
295#define DCPLB_DATA1 0xFFE00204
296#define DCPLB_DATA2 0xFFE00208
297#define DCPLB_DATA3 0xFFE0020C
298#define DCPLB_DATA4 0xFFE00210
299#define DCPLB_DATA5 0xFFE00214
300#define DCPLB_DATA6 0xFFE00218
301#define DCPLB_DATA7 0xFFE0021C
302#define DCPLB_DATA8 0xFFE00220
303#define DCPLB_DATA9 0xFFE00224
304#define DCPLB_DATA10 0xFFE00228
305#define DCPLB_DATA11 0xFFE0022C
306#define DCPLB_DATA12 0xFFE00230
307#define DCPLB_DATA13 0xFFE00234
308#define DCPLB_DATA14 0xFFE00238
309#define DCPLB_DATA15 0xFFE0023C
310#define DCPLB_DATA16 0xFFE00240
311
312#define DTEST_COMMAND 0xFFE00300
313#define DTEST_DATA0 0xFFE00400
314#define DTEST_DATA1 0xFFE00404
315
316
317
318#define IMEM_CONTROL 0xFFE01004
319#define ICPLB_STATUS 0xFFE01008
320#define CODE_FAULT_STATUS 0xFFE01008
321#define ICPLB_FAULT_ADDR 0xFFE0100C
322#define CODE_FAULT_ADDR 0xFFE0100C
323#define ICPLB_ADDR0 0xFFE01100
324
325
326#define ICPLB_ADDR1 0xFFE01104
327
328
329#define ICPLB_ADDR2 0xFFE01108
330
331
332#define ICPLB_ADDR3 0xFFE0110C
333
334
335#define ICPLB_ADDR4 0xFFE01110
336
337
338#define ICPLB_ADDR5 0xFFE01114
339
340
341#define ICPLB_ADDR6 0xFFE01118
342
343
344#define ICPLB_ADDR7 0xFFE0111C
345
346
347#define ICPLB_ADDR8 0xFFE01120
348
349
350#define ICPLB_ADDR9 0xFFE01124
351
352
353#define ICPLB_ADDR10 0xFFE01128
354
355
356#define ICPLB_ADDR11 0xFFE0112C
357
358
359#define ICPLB_ADDR12 0xFFE01130
360
361
362#define ICPLB_ADDR13 0xFFE01134
363
364
365#define ICPLB_ADDR14 0xFFE01138
366
367
368#define ICPLB_ADDR15 0xFFE0113C
369
370
371#define ICPLB_DATA0 0xFFE01200
372#define ICPLB_DATA1 0xFFE01204
373#define ICPLB_DATA2 0xFFE01208
374#define ICPLB_DATA3 0xFFE0120C
375#define ICPLB_DATA4 0xFFE01210
376#define ICPLB_DATA5 0xFFE01214
377#define ICPLB_DATA6 0xFFE01218
378#define ICPLB_DATA7 0xFFE0121C
379#define ICPLB_DATA8 0xFFE01220
380#define ICPLB_DATA9 0xFFE01224
381#define ICPLB_DATA10 0xFFE01228
382#define ICPLB_DATA11 0xFFE0122C
383#define ICPLB_DATA12 0xFFE01230
384#define ICPLB_DATA13 0xFFE01234
385#define ICPLB_DATA14 0xFFE01238
386#define ICPLB_DATA15 0xFFE0123C
387#define ITEST_COMMAND 0xFFE01300
388#define ITEST_DATA0 0xFFE01400
389#define ITEST_DATA1 0xFFE01404
390
391
392
393#define EVT0 0xFFE02000
394#define EVT1 0xFFE02004
395#define EVT2 0xFFE02008
396#define EVT3 0xFFE0200C
397#define EVT4 0xFFE02010
398#define EVT5 0xFFE02014
399#define EVT6 0xFFE02018
400#define EVT7 0xFFE0201C
401#define EVT8 0xFFE02020
402#define EVT9 0xFFE02024
403#define EVT10 0xFFE02028
404#define EVT11 0xFFE0202C
405#define EVT12 0xFFE02030
406#define EVT13 0xFFE02034
407#define EVT14 0xFFE02038
408#define EVT15 0xFFE0203C
409#define EVT_OVERRIDE 0xFFE02100
410#define IMASK 0xFFE02104
411#define IPEND 0xFFE02108
412#define ILAT 0xFFE0210C
413#define IPRIO 0xFFE02110
414
415
416
417#define TCNTL 0xFFE03000
418#define TPERIOD 0xFFE03004
419#define TSCALE 0xFFE03008
420#define TCOUNT 0xFFE0300C
421
422
423#define DSPID 0xFFE05000
424
425
426
427#define DBGSTAT 0xFFE05008
428
429
430
431#define TBUFCTL 0xFFE06000
432#define TBUFSTAT 0xFFE06004
433#define TBUF 0xFFE06100
434
435
436
437
438#define WPIACTL 0xFFE07000
439
440#define WPIA0 0xFFE07040
441
442#define WPIA1 0xFFE07044
443
444#define WPIA2 0xFFE07048
445
446#define WPIA3 0xFFE0704C
447
448#define WPIA4 0xFFE07050
449
450#define WPIA5 0xFFE07054
451
452#define WPIACNT0 0xFFE07080
453
454#define WPIACNT1 0xFFE07084
455
456#define WPIACNT2 0xFFE07088
457
458#define WPIACNT3 0xFFE0708C
459
460#define WPIACNT4 0xFFE07090
461
462#define WPIACNT5 0xFFE07094
463
464#define WPDACTL 0xFFE07100
465
466#define WPDA0 0xFFE07140
467
468#define WPDA1 0xFFE07144
469
470#define WPDACNT0 0xFFE07180
471
472#define WPDACNT1 0xFFE07184
473
474#define WPSTAT 0xFFE07200
475
476
477
478
479#define PFCTL 0xFFE08000
480
481#define PFCNTR0 0xFFE08100
482
483#define PFCNTR1 0xFFE08104
484
485
486
487
488
489
490
491
492
493
494#define EVT_EMU_P 0x00000000
495#define EVT_RST_P 0x00000001
496#define EVT_NMI_P 0x00000002
497#define EVT_EVX_P 0x00000003
498#define EVT_IRPTEN_P 0x00000004
499#define EVT_IVHW_P 0x00000005
500#define EVT_IVTMR_P 0x00000006
501#define EVT_IVG7_P 0x00000007
502#define EVT_IVG8_P 0x00000008
503#define EVT_IVG9_P 0x00000009
504#define EVT_IVG10_P 0x0000000a
505#define EVT_IVG11_P 0x0000000b
506#define EVT_IVG12_P 0x0000000c
507#define EVT_IVG13_P 0x0000000d
508#define EVT_IVG14_P 0x0000000e
509#define EVT_IVG15_P 0x0000000f
510
511
512#define EVT_EMU MK_BMSK_(EVT_EMU_P )
513#define EVT_RST MK_BMSK_(EVT_RST_P )
514#define EVT_NMI MK_BMSK_(EVT_NMI_P )
515#define EVT_EVX MK_BMSK_(EVT_EVX_P )
516#define EVT_IRPTEN MK_BMSK_(EVT_IRPTEN_P)
517#define EVT_IVHW MK_BMSK_(EVT_IVHW_P )
518#define EVT_IVTMR MK_BMSK_(EVT_IVTMR_P )
519#define EVT_IVG7 MK_BMSK_(EVT_IVG7_P )
520#define EVT_IVG8 MK_BMSK_(EVT_IVG8_P )
521#define EVT_IVG9 MK_BMSK_(EVT_IVG9_P )
522#define EVT_IVG10 MK_BMSK_(EVT_IVG10_P )
523#define EVT_IVG11 MK_BMSK_(EVT_IVG11_P )
524#define EVT_IVG12 MK_BMSK_(EVT_IVG12_P )
525#define EVT_IVG13 MK_BMSK_(EVT_IVG13_P )
526#define EVT_IVG14 MK_BMSK_(EVT_IVG14_P )
527#define EVT_IVG15 MK_BMSK_(EVT_IVG15_P )
528
529
530
531
532
533#define ENDM_P 0x00
534
535
536#define DMCTL_ENDM_P ENDM_P
537
538#define ENDCPLB_P 0x01
539#define DMCTL_ENDCPLB_P ENDCPLB_P
540#define DMC0_P 0x02
541#define DMCTL_DMC0_P DMC0_P
542#define DMC1_P 0x03
543#define DMCTL_DMC1_P DMC1_P
544#define DCBS_P 0x04
545#define PORT_PREF0_P 0x12
546#define PORT_PREF1_P 0x13
547#define RDCHK 0x9
548
549
550#define ENDM 0x00000001
551
552
553#define ENDCPLB 0x00000002
554#define ASRAM_BSRAM 0x00000000
555#define ACACHE_BSRAM 0x00000008
556#define ACACHE_BCACHE 0x0000000C
557#define DCBS 0x00000010
558#define PORT_PREF0 0x00001000
559#define PORT_PREF1 0x00002000
560
561
562
563#define ENIM_P 0x00
564#define IMCTL_ENIM_P 0x00
565#define ENICPLB_P 0x01
566#define IMCTL_ENICPLB_P 0x01
567#define IMC_P 0x02
568#define IMCTL_IMC_P 0x02
569
570
571#define ILOC0_P 0x03
572#define ILOC1_P 0x04
573#define ILOC2_P 0x05
574#define ILOC3_P 0x06
575#define LRUPRIORST_P 0x0D
576
577
578
579#define ENIM 0x00000001
580#define ENICPLB 0x00000002
581#define IMC 0x00000004
582
583
584#define ILOC0 0x00000008
585#define ILOC1 0x00000010
586#define ILOC2 0x00000020
587#define ILOC3 0x00000040
588#define LRUPRIORST 0x00002000
589
590
591
592
593#define TMPWR 0x00000001
594
595
596#define TMREN 0x00000002
597#define TAUTORLD 0x00000004
598#define TINT 0x00000008
599
600
601
602
603
604
605
606#define CPLB_VALID_P 0x00000000
607#define CPLB_LOCK_P 0x00000001
608
609
610#define CPLB_USER_RD_P 0x00000002
611
612
613
614#define CPLB_VALID 0x00000001
615#define CPLB_LOCK 0x00000002
616
617
618#define CPLB_USER_RD 0x00000004
619
620
621
622#define PAGE_SIZE_1KB 0x00000000
623#define PAGE_SIZE_4KB 0x00010000
624#define PAGE_SIZE_1MB 0x00020000
625#define PAGE_SIZE_4MB 0x00030000
626#ifdef CONFIG_BF60x
627#define PAGE_SIZE_16KB 0x00040000
628#define PAGE_SIZE_64KB 0x00050000
629#define PAGE_SIZE_16MB 0x00060000
630#define PAGE_SIZE_64MB 0x00070000
631#endif
632#define CPLB_L1SRAM 0x00000020
633
634
635#define CPLB_PORTPRIO 0x00000200
636
637
638#define CPLB_L1_CHBL 0x00001000
639
640
641
642#define CPLB_LRUPRIO 0x00000100
643
644
645
646#define CPLB_USER_WR 0x00000008
647
648
649#define CPLB_SUPV_WR 0x00000010
650
651
652#define CPLB_DIRTY 0x00000080
653#define CPLB_L1_AOW 0x00008000
654
655
656
657
658#define CPLB_WT 0x00004000
659
660#define CPLB_ALL_ACCESS CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR
661
662
663#define TBUFPWR 0x0001
664#define TBUFEN 0x0002
665#define TBUFOVF 0x0004
666#define TBUFCMPLP_SINGLE 0x0008
667#define TBUFCMPLP_DOUBLE 0x0010
668#define TBUFCMPLP (TBUFCMPLP_SINGLE | TBUFCMPLP_DOUBLE)
669
670
671#define TBUFCNT 0x001F
672
673
674
675#define TEST_READ 0x00000000
676#define TEST_WRITE 0x00000002
677#define TEST_TAG 0x00000000
678#define TEST_DATA 0x00000004
679#define TEST_DW0 0x00000000
680#define TEST_DW1 0x00000008
681#define TEST_DW2 0x00000010
682#define TEST_DW3 0x00000018
683#define TEST_MB0 0x00000000
684#define TEST_MB1 0x00010000
685#define TEST_MB2 0x00020000
686#define TEST_MB3 0x00030000
687#define TEST_SET(x) ((x << 5) & 0x03E0)
688#define TEST_WAY0 0x00000000
689#define TEST_WAY1 0x04000000
690
691#define TEST_WAY2 0x08000000
692#define TEST_WAY3 0x0C000000
693
694#define TEST_BNKSELA 0x00000000
695#define TEST_BNKSELB 0x00800000
696
697#endif
698