LXR linux/arch/mips/include/asm/mmu

   1/*
   2 * Switch a MMU context.
   3 *
   4 * This file is subject to the terms and conditions of the GNU General Public
   5 * License.  See the file "COPYING" in the main directory of this archive
   6 * for more details.
   7 *
   8 * Copyright (C) 1996, 1997, 1998, 1999 by Ralf Baechle
   9 * Copyright (C) 1999 Silicon Graphics, Inc.
  10 */
  11#ifndef _ASM_MMU_CONTEXT_H
  12#define _ASM_MMU_CONTEXT_H
  13
  14#include <linux/errno.h>
  15#include <linux/sched.h>
  16#include <linux/smp.h>
  17#include <linux/slab.h>
  18#include <asm/cacheflush.h>
  19#include <asm/hazards.h>
  20#include <asm/tlbflush.h>
  21#include <asm-generic/mm_hooks.h>
  22
  23#define htw_set_pwbase(pgd)                                             \
  24do {                                                                    \
  25        if (cpu_has_htw) {                                              \
  26                write_c0_pwbase(pgd);                                   \
  27                back_to_back_c0_hazard();                               \
  28        }                                                               \
  29} while (0)
  30
  31#define TLBMISS_HANDLER_SETUP_PGD(pgd)                                  \
  32do {                                                                    \
  33        extern void tlbmiss_handler_setup_pgd(unsigned long);           \
  34        tlbmiss_handler_setup_pgd((unsigned long)(pgd));                \
  35        htw_set_pwbase((unsigned long)pgd);                             \
  36} while (0)
  37
  38#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
  39
  40#define TLBMISS_HANDLER_RESTORE()                                       \
  41        write_c0_xcontext((unsigned long) smp_processor_id() <<         \
  42                          SMP_CPUID_REGSHIFT)
  43
  44#define TLBMISS_HANDLER_SETUP()                                         \
  45        do {                                                            \
  46                TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir);              \
  47                TLBMISS_HANDLER_RESTORE();                              \
  48        } while (0)
  49
  50#else /* !CONFIG_MIPS_PGD_C0_CONTEXT: using  pgd_current*/
  51
  52/*
  53 * For the fast tlb miss handlers, we keep a per cpu array of pointers
  54 * to the current pgd for each processor. Also, the proc. id is stuffed
  55 * into the context register.
  56 */
  57extern unsigned long pgd_current[];
  58
  59#define TLBMISS_HANDLER_RESTORE()                                       \
  60        write_c0_context((unsigned long) smp_processor_id() <<          \
  61                         SMP_CPUID_REGSHIFT)
  62
  63#define TLBMISS_HANDLER_SETUP()                                         \
  64        TLBMISS_HANDLER_RESTORE();                                      \
  65        back_to_back_c0_hazard();                                       \
  66        TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
  67#endif /* CONFIG_MIPS_PGD_C0_CONTEXT*/
  68#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
  69
  70#define ASID_INC        0x40
  71#define ASID_MASK       0xfc0
  72
  73#elif defined(CONFIG_CPU_R8000)
  74
  75#define ASID_INC        0x10
  76#define ASID_MASK       0xff0
  77
  78#else /* FIXME: not correct for R6000 */
  79
  80#define ASID_INC        0x1
  81#define ASID_MASK       0xff
  82
  83#endif
  84
  85#define cpu_context(cpu, mm)    ((mm)->context.asid[cpu])
  86#define cpu_asid(cpu, mm)       (cpu_context((cpu), (mm)) & ASID_MASK)
  87#define asid_cache(cpu)         (cpu_data[cpu].asid_cache)
  88
  89static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
  90{
  91}
  92
  93/*
  94 *  All unused by hardware upper bits will be considered
  95 *  as a software asid extension.
  96 */
  97#define ASID_VERSION_MASK  ((unsigned long)~(ASID_MASK|(ASID_MASK-1)))
  98#define ASID_FIRST_VERSION ((unsigned long)(~ASID_VERSION_MASK) + 1)
  99
 100/* Normal, classic MIPS get_new_mmu_context */
 101static inline void
 102get_new_mmu_context(struct mm_struct *mm, unsigned long cpu)
 103{
 104        extern void kvm_local_flush_tlb_all(void);
 105        unsigned long asid = asid_cache(cpu);
 106
 107        if (! ((asid += ASID_INC) & ASID_MASK) ) {
 108                if (cpu_has_vtag_icache)
 109                        flush_icache_all();
 110#ifdef CONFIG_KVM
 111                kvm_local_flush_tlb_all();      /* start new asid cycle */
 112#else
 113                local_flush_tlb_all();  /* start new asid cycle */
 114#endif
 115                if (!asid)              /* fix version if needed */
 116                        asid = ASID_FIRST_VERSION;
 117        }
 118
 119        cpu_context(cpu, mm) = asid_cache(cpu) = asid;
 120}
 121
 122/*
 123 * Initialize the context related info for a new mm_struct
 124 * instance.
 125 */
 126static inline int
 127init_new_context(struct task_struct *tsk, struct mm_struct *mm)
 128{
 129        int i;
 130
 131        for_each_possible_cpu(i)
 132                cpu_context(i, mm) = 0;
 133
 134        atomic_set(&mm->context.fp_mode_switching, 0);
 135
 136        return 0;
 137}
 138
 139static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
 140                             struct task_struct *tsk)
 141{
 142        unsigned int cpu = smp_processor_id();
 143        unsigned long flags;
 144        local_irq_save(flags);
 145
 146        htw_stop();
 147        /* Check if our ASID is of an older version and thus invalid */
 148        if ((cpu_context(cpu, next) ^ asid_cache(cpu)) & ASID_VERSION_MASK)
 149                get_new_mmu_context(next, cpu);
 150        write_c0_entryhi(cpu_asid(cpu, next));
 151        TLBMISS_HANDLER_SETUP_PGD(next->pgd);
 152
 153        /*
 154         * Mark current->active_mm as not "active" anymore.
 155         * We don't want to mislead possible IPI tlb flush routines.
 156         */
 157        cpumask_clear_cpu(cpu, mm_cpumask(prev));
 158        cpumask_set_cpu(cpu, mm_cpumask(next));
 159        htw_start();
 160
 161        local_irq_restore(flags);
 162}
 163
 164/*
 165 * Destroy context related info for an mm_struct that is about
 166 * to be put to rest.
 167 */
 168static inline void destroy_context(struct mm_struct *mm)
 169{
 170}
 171
 172#define deactivate_mm(tsk, mm)  do { } while (0)
 173
 174/*
 175 * After we have set current->mm to a new value, this activates
 176 * the context for the new mm so we see the new mappings.
 177 */
 178static inline void
 179activate_mm(struct mm_struct *prev, struct mm_struct *next)
 180{
 181        unsigned long flags;
 182        unsigned int cpu = smp_processor_id();
 183
 184        local_irq_save(flags);
 185
 186        htw_stop();
 187        /* Unconditionally get a new ASID.  */
 188        get_new_mmu_context(next, cpu);
 189
 190        write_c0_entryhi(cpu_asid(cpu, next));
 191        TLBMISS_HANDLER_SETUP_PGD(next->pgd);
 192
 193        /* mark mmu ownership change */
 194        cpumask_clear_cpu(cpu, mm_cpumask(prev));
 195        cpumask_set_cpu(cpu, mm_cpumask(next));
 196        htw_start();
 197
 198        local_irq_restore(flags);
 199}
 200
 201/*
 202 * If mm is currently active_mm, we can't really drop it.  Instead,
 203 * we will get a new one for it.
 204 */
 205static inline void
 206drop_mmu_context(struct mm_struct *mm, unsigned cpu)
 207{
 208        unsigned long flags;
 209
 210        local_irq_save(flags);
 211        htw_stop();
 212
 213        if (cpumask_test_cpu(cpu, mm_cpumask(mm)))  {
 214                get_new_mmu_context(mm, cpu);
 215                write_c0_entryhi(cpu_asid(cpu, mm));
 216        } else {
 217                /* will get a new context next time */
 218                cpu_context(cpu, mm) = 0;
 219        }
 220        htw_start();
 221        local_irq_restore(flags);
 222}
 223
 224#endif /* _ASM_MMU_CONTEXT_H */
 225