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12#include <linux/gpio.h>
13#include <linux/errno.h>
14#include <linux/kernel.h>
15#include <linux/clk.h>
16#include <linux/err.h>
17#include <linux/io.h>
18#include <linux/irq.h>
19#include <linux/irqdomain.h>
20#include <linux/module.h>
21#include <linux/of.h>
22#include <linux/of_device.h>
23#include <linux/platform_device.h>
24#include <linux/platform_data/gpio-davinci.h>
25#include <linux/irqchip/chained_irq.h>
26
27struct davinci_gpio_regs {
28 u32 dir;
29 u32 out_data;
30 u32 set_data;
31 u32 clr_data;
32 u32 in_data;
33 u32 set_rising;
34 u32 clr_rising;
35 u32 set_falling;
36 u32 clr_falling;
37 u32 intstat;
38};
39
40typedef struct irq_chip *(*gpio_get_irq_chip_cb_t)(unsigned int irq);
41
42#define BINTEN 0x8
43
44static void __iomem *gpio_base;
45
46static struct davinci_gpio_regs __iomem *gpio2regs(unsigned gpio)
47{
48 void __iomem *ptr;
49
50 if (gpio < 32 * 1)
51 ptr = gpio_base + 0x10;
52 else if (gpio < 32 * 2)
53 ptr = gpio_base + 0x38;
54 else if (gpio < 32 * 3)
55 ptr = gpio_base + 0x60;
56 else if (gpio < 32 * 4)
57 ptr = gpio_base + 0x88;
58 else if (gpio < 32 * 5)
59 ptr = gpio_base + 0xb0;
60 else
61 ptr = NULL;
62 return ptr;
63}
64
65static inline struct davinci_gpio_regs __iomem *irq2regs(struct irq_data *d)
66{
67 struct davinci_gpio_regs __iomem *g;
68
69 g = (__force struct davinci_gpio_regs __iomem *)irq_data_get_irq_chip_data(d);
70
71 return g;
72}
73
74static int davinci_gpio_irq_setup(struct platform_device *pdev);
75
76
77
78
79static inline int __davinci_direction(struct gpio_chip *chip,
80 unsigned offset, bool out, int value)
81{
82 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
83 struct davinci_gpio_regs __iomem *g = d->regs;
84 unsigned long flags;
85 u32 temp;
86 u32 mask = 1 << offset;
87
88 spin_lock_irqsave(&d->lock, flags);
89 temp = readl_relaxed(&g->dir);
90 if (out) {
91 temp &= ~mask;
92 writel_relaxed(mask, value ? &g->set_data : &g->clr_data);
93 } else {
94 temp |= mask;
95 }
96 writel_relaxed(temp, &g->dir);
97 spin_unlock_irqrestore(&d->lock, flags);
98
99 return 0;
100}
101
102static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
103{
104 return __davinci_direction(chip, offset, false, 0);
105}
106
107static int
108davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
109{
110 return __davinci_direction(chip, offset, true, value);
111}
112
113
114
115
116
117
118
119
120static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
121{
122 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
123 struct davinci_gpio_regs __iomem *g = d->regs;
124
125 return !!((1 << offset) & readl_relaxed(&g->in_data));
126}
127
128
129
130
131static void
132davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
133{
134 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
135 struct davinci_gpio_regs __iomem *g = d->regs;
136
137 writel_relaxed((1 << offset), value ? &g->set_data : &g->clr_data);
138}
139
140static struct davinci_gpio_platform_data *
141davinci_gpio_get_pdata(struct platform_device *pdev)
142{
143 struct device_node *dn = pdev->dev.of_node;
144 struct davinci_gpio_platform_data *pdata;
145 int ret;
146 u32 val;
147
148 if (!IS_ENABLED(CONFIG_OF) || !pdev->dev.of_node)
149 return dev_get_platdata(&pdev->dev);
150
151 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
152 if (!pdata)
153 return NULL;
154
155 ret = of_property_read_u32(dn, "ti,ngpio", &val);
156 if (ret)
157 goto of_err;
158
159 pdata->ngpio = val;
160
161 ret = of_property_read_u32(dn, "ti,davinci-gpio-unbanked", &val);
162 if (ret)
163 goto of_err;
164
165 pdata->gpio_unbanked = val;
166
167 return pdata;
168
169of_err:
170 dev_err(&pdev->dev, "Populating pdata from DT failed: err %d\n", ret);
171 return NULL;
172}
173
174#ifdef CONFIG_OF_GPIO
175static int davinci_gpio_of_xlate(struct gpio_chip *gc,
176 const struct of_phandle_args *gpiospec,
177 u32 *flags)
178{
179 struct davinci_gpio_controller *chips = dev_get_drvdata(gc->parent);
180 struct davinci_gpio_platform_data *pdata = dev_get_platdata(gc->parent);
181
182 if (gpiospec->args[0] > pdata->ngpio)
183 return -EINVAL;
184
185 if (gc != &chips[gpiospec->args[0] / 32].chip)
186 return -EINVAL;
187
188 if (flags)
189 *flags = gpiospec->args[1];
190
191 return gpiospec->args[0] % 32;
192}
193#endif
194
195static int davinci_gpio_probe(struct platform_device *pdev)
196{
197 int i, base;
198 unsigned ngpio, nbank;
199 struct davinci_gpio_controller *chips;
200 struct davinci_gpio_platform_data *pdata;
201 struct davinci_gpio_regs __iomem *regs;
202 struct device *dev = &pdev->dev;
203 struct resource *res;
204
205 pdata = davinci_gpio_get_pdata(pdev);
206 if (!pdata) {
207 dev_err(dev, "No platform data found\n");
208 return -EINVAL;
209 }
210
211 dev->platform_data = pdata;
212
213
214
215
216
217
218 ngpio = pdata->ngpio;
219 if (ngpio == 0) {
220 dev_err(dev, "How many GPIOs?\n");
221 return -EINVAL;
222 }
223
224 if (WARN_ON(ARCH_NR_GPIOS < ngpio))
225 ngpio = ARCH_NR_GPIOS;
226
227 nbank = DIV_ROUND_UP(ngpio, 32);
228 chips = devm_kzalloc(dev,
229 nbank * sizeof(struct davinci_gpio_controller),
230 GFP_KERNEL);
231 if (!chips)
232 return -ENOMEM;
233
234 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
235 gpio_base = devm_ioremap_resource(dev, res);
236 if (IS_ERR(gpio_base))
237 return PTR_ERR(gpio_base);
238
239 for (i = 0, base = 0; base < ngpio; i++, base += 32) {
240 chips[i].chip.label = "DaVinci";
241
242 chips[i].chip.direction_input = davinci_direction_in;
243 chips[i].chip.get = davinci_gpio_get;
244 chips[i].chip.direction_output = davinci_direction_out;
245 chips[i].chip.set = davinci_gpio_set;
246
247 chips[i].chip.base = base;
248 chips[i].chip.ngpio = ngpio - base;
249 if (chips[i].chip.ngpio > 32)
250 chips[i].chip.ngpio = 32;
251
252#ifdef CONFIG_OF_GPIO
253 chips[i].chip.of_gpio_n_cells = 2;
254 chips[i].chip.of_xlate = davinci_gpio_of_xlate;
255 chips[i].chip.parent = dev;
256 chips[i].chip.of_node = dev->of_node;
257#endif
258 spin_lock_init(&chips[i].lock);
259
260 regs = gpio2regs(base);
261 chips[i].regs = regs;
262 chips[i].set_data = ®s->set_data;
263 chips[i].clr_data = ®s->clr_data;
264 chips[i].in_data = ®s->in_data;
265
266 gpiochip_add_data(&chips[i].chip, &chips[i]);
267 }
268
269 platform_set_drvdata(pdev, chips);
270 davinci_gpio_irq_setup(pdev);
271 return 0;
272}
273
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284
285
286static void gpio_irq_disable(struct irq_data *d)
287{
288 struct davinci_gpio_regs __iomem *g = irq2regs(d);
289 u32 mask = (u32) irq_data_get_irq_handler_data(d);
290
291 writel_relaxed(mask, &g->clr_falling);
292 writel_relaxed(mask, &g->clr_rising);
293}
294
295static void gpio_irq_enable(struct irq_data *d)
296{
297 struct davinci_gpio_regs __iomem *g = irq2regs(d);
298 u32 mask = (u32) irq_data_get_irq_handler_data(d);
299 unsigned status = irqd_get_trigger_type(d);
300
301 status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
302 if (!status)
303 status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
304
305 if (status & IRQ_TYPE_EDGE_FALLING)
306 writel_relaxed(mask, &g->set_falling);
307 if (status & IRQ_TYPE_EDGE_RISING)
308 writel_relaxed(mask, &g->set_rising);
309}
310
311static int gpio_irq_type(struct irq_data *d, unsigned trigger)
312{
313 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
314 return -EINVAL;
315
316 return 0;
317}
318
319static struct irq_chip gpio_irqchip = {
320 .name = "GPIO",
321 .irq_enable = gpio_irq_enable,
322 .irq_disable = gpio_irq_disable,
323 .irq_set_type = gpio_irq_type,
324 .flags = IRQCHIP_SET_TYPE_MASKED,
325};
326
327static void gpio_irq_handler(struct irq_desc *desc)
328{
329 unsigned int irq = irq_desc_get_irq(desc);
330 struct davinci_gpio_regs __iomem *g;
331 u32 mask = 0xffff;
332 struct davinci_gpio_controller *d;
333
334 d = (struct davinci_gpio_controller *)irq_desc_get_handler_data(desc);
335 g = (struct davinci_gpio_regs __iomem *)d->regs;
336
337
338 if (irq & 1)
339 mask <<= 16;
340
341
342 chained_irq_enter(irq_desc_get_chip(desc), desc);
343 while (1) {
344 u32 status;
345 int bit;
346
347
348 status = readl_relaxed(&g->intstat) & mask;
349 if (!status)
350 break;
351 writel_relaxed(status, &g->intstat);
352
353
354
355 while (status) {
356 bit = __ffs(status);
357 status &= ~BIT(bit);
358 generic_handle_irq(
359 irq_find_mapping(d->irq_domain,
360 d->chip.base + bit));
361 }
362 }
363 chained_irq_exit(irq_desc_get_chip(desc), desc);
364
365}
366
367static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset)
368{
369 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
370
371 if (d->irq_domain)
372 return irq_create_mapping(d->irq_domain, d->chip.base + offset);
373 else
374 return -ENXIO;
375}
376
377static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
378{
379 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
380
381
382
383
384
385 if (offset < d->gpio_unbanked)
386 return d->gpio_irq + offset;
387 else
388 return -ENODEV;
389}
390
391static int gpio_irq_type_unbanked(struct irq_data *data, unsigned trigger)
392{
393 struct davinci_gpio_controller *d;
394 struct davinci_gpio_regs __iomem *g;
395 u32 mask;
396
397 d = (struct davinci_gpio_controller *)irq_data_get_irq_handler_data(data);
398 g = (struct davinci_gpio_regs __iomem *)d->regs;
399 mask = __gpio_mask(data->irq - d->gpio_irq);
400
401 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
402 return -EINVAL;
403
404 writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
405 ? &g->set_falling : &g->clr_falling);
406 writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_RISING)
407 ? &g->set_rising : &g->clr_rising);
408
409 return 0;
410}
411
412static int
413davinci_gpio_irq_map(struct irq_domain *d, unsigned int irq,
414 irq_hw_number_t hw)
415{
416 struct davinci_gpio_regs __iomem *g = gpio2regs(hw);
417
418 irq_set_chip_and_handler_name(irq, &gpio_irqchip, handle_simple_irq,
419 "davinci_gpio");
420 irq_set_irq_type(irq, IRQ_TYPE_NONE);
421 irq_set_chip_data(irq, (__force void *)g);
422 irq_set_handler_data(irq, (void *)__gpio_mask(hw));
423
424 return 0;
425}
426
427static const struct irq_domain_ops davinci_gpio_irq_ops = {
428 .map = davinci_gpio_irq_map,
429 .xlate = irq_domain_xlate_onetwocell,
430};
431
432static struct irq_chip *davinci_gpio_get_irq_chip(unsigned int irq)
433{
434 static struct irq_chip_type gpio_unbanked;
435
436 gpio_unbanked = *container_of(irq_get_chip(irq),
437 struct irq_chip_type, chip);
438
439 return &gpio_unbanked.chip;
440};
441
442static struct irq_chip *keystone_gpio_get_irq_chip(unsigned int irq)
443{
444 static struct irq_chip gpio_unbanked;
445
446 gpio_unbanked = *irq_get_chip(irq);
447 return &gpio_unbanked;
448};
449
450static const struct of_device_id davinci_gpio_ids[];
451
452
453
454
455
456
457
458
459
460static int davinci_gpio_irq_setup(struct platform_device *pdev)
461{
462 unsigned gpio, bank;
463 int irq;
464 struct clk *clk;
465 u32 binten = 0;
466 unsigned ngpio, bank_irq;
467 struct device *dev = &pdev->dev;
468 struct resource *res;
469 struct davinci_gpio_controller *chips = platform_get_drvdata(pdev);
470 struct davinci_gpio_platform_data *pdata = dev->platform_data;
471 struct davinci_gpio_regs __iomem *g;
472 struct irq_domain *irq_domain = NULL;
473 const struct of_device_id *match;
474 struct irq_chip *irq_chip;
475 gpio_get_irq_chip_cb_t gpio_get_irq_chip;
476
477
478
479
480 gpio_get_irq_chip = davinci_gpio_get_irq_chip;
481 match = of_match_device(of_match_ptr(davinci_gpio_ids),
482 dev);
483 if (match)
484 gpio_get_irq_chip = (gpio_get_irq_chip_cb_t)match->data;
485
486 ngpio = pdata->ngpio;
487 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
488 if (!res) {
489 dev_err(dev, "Invalid IRQ resource\n");
490 return -EBUSY;
491 }
492
493 bank_irq = res->start;
494
495 if (!bank_irq) {
496 dev_err(dev, "Invalid IRQ resource\n");
497 return -ENODEV;
498 }
499
500 clk = devm_clk_get(dev, "gpio");
501 if (IS_ERR(clk)) {
502 printk(KERN_ERR "Error %ld getting gpio clock?\n",
503 PTR_ERR(clk));
504 return PTR_ERR(clk);
505 }
506 clk_prepare_enable(clk);
507
508 if (!pdata->gpio_unbanked) {
509 irq = irq_alloc_descs(-1, 0, ngpio, 0);
510 if (irq < 0) {
511 dev_err(dev, "Couldn't allocate IRQ numbers\n");
512 return irq;
513 }
514
515 irq_domain = irq_domain_add_legacy(dev->of_node, ngpio, irq, 0,
516 &davinci_gpio_irq_ops,
517 chips);
518 if (!irq_domain) {
519 dev_err(dev, "Couldn't register an IRQ domain\n");
520 return -ENODEV;
521 }
522 }
523
524
525
526
527
528
529
530 for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 32) {
531 chips[bank].chip.to_irq = gpio_to_irq_banked;
532 chips[bank].irq_domain = irq_domain;
533 }
534
535
536
537
538
539
540 if (pdata->gpio_unbanked) {
541
542 chips[0].chip.to_irq = gpio_to_irq_unbanked;
543 chips[0].gpio_irq = bank_irq;
544 chips[0].gpio_unbanked = pdata->gpio_unbanked;
545 binten = GENMASK(pdata->gpio_unbanked / 16, 0);
546
547
548 irq = bank_irq;
549 irq_chip = gpio_get_irq_chip(irq);
550 irq_chip->name = "GPIO-AINTC";
551 irq_chip->irq_set_type = gpio_irq_type_unbanked;
552
553
554 g = gpio2regs(0);
555 writel_relaxed(~0, &g->set_falling);
556 writel_relaxed(~0, &g->set_rising);
557
558
559 for (gpio = 0; gpio < pdata->gpio_unbanked; gpio++, irq++) {
560 irq_set_chip(irq, irq_chip);
561 irq_set_handler_data(irq, &chips[gpio / 32]);
562 irq_set_status_flags(irq, IRQ_TYPE_EDGE_BOTH);
563 }
564
565 goto done;
566 }
567
568
569
570
571
572 for (gpio = 0, bank = 0; gpio < ngpio; bank++, bank_irq++, gpio += 16) {
573
574 g = gpio2regs(gpio);
575 writel_relaxed(~0, &g->clr_falling);
576 writel_relaxed(~0, &g->clr_rising);
577
578
579
580
581
582
583 irq_set_chained_handler_and_data(bank_irq, gpio_irq_handler,
584 &chips[gpio / 32]);
585
586 binten |= BIT(bank);
587 }
588
589done:
590
591
592
593
594 writel_relaxed(binten, gpio_base + BINTEN);
595
596 return 0;
597}
598
599#if IS_ENABLED(CONFIG_OF)
600static const struct of_device_id davinci_gpio_ids[] = {
601 { .compatible = "ti,keystone-gpio", keystone_gpio_get_irq_chip},
602 { .compatible = "ti,dm6441-gpio", davinci_gpio_get_irq_chip},
603 { },
604};
605MODULE_DEVICE_TABLE(of, davinci_gpio_ids);
606#endif
607
608static struct platform_driver davinci_gpio_driver = {
609 .probe = davinci_gpio_probe,
610 .driver = {
611 .name = "davinci_gpio",
612 .of_match_table = of_match_ptr(davinci_gpio_ids),
613 },
614};
615
616
617
618
619
620static int __init davinci_gpio_drv_reg(void)
621{
622 return platform_driver_register(&davinci_gpio_driver);
623}
624postcore_initcall(davinci_gpio_drv_reg);
625