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25#include <linux/firmware.h>
26#include <drm/drmP.h>
27#include "radeon.h"
28#include "radeon_asic.h"
29#include "rv770d.h"
30
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38
39void uvd_v2_2_fence_emit(struct radeon_device *rdev,
40 struct radeon_fence *fence)
41{
42 struct radeon_ring *ring = &rdev->ring[fence->ring];
43 uint64_t addr = rdev->fence_drv[fence->ring].gpu_addr;
44
45 radeon_ring_write(ring, PACKET0(UVD_CONTEXT_ID, 0));
46 radeon_ring_write(ring, fence->seq);
47 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0));
48 radeon_ring_write(ring, lower_32_bits(addr));
49 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0));
50 radeon_ring_write(ring, upper_32_bits(addr) & 0xff);
51 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0));
52 radeon_ring_write(ring, 0);
53
54 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0));
55 radeon_ring_write(ring, 0);
56 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0));
57 radeon_ring_write(ring, 0);
58 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0));
59 radeon_ring_write(ring, 2);
60}
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71
72bool uvd_v2_2_semaphore_emit(struct radeon_device *rdev,
73 struct radeon_ring *ring,
74 struct radeon_semaphore *semaphore,
75 bool emit_wait)
76{
77 uint64_t addr = semaphore->gpu_addr;
78
79 radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_LOW, 0));
80 radeon_ring_write(ring, (addr >> 3) & 0x000FFFFF);
81
82 radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_HIGH, 0));
83 radeon_ring_write(ring, (addr >> 23) & 0x000FFFFF);
84
85 radeon_ring_write(ring, PACKET0(UVD_SEMA_CMD, 0));
86 radeon_ring_write(ring, emit_wait ? 1 : 0);
87
88 return true;
89}
90
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96
97
98int uvd_v2_2_resume(struct radeon_device *rdev)
99{
100 uint64_t addr;
101 uint32_t chip_id, size;
102 int r;
103
104
105 if (rdev->family == CHIP_RV770)
106 return uvd_v1_0_resume(rdev);
107
108 r = radeon_uvd_resume(rdev);
109 if (r)
110 return r;
111
112
113 addr = rdev->uvd.gpu_addr >> 3;
114 size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->size + 4) >> 3;
115 WREG32(UVD_VCPU_CACHE_OFFSET0, addr);
116 WREG32(UVD_VCPU_CACHE_SIZE0, size);
117
118 addr += size;
119 size = RADEON_UVD_STACK_SIZE >> 3;
120 WREG32(UVD_VCPU_CACHE_OFFSET1, addr);
121 WREG32(UVD_VCPU_CACHE_SIZE1, size);
122
123 addr += size;
124 size = RADEON_UVD_HEAP_SIZE >> 3;
125 WREG32(UVD_VCPU_CACHE_OFFSET2, addr);
126 WREG32(UVD_VCPU_CACHE_SIZE2, size);
127
128
129 addr = (rdev->uvd.gpu_addr >> 28) & 0xF;
130 WREG32(UVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0));
131
132
133 addr = (rdev->uvd.gpu_addr >> 32) & 0xFF;
134 WREG32(UVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31));
135
136
137 switch (rdev->family) {
138 default:
139 return -EINVAL;
140 case CHIP_RV710:
141 chip_id = 0x01000005;
142 break;
143 case CHIP_RV730:
144 chip_id = 0x01000006;
145 break;
146 case CHIP_RV740:
147 chip_id = 0x01000007;
148 break;
149 case CHIP_CYPRESS:
150 case CHIP_HEMLOCK:
151 chip_id = 0x01000008;
152 break;
153 case CHIP_JUNIPER:
154 chip_id = 0x01000009;
155 break;
156 case CHIP_REDWOOD:
157 chip_id = 0x0100000a;
158 break;
159 case CHIP_CEDAR:
160 chip_id = 0x0100000b;
161 break;
162 case CHIP_SUMO:
163 case CHIP_SUMO2:
164 chip_id = 0x0100000c;
165 break;
166 case CHIP_PALM:
167 chip_id = 0x0100000e;
168 break;
169 case CHIP_CAYMAN:
170 chip_id = 0x0100000f;
171 break;
172 case CHIP_BARTS:
173 chip_id = 0x01000010;
174 break;
175 case CHIP_TURKS:
176 chip_id = 0x01000011;
177 break;
178 case CHIP_CAICOS:
179 chip_id = 0x01000012;
180 break;
181 case CHIP_TAHITI:
182 chip_id = 0x01000014;
183 break;
184 case CHIP_VERDE:
185 chip_id = 0x01000015;
186 break;
187 case CHIP_PITCAIRN:
188 case CHIP_OLAND:
189 chip_id = 0x01000016;
190 break;
191 case CHIP_ARUBA:
192 chip_id = 0x01000017;
193 break;
194 }
195 WREG32(UVD_VCPU_CHIP_ID, chip_id);
196
197 return 0;
198}
199