LXR linux/drivers/gpu/drm/sti/sti

   1/*
   2 * Copyright (C) STMicroelectronics SA 2014
   3 * Author: Vincent Abriou <vincent.abriou@st.com> for STMicroelectronics.
   4 * License terms:  GNU General Public License (GPL), version 2
   5 */
   6
   7#ifndef _STI_HDMI_H_
   8#define _STI_HDMI_H_
   9
  10#include <linux/platform_device.h>
  11
  12#include <drm/drmP.h>
  13
  14#define HDMI_STA           0x0010
  15#define HDMI_STA_DLL_LCK   BIT(5)
  16
  17#define HDMI_STA_HOT_PLUG_SHIFT 4
  18#define HDMI_STA_HOT_PLUG       (1 << HDMI_STA_HOT_PLUG_SHIFT)
  19
  20struct sti_hdmi;
  21
  22struct hdmi_phy_ops {
  23        bool (*start)(struct sti_hdmi *hdmi);
  24        void (*stop)(struct sti_hdmi *hdmi);
  25};
  26
  27/**
  28 * STI hdmi structure
  29 *
  30 * @dev: driver device
  31 * @drm_dev: pointer to drm device
  32 * @mode: current display mode selected
  33 * @regs: hdmi register
  34 * @syscfg: syscfg register for pll rejection configuration
  35 * @clk_pix: hdmi pixel clock
  36 * @clk_tmds: hdmi tmds clock
  37 * @clk_phy: hdmi phy clock
  38 * @clk_audio: hdmi audio clock
  39 * @irq: hdmi interrupt number
  40 * @irq_status: interrupt status register
  41 * @phy_ops: phy start/stop operations
  42 * @enabled: true if hdmi is enabled else false
  43 * @hpd: hot plug detect status
  44 * @wait_event: wait event
  45 * @event_received: wait event status
  46 * @reset: reset control of the hdmi phy
  47 */
  48struct sti_hdmi {
  49        struct device dev;
  50        struct drm_device *drm_dev;
  51        struct drm_display_mode mode;
  52        void __iomem *regs;
  53        void __iomem *syscfg;
  54        struct clk *clk_pix;
  55        struct clk *clk_tmds;
  56        struct clk *clk_phy;
  57        struct clk *clk_audio;
  58        int irq;
  59        u32 irq_status;
  60        struct hdmi_phy_ops *phy_ops;
  61        bool enabled;
  62        bool hpd;
  63        wait_queue_head_t wait_event;
  64        bool event_received;
  65        struct reset_control *reset;
  66        struct i2c_adapter *ddc_adapt;
  67};
  68
  69u32 hdmi_read(struct sti_hdmi *hdmi, int offset);
  70void hdmi_write(struct sti_hdmi *hdmi, u32 val, int offset);
  71
  72/**
  73 * hdmi phy config structure
  74 *
  75 * A pointer to an array of these structures is passed to a TMDS (HDMI) output
  76 * via the control interface to provide board and SoC specific
  77 * configurations of the HDMI PHY. Each entry in the array specifies a hardware
  78 * specific configuration for a given TMDS clock frequency range.
  79 *
  80 * @min_tmds_freq: Lower bound of TMDS clock frequency this entry applies to
  81 * @max_tmds_freq: Upper bound of TMDS clock frequency this entry applies to
  82 * @config: SoC specific register configuration
  83 */
  84struct hdmi_phy_config {
  85        u32 min_tmds_freq;
  86        u32 max_tmds_freq;
  87        u32 config[4];
  88};
  89
  90#endif
  91