1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21#include <linux/module.h>
22#include <linux/i2c.h>
23#include <linux/iio/iio.h>
24#include <linux/iio/sysfs.h>
25#include <linux/iio/buffer.h>
26#include <linux/iio/trigger.h>
27#include <linux/iio/trigger_consumer.h>
28#include <linux/iio/triggered_buffer.h>
29#include <linux/iio/events.h>
30#include <linux/delay.h>
31#include <linux/of_device.h>
32#include <linux/of_irq.h>
33
34#define MMA8452_STATUS 0x00
35#define MMA8452_STATUS_DRDY (BIT(2) | BIT(1) | BIT(0))
36#define MMA8452_OUT_X 0x01
37#define MMA8452_OUT_Y 0x03
38#define MMA8452_OUT_Z 0x05
39#define MMA8452_INT_SRC 0x0c
40#define MMA8452_WHO_AM_I 0x0d
41#define MMA8452_DATA_CFG 0x0e
42#define MMA8452_DATA_CFG_FS_MASK GENMASK(1, 0)
43#define MMA8452_DATA_CFG_FS_2G 0
44#define MMA8452_DATA_CFG_FS_4G 1
45#define MMA8452_DATA_CFG_FS_8G 2
46#define MMA8452_DATA_CFG_HPF_MASK BIT(4)
47#define MMA8452_HP_FILTER_CUTOFF 0x0f
48#define MMA8452_HP_FILTER_CUTOFF_SEL_MASK GENMASK(1, 0)
49#define MMA8452_FF_MT_CFG 0x15
50#define MMA8452_FF_MT_CFG_OAE BIT(6)
51#define MMA8452_FF_MT_CFG_ELE BIT(7)
52#define MMA8452_FF_MT_SRC 0x16
53#define MMA8452_FF_MT_SRC_XHE BIT(1)
54#define MMA8452_FF_MT_SRC_YHE BIT(3)
55#define MMA8452_FF_MT_SRC_ZHE BIT(5)
56#define MMA8452_FF_MT_THS 0x17
57#define MMA8452_FF_MT_THS_MASK 0x7f
58#define MMA8452_FF_MT_COUNT 0x18
59#define MMA8452_TRANSIENT_CFG 0x1d
60#define MMA8452_TRANSIENT_CFG_HPF_BYP BIT(0)
61#define MMA8452_TRANSIENT_CFG_ELE BIT(4)
62#define MMA8452_TRANSIENT_SRC 0x1e
63#define MMA8452_TRANSIENT_SRC_XTRANSE BIT(1)
64#define MMA8452_TRANSIENT_SRC_YTRANSE BIT(3)
65#define MMA8452_TRANSIENT_SRC_ZTRANSE BIT(5)
66#define MMA8452_TRANSIENT_THS 0x1f
67#define MMA8452_TRANSIENT_THS_MASK GENMASK(6, 0)
68#define MMA8452_TRANSIENT_COUNT 0x20
69#define MMA8452_CTRL_REG1 0x2a
70#define MMA8452_CTRL_ACTIVE BIT(0)
71#define MMA8452_CTRL_DR_MASK GENMASK(5, 3)
72#define MMA8452_CTRL_DR_SHIFT 3
73#define MMA8452_CTRL_DR_DEFAULT 0x4
74#define MMA8452_CTRL_REG2 0x2b
75#define MMA8452_CTRL_REG2_RST BIT(6)
76#define MMA8452_CTRL_REG4 0x2d
77#define MMA8452_CTRL_REG5 0x2e
78#define MMA8452_OFF_X 0x2f
79#define MMA8452_OFF_Y 0x30
80#define MMA8452_OFF_Z 0x31
81
82#define MMA8452_MAX_REG 0x31
83
84#define MMA8452_INT_DRDY BIT(0)
85#define MMA8452_INT_FF_MT BIT(2)
86#define MMA8452_INT_TRANS BIT(5)
87
88#define MMA8452_DEVICE_ID 0x2a
89#define MMA8453_DEVICE_ID 0x3a
90#define MMA8652_DEVICE_ID 0x4a
91#define MMA8653_DEVICE_ID 0x5a
92
93struct mma8452_data {
94 struct i2c_client *client;
95 struct mutex lock;
96 u8 ctrl_reg1;
97 u8 data_cfg;
98 const struct mma_chip_info *chip_info;
99};
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129struct mma_chip_info {
130 u8 chip_id;
131 const struct iio_chan_spec *channels;
132 int num_channels;
133 const int mma_scales[3][2];
134 u8 ev_cfg;
135 u8 ev_cfg_ele;
136 u8 ev_cfg_chan_shift;
137 u8 ev_src;
138 u8 ev_src_xe;
139 u8 ev_src_ye;
140 u8 ev_src_ze;
141 u8 ev_ths;
142 u8 ev_ths_mask;
143 u8 ev_count;
144};
145
146enum {
147 idx_x,
148 idx_y,
149 idx_z,
150 idx_ts,
151};
152
153static int mma8452_drdy(struct mma8452_data *data)
154{
155 int tries = 150;
156
157 while (tries-- > 0) {
158 int ret = i2c_smbus_read_byte_data(data->client,
159 MMA8452_STATUS);
160 if (ret < 0)
161 return ret;
162 if ((ret & MMA8452_STATUS_DRDY) == MMA8452_STATUS_DRDY)
163 return 0;
164
165 msleep(20);
166 }
167
168 dev_err(&data->client->dev, "data not ready\n");
169
170 return -EIO;
171}
172
173static int mma8452_read(struct mma8452_data *data, __be16 buf[3])
174{
175 int ret = mma8452_drdy(data);
176
177 if (ret < 0)
178 return ret;
179
180 return i2c_smbus_read_i2c_block_data(data->client, MMA8452_OUT_X,
181 3 * sizeof(__be16), (u8 *)buf);
182}
183
184static ssize_t mma8452_show_int_plus_micros(char *buf, const int (*vals)[2],
185 int n)
186{
187 size_t len = 0;
188
189 while (n-- > 0)
190 len += scnprintf(buf + len, PAGE_SIZE - len, "%d.%06d ",
191 vals[n][0], vals[n][1]);
192
193
194 buf[len - 1] = '\n';
195
196 return len;
197}
198
199static int mma8452_get_int_plus_micros_index(const int (*vals)[2], int n,
200 int val, int val2)
201{
202 while (n-- > 0)
203 if (val == vals[n][0] && val2 == vals[n][1])
204 return n;
205
206 return -EINVAL;
207}
208
209static int mma8452_get_odr_index(struct mma8452_data *data)
210{
211 return (data->ctrl_reg1 & MMA8452_CTRL_DR_MASK) >>
212 MMA8452_CTRL_DR_SHIFT;
213}
214
215static const int mma8452_samp_freq[8][2] = {
216 {800, 0}, {400, 0}, {200, 0}, {100, 0}, {50, 0}, {12, 500000},
217 {6, 250000}, {1, 560000}
218};
219
220
221static const int mma8452_transient_time_step_us[8] = {
222 1250,
223 2500,
224 5000,
225 10000,
226 20000,
227 20000,
228 20000,
229 20000
230};
231
232
233static const int mma8452_hp_filter_cutoff[8][4][2] = {
234 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
235 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
236 { {8, 0}, {4, 0}, {2, 0}, {1, 0} },
237 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} },
238 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} },
239 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} },
240 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} },
241 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }
242};
243
244static ssize_t mma8452_show_samp_freq_avail(struct device *dev,
245 struct device_attribute *attr,
246 char *buf)
247{
248 return mma8452_show_int_plus_micros(buf, mma8452_samp_freq,
249 ARRAY_SIZE(mma8452_samp_freq));
250}
251
252static ssize_t mma8452_show_scale_avail(struct device *dev,
253 struct device_attribute *attr,
254 char *buf)
255{
256 struct mma8452_data *data = iio_priv(i2c_get_clientdata(
257 to_i2c_client(dev)));
258
259 return mma8452_show_int_plus_micros(buf, data->chip_info->mma_scales,
260 ARRAY_SIZE(data->chip_info->mma_scales));
261}
262
263static ssize_t mma8452_show_hp_cutoff_avail(struct device *dev,
264 struct device_attribute *attr,
265 char *buf)
266{
267 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
268 struct mma8452_data *data = iio_priv(indio_dev);
269 int i = mma8452_get_odr_index(data);
270
271 return mma8452_show_int_plus_micros(buf, mma8452_hp_filter_cutoff[i],
272 ARRAY_SIZE(mma8452_hp_filter_cutoff[0]));
273}
274
275static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(mma8452_show_samp_freq_avail);
276static IIO_DEVICE_ATTR(in_accel_scale_available, S_IRUGO,
277 mma8452_show_scale_avail, NULL, 0);
278static IIO_DEVICE_ATTR(in_accel_filter_high_pass_3db_frequency_available,
279 S_IRUGO, mma8452_show_hp_cutoff_avail, NULL, 0);
280
281static int mma8452_get_samp_freq_index(struct mma8452_data *data,
282 int val, int val2)
283{
284 return mma8452_get_int_plus_micros_index(mma8452_samp_freq,
285 ARRAY_SIZE(mma8452_samp_freq),
286 val, val2);
287}
288
289static int mma8452_get_scale_index(struct mma8452_data *data, int val, int val2)
290{
291 return mma8452_get_int_plus_micros_index(data->chip_info->mma_scales,
292 ARRAY_SIZE(data->chip_info->mma_scales), val, val2);
293}
294
295static int mma8452_get_hp_filter_index(struct mma8452_data *data,
296 int val, int val2)
297{
298 int i = mma8452_get_odr_index(data);
299
300 return mma8452_get_int_plus_micros_index(mma8452_hp_filter_cutoff[i],
301 ARRAY_SIZE(mma8452_hp_filter_cutoff[0]), val, val2);
302}
303
304static int mma8452_read_hp_filter(struct mma8452_data *data, int *hz, int *uHz)
305{
306 int i, ret;
307
308 ret = i2c_smbus_read_byte_data(data->client, MMA8452_HP_FILTER_CUTOFF);
309 if (ret < 0)
310 return ret;
311
312 i = mma8452_get_odr_index(data);
313 ret &= MMA8452_HP_FILTER_CUTOFF_SEL_MASK;
314 *hz = mma8452_hp_filter_cutoff[i][ret][0];
315 *uHz = mma8452_hp_filter_cutoff[i][ret][1];
316
317 return 0;
318}
319
320static int mma8452_read_raw(struct iio_dev *indio_dev,
321 struct iio_chan_spec const *chan,
322 int *val, int *val2, long mask)
323{
324 struct mma8452_data *data = iio_priv(indio_dev);
325 __be16 buffer[3];
326 int i, ret;
327
328 switch (mask) {
329 case IIO_CHAN_INFO_RAW:
330 if (iio_buffer_enabled(indio_dev))
331 return -EBUSY;
332
333 mutex_lock(&data->lock);
334 ret = mma8452_read(data, buffer);
335 mutex_unlock(&data->lock);
336 if (ret < 0)
337 return ret;
338
339 *val = sign_extend32(be16_to_cpu(
340 buffer[chan->scan_index]) >> chan->scan_type.shift,
341 chan->scan_type.realbits - 1);
342
343 return IIO_VAL_INT;
344 case IIO_CHAN_INFO_SCALE:
345 i = data->data_cfg & MMA8452_DATA_CFG_FS_MASK;
346 *val = data->chip_info->mma_scales[i][0];
347 *val2 = data->chip_info->mma_scales[i][1];
348
349 return IIO_VAL_INT_PLUS_MICRO;
350 case IIO_CHAN_INFO_SAMP_FREQ:
351 i = mma8452_get_odr_index(data);
352 *val = mma8452_samp_freq[i][0];
353 *val2 = mma8452_samp_freq[i][1];
354
355 return IIO_VAL_INT_PLUS_MICRO;
356 case IIO_CHAN_INFO_CALIBBIAS:
357 ret = i2c_smbus_read_byte_data(data->client,
358 MMA8452_OFF_X + chan->scan_index);
359 if (ret < 0)
360 return ret;
361
362 *val = sign_extend32(ret, 7);
363
364 return IIO_VAL_INT;
365 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
366 if (data->data_cfg & MMA8452_DATA_CFG_HPF_MASK) {
367 ret = mma8452_read_hp_filter(data, val, val2);
368 if (ret < 0)
369 return ret;
370 } else {
371 *val = 0;
372 *val2 = 0;
373 }
374
375 return IIO_VAL_INT_PLUS_MICRO;
376 }
377
378 return -EINVAL;
379}
380
381static int mma8452_standby(struct mma8452_data *data)
382{
383 return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1,
384 data->ctrl_reg1 & ~MMA8452_CTRL_ACTIVE);
385}
386
387static int mma8452_active(struct mma8452_data *data)
388{
389 return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1,
390 data->ctrl_reg1);
391}
392
393static int mma8452_change_config(struct mma8452_data *data, u8 reg, u8 val)
394{
395 int ret;
396
397 mutex_lock(&data->lock);
398
399
400 ret = mma8452_standby(data);
401 if (ret < 0)
402 goto fail;
403
404 ret = i2c_smbus_write_byte_data(data->client, reg, val);
405 if (ret < 0)
406 goto fail;
407
408 ret = mma8452_active(data);
409 if (ret < 0)
410 goto fail;
411
412 ret = 0;
413fail:
414 mutex_unlock(&data->lock);
415
416 return ret;
417}
418
419static int mma8452_set_hp_filter_frequency(struct mma8452_data *data,
420 int val, int val2)
421{
422 int i, reg;
423
424 i = mma8452_get_hp_filter_index(data, val, val2);
425 if (i < 0)
426 return i;
427
428 reg = i2c_smbus_read_byte_data(data->client,
429 MMA8452_HP_FILTER_CUTOFF);
430 if (reg < 0)
431 return reg;
432
433 reg &= ~MMA8452_HP_FILTER_CUTOFF_SEL_MASK;
434 reg |= i;
435
436 return mma8452_change_config(data, MMA8452_HP_FILTER_CUTOFF, reg);
437}
438
439static int mma8452_write_raw(struct iio_dev *indio_dev,
440 struct iio_chan_spec const *chan,
441 int val, int val2, long mask)
442{
443 struct mma8452_data *data = iio_priv(indio_dev);
444 int i, ret;
445
446 if (iio_buffer_enabled(indio_dev))
447 return -EBUSY;
448
449 switch (mask) {
450 case IIO_CHAN_INFO_SAMP_FREQ:
451 i = mma8452_get_samp_freq_index(data, val, val2);
452 if (i < 0)
453 return i;
454
455 data->ctrl_reg1 &= ~MMA8452_CTRL_DR_MASK;
456 data->ctrl_reg1 |= i << MMA8452_CTRL_DR_SHIFT;
457
458 return mma8452_change_config(data, MMA8452_CTRL_REG1,
459 data->ctrl_reg1);
460 case IIO_CHAN_INFO_SCALE:
461 i = mma8452_get_scale_index(data, val, val2);
462 if (i < 0)
463 return i;
464
465 data->data_cfg &= ~MMA8452_DATA_CFG_FS_MASK;
466 data->data_cfg |= i;
467
468 return mma8452_change_config(data, MMA8452_DATA_CFG,
469 data->data_cfg);
470 case IIO_CHAN_INFO_CALIBBIAS:
471 if (val < -128 || val > 127)
472 return -EINVAL;
473
474 return mma8452_change_config(data,
475 MMA8452_OFF_X + chan->scan_index,
476 val);
477
478 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
479 if (val == 0 && val2 == 0) {
480 data->data_cfg &= ~MMA8452_DATA_CFG_HPF_MASK;
481 } else {
482 data->data_cfg |= MMA8452_DATA_CFG_HPF_MASK;
483 ret = mma8452_set_hp_filter_frequency(data, val, val2);
484 if (ret < 0)
485 return ret;
486 }
487
488 return mma8452_change_config(data, MMA8452_DATA_CFG,
489 data->data_cfg);
490
491 default:
492 return -EINVAL;
493 }
494}
495
496static int mma8452_read_thresh(struct iio_dev *indio_dev,
497 const struct iio_chan_spec *chan,
498 enum iio_event_type type,
499 enum iio_event_direction dir,
500 enum iio_event_info info,
501 int *val, int *val2)
502{
503 struct mma8452_data *data = iio_priv(indio_dev);
504 int ret, us;
505
506 switch (info) {
507 case IIO_EV_INFO_VALUE:
508 ret = i2c_smbus_read_byte_data(data->client,
509 data->chip_info->ev_ths);
510 if (ret < 0)
511 return ret;
512
513 *val = ret & data->chip_info->ev_ths_mask;
514
515 return IIO_VAL_INT;
516
517 case IIO_EV_INFO_PERIOD:
518 ret = i2c_smbus_read_byte_data(data->client,
519 data->chip_info->ev_count);
520 if (ret < 0)
521 return ret;
522
523 us = ret * mma8452_transient_time_step_us[
524 mma8452_get_odr_index(data)];
525 *val = us / USEC_PER_SEC;
526 *val2 = us % USEC_PER_SEC;
527
528 return IIO_VAL_INT_PLUS_MICRO;
529
530 case IIO_EV_INFO_HIGH_PASS_FILTER_3DB:
531 ret = i2c_smbus_read_byte_data(data->client,
532 MMA8452_TRANSIENT_CFG);
533 if (ret < 0)
534 return ret;
535
536 if (ret & MMA8452_TRANSIENT_CFG_HPF_BYP) {
537 *val = 0;
538 *val2 = 0;
539 } else {
540 ret = mma8452_read_hp_filter(data, val, val2);
541 if (ret < 0)
542 return ret;
543 }
544
545 return IIO_VAL_INT_PLUS_MICRO;
546
547 default:
548 return -EINVAL;
549 }
550}
551
552static int mma8452_write_thresh(struct iio_dev *indio_dev,
553 const struct iio_chan_spec *chan,
554 enum iio_event_type type,
555 enum iio_event_direction dir,
556 enum iio_event_info info,
557 int val, int val2)
558{
559 struct mma8452_data *data = iio_priv(indio_dev);
560 int ret, reg, steps;
561
562 switch (info) {
563 case IIO_EV_INFO_VALUE:
564 if (val < 0 || val > MMA8452_TRANSIENT_THS_MASK)
565 return -EINVAL;
566
567 return mma8452_change_config(data, data->chip_info->ev_ths,
568 val);
569
570 case IIO_EV_INFO_PERIOD:
571 steps = (val * USEC_PER_SEC + val2) /
572 mma8452_transient_time_step_us[
573 mma8452_get_odr_index(data)];
574
575 if (steps < 0 || steps > 0xff)
576 return -EINVAL;
577
578 return mma8452_change_config(data, data->chip_info->ev_count,
579 steps);
580
581 case IIO_EV_INFO_HIGH_PASS_FILTER_3DB:
582 reg = i2c_smbus_read_byte_data(data->client,
583 MMA8452_TRANSIENT_CFG);
584 if (reg < 0)
585 return reg;
586
587 if (val == 0 && val2 == 0) {
588 reg |= MMA8452_TRANSIENT_CFG_HPF_BYP;
589 } else {
590 reg &= ~MMA8452_TRANSIENT_CFG_HPF_BYP;
591 ret = mma8452_set_hp_filter_frequency(data, val, val2);
592 if (ret < 0)
593 return ret;
594 }
595
596 return mma8452_change_config(data, MMA8452_TRANSIENT_CFG, reg);
597
598 default:
599 return -EINVAL;
600 }
601}
602
603static int mma8452_read_event_config(struct iio_dev *indio_dev,
604 const struct iio_chan_spec *chan,
605 enum iio_event_type type,
606 enum iio_event_direction dir)
607{
608 struct mma8452_data *data = iio_priv(indio_dev);
609 const struct mma_chip_info *chip = data->chip_info;
610 int ret;
611
612 ret = i2c_smbus_read_byte_data(data->client,
613 data->chip_info->ev_cfg);
614 if (ret < 0)
615 return ret;
616
617 return !!(ret & BIT(chan->scan_index + chip->ev_cfg_chan_shift));
618}
619
620static int mma8452_write_event_config(struct iio_dev *indio_dev,
621 const struct iio_chan_spec *chan,
622 enum iio_event_type type,
623 enum iio_event_direction dir,
624 int state)
625{
626 struct mma8452_data *data = iio_priv(indio_dev);
627 const struct mma_chip_info *chip = data->chip_info;
628 int val;
629
630 val = i2c_smbus_read_byte_data(data->client, chip->ev_cfg);
631 if (val < 0)
632 return val;
633
634 if (state)
635 val |= BIT(chan->scan_index + chip->ev_cfg_chan_shift);
636 else
637 val &= ~BIT(chan->scan_index + chip->ev_cfg_chan_shift);
638
639 val |= chip->ev_cfg_ele;
640 val |= MMA8452_FF_MT_CFG_OAE;
641
642 return mma8452_change_config(data, chip->ev_cfg, val);
643}
644
645static void mma8452_transient_interrupt(struct iio_dev *indio_dev)
646{
647 struct mma8452_data *data = iio_priv(indio_dev);
648 s64 ts = iio_get_time_ns();
649 int src;
650
651 src = i2c_smbus_read_byte_data(data->client, data->chip_info->ev_src);
652 if (src < 0)
653 return;
654
655 if (src & data->chip_info->ev_src_xe)
656 iio_push_event(indio_dev,
657 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X,
658 IIO_EV_TYPE_MAG,
659 IIO_EV_DIR_RISING),
660 ts);
661
662 if (src & data->chip_info->ev_src_ye)
663 iio_push_event(indio_dev,
664 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Y,
665 IIO_EV_TYPE_MAG,
666 IIO_EV_DIR_RISING),
667 ts);
668
669 if (src & data->chip_info->ev_src_ze)
670 iio_push_event(indio_dev,
671 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Z,
672 IIO_EV_TYPE_MAG,
673 IIO_EV_DIR_RISING),
674 ts);
675}
676
677static irqreturn_t mma8452_interrupt(int irq, void *p)
678{
679 struct iio_dev *indio_dev = p;
680 struct mma8452_data *data = iio_priv(indio_dev);
681 const struct mma_chip_info *chip = data->chip_info;
682 int ret = IRQ_NONE;
683 int src;
684
685 src = i2c_smbus_read_byte_data(data->client, MMA8452_INT_SRC);
686 if (src < 0)
687 return IRQ_NONE;
688
689 if (src & MMA8452_INT_DRDY) {
690 iio_trigger_poll_chained(indio_dev->trig);
691 ret = IRQ_HANDLED;
692 }
693
694 if ((src & MMA8452_INT_TRANS &&
695 chip->ev_src == MMA8452_TRANSIENT_SRC) ||
696 (src & MMA8452_INT_FF_MT &&
697 chip->ev_src == MMA8452_FF_MT_SRC)) {
698 mma8452_transient_interrupt(indio_dev);
699 ret = IRQ_HANDLED;
700 }
701
702 return ret;
703}
704
705static irqreturn_t mma8452_trigger_handler(int irq, void *p)
706{
707 struct iio_poll_func *pf = p;
708 struct iio_dev *indio_dev = pf->indio_dev;
709 struct mma8452_data *data = iio_priv(indio_dev);
710 u8 buffer[16];
711 int ret;
712
713 ret = mma8452_read(data, (__be16 *)buffer);
714 if (ret < 0)
715 goto done;
716
717 iio_push_to_buffers_with_timestamp(indio_dev, buffer,
718 iio_get_time_ns());
719
720done:
721 iio_trigger_notify_done(indio_dev->trig);
722
723 return IRQ_HANDLED;
724}
725
726static int mma8452_reg_access_dbg(struct iio_dev *indio_dev,
727 unsigned reg, unsigned writeval,
728 unsigned *readval)
729{
730 int ret;
731 struct mma8452_data *data = iio_priv(indio_dev);
732
733 if (reg > MMA8452_MAX_REG)
734 return -EINVAL;
735
736 if (!readval)
737 return mma8452_change_config(data, reg, writeval);
738
739 ret = i2c_smbus_read_byte_data(data->client, reg);
740 if (ret < 0)
741 return ret;
742
743 *readval = ret;
744
745 return 0;
746}
747
748static const struct iio_event_spec mma8452_transient_event[] = {
749 {
750 .type = IIO_EV_TYPE_MAG,
751 .dir = IIO_EV_DIR_RISING,
752 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
753 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
754 BIT(IIO_EV_INFO_PERIOD) |
755 BIT(IIO_EV_INFO_HIGH_PASS_FILTER_3DB)
756 },
757};
758
759static const struct iio_event_spec mma8452_motion_event[] = {
760 {
761 .type = IIO_EV_TYPE_MAG,
762 .dir = IIO_EV_DIR_RISING,
763 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
764 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
765 BIT(IIO_EV_INFO_PERIOD)
766 },
767};
768
769
770
771
772
773static IIO_CONST_ATTR_NAMED(accel_transient_scale, in_accel_scale, "0.617742");
774
775static struct attribute *mma8452_event_attributes[] = {
776 &iio_const_attr_accel_transient_scale.dev_attr.attr,
777 NULL,
778};
779
780static struct attribute_group mma8452_event_attribute_group = {
781 .attrs = mma8452_event_attributes,
782};
783
784#define MMA8452_CHANNEL(axis, idx, bits) { \
785 .type = IIO_ACCEL, \
786 .modified = 1, \
787 .channel2 = IIO_MOD_##axis, \
788 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
789 BIT(IIO_CHAN_INFO_CALIBBIAS), \
790 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
791 BIT(IIO_CHAN_INFO_SCALE) | \
792 BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY), \
793 .scan_index = idx, \
794 .scan_type = { \
795 .sign = 's', \
796 .realbits = (bits), \
797 .storagebits = 16, \
798 .shift = 16 - (bits), \
799 .endianness = IIO_BE, \
800 }, \
801 .event_spec = mma8452_transient_event, \
802 .num_event_specs = ARRAY_SIZE(mma8452_transient_event), \
803}
804
805#define MMA8652_CHANNEL(axis, idx, bits) { \
806 .type = IIO_ACCEL, \
807 .modified = 1, \
808 .channel2 = IIO_MOD_##axis, \
809 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
810 BIT(IIO_CHAN_INFO_CALIBBIAS), \
811 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
812 BIT(IIO_CHAN_INFO_SCALE), \
813 .scan_index = idx, \
814 .scan_type = { \
815 .sign = 's', \
816 .realbits = (bits), \
817 .storagebits = 16, \
818 .shift = 16 - (bits), \
819 .endianness = IIO_BE, \
820 }, \
821 .event_spec = mma8452_motion_event, \
822 .num_event_specs = ARRAY_SIZE(mma8452_motion_event), \
823}
824
825static const struct iio_chan_spec mma8452_channels[] = {
826 MMA8452_CHANNEL(X, idx_x, 12),
827 MMA8452_CHANNEL(Y, idx_y, 12),
828 MMA8452_CHANNEL(Z, idx_z, 12),
829 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
830};
831
832static const struct iio_chan_spec mma8453_channels[] = {
833 MMA8452_CHANNEL(X, idx_x, 10),
834 MMA8452_CHANNEL(Y, idx_y, 10),
835 MMA8452_CHANNEL(Z, idx_z, 10),
836 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
837};
838
839static const struct iio_chan_spec mma8652_channels[] = {
840 MMA8652_CHANNEL(X, idx_x, 12),
841 MMA8652_CHANNEL(Y, idx_y, 12),
842 MMA8652_CHANNEL(Z, idx_z, 12),
843 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
844};
845
846static const struct iio_chan_spec mma8653_channels[] = {
847 MMA8652_CHANNEL(X, idx_x, 10),
848 MMA8652_CHANNEL(Y, idx_y, 10),
849 MMA8652_CHANNEL(Z, idx_z, 10),
850 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
851};
852
853enum {
854 mma8452,
855 mma8453,
856 mma8652,
857 mma8653,
858};
859
860static const struct mma_chip_info mma_chip_info_table[] = {
861 [mma8452] = {
862 .chip_id = MMA8452_DEVICE_ID,
863 .channels = mma8452_channels,
864 .num_channels = ARRAY_SIZE(mma8452_channels),
865
866
867
868
869
870
871
872 .mma_scales = { {0, 9577}, {0, 19154}, {0, 38307} },
873 .ev_cfg = MMA8452_TRANSIENT_CFG,
874 .ev_cfg_ele = MMA8452_TRANSIENT_CFG_ELE,
875 .ev_cfg_chan_shift = 1,
876 .ev_src = MMA8452_TRANSIENT_SRC,
877 .ev_src_xe = MMA8452_TRANSIENT_SRC_XTRANSE,
878 .ev_src_ye = MMA8452_TRANSIENT_SRC_YTRANSE,
879 .ev_src_ze = MMA8452_TRANSIENT_SRC_ZTRANSE,
880 .ev_ths = MMA8452_TRANSIENT_THS,
881 .ev_ths_mask = MMA8452_TRANSIENT_THS_MASK,
882 .ev_count = MMA8452_TRANSIENT_COUNT,
883 },
884 [mma8453] = {
885 .chip_id = MMA8453_DEVICE_ID,
886 .channels = mma8453_channels,
887 .num_channels = ARRAY_SIZE(mma8453_channels),
888 .mma_scales = { {0, 38307}, {0, 76614}, {0, 153228} },
889 .ev_cfg = MMA8452_TRANSIENT_CFG,
890 .ev_cfg_ele = MMA8452_TRANSIENT_CFG_ELE,
891 .ev_cfg_chan_shift = 1,
892 .ev_src = MMA8452_TRANSIENT_SRC,
893 .ev_src_xe = MMA8452_TRANSIENT_SRC_XTRANSE,
894 .ev_src_ye = MMA8452_TRANSIENT_SRC_YTRANSE,
895 .ev_src_ze = MMA8452_TRANSIENT_SRC_ZTRANSE,
896 .ev_ths = MMA8452_TRANSIENT_THS,
897 .ev_ths_mask = MMA8452_TRANSIENT_THS_MASK,
898 .ev_count = MMA8452_TRANSIENT_COUNT,
899 },
900 [mma8652] = {
901 .chip_id = MMA8652_DEVICE_ID,
902 .channels = mma8652_channels,
903 .num_channels = ARRAY_SIZE(mma8652_channels),
904 .mma_scales = { {0, 9577}, {0, 19154}, {0, 38307} },
905 .ev_cfg = MMA8452_FF_MT_CFG,
906 .ev_cfg_ele = MMA8452_FF_MT_CFG_ELE,
907 .ev_cfg_chan_shift = 3,
908 .ev_src = MMA8452_FF_MT_SRC,
909 .ev_src_xe = MMA8452_FF_MT_SRC_XHE,
910 .ev_src_ye = MMA8452_FF_MT_SRC_YHE,
911 .ev_src_ze = MMA8452_FF_MT_SRC_ZHE,
912 .ev_ths = MMA8452_FF_MT_THS,
913 .ev_ths_mask = MMA8452_FF_MT_THS_MASK,
914 .ev_count = MMA8452_FF_MT_COUNT,
915 },
916 [mma8653] = {
917 .chip_id = MMA8653_DEVICE_ID,
918 .channels = mma8653_channels,
919 .num_channels = ARRAY_SIZE(mma8653_channels),
920 .mma_scales = { {0, 38307}, {0, 76614}, {0, 153228} },
921 .ev_cfg = MMA8452_FF_MT_CFG,
922 .ev_cfg_ele = MMA8452_FF_MT_CFG_ELE,
923 .ev_cfg_chan_shift = 3,
924 .ev_src = MMA8452_FF_MT_SRC,
925 .ev_src_xe = MMA8452_FF_MT_SRC_XHE,
926 .ev_src_ye = MMA8452_FF_MT_SRC_YHE,
927 .ev_src_ze = MMA8452_FF_MT_SRC_ZHE,
928 .ev_ths = MMA8452_FF_MT_THS,
929 .ev_ths_mask = MMA8452_FF_MT_THS_MASK,
930 .ev_count = MMA8452_FF_MT_COUNT,
931 },
932};
933
934static struct attribute *mma8452_attributes[] = {
935 &iio_dev_attr_sampling_frequency_available.dev_attr.attr,
936 &iio_dev_attr_in_accel_scale_available.dev_attr.attr,
937 &iio_dev_attr_in_accel_filter_high_pass_3db_frequency_available.dev_attr.attr,
938 NULL
939};
940
941static const struct attribute_group mma8452_group = {
942 .attrs = mma8452_attributes,
943};
944
945static const struct iio_info mma8452_info = {
946 .attrs = &mma8452_group,
947 .read_raw = &mma8452_read_raw,
948 .write_raw = &mma8452_write_raw,
949 .event_attrs = &mma8452_event_attribute_group,
950 .read_event_value = &mma8452_read_thresh,
951 .write_event_value = &mma8452_write_thresh,
952 .read_event_config = &mma8452_read_event_config,
953 .write_event_config = &mma8452_write_event_config,
954 .debugfs_reg_access = &mma8452_reg_access_dbg,
955 .driver_module = THIS_MODULE,
956};
957
958static const unsigned long mma8452_scan_masks[] = {0x7, 0};
959
960static int mma8452_data_rdy_trigger_set_state(struct iio_trigger *trig,
961 bool state)
962{
963 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
964 struct mma8452_data *data = iio_priv(indio_dev);
965 int reg;
966
967 reg = i2c_smbus_read_byte_data(data->client, MMA8452_CTRL_REG4);
968 if (reg < 0)
969 return reg;
970
971 if (state)
972 reg |= MMA8452_INT_DRDY;
973 else
974 reg &= ~MMA8452_INT_DRDY;
975
976 return mma8452_change_config(data, MMA8452_CTRL_REG4, reg);
977}
978
979static int mma8452_validate_device(struct iio_trigger *trig,
980 struct iio_dev *indio_dev)
981{
982 struct iio_dev *indio = iio_trigger_get_drvdata(trig);
983
984 if (indio != indio_dev)
985 return -EINVAL;
986
987 return 0;
988}
989
990static const struct iio_trigger_ops mma8452_trigger_ops = {
991 .set_trigger_state = mma8452_data_rdy_trigger_set_state,
992 .validate_device = mma8452_validate_device,
993 .owner = THIS_MODULE,
994};
995
996static int mma8452_trigger_setup(struct iio_dev *indio_dev)
997{
998 struct mma8452_data *data = iio_priv(indio_dev);
999 struct iio_trigger *trig;
1000 int ret;
1001
1002 trig = devm_iio_trigger_alloc(&data->client->dev, "%s-dev%d",
1003 indio_dev->name,
1004 indio_dev->id);
1005 if (!trig)
1006 return -ENOMEM;
1007
1008 trig->dev.parent = &data->client->dev;
1009 trig->ops = &mma8452_trigger_ops;
1010 iio_trigger_set_drvdata(trig, indio_dev);
1011
1012 ret = iio_trigger_register(trig);
1013 if (ret)
1014 return ret;
1015
1016 indio_dev->trig = trig;
1017
1018 return 0;
1019}
1020
1021static void mma8452_trigger_cleanup(struct iio_dev *indio_dev)
1022{
1023 if (indio_dev->trig)
1024 iio_trigger_unregister(indio_dev->trig);
1025}
1026
1027static int mma8452_reset(struct i2c_client *client)
1028{
1029 int i;
1030 int ret;
1031
1032 ret = i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG2,
1033 MMA8452_CTRL_REG2_RST);
1034 if (ret < 0)
1035 return ret;
1036
1037 for (i = 0; i < 10; i++) {
1038 usleep_range(100, 200);
1039 ret = i2c_smbus_read_byte_data(client, MMA8452_CTRL_REG2);
1040 if (ret == -EIO)
1041 continue;
1042 if (ret < 0)
1043 return ret;
1044 if (!(ret & MMA8452_CTRL_REG2_RST))
1045 return 0;
1046 }
1047
1048 return -ETIMEDOUT;
1049}
1050
1051static const struct of_device_id mma8452_dt_ids[] = {
1052 { .compatible = "fsl,mma8452", .data = &mma_chip_info_table[mma8452] },
1053 { .compatible = "fsl,mma8453", .data = &mma_chip_info_table[mma8453] },
1054 { .compatible = "fsl,mma8652", .data = &mma_chip_info_table[mma8652] },
1055 { .compatible = "fsl,mma8653", .data = &mma_chip_info_table[mma8653] },
1056 { }
1057};
1058MODULE_DEVICE_TABLE(of, mma8452_dt_ids);
1059
1060static int mma8452_probe(struct i2c_client *client,
1061 const struct i2c_device_id *id)
1062{
1063 struct mma8452_data *data;
1064 struct iio_dev *indio_dev;
1065 int ret;
1066 const struct of_device_id *match;
1067
1068 match = of_match_device(mma8452_dt_ids, &client->dev);
1069 if (!match) {
1070 dev_err(&client->dev, "unknown device model\n");
1071 return -ENODEV;
1072 }
1073
1074 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
1075 if (!indio_dev)
1076 return -ENOMEM;
1077
1078 data = iio_priv(indio_dev);
1079 data->client = client;
1080 mutex_init(&data->lock);
1081 data->chip_info = match->data;
1082
1083 ret = i2c_smbus_read_byte_data(client, MMA8452_WHO_AM_I);
1084 if (ret < 0)
1085 return ret;
1086
1087 switch (ret) {
1088 case MMA8452_DEVICE_ID:
1089 case MMA8453_DEVICE_ID:
1090 case MMA8652_DEVICE_ID:
1091 case MMA8653_DEVICE_ID:
1092 if (ret == data->chip_info->chip_id)
1093 break;
1094 default:
1095 return -ENODEV;
1096 }
1097
1098 dev_info(&client->dev, "registering %s accelerometer; ID 0x%x\n",
1099 match->compatible, data->chip_info->chip_id);
1100
1101 i2c_set_clientdata(client, indio_dev);
1102 indio_dev->info = &mma8452_info;
1103 indio_dev->name = id->name;
1104 indio_dev->dev.parent = &client->dev;
1105 indio_dev->modes = INDIO_DIRECT_MODE;
1106 indio_dev->channels = data->chip_info->channels;
1107 indio_dev->num_channels = data->chip_info->num_channels;
1108 indio_dev->available_scan_masks = mma8452_scan_masks;
1109
1110 ret = mma8452_reset(client);
1111 if (ret < 0)
1112 return ret;
1113
1114 data->data_cfg = MMA8452_DATA_CFG_FS_2G;
1115 ret = i2c_smbus_write_byte_data(client, MMA8452_DATA_CFG,
1116 data->data_cfg);
1117 if (ret < 0)
1118 return ret;
1119
1120
1121
1122
1123
1124 ret = i2c_smbus_write_byte_data(client, MMA8452_TRANSIENT_THS,
1125 MMA8452_TRANSIENT_THS_MASK);
1126 if (ret < 0)
1127 return ret;
1128
1129 if (client->irq) {
1130
1131
1132
1133
1134
1135 int supported_interrupts = MMA8452_INT_DRDY |
1136 MMA8452_INT_TRANS |
1137 MMA8452_INT_FF_MT;
1138 int enabled_interrupts = MMA8452_INT_TRANS |
1139 MMA8452_INT_FF_MT;
1140 int irq2;
1141
1142 irq2 = of_irq_get_byname(client->dev.of_node, "INT2");
1143
1144 if (irq2 == client->irq) {
1145 dev_dbg(&client->dev, "using interrupt line INT2\n");
1146 } else {
1147 ret = i2c_smbus_write_byte_data(client,
1148 MMA8452_CTRL_REG5,
1149 supported_interrupts);
1150 if (ret < 0)
1151 return ret;
1152
1153 dev_dbg(&client->dev, "using interrupt line INT1\n");
1154 }
1155
1156 ret = i2c_smbus_write_byte_data(client,
1157 MMA8452_CTRL_REG4,
1158 enabled_interrupts);
1159 if (ret < 0)
1160 return ret;
1161
1162 ret = mma8452_trigger_setup(indio_dev);
1163 if (ret < 0)
1164 return ret;
1165 }
1166
1167 data->ctrl_reg1 = MMA8452_CTRL_ACTIVE |
1168 (MMA8452_CTRL_DR_DEFAULT << MMA8452_CTRL_DR_SHIFT);
1169 ret = i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG1,
1170 data->ctrl_reg1);
1171 if (ret < 0)
1172 goto trigger_cleanup;
1173
1174 ret = iio_triggered_buffer_setup(indio_dev, NULL,
1175 mma8452_trigger_handler, NULL);
1176 if (ret < 0)
1177 goto trigger_cleanup;
1178
1179 if (client->irq) {
1180 ret = devm_request_threaded_irq(&client->dev,
1181 client->irq,
1182 NULL, mma8452_interrupt,
1183 IRQF_TRIGGER_LOW | IRQF_ONESHOT,
1184 client->name, indio_dev);
1185 if (ret)
1186 goto buffer_cleanup;
1187 }
1188
1189 ret = iio_device_register(indio_dev);
1190 if (ret < 0)
1191 goto buffer_cleanup;
1192
1193 return 0;
1194
1195buffer_cleanup:
1196 iio_triggered_buffer_cleanup(indio_dev);
1197
1198trigger_cleanup:
1199 mma8452_trigger_cleanup(indio_dev);
1200
1201 return ret;
1202}
1203
1204static int mma8452_remove(struct i2c_client *client)
1205{
1206 struct iio_dev *indio_dev = i2c_get_clientdata(client);
1207
1208 iio_device_unregister(indio_dev);
1209 iio_triggered_buffer_cleanup(indio_dev);
1210 mma8452_trigger_cleanup(indio_dev);
1211 mma8452_standby(iio_priv(indio_dev));
1212
1213 return 0;
1214}
1215
1216#ifdef CONFIG_PM_SLEEP
1217static int mma8452_suspend(struct device *dev)
1218{
1219 return mma8452_standby(iio_priv(i2c_get_clientdata(
1220 to_i2c_client(dev))));
1221}
1222
1223static int mma8452_resume(struct device *dev)
1224{
1225 return mma8452_active(iio_priv(i2c_get_clientdata(
1226 to_i2c_client(dev))));
1227}
1228
1229static SIMPLE_DEV_PM_OPS(mma8452_pm_ops, mma8452_suspend, mma8452_resume);
1230#define MMA8452_PM_OPS (&mma8452_pm_ops)
1231#else
1232#define MMA8452_PM_OPS NULL
1233#endif
1234
1235static const struct i2c_device_id mma8452_id[] = {
1236 { "mma8452", mma8452 },
1237 { "mma8453", mma8453 },
1238 { "mma8652", mma8652 },
1239 { "mma8653", mma8653 },
1240 { }
1241};
1242MODULE_DEVICE_TABLE(i2c, mma8452_id);
1243
1244static struct i2c_driver mma8452_driver = {
1245 .driver = {
1246 .name = "mma8452",
1247 .of_match_table = of_match_ptr(mma8452_dt_ids),
1248 .pm = MMA8452_PM_OPS,
1249 },
1250 .probe = mma8452_probe,
1251 .remove = mma8452_remove,
1252 .id_table = mma8452_id,
1253};
1254module_i2c_driver(mma8452_driver);
1255
1256MODULE_AUTHOR("Peter Meerwald <pmeerw@pmeerw.net>");
1257MODULE_DESCRIPTION("Freescale MMA8452 accelerometer driver");
1258MODULE_LICENSE("GPL");
1259
