LXR linux/drivers/infiniband/hw/mthca/mthca

   1/*
   2 * Copyright (c) 2005 Cisco Systems. All rights reserved.
   3 *
   4 * This software is available to you under a choice of one of two
   5 * licenses.  You may choose to be licensed under the terms of the GNU
   6 * General Public License (GPL) Version 2, available from the file
   7 * COPYING in the main directory of this source tree, or the
   8 * OpenIB.org BSD license below:
   9 *
  10 *     Redistribution and use in source and binary forms, with or
  11 *     without modification, are permitted provided that the following
  12 *     conditions are met:
  13 *
  14 *      - Redistributions of source code must retain the above
  15 *        copyright notice, this list of conditions and the following
  16 *        disclaimer.
  17 *
  18 *      - Redistributions in binary form must reproduce the above
  19 *        copyright notice, this list of conditions and the following
  20 *        disclaimer in the documentation and/or other materials
  21 *        provided with the distribution.
  22 *
  23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30 * SOFTWARE.
  31 */
  32
  33#ifndef MTHCA_WQE_H
  34#define MTHCA_WQE_H
  35
  36#include <linux/types.h>
  37
  38enum {
  39        MTHCA_NEXT_DBD          = 1 << 7,
  40        MTHCA_NEXT_FENCE        = 1 << 6,
  41        MTHCA_NEXT_CQ_UPDATE    = 1 << 3,
  42        MTHCA_NEXT_EVENT_GEN    = 1 << 2,
  43        MTHCA_NEXT_SOLICIT      = 1 << 1,
  44        MTHCA_NEXT_IP_CSUM      = 1 << 4,
  45        MTHCA_NEXT_TCP_UDP_CSUM = 1 << 5,
  46
  47        MTHCA_MLX_VL15          = 1 << 17,
  48        MTHCA_MLX_SLR           = 1 << 16
  49};
  50
  51enum {
  52        MTHCA_INVAL_LKEY                        = 0x100,
  53        MTHCA_TAVOR_MAX_WQES_PER_RECV_DB        = 256,
  54        MTHCA_ARBEL_MAX_WQES_PER_SEND_DB        = 255
  55};
  56
  57struct mthca_next_seg {
  58        __be32 nda_op;          /* [31:6] next WQE [4:0] next opcode */
  59        __be32 ee_nds;          /* [31:8] next EE  [7] DBD [6] F [5:0] next WQE size */
  60        __be32 flags;           /* [3] CQ [2] Event [1] Solicit */
  61        __be32 imm;             /* immediate data */
  62};
  63
  64struct mthca_tavor_ud_seg {
  65        u32    reserved1;
  66        __be32 lkey;
  67        __be64 av_addr;
  68        u32    reserved2[4];
  69        __be32 dqpn;
  70        __be32 qkey;
  71        u32    reserved3[2];
  72};
  73
  74struct mthca_arbel_ud_seg {
  75        __be32 av[8];
  76        __be32 dqpn;
  77        __be32 qkey;
  78        u32    reserved[2];
  79};
  80
  81struct mthca_bind_seg {
  82        __be32 flags;           /* [31] Atomic [30] rem write [29] rem read */
  83        u32    reserved;
  84        __be32 new_rkey;
  85        __be32 lkey;
  86        __be64 addr;
  87        __be64 length;
  88};
  89
  90struct mthca_raddr_seg {
  91        __be64 raddr;
  92        __be32 rkey;
  93        u32    reserved;
  94};
  95
  96struct mthca_atomic_seg {
  97        __be64 swap_add;
  98        __be64 compare;
  99};
 100
 101struct mthca_data_seg {
 102        __be32 byte_count;
 103        __be32 lkey;
 104        __be64 addr;
 105};
 106
 107struct mthca_mlx_seg {
 108        __be32 nda_op;
 109        __be32 nds;
 110        __be32 flags;           /* [17] VL15 [16] SLR [14:12] static rate
 111                                   [11:8] SL [3] C [2] E */
 112        __be16 rlid;
 113        __be16 vcrc;
 114};
 115
 116static __always_inline void mthca_set_data_seg(struct mthca_data_seg *dseg,
 117                                               struct ib_sge *sg)
 118{
 119        dseg->byte_count = cpu_to_be32(sg->length);
 120        dseg->lkey       = cpu_to_be32(sg->lkey);
 121        dseg->addr       = cpu_to_be64(sg->addr);
 122}
 123
 124static __always_inline void mthca_set_data_seg_inval(struct mthca_data_seg *dseg)
 125{
 126        dseg->byte_count = 0;
 127        dseg->lkey       = cpu_to_be32(MTHCA_INVAL_LKEY);
 128        dseg->addr       = 0;
 129}
 130
 131#endif /* MTHCA_WQE_H */
 132