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25#include <linux/dma-mapping.h>
26#include <linux/slab.h>
27#include <linux/module.h>
28#include <linux/moduleparam.h>
29#include <linux/platform_device.h>
30#include <linux/of.h>
31#include <linux/of_device.h>
32#include <linux/of_gpio.h>
33#include <linux/of_mtd.h>
34#include <linux/mtd/mtd.h>
35#include <linux/mtd/nand.h>
36#include <linux/mtd/partitions.h>
37#include <linux/clk.h>
38#include <linux/delay.h>
39#include <linux/dmaengine.h>
40#include <linux/gpio.h>
41#include <linux/interrupt.h>
42#include <linux/io.h>
43
44#define NFC_REG_CTL 0x0000
45#define NFC_REG_ST 0x0004
46#define NFC_REG_INT 0x0008
47#define NFC_REG_TIMING_CTL 0x000C
48#define NFC_REG_TIMING_CFG 0x0010
49#define NFC_REG_ADDR_LOW 0x0014
50#define NFC_REG_ADDR_HIGH 0x0018
51#define NFC_REG_SECTOR_NUM 0x001C
52#define NFC_REG_CNT 0x0020
53#define NFC_REG_CMD 0x0024
54#define NFC_REG_RCMD_SET 0x0028
55#define NFC_REG_WCMD_SET 0x002C
56#define NFC_REG_IO_DATA 0x0030
57#define NFC_REG_ECC_CTL 0x0034
58#define NFC_REG_ECC_ST 0x0038
59#define NFC_REG_DEBUG 0x003C
60#define NFC_REG_ECC_ERR_CNT(x) ((0x0040 + (x)) & ~0x3)
61#define NFC_REG_USER_DATA(x) (0x0050 + ((x) * 4))
62#define NFC_REG_SPARE_AREA 0x00A0
63#define NFC_RAM0_BASE 0x0400
64#define NFC_RAM1_BASE 0x0800
65
66
67#define NFC_EN BIT(0)
68#define NFC_RESET BIT(1)
69#define NFC_BUS_WIDTH_MSK BIT(2)
70#define NFC_BUS_WIDTH_8 (0 << 2)
71#define NFC_BUS_WIDTH_16 (1 << 2)
72#define NFC_RB_SEL_MSK BIT(3)
73#define NFC_RB_SEL(x) ((x) << 3)
74#define NFC_CE_SEL_MSK GENMASK(26, 24)
75#define NFC_CE_SEL(x) ((x) << 24)
76#define NFC_CE_CTL BIT(6)
77#define NFC_PAGE_SHIFT_MSK GENMASK(11, 8)
78#define NFC_PAGE_SHIFT(x) (((x) < 10 ? 0 : (x) - 10) << 8)
79#define NFC_SAM BIT(12)
80#define NFC_RAM_METHOD BIT(14)
81#define NFC_DEBUG_CTL BIT(31)
82
83
84#define NFC_RB_B2R BIT(0)
85#define NFC_CMD_INT_FLAG BIT(1)
86#define NFC_DMA_INT_FLAG BIT(2)
87#define NFC_CMD_FIFO_STATUS BIT(3)
88#define NFC_STA BIT(4)
89#define NFC_NATCH_INT_FLAG BIT(5)
90#define NFC_RB_STATE(x) BIT(x + 8)
91
92
93#define NFC_B2R_INT_ENABLE BIT(0)
94#define NFC_CMD_INT_ENABLE BIT(1)
95#define NFC_DMA_INT_ENABLE BIT(2)
96#define NFC_INT_MASK (NFC_B2R_INT_ENABLE | \
97 NFC_CMD_INT_ENABLE | \
98 NFC_DMA_INT_ENABLE)
99
100
101#define NFC_TIMING_CTL_EDO BIT(8)
102
103
104#define NFC_TIMING_CFG(tWB, tADL, tWHR, tRHW, tCAD) \
105 (((tWB) & 0x3) | (((tADL) & 0x3) << 2) | \
106 (((tWHR) & 0x3) << 4) | (((tRHW) & 0x3) << 6) | \
107 (((tCAD) & 0x7) << 8))
108
109
110#define NFC_CMD_LOW_BYTE_MSK GENMASK(7, 0)
111#define NFC_CMD_HIGH_BYTE_MSK GENMASK(15, 8)
112#define NFC_CMD(x) (x)
113#define NFC_ADR_NUM_MSK GENMASK(18, 16)
114#define NFC_ADR_NUM(x) (((x) - 1) << 16)
115#define NFC_SEND_ADR BIT(19)
116#define NFC_ACCESS_DIR BIT(20)
117#define NFC_DATA_TRANS BIT(21)
118#define NFC_SEND_CMD1 BIT(22)
119#define NFC_WAIT_FLAG BIT(23)
120#define NFC_SEND_CMD2 BIT(24)
121#define NFC_SEQ BIT(25)
122#define NFC_DATA_SWAP_METHOD BIT(26)
123#define NFC_ROW_AUTO_INC BIT(27)
124#define NFC_SEND_CMD3 BIT(28)
125#define NFC_SEND_CMD4 BIT(29)
126#define NFC_CMD_TYPE_MSK GENMASK(31, 30)
127#define NFC_NORMAL_OP (0 << 30)
128#define NFC_ECC_OP (1 << 30)
129#define NFC_PAGE_OP (2 << 30)
130
131
132#define NFC_READ_CMD_MSK GENMASK(7, 0)
133#define NFC_RND_READ_CMD0_MSK GENMASK(15, 8)
134#define NFC_RND_READ_CMD1_MSK GENMASK(23, 16)
135
136
137#define NFC_PROGRAM_CMD_MSK GENMASK(7, 0)
138#define NFC_RND_WRITE_CMD_MSK GENMASK(15, 8)
139#define NFC_READ_CMD0_MSK GENMASK(23, 16)
140#define NFC_READ_CMD1_MSK GENMASK(31, 24)
141
142
143#define NFC_ECC_EN BIT(0)
144#define NFC_ECC_PIPELINE BIT(3)
145#define NFC_ECC_EXCEPTION BIT(4)
146#define NFC_ECC_BLOCK_SIZE_MSK BIT(5)
147#define NFC_RANDOM_EN BIT(9)
148#define NFC_RANDOM_DIRECTION BIT(10)
149#define NFC_ECC_MODE_MSK GENMASK(15, 12)
150#define NFC_ECC_MODE(x) ((x) << 12)
151#define NFC_RANDOM_SEED_MSK GENMASK(30, 16)
152#define NFC_RANDOM_SEED(x) ((x) << 16)
153
154
155#define NFC_ECC_ERR(x) BIT(x)
156#define NFC_ECC_PAT_FOUND(x) BIT(x + 16)
157#define NFC_ECC_ERR_CNT(b, x) (((x) >> ((b) * 8)) & 0xff)
158
159#define NFC_DEFAULT_TIMEOUT_MS 1000
160
161#define NFC_SRAM_SIZE 1024
162
163#define NFC_MAX_CS 7
164
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177
178enum sunxi_nand_rb_type {
179 RB_NONE,
180 RB_NATIVE,
181 RB_GPIO,
182};
183
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191struct sunxi_nand_rb {
192 enum sunxi_nand_rb_type type;
193 union {
194 int gpio;
195 int nativeid;
196 } info;
197};
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205struct sunxi_nand_chip_sel {
206 u8 cs;
207 struct sunxi_nand_rb rb;
208};
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217struct sunxi_nand_hw_ecc {
218 int mode;
219 struct nand_ecclayout layout;
220};
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234struct sunxi_nand_chip {
235 struct list_head node;
236 struct nand_chip nand;
237 unsigned long clk_rate;
238 u32 timing_cfg;
239 u32 timing_ctl;
240 int selected;
241 int nsels;
242 struct sunxi_nand_chip_sel sels[0];
243};
244
245static inline struct sunxi_nand_chip *to_sunxi_nand(struct nand_chip *nand)
246{
247 return container_of(nand, struct sunxi_nand_chip, nand);
248}
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265struct sunxi_nfc {
266 struct nand_hw_control controller;
267 struct device *dev;
268 void __iomem *regs;
269 struct clk *ahb_clk;
270 struct clk *mod_clk;
271 unsigned long assigned_cs;
272 unsigned long clk_rate;
273 struct list_head chips;
274 struct completion complete;
275};
276
277static inline struct sunxi_nfc *to_sunxi_nfc(struct nand_hw_control *ctrl)
278{
279 return container_of(ctrl, struct sunxi_nfc, controller);
280}
281
282static irqreturn_t sunxi_nfc_interrupt(int irq, void *dev_id)
283{
284 struct sunxi_nfc *nfc = dev_id;
285 u32 st = readl(nfc->regs + NFC_REG_ST);
286 u32 ien = readl(nfc->regs + NFC_REG_INT);
287
288 if (!(ien & st))
289 return IRQ_NONE;
290
291 if ((ien & st) == ien)
292 complete(&nfc->complete);
293
294 writel(st & NFC_INT_MASK, nfc->regs + NFC_REG_ST);
295 writel(~st & ien & NFC_INT_MASK, nfc->regs + NFC_REG_INT);
296
297 return IRQ_HANDLED;
298}
299
300static int sunxi_nfc_wait_int(struct sunxi_nfc *nfc, u32 flags,
301 unsigned int timeout_ms)
302{
303 init_completion(&nfc->complete);
304
305 writel(flags, nfc->regs + NFC_REG_INT);
306
307 if (!timeout_ms)
308 timeout_ms = NFC_DEFAULT_TIMEOUT_MS;
309
310 if (!wait_for_completion_timeout(&nfc->complete,
311 msecs_to_jiffies(timeout_ms))) {
312 dev_err(nfc->dev, "wait interrupt timedout\n");
313 return -ETIMEDOUT;
314 }
315
316 return 0;
317}
318
319static int sunxi_nfc_wait_cmd_fifo_empty(struct sunxi_nfc *nfc)
320{
321 unsigned long timeout = jiffies +
322 msecs_to_jiffies(NFC_DEFAULT_TIMEOUT_MS);
323
324 do {
325 if (!(readl(nfc->regs + NFC_REG_ST) & NFC_CMD_FIFO_STATUS))
326 return 0;
327 } while (time_before(jiffies, timeout));
328
329 dev_err(nfc->dev, "wait for empty cmd FIFO timedout\n");
330 return -ETIMEDOUT;
331}
332
333static int sunxi_nfc_rst(struct sunxi_nfc *nfc)
334{
335 unsigned long timeout = jiffies +
336 msecs_to_jiffies(NFC_DEFAULT_TIMEOUT_MS);
337
338 writel(0, nfc->regs + NFC_REG_ECC_CTL);
339 writel(NFC_RESET, nfc->regs + NFC_REG_CTL);
340
341 do {
342 if (!(readl(nfc->regs + NFC_REG_CTL) & NFC_RESET))
343 return 0;
344 } while (time_before(jiffies, timeout));
345
346 dev_err(nfc->dev, "wait for NAND controller reset timedout\n");
347 return -ETIMEDOUT;
348}
349
350static int sunxi_nfc_dev_ready(struct mtd_info *mtd)
351{
352 struct nand_chip *nand = mtd_to_nand(mtd);
353 struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
354 struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
355 struct sunxi_nand_rb *rb;
356 unsigned long timeo = (sunxi_nand->nand.state == FL_ERASING ? 400 : 20);
357 int ret;
358
359 if (sunxi_nand->selected < 0)
360 return 0;
361
362 rb = &sunxi_nand->sels[sunxi_nand->selected].rb;
363
364 switch (rb->type) {
365 case RB_NATIVE:
366 ret = !!(readl(nfc->regs + NFC_REG_ST) &
367 NFC_RB_STATE(rb->info.nativeid));
368 if (ret)
369 break;
370
371 sunxi_nfc_wait_int(nfc, NFC_RB_B2R, timeo);
372 ret = !!(readl(nfc->regs + NFC_REG_ST) &
373 NFC_RB_STATE(rb->info.nativeid));
374 break;
375 case RB_GPIO:
376 ret = gpio_get_value(rb->info.gpio);
377 break;
378 case RB_NONE:
379 default:
380 ret = 0;
381 dev_err(nfc->dev, "cannot check R/B NAND status!\n");
382 break;
383 }
384
385 return ret;
386}
387
388static void sunxi_nfc_select_chip(struct mtd_info *mtd, int chip)
389{
390 struct nand_chip *nand = mtd_to_nand(mtd);
391 struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
392 struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
393 struct sunxi_nand_chip_sel *sel;
394 u32 ctl;
395
396 if (chip > 0 && chip >= sunxi_nand->nsels)
397 return;
398
399 if (chip == sunxi_nand->selected)
400 return;
401
402 ctl = readl(nfc->regs + NFC_REG_CTL) &
403 ~(NFC_PAGE_SHIFT_MSK | NFC_CE_SEL_MSK | NFC_RB_SEL_MSK | NFC_EN);
404
405 if (chip >= 0) {
406 sel = &sunxi_nand->sels[chip];
407
408 ctl |= NFC_CE_SEL(sel->cs) | NFC_EN |
409 NFC_PAGE_SHIFT(nand->page_shift - 10);
410 if (sel->rb.type == RB_NONE) {
411 nand->dev_ready = NULL;
412 } else {
413 nand->dev_ready = sunxi_nfc_dev_ready;
414 if (sel->rb.type == RB_NATIVE)
415 ctl |= NFC_RB_SEL(sel->rb.info.nativeid);
416 }
417
418 writel(mtd->writesize, nfc->regs + NFC_REG_SPARE_AREA);
419
420 if (nfc->clk_rate != sunxi_nand->clk_rate) {
421 clk_set_rate(nfc->mod_clk, sunxi_nand->clk_rate);
422 nfc->clk_rate = sunxi_nand->clk_rate;
423 }
424 }
425
426 writel(sunxi_nand->timing_ctl, nfc->regs + NFC_REG_TIMING_CTL);
427 writel(sunxi_nand->timing_cfg, nfc->regs + NFC_REG_TIMING_CFG);
428 writel(ctl, nfc->regs + NFC_REG_CTL);
429
430 sunxi_nand->selected = chip;
431}
432
433static void sunxi_nfc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
434{
435 struct nand_chip *nand = mtd_to_nand(mtd);
436 struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
437 struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
438 int ret;
439 int cnt;
440 int offs = 0;
441 u32 tmp;
442
443 while (len > offs) {
444 cnt = min(len - offs, NFC_SRAM_SIZE);
445
446 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
447 if (ret)
448 break;
449
450 writel(cnt, nfc->regs + NFC_REG_CNT);
451 tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD;
452 writel(tmp, nfc->regs + NFC_REG_CMD);
453
454 ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
455 if (ret)
456 break;
457
458 if (buf)
459 memcpy_fromio(buf + offs, nfc->regs + NFC_RAM0_BASE,
460 cnt);
461 offs += cnt;
462 }
463}
464
465static void sunxi_nfc_write_buf(struct mtd_info *mtd, const uint8_t *buf,
466 int len)
467{
468 struct nand_chip *nand = mtd_to_nand(mtd);
469 struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
470 struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
471 int ret;
472 int cnt;
473 int offs = 0;
474 u32 tmp;
475
476 while (len > offs) {
477 cnt = min(len - offs, NFC_SRAM_SIZE);
478
479 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
480 if (ret)
481 break;
482
483 writel(cnt, nfc->regs + NFC_REG_CNT);
484 memcpy_toio(nfc->regs + NFC_RAM0_BASE, buf + offs, cnt);
485 tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD |
486 NFC_ACCESS_DIR;
487 writel(tmp, nfc->regs + NFC_REG_CMD);
488
489 ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
490 if (ret)
491 break;
492
493 offs += cnt;
494 }
495}
496
497static uint8_t sunxi_nfc_read_byte(struct mtd_info *mtd)
498{
499 uint8_t ret;
500
501 sunxi_nfc_read_buf(mtd, &ret, 1);
502
503 return ret;
504}
505
506static void sunxi_nfc_cmd_ctrl(struct mtd_info *mtd, int dat,
507 unsigned int ctrl)
508{
509 struct nand_chip *nand = mtd_to_nand(mtd);
510 struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
511 struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
512 int ret;
513 u32 tmp;
514
515 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
516 if (ret)
517 return;
518
519 if (ctrl & NAND_CTRL_CHANGE) {
520 tmp = readl(nfc->regs + NFC_REG_CTL);
521 if (ctrl & NAND_NCE)
522 tmp |= NFC_CE_CTL;
523 else
524 tmp &= ~NFC_CE_CTL;
525 writel(tmp, nfc->regs + NFC_REG_CTL);
526 }
527
528 if (dat == NAND_CMD_NONE)
529 return;
530
531 if (ctrl & NAND_CLE) {
532 writel(NFC_SEND_CMD1 | dat, nfc->regs + NFC_REG_CMD);
533 } else {
534 writel(dat, nfc->regs + NFC_REG_ADDR_LOW);
535 writel(NFC_SEND_ADR, nfc->regs + NFC_REG_CMD);
536 }
537
538 sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
539}
540
541static void sunxi_nfc_hw_ecc_enable(struct mtd_info *mtd)
542{
543 struct nand_chip *nand = mtd_to_nand(mtd);
544 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
545 struct sunxi_nand_hw_ecc *data = nand->ecc.priv;
546 u32 ecc_ctl;
547
548 ecc_ctl = readl(nfc->regs + NFC_REG_ECC_CTL);
549 ecc_ctl &= ~(NFC_ECC_MODE_MSK | NFC_ECC_PIPELINE |
550 NFC_ECC_BLOCK_SIZE_MSK);
551 ecc_ctl |= NFC_ECC_EN | NFC_ECC_MODE(data->mode) | NFC_ECC_EXCEPTION;
552
553 writel(ecc_ctl, nfc->regs + NFC_REG_ECC_CTL);
554}
555
556static void sunxi_nfc_hw_ecc_disable(struct mtd_info *mtd)
557{
558 struct nand_chip *nand = mtd_to_nand(mtd);
559 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
560
561 writel(readl(nfc->regs + NFC_REG_ECC_CTL) & ~NFC_ECC_EN,
562 nfc->regs + NFC_REG_ECC_CTL);
563}
564
565static inline void sunxi_nfc_user_data_to_buf(u32 user_data, u8 *buf)
566{
567 buf[0] = user_data;
568 buf[1] = user_data >> 8;
569 buf[2] = user_data >> 16;
570 buf[3] = user_data >> 24;
571}
572
573static int sunxi_nfc_hw_ecc_read_chunk(struct mtd_info *mtd,
574 u8 *data, int data_off,
575 u8 *oob, int oob_off,
576 int *cur_off,
577 unsigned int *max_bitflips)
578{
579 struct nand_chip *nand = mtd_to_nand(mtd);
580 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
581 struct nand_ecc_ctrl *ecc = &nand->ecc;
582 u32 status;
583 int ret;
584
585 if (*cur_off != data_off)
586 nand->cmdfunc(mtd, NAND_CMD_RNDOUT, data_off, -1);
587
588 sunxi_nfc_read_buf(mtd, NULL, ecc->size);
589
590 if (data_off + ecc->size != oob_off)
591 nand->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_off, -1);
592
593 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
594 if (ret)
595 return ret;
596
597 writel(NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD | NFC_ECC_OP,
598 nfc->regs + NFC_REG_CMD);
599
600 ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
601 if (ret)
602 return ret;
603
604 status = readl(nfc->regs + NFC_REG_ECC_ST);
605 ret = NFC_ECC_ERR_CNT(0, readl(nfc->regs + NFC_REG_ECC_ERR_CNT(0)));
606
607 memcpy_fromio(data, nfc->regs + NFC_RAM0_BASE, ecc->size);
608
609 nand->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_off, -1);
610 sunxi_nfc_read_buf(mtd, oob, ecc->bytes + 4);
611
612 if (status & NFC_ECC_ERR(0)) {
613 ret = nand_check_erased_ecc_chunk(data, ecc->size,
614 oob, ecc->bytes + 4,
615 NULL, 0, ecc->strength);
616 } else {
617
618
619
620
621 sunxi_nfc_user_data_to_buf(readl(nfc->regs + NFC_REG_USER_DATA(0)),
622 oob);
623 }
624
625 if (ret < 0) {
626 mtd->ecc_stats.failed++;
627 } else {
628 mtd->ecc_stats.corrected += ret;
629 *max_bitflips = max_t(unsigned int, *max_bitflips, ret);
630 }
631
632 *cur_off = oob_off + ecc->bytes + 4;
633
634 return 0;
635}
636
637static void sunxi_nfc_hw_ecc_read_extra_oob(struct mtd_info *mtd,
638 u8 *oob, int *cur_off)
639{
640 struct nand_chip *nand = mtd_to_nand(mtd);
641 struct nand_ecc_ctrl *ecc = &nand->ecc;
642 int offset = ((ecc->bytes + 4) * ecc->steps);
643 int len = mtd->oobsize - offset;
644
645 if (len <= 0)
646 return;
647
648 if (*cur_off != offset)
649 nand->cmdfunc(mtd, NAND_CMD_RNDOUT,
650 offset + mtd->writesize, -1);
651
652 sunxi_nfc_read_buf(mtd, oob + offset, len);
653
654 *cur_off = mtd->oobsize + mtd->writesize;
655}
656
657static inline u32 sunxi_nfc_buf_to_user_data(const u8 *buf)
658{
659 return buf[0] | (buf[1] << 8) | (buf[2] << 16) | (buf[3] << 24);
660}
661
662static int sunxi_nfc_hw_ecc_write_chunk(struct mtd_info *mtd,
663 const u8 *data, int data_off,
664 const u8 *oob, int oob_off,
665 int *cur_off)
666{
667 struct nand_chip *nand = mtd_to_nand(mtd);
668 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
669 struct nand_ecc_ctrl *ecc = &nand->ecc;
670 int ret;
671
672 if (data_off != *cur_off)
673 nand->cmdfunc(mtd, NAND_CMD_RNDIN, data_off, -1);
674
675 sunxi_nfc_write_buf(mtd, data, ecc->size);
676
677
678 writel(sunxi_nfc_buf_to_user_data(oob),
679 nfc->regs + NFC_REG_USER_DATA(0));
680
681 if (data_off + ecc->size != oob_off)
682 nand->cmdfunc(mtd, NAND_CMD_RNDIN, oob_off, -1);
683
684 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
685 if (ret)
686 return ret;
687
688 writel(NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD |
689 NFC_ACCESS_DIR | NFC_ECC_OP,
690 nfc->regs + NFC_REG_CMD);
691
692 ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
693 if (ret)
694 return ret;
695
696 *cur_off = oob_off + ecc->bytes + 4;
697
698 return 0;
699}
700
701static void sunxi_nfc_hw_ecc_write_extra_oob(struct mtd_info *mtd,
702 u8 *oob, int *cur_off)
703{
704 struct nand_chip *nand = mtd_to_nand(mtd);
705 struct nand_ecc_ctrl *ecc = &nand->ecc;
706 int offset = ((ecc->bytes + 4) * ecc->steps);
707 int len = mtd->oobsize - offset;
708
709 if (len <= 0)
710 return;
711
712 if (*cur_off != offset)
713 nand->cmdfunc(mtd, NAND_CMD_RNDIN,
714 offset + mtd->writesize, -1);
715
716 sunxi_nfc_write_buf(mtd, oob + offset, len);
717
718 *cur_off = mtd->oobsize + mtd->writesize;
719}
720
721static int sunxi_nfc_hw_ecc_read_page(struct mtd_info *mtd,
722 struct nand_chip *chip, uint8_t *buf,
723 int oob_required, int page)
724{
725 struct nand_ecc_ctrl *ecc = &chip->ecc;
726 unsigned int max_bitflips = 0;
727 int ret, i, cur_off = 0;
728
729 sunxi_nfc_hw_ecc_enable(mtd);
730
731 for (i = 0; i < ecc->steps; i++) {
732 int data_off = i * ecc->size;
733 int oob_off = i * (ecc->bytes + 4);
734 u8 *data = buf + data_off;
735 u8 *oob = chip->oob_poi + oob_off;
736
737 ret = sunxi_nfc_hw_ecc_read_chunk(mtd, data, data_off, oob,
738 oob_off + mtd->writesize,
739 &cur_off, &max_bitflips);
740 if (ret)
741 return ret;
742 }
743
744 if (oob_required)
745 sunxi_nfc_hw_ecc_read_extra_oob(mtd, chip->oob_poi, &cur_off);
746
747 sunxi_nfc_hw_ecc_disable(mtd);
748
749 return max_bitflips;
750}
751
752static int sunxi_nfc_hw_ecc_write_page(struct mtd_info *mtd,
753 struct nand_chip *chip,
754 const uint8_t *buf, int oob_required,
755 int page)
756{
757 struct nand_ecc_ctrl *ecc = &chip->ecc;
758 int ret, i, cur_off = 0;
759
760 sunxi_nfc_hw_ecc_enable(mtd);
761
762 for (i = 0; i < ecc->steps; i++) {
763 int data_off = i * ecc->size;
764 int oob_off = i * (ecc->bytes + 4);
765 const u8 *data = buf + data_off;
766 const u8 *oob = chip->oob_poi + oob_off;
767
768 ret = sunxi_nfc_hw_ecc_write_chunk(mtd, data, data_off, oob,
769 oob_off + mtd->writesize,
770 &cur_off);
771 if (ret)
772 return ret;
773 }
774
775 if (oob_required)
776 sunxi_nfc_hw_ecc_write_extra_oob(mtd, chip->oob_poi, &cur_off);
777
778 sunxi_nfc_hw_ecc_disable(mtd);
779
780 return 0;
781}
782
783static int sunxi_nfc_hw_syndrome_ecc_read_page(struct mtd_info *mtd,
784 struct nand_chip *chip,
785 uint8_t *buf, int oob_required,
786 int page)
787{
788 struct nand_ecc_ctrl *ecc = &chip->ecc;
789 unsigned int max_bitflips = 0;
790 int ret, i, cur_off = 0;
791
792 sunxi_nfc_hw_ecc_enable(mtd);
793
794 for (i = 0; i < ecc->steps; i++) {
795 int data_off = i * (ecc->size + ecc->bytes + 4);
796 int oob_off = data_off + ecc->size;
797 u8 *data = buf + (i * ecc->size);
798 u8 *oob = chip->oob_poi + (i * (ecc->bytes + 4));
799
800 ret = sunxi_nfc_hw_ecc_read_chunk(mtd, data, data_off, oob,
801 oob_off, &cur_off,
802 &max_bitflips);
803 if (ret)
804 return ret;
805 }
806
807 if (oob_required)
808 sunxi_nfc_hw_ecc_read_extra_oob(mtd, chip->oob_poi, &cur_off);
809
810 sunxi_nfc_hw_ecc_disable(mtd);
811
812 return max_bitflips;
813}
814
815static int sunxi_nfc_hw_syndrome_ecc_write_page(struct mtd_info *mtd,
816 struct nand_chip *chip,
817 const uint8_t *buf,
818 int oob_required, int page)
819{
820 struct nand_ecc_ctrl *ecc = &chip->ecc;
821 int ret, i, cur_off = 0;
822
823 sunxi_nfc_hw_ecc_enable(mtd);
824
825 for (i = 0; i < ecc->steps; i++) {
826 int data_off = i * (ecc->size + ecc->bytes + 4);
827 int oob_off = data_off + ecc->size;
828 const u8 *data = buf + (i * ecc->size);
829 const u8 *oob = chip->oob_poi + (i * (ecc->bytes + 4));
830
831 ret = sunxi_nfc_hw_ecc_write_chunk(mtd, data, data_off,
832 oob, oob_off, &cur_off);
833 if (ret)
834 return ret;
835 }
836
837 if (oob_required)
838 sunxi_nfc_hw_ecc_write_extra_oob(mtd, chip->oob_poi, &cur_off);
839
840 sunxi_nfc_hw_ecc_disable(mtd);
841
842 return 0;
843}
844
845static const s32 tWB_lut[] = {6, 12, 16, 20};
846static const s32 tRHW_lut[] = {4, 8, 12, 20};
847
848static int _sunxi_nand_lookup_timing(const s32 *lut, int lut_size, u32 duration,
849 u32 clk_period)
850{
851 u32 clk_cycles = DIV_ROUND_UP(duration, clk_period);
852 int i;
853
854 for (i = 0; i < lut_size; i++) {
855 if (clk_cycles <= lut[i])
856 return i;
857 }
858
859
860 return -EINVAL;
861}
862
863#define sunxi_nand_lookup_timing(l, p, c) \
864 _sunxi_nand_lookup_timing(l, ARRAY_SIZE(l), p, c)
865
866static int sunxi_nand_chip_set_timings(struct sunxi_nand_chip *chip,
867 const struct nand_sdr_timings *timings)
868{
869 struct sunxi_nfc *nfc = to_sunxi_nfc(chip->nand.controller);
870 u32 min_clk_period = 0;
871 s32 tWB, tADL, tWHR, tRHW, tCAD;
872
873
874 if (timings->tCLS_min > min_clk_period)
875 min_clk_period = timings->tCLS_min;
876
877
878 if (timings->tCLH_min > min_clk_period)
879 min_clk_period = timings->tCLH_min;
880
881
882 if (timings->tCS_min > min_clk_period)
883 min_clk_period = timings->tCS_min;
884
885
886 if (timings->tCH_min > min_clk_period)
887 min_clk_period = timings->tCH_min;
888
889
890 if (timings->tWP_min > min_clk_period)
891 min_clk_period = timings->tWP_min;
892
893
894 if (timings->tWH_min > min_clk_period)
895 min_clk_period = timings->tWH_min;
896
897
898 if (timings->tALS_min > min_clk_period)
899 min_clk_period = timings->tALS_min;
900
901
902 if (timings->tDS_min > min_clk_period)
903 min_clk_period = timings->tDS_min;
904
905
906 if (timings->tDH_min > min_clk_period)
907 min_clk_period = timings->tDH_min;
908
909
910 if (timings->tRR_min > (min_clk_period * 3))
911 min_clk_period = DIV_ROUND_UP(timings->tRR_min, 3);
912
913
914 if (timings->tALH_min > min_clk_period)
915 min_clk_period = timings->tALH_min;
916
917
918 if (timings->tRP_min > min_clk_period)
919 min_clk_period = timings->tRP_min;
920
921
922 if (timings->tREH_min > min_clk_period)
923 min_clk_period = timings->tREH_min;
924
925
926 if (timings->tRC_min > (min_clk_period * 2))
927 min_clk_period = DIV_ROUND_UP(timings->tRC_min, 2);
928
929
930 if (timings->tWC_min > (min_clk_period * 2))
931 min_clk_period = DIV_ROUND_UP(timings->tWC_min, 2);
932
933
934 tWB = sunxi_nand_lookup_timing(tWB_lut, timings->tWB_max,
935 min_clk_period);
936 if (tWB < 0) {
937 dev_err(nfc->dev, "unsupported tWB\n");
938 return tWB;
939 }
940
941 tADL = DIV_ROUND_UP(timings->tADL_min, min_clk_period) >> 3;
942 if (tADL > 3) {
943 dev_err(nfc->dev, "unsupported tADL\n");
944 return -EINVAL;
945 }
946
947 tWHR = DIV_ROUND_UP(timings->tWHR_min, min_clk_period) >> 3;
948 if (tWHR > 3) {
949 dev_err(nfc->dev, "unsupported tWHR\n");
950 return -EINVAL;
951 }
952
953 tRHW = sunxi_nand_lookup_timing(tRHW_lut, timings->tRHW_min,
954 min_clk_period);
955 if (tRHW < 0) {
956 dev_err(nfc->dev, "unsupported tRHW\n");
957 return tRHW;
958 }
959
960
961
962
963
964 tCAD = 0x7;
965
966
967 chip->timing_cfg = NFC_TIMING_CFG(tWB, tADL, tWHR, tRHW, tCAD);
968
969
970
971
972
973
974 chip->timing_ctl = (timings->tRC_min < 30000) ? NFC_TIMING_CTL_EDO : 0;
975
976
977 min_clk_period = DIV_ROUND_UP(min_clk_period, 1000);
978
979
980
981
982
983
984
985 chip->clk_rate = (2 * NSEC_PER_SEC) / min_clk_period;
986
987 return 0;
988}
989
990static int sunxi_nand_chip_init_timings(struct sunxi_nand_chip *chip,
991 struct device_node *np)
992{
993 struct mtd_info *mtd = nand_to_mtd(&chip->nand);
994 const struct nand_sdr_timings *timings;
995 int ret;
996 int mode;
997
998 mode = onfi_get_async_timing_mode(&chip->nand);
999 if (mode == ONFI_TIMING_MODE_UNKNOWN) {
1000 mode = chip->nand.onfi_timing_mode_default;
1001 } else {
1002 uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {};
1003 int i;
1004
1005 mode = fls(mode) - 1;
1006 if (mode < 0)
1007 mode = 0;
1008
1009 feature[0] = mode;
1010 for (i = 0; i < chip->nsels; i++) {
1011 chip->nand.select_chip(mtd, i);
1012 ret = chip->nand.onfi_set_features(mtd, &chip->nand,
1013 ONFI_FEATURE_ADDR_TIMING_MODE,
1014 feature);
1015 chip->nand.select_chip(mtd, -1);
1016 if (ret)
1017 return ret;
1018 }
1019 }
1020
1021 timings = onfi_async_timing_mode_to_sdr_timings(mode);
1022 if (IS_ERR(timings))
1023 return PTR_ERR(timings);
1024
1025 return sunxi_nand_chip_set_timings(chip, timings);
1026}
1027
1028static int sunxi_nand_hw_common_ecc_ctrl_init(struct mtd_info *mtd,
1029 struct nand_ecc_ctrl *ecc,
1030 struct device_node *np)
1031{
1032 static const u8 strengths[] = { 16, 24, 28, 32, 40, 48, 56, 60, 64 };
1033 struct nand_chip *nand = mtd_to_nand(mtd);
1034 struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
1035 struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
1036 struct sunxi_nand_hw_ecc *data;
1037 struct nand_ecclayout *layout;
1038 int nsectors;
1039 int ret;
1040 int i;
1041
1042 data = kzalloc(sizeof(*data), GFP_KERNEL);
1043 if (!data)
1044 return -ENOMEM;
1045
1046
1047 for (i = 0; i < ARRAY_SIZE(strengths); i++) {
1048 if (ecc->strength <= strengths[i])
1049 break;
1050 }
1051
1052 if (i >= ARRAY_SIZE(strengths)) {
1053 dev_err(nfc->dev, "unsupported strength\n");
1054 ret = -ENOTSUPP;
1055 goto err;
1056 }
1057
1058 data->mode = i;
1059
1060
1061 ecc->bytes = DIV_ROUND_UP(ecc->strength * fls(8 * 1024), 8);
1062
1063
1064 ecc->bytes = ALIGN(ecc->bytes, 2);
1065
1066 layout = &data->layout;
1067 nsectors = mtd->writesize / ecc->size;
1068
1069 if (mtd->oobsize < ((ecc->bytes + 4) * nsectors)) {
1070 ret = -EINVAL;
1071 goto err;
1072 }
1073
1074 layout->eccbytes = (ecc->bytes * nsectors);
1075
1076 ecc->layout = layout;
1077 ecc->priv = data;
1078
1079 return 0;
1080
1081err:
1082 kfree(data);
1083
1084 return ret;
1085}
1086
1087static void sunxi_nand_hw_common_ecc_ctrl_cleanup(struct nand_ecc_ctrl *ecc)
1088{
1089 kfree(ecc->priv);
1090}
1091
1092static int sunxi_nand_hw_ecc_ctrl_init(struct mtd_info *mtd,
1093 struct nand_ecc_ctrl *ecc,
1094 struct device_node *np)
1095{
1096 struct nand_ecclayout *layout;
1097 int nsectors;
1098 int i, j;
1099 int ret;
1100
1101 ret = sunxi_nand_hw_common_ecc_ctrl_init(mtd, ecc, np);
1102 if (ret)
1103 return ret;
1104
1105 ecc->read_page = sunxi_nfc_hw_ecc_read_page;
1106 ecc->write_page = sunxi_nfc_hw_ecc_write_page;
1107 layout = ecc->layout;
1108 nsectors = mtd->writesize / ecc->size;
1109
1110 for (i = 0; i < nsectors; i++) {
1111 if (i) {
1112 layout->oobfree[i].offset =
1113 layout->oobfree[i - 1].offset +
1114 layout->oobfree[i - 1].length +
1115 ecc->bytes;
1116 layout->oobfree[i].length = 4;
1117 } else {
1118
1119
1120
1121
1122
1123 layout->oobfree[i].length = 2;
1124 layout->oobfree[i].offset = 2;
1125 }
1126
1127 for (j = 0; j < ecc->bytes; j++)
1128 layout->eccpos[(ecc->bytes * i) + j] =
1129 layout->oobfree[i].offset +
1130 layout->oobfree[i].length + j;
1131 }
1132
1133 if (mtd->oobsize > (ecc->bytes + 4) * nsectors) {
1134 layout->oobfree[nsectors].offset =
1135 layout->oobfree[nsectors - 1].offset +
1136 layout->oobfree[nsectors - 1].length +
1137 ecc->bytes;
1138 layout->oobfree[nsectors].length = mtd->oobsize -
1139 ((ecc->bytes + 4) * nsectors);
1140 }
1141
1142 return 0;
1143}
1144
1145static int sunxi_nand_hw_syndrome_ecc_ctrl_init(struct mtd_info *mtd,
1146 struct nand_ecc_ctrl *ecc,
1147 struct device_node *np)
1148{
1149 struct nand_ecclayout *layout;
1150 int nsectors;
1151 int i;
1152 int ret;
1153
1154 ret = sunxi_nand_hw_common_ecc_ctrl_init(mtd, ecc, np);
1155 if (ret)
1156 return ret;
1157
1158 ecc->prepad = 4;
1159 ecc->read_page = sunxi_nfc_hw_syndrome_ecc_read_page;
1160 ecc->write_page = sunxi_nfc_hw_syndrome_ecc_write_page;
1161
1162 layout = ecc->layout;
1163 nsectors = mtd->writesize / ecc->size;
1164
1165 for (i = 0; i < (ecc->bytes * nsectors); i++)
1166 layout->eccpos[i] = i;
1167
1168 layout->oobfree[0].length = mtd->oobsize - i;
1169 layout->oobfree[0].offset = i;
1170
1171 return 0;
1172}
1173
1174static void sunxi_nand_ecc_cleanup(struct nand_ecc_ctrl *ecc)
1175{
1176 switch (ecc->mode) {
1177 case NAND_ECC_HW:
1178 case NAND_ECC_HW_SYNDROME:
1179 sunxi_nand_hw_common_ecc_ctrl_cleanup(ecc);
1180 break;
1181 case NAND_ECC_NONE:
1182 kfree(ecc->layout);
1183 default:
1184 break;
1185 }
1186}
1187
1188static int sunxi_nand_ecc_init(struct mtd_info *mtd, struct nand_ecc_ctrl *ecc,
1189 struct device_node *np)
1190{
1191 struct nand_chip *nand = mtd_to_nand(mtd);
1192 int ret;
1193
1194 if (!ecc->size) {
1195 ecc->size = nand->ecc_step_ds;
1196 ecc->strength = nand->ecc_strength_ds;
1197 }
1198
1199 if (!ecc->size || !ecc->strength)
1200 return -EINVAL;
1201
1202 switch (ecc->mode) {
1203 case NAND_ECC_SOFT_BCH:
1204 break;
1205 case NAND_ECC_HW:
1206 ret = sunxi_nand_hw_ecc_ctrl_init(mtd, ecc, np);
1207 if (ret)
1208 return ret;
1209 break;
1210 case NAND_ECC_HW_SYNDROME:
1211 ret = sunxi_nand_hw_syndrome_ecc_ctrl_init(mtd, ecc, np);
1212 if (ret)
1213 return ret;
1214 break;
1215 case NAND_ECC_NONE:
1216 ecc->layout = kzalloc(sizeof(*ecc->layout), GFP_KERNEL);
1217 if (!ecc->layout)
1218 return -ENOMEM;
1219 ecc->layout->oobfree[0].length = mtd->oobsize;
1220 case NAND_ECC_SOFT:
1221 break;
1222 default:
1223 return -EINVAL;
1224 }
1225
1226 return 0;
1227}
1228
1229static int sunxi_nand_chip_init(struct device *dev, struct sunxi_nfc *nfc,
1230 struct device_node *np)
1231{
1232 const struct nand_sdr_timings *timings;
1233 struct sunxi_nand_chip *chip;
1234 struct mtd_info *mtd;
1235 struct nand_chip *nand;
1236 int nsels;
1237 int ret;
1238 int i;
1239 u32 tmp;
1240
1241 if (!of_get_property(np, "reg", &nsels))
1242 return -EINVAL;
1243
1244 nsels /= sizeof(u32);
1245 if (!nsels) {
1246 dev_err(dev, "invalid reg property size\n");
1247 return -EINVAL;
1248 }
1249
1250 chip = devm_kzalloc(dev,
1251 sizeof(*chip) +
1252 (nsels * sizeof(struct sunxi_nand_chip_sel)),
1253 GFP_KERNEL);
1254 if (!chip) {
1255 dev_err(dev, "could not allocate chip\n");
1256 return -ENOMEM;
1257 }
1258
1259 chip->nsels = nsels;
1260 chip->selected = -1;
1261
1262 for (i = 0; i < nsels; i++) {
1263 ret = of_property_read_u32_index(np, "reg", i, &tmp);
1264 if (ret) {
1265 dev_err(dev, "could not retrieve reg property: %d\n",
1266 ret);
1267 return ret;
1268 }
1269
1270 if (tmp > NFC_MAX_CS) {
1271 dev_err(dev,
1272 "invalid reg value: %u (max CS = 7)\n",
1273 tmp);
1274 return -EINVAL;
1275 }
1276
1277 if (test_and_set_bit(tmp, &nfc->assigned_cs)) {
1278 dev_err(dev, "CS %d already assigned\n", tmp);
1279 return -EINVAL;
1280 }
1281
1282 chip->sels[i].cs = tmp;
1283
1284 if (!of_property_read_u32_index(np, "allwinner,rb", i, &tmp) &&
1285 tmp < 2) {
1286 chip->sels[i].rb.type = RB_NATIVE;
1287 chip->sels[i].rb.info.nativeid = tmp;
1288 } else {
1289 ret = of_get_named_gpio(np, "rb-gpios", i);
1290 if (ret >= 0) {
1291 tmp = ret;
1292 chip->sels[i].rb.type = RB_GPIO;
1293 chip->sels[i].rb.info.gpio = tmp;
1294 ret = devm_gpio_request(dev, tmp, "nand-rb");
1295 if (ret)
1296 return ret;
1297
1298 ret = gpio_direction_input(tmp);
1299 if (ret)
1300 return ret;
1301 } else {
1302 chip->sels[i].rb.type = RB_NONE;
1303 }
1304 }
1305 }
1306
1307 timings = onfi_async_timing_mode_to_sdr_timings(0);
1308 if (IS_ERR(timings)) {
1309 ret = PTR_ERR(timings);
1310 dev_err(dev,
1311 "could not retrieve timings for ONFI mode 0: %d\n",
1312 ret);
1313 return ret;
1314 }
1315
1316 ret = sunxi_nand_chip_set_timings(chip, timings);
1317 if (ret) {
1318 dev_err(dev, "could not configure chip timings: %d\n", ret);
1319 return ret;
1320 }
1321
1322 nand = &chip->nand;
1323
1324 nand->chip_delay = 200;
1325 nand->controller = &nfc->controller;
1326
1327
1328
1329
1330 nand->ecc.mode = NAND_ECC_HW;
1331 nand_set_flash_node(nand, np);
1332 nand->select_chip = sunxi_nfc_select_chip;
1333 nand->cmd_ctrl = sunxi_nfc_cmd_ctrl;
1334 nand->read_buf = sunxi_nfc_read_buf;
1335 nand->write_buf = sunxi_nfc_write_buf;
1336 nand->read_byte = sunxi_nfc_read_byte;
1337
1338 mtd = nand_to_mtd(nand);
1339 mtd->dev.parent = dev;
1340
1341 ret = nand_scan_ident(mtd, nsels, NULL);
1342 if (ret)
1343 return ret;
1344
1345 if (nand->bbt_options & NAND_BBT_USE_FLASH)
1346 nand->bbt_options |= NAND_BBT_NO_OOB;
1347
1348 ret = sunxi_nand_chip_init_timings(chip, np);
1349 if (ret) {
1350 dev_err(dev, "could not configure chip timings: %d\n", ret);
1351 return ret;
1352 }
1353
1354 ret = sunxi_nand_ecc_init(mtd, &nand->ecc, np);
1355 if (ret) {
1356 dev_err(dev, "ECC init failed: %d\n", ret);
1357 return ret;
1358 }
1359
1360 ret = nand_scan_tail(mtd);
1361 if (ret) {
1362 dev_err(dev, "nand_scan_tail failed: %d\n", ret);
1363 return ret;
1364 }
1365
1366 ret = mtd_device_register(mtd, NULL, 0);
1367 if (ret) {
1368 dev_err(dev, "failed to register mtd device: %d\n", ret);
1369 nand_release(mtd);
1370 return ret;
1371 }
1372
1373 list_add_tail(&chip->node, &nfc->chips);
1374
1375 return 0;
1376}
1377
1378static int sunxi_nand_chips_init(struct device *dev, struct sunxi_nfc *nfc)
1379{
1380 struct device_node *np = dev->of_node;
1381 struct device_node *nand_np;
1382 int nchips = of_get_child_count(np);
1383 int ret;
1384
1385 if (nchips > 8) {
1386 dev_err(dev, "too many NAND chips: %d (max = 8)\n", nchips);
1387 return -EINVAL;
1388 }
1389
1390 for_each_child_of_node(np, nand_np) {
1391 ret = sunxi_nand_chip_init(dev, nfc, nand_np);
1392 if (ret) {
1393 of_node_put(nand_np);
1394 return ret;
1395 }
1396 }
1397
1398 return 0;
1399}
1400
1401static void sunxi_nand_chips_cleanup(struct sunxi_nfc *nfc)
1402{
1403 struct sunxi_nand_chip *chip;
1404
1405 while (!list_empty(&nfc->chips)) {
1406 chip = list_first_entry(&nfc->chips, struct sunxi_nand_chip,
1407 node);
1408 nand_release(nand_to_mtd(&chip->nand));
1409 sunxi_nand_ecc_cleanup(&chip->nand.ecc);
1410 list_del(&chip->node);
1411 }
1412}
1413
1414static int sunxi_nfc_probe(struct platform_device *pdev)
1415{
1416 struct device *dev = &pdev->dev;
1417 struct resource *r;
1418 struct sunxi_nfc *nfc;
1419 int irq;
1420 int ret;
1421
1422 nfc = devm_kzalloc(dev, sizeof(*nfc), GFP_KERNEL);
1423 if (!nfc)
1424 return -ENOMEM;
1425
1426 nfc->dev = dev;
1427 spin_lock_init(&nfc->controller.lock);
1428 init_waitqueue_head(&nfc->controller.wq);
1429 INIT_LIST_HEAD(&nfc->chips);
1430
1431 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1432 nfc->regs = devm_ioremap_resource(dev, r);
1433 if (IS_ERR(nfc->regs))
1434 return PTR_ERR(nfc->regs);
1435
1436 irq = platform_get_irq(pdev, 0);
1437 if (irq < 0) {
1438 dev_err(dev, "failed to retrieve irq\n");
1439 return irq;
1440 }
1441
1442 nfc->ahb_clk = devm_clk_get(dev, "ahb");
1443 if (IS_ERR(nfc->ahb_clk)) {
1444 dev_err(dev, "failed to retrieve ahb clk\n");
1445 return PTR_ERR(nfc->ahb_clk);
1446 }
1447
1448 ret = clk_prepare_enable(nfc->ahb_clk);
1449 if (ret)
1450 return ret;
1451
1452 nfc->mod_clk = devm_clk_get(dev, "mod");
1453 if (IS_ERR(nfc->mod_clk)) {
1454 dev_err(dev, "failed to retrieve mod clk\n");
1455 ret = PTR_ERR(nfc->mod_clk);
1456 goto out_ahb_clk_unprepare;
1457 }
1458
1459 ret = clk_prepare_enable(nfc->mod_clk);
1460 if (ret)
1461 goto out_ahb_clk_unprepare;
1462
1463 ret = sunxi_nfc_rst(nfc);
1464 if (ret)
1465 goto out_mod_clk_unprepare;
1466
1467 writel(0, nfc->regs + NFC_REG_INT);
1468 ret = devm_request_irq(dev, irq, sunxi_nfc_interrupt,
1469 0, "sunxi-nand", nfc);
1470 if (ret)
1471 goto out_mod_clk_unprepare;
1472
1473 platform_set_drvdata(pdev, nfc);
1474
1475 ret = sunxi_nand_chips_init(dev, nfc);
1476 if (ret) {
1477 dev_err(dev, "failed to init nand chips\n");
1478 goto out_mod_clk_unprepare;
1479 }
1480
1481 return 0;
1482
1483out_mod_clk_unprepare:
1484 clk_disable_unprepare(nfc->mod_clk);
1485out_ahb_clk_unprepare:
1486 clk_disable_unprepare(nfc->ahb_clk);
1487
1488 return ret;
1489}
1490
1491static int sunxi_nfc_remove(struct platform_device *pdev)
1492{
1493 struct sunxi_nfc *nfc = platform_get_drvdata(pdev);
1494
1495 sunxi_nand_chips_cleanup(nfc);
1496
1497 return 0;
1498}
1499
1500static const struct of_device_id sunxi_nfc_ids[] = {
1501 { .compatible = "allwinner,sun4i-a10-nand" },
1502 { }
1503};
1504MODULE_DEVICE_TABLE(of, sunxi_nfc_ids);
1505
1506static struct platform_driver sunxi_nfc_driver = {
1507 .driver = {
1508 .name = "sunxi_nand",
1509 .of_match_table = sunxi_nfc_ids,
1510 },
1511 .probe = sunxi_nfc_probe,
1512 .remove = sunxi_nfc_remove,
1513};
1514module_platform_driver(sunxi_nfc_driver);
1515
1516MODULE_LICENSE("GPL v2");
1517MODULE_AUTHOR("Boris BREZILLON");
1518MODULE_DESCRIPTION("Allwinner NAND Flash Controller driver");
1519MODULE_ALIAS("platform:sunxi_nand");
1520
