1/* 2 * Copyright(c) 2015 EZchip Technologies. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * The full GNU General Public License is included in this distribution in 14 * the file called "COPYING". 15 */ 16 17#ifndef _NPS_ENET_H 18#define _NPS_ENET_H 19 20/* default values */ 21#define NPS_ENET_NAPI_POLL_WEIGHT 0x2 22#define NPS_ENET_MAX_FRAME_LENGTH 0x3FFF 23#define NPS_ENET_GE_MAC_CFG_0_TX_FC_RETR 0x7 24#define NPS_ENET_GE_MAC_CFG_0_RX_IFG 0x5 25#define NPS_ENET_GE_MAC_CFG_0_TX_IFG 0xC 26#define NPS_ENET_GE_MAC_CFG_0_TX_PR_LEN 0x7 27#define NPS_ENET_GE_MAC_CFG_2_STAT_EN 0x3 28#define NPS_ENET_GE_MAC_CFG_3_RX_IFG_TH 0x14 29#define NPS_ENET_GE_MAC_CFG_3_MAX_LEN 0x3FFC 30#define NPS_ENET_ENABLE 1 31#define NPS_ENET_DISABLE 0 32 33/* register definitions */ 34#define NPS_ENET_REG_TX_CTL 0x800 35#define NPS_ENET_REG_TX_BUF 0x808 36#define NPS_ENET_REG_RX_CTL 0x810 37#define NPS_ENET_REG_RX_BUF 0x818 38#define NPS_ENET_REG_BUF_INT_ENABLE 0x8C0 39#define NPS_ENET_REG_GE_MAC_CFG_0 0x1000 40#define NPS_ENET_REG_GE_MAC_CFG_1 0x1004 41#define NPS_ENET_REG_GE_MAC_CFG_2 0x1008 42#define NPS_ENET_REG_GE_MAC_CFG_3 0x100C 43#define NPS_ENET_REG_GE_RST 0x1400 44#define NPS_ENET_REG_PHASE_FIFO_CTL 0x1404 45 46/* Tx control register */ 47struct nps_enet_tx_ctl { 48 union { 49 /* ct: SW sets to indicate frame ready in Tx buffer for 50 * transmission. HW resets to when transmission done 51 * et: Transmit error 52 * nt: Length in bytes of Tx frame loaded to Tx buffer 53 */ 54 struct { 55 u32 56 __reserved_1:16, 57 ct:1, 58 et:1, 59 __reserved_2:3, 60 nt:11; 61 }; 62 63 u32 value; 64 }; 65}; 66 67/* Rx control register */ 68struct nps_enet_rx_ctl { 69 union { 70 /* cr: HW sets to indicate frame ready in Rx buffer. 71 * SW resets to indicate host read received frame 72 * and new frames can be written to Rx buffer 73 * er: Rx error indication 74 * crc: Rx CRC error indication 75 * nr: Length in bytes of Rx frame loaded by MAC to Rx buffer 76 */ 77 struct { 78 u32 79 __reserved_1:16, 80 cr:1, 81 er:1, 82 crc:1, 83 __reserved_2:2, 84 nr:11; 85 }; 86 87 u32 value; 88 }; 89}; 90 91/* Interrupt enable for data buffer events register */ 92struct nps_enet_buf_int_enable { 93 union { 94 /* tx_done: Interrupt generation in the case when new frame 95 * is ready in Rx buffer 96 * rx_rdy: Interrupt generation in the case when current frame 97 * was read from TX buffer 98 */ 99 struct { 100 u32 101 __reserved:30, 102 tx_done:1, 103 rx_rdy:1; 104 }; 105 106 u32 value; 107 }; 108}; 109 110/* Gbps Eth MAC Configuration 0 register */ 111struct nps_enet_ge_mac_cfg_0 { 112 union { 113 /* tx_pr_len: Transmit preamble length in bytes 114 * tx_ifg_nib: Tx idle pattern 115 * nib_mode: Nibble (4-bit) Mode 116 * rx_pr_check_en: Receive preamble Check Enable 117 * tx_ifg: Transmit inter-Frame Gap 118 * rx_ifg: Receive inter-Frame Gap 119 * tx_fc_retr: Transmit Flow Control Retransmit Mode 120 * rx_length_check_en: Receive Length Check Enable 121 * rx_crc_ignore: Results of the CRC check are ignored 122 * rx_crc_strip: MAC strips the CRC from received frames 123 * rx_fc_en: Receive Flow Control Enable 124 * tx_crc_en: Transmit CRC Enabled 125 * tx_pad_en: Transmit Padding Enable 126 * tx_cf_en: Transmit Flow Control Enable 127 * tx_en: Transmit Enable 128 * rx_en: Receive Enable 129 */ 130 struct { 131 u32 132 tx_pr_len:4, 133 tx_ifg_nib:4, 134 nib_mode:1, 135 rx_pr_check_en:1, 136 tx_ifg:6, 137 rx_ifg:4, 138 tx_fc_retr:3, 139 rx_length_check_en:1, 140 rx_crc_ignore:1, 141 rx_crc_strip:1, 142 rx_fc_en:1, 143 tx_crc_en:1, 144 tx_pad_en:1, 145 tx_fc_en:1, 146 tx_en:1, 147 rx_en:1; 148 }; 149 150 u32 value; 151 }; 152}; 153 154/* Gbps Eth MAC Configuration 1 register */ 155struct nps_enet_ge_mac_cfg_1 { 156 union { 157 /* octet_3: MAC address octet 3 158 * octet_2: MAC address octet 2 159 * octet_1: MAC address octet 1 160 * octet_0: MAC address octet 0 161 */ 162 struct { 163 u32 164 octet_3:8, 165 octet_2:8, 166 octet_1:8, 167 octet_0:8; 168 }; 169 170 u32 value; 171 }; 172}; 173 174/* Gbps Eth MAC Configuration 2 register */ 175struct nps_enet_ge_mac_cfg_2 { 176 union { 177 /* transmit_flush_en: MAC flush enable 178 * stat_en: RMON statistics interface enable 179 * disc_da: Discard frames with DA different 180 * from MAC address 181 * disc_bc: Discard broadcast frames 182 * disc_mc: Discard multicast frames 183 * octet_5: MAC address octet 5 184 * octet_4: MAC address octet 4 185 */ 186 struct { 187 u32 188 transmit_flush_en:1, 189 __reserved_1:5, 190 stat_en:2, 191 __reserved_2:1, 192 disc_da:1, 193 disc_bc:1, 194 disc_mc:1, 195 __reserved_3:4, 196 octet_5:8, 197 octet_4:8; 198 }; 199 200 u32 value; 201 }; 202}; 203 204/* Gbps Eth MAC Configuration 3 register */ 205struct nps_enet_ge_mac_cfg_3 { 206 union { 207 /* ext_oob_cbfc_sel: Selects one of the 4 profiles for 208 * extended OOB in-flow-control indication 209 * max_len: Maximum receive frame length in bytes 210 * tx_cbfc_en: Enable transmission of class-based 211 * flow control packets 212 * rx_ifg_th: Threshold for IFG status reporting via OOB 213 * cf_timeout: Configurable time to decrement FC counters 214 * cf_drop: Drop control frames 215 * redirect_cbfc_sel: Selects one of CBFC redirect profiles 216 * rx_cbfc_redir_en: Enable Rx class-based flow 217 * control redirect 218 * rx_cbfc_en: Enable Rx class-based flow control 219 * tm_hd_mode: TM header mode 220 */ 221 struct { 222 u32 223 ext_oob_cbfc_sel:2, 224 max_len:14, 225 tx_cbfc_en:1, 226 rx_ifg_th:5, 227 cf_timeout:4, 228 cf_drop:1, 229 redirect_cbfc_sel:2, 230 rx_cbfc_redir_en:1, 231 rx_cbfc_en:1, 232 tm_hd_mode:1; 233 }; 234 235 u32 value; 236 }; 237}; 238 239/* GE MAC, PCS reset control register */ 240struct nps_enet_ge_rst { 241 union { 242 /* gmac_0: GE MAC reset 243 * spcs_0: SGMII PCS reset 244 */ 245 struct { 246 u32 247 __reserved_1:23, 248 gmac_0:1, 249 __reserved_2:7, 250 spcs_0:1; 251 }; 252 253 u32 value; 254 }; 255}; 256 257/* Tx phase sync FIFO control register */ 258struct nps_enet_phase_fifo_ctl { 259 union { 260 /* init: initialize serdes TX phase sync FIFO pointers 261 * rst: reset serdes TX phase sync FIFO 262 */ 263 struct { 264 u32 265 __reserved:30, 266 init:1, 267 rst:1; 268 }; 269 270 u32 value; 271 }; 272}; 273 274/** 275 * struct nps_enet_priv - Storage of ENET's private information. 276 * @regs_base: Base address of ENET memory-mapped control registers. 277 * @irq: For RX/TX IRQ number. 278 * @tx_packet_sent: SW indication if frame is being sent. 279 * @tx_skb: socket buffer of sent frame. 280 * @napi: Structure for NAPI. 281 */ 282struct nps_enet_priv { 283 void __iomem *regs_base; 284 s32 irq; 285 bool tx_packet_sent; 286 struct sk_buff *tx_skb; 287 struct napi_struct napi; 288 struct nps_enet_ge_mac_cfg_2 ge_mac_cfg_2; 289 struct nps_enet_ge_mac_cfg_3 ge_mac_cfg_3; 290}; 291 292/** 293 * nps_reg_set - Sets ENET register with provided value. 294 * @priv: Pointer to EZchip ENET private data structure. 295 * @reg: Register offset from base address. 296 * @value: Value to set in register. 297 */ 298static inline void nps_enet_reg_set(struct nps_enet_priv *priv, 299 s32 reg, s32 value) 300{ 301 iowrite32be(value, priv->regs_base + reg); 302} 303 304/** 305 * nps_reg_get - Gets value of specified ENET register. 306 * @priv: Pointer to EZchip ENET private data structure. 307 * @reg: Register offset from base address. 308 * 309 * returns: Value of requested register. 310 */ 311static inline u32 nps_enet_reg_get(struct nps_enet_priv *priv, s32 reg) 312{ 313 return ioread32be(priv->regs_base + reg); 314} 315 316#endif /* _NPS_ENET_H */ 317