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27#ifndef _IXGBEVF_H_
28#define _IXGBEVF_H_
29
30#include <linux/types.h>
31#include <linux/bitops.h>
32#include <linux/timer.h>
33#include <linux/io.h>
34#include <linux/netdevice.h>
35#include <linux/if_vlan.h>
36#include <linux/u64_stats_sync.h>
37
38#include "vf.h"
39
40#ifdef CONFIG_NET_RX_BUSY_POLL
41#include <net/busy_poll.h>
42#define BP_EXTENDED_STATS
43#endif
44
45#define IXGBE_MAX_TXD_PWR 14
46#define IXGBE_MAX_DATA_PER_TXD BIT(IXGBE_MAX_TXD_PWR)
47
48
49#define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IXGBE_MAX_DATA_PER_TXD)
50#define DESC_NEEDED (MAX_SKB_FRAGS + 4)
51
52
53
54
55struct ixgbevf_tx_buffer {
56 union ixgbe_adv_tx_desc *next_to_watch;
57 unsigned long time_stamp;
58 struct sk_buff *skb;
59 unsigned int bytecount;
60 unsigned short gso_segs;
61 __be16 protocol;
62 DEFINE_DMA_UNMAP_ADDR(dma);
63 DEFINE_DMA_UNMAP_LEN(len);
64 u32 tx_flags;
65};
66
67struct ixgbevf_rx_buffer {
68 dma_addr_t dma;
69 struct page *page;
70 unsigned int page_offset;
71};
72
73struct ixgbevf_stats {
74 u64 packets;
75 u64 bytes;
76#ifdef BP_EXTENDED_STATS
77 u64 yields;
78 u64 misses;
79 u64 cleaned;
80#endif
81};
82
83struct ixgbevf_tx_queue_stats {
84 u64 restart_queue;
85 u64 tx_busy;
86 u64 tx_done_old;
87};
88
89struct ixgbevf_rx_queue_stats {
90 u64 alloc_rx_page_failed;
91 u64 alloc_rx_buff_failed;
92 u64 csum_err;
93};
94
95enum ixgbevf_ring_state_t {
96 __IXGBEVF_TX_DETECT_HANG,
97 __IXGBEVF_HANG_CHECK_ARMED,
98};
99
100#define check_for_tx_hang(ring) \
101 test_bit(__IXGBEVF_TX_DETECT_HANG, &(ring)->state)
102#define set_check_for_tx_hang(ring) \
103 set_bit(__IXGBEVF_TX_DETECT_HANG, &(ring)->state)
104#define clear_check_for_tx_hang(ring) \
105 clear_bit(__IXGBEVF_TX_DETECT_HANG, &(ring)->state)
106
107struct ixgbevf_ring {
108 struct ixgbevf_ring *next;
109 struct net_device *netdev;
110 struct device *dev;
111 void *desc;
112 dma_addr_t dma;
113 unsigned int size;
114 u16 count;
115 u16 next_to_use;
116 u16 next_to_clean;
117 u16 next_to_alloc;
118
119 union {
120 struct ixgbevf_tx_buffer *tx_buffer_info;
121 struct ixgbevf_rx_buffer *rx_buffer_info;
122 };
123 unsigned long state;
124 struct ixgbevf_stats stats;
125 struct u64_stats_sync syncp;
126 union {
127 struct ixgbevf_tx_queue_stats tx_stats;
128 struct ixgbevf_rx_queue_stats rx_stats;
129 };
130
131 u64 hw_csum_rx_error;
132 u8 __iomem *tail;
133 struct sk_buff *skb;
134
135
136
137
138 u16 reg_idx;
139 int queue_index;
140};
141
142
143#define IXGBEVF_RX_BUFFER_WRITE 16
144
145#define MAX_RX_QUEUES IXGBE_VF_MAX_RX_QUEUES
146#define MAX_TX_QUEUES IXGBE_VF_MAX_TX_QUEUES
147#define IXGBEVF_MAX_RSS_QUEUES 2
148#define IXGBEVF_82599_RETA_SIZE 128
149#define IXGBEVF_X550_VFRETA_SIZE 64
150#define IXGBEVF_RSS_HASH_KEY_SIZE 40
151#define IXGBEVF_VFRSSRK_REGS 10
152
153#define IXGBEVF_DEFAULT_TXD 1024
154#define IXGBEVF_DEFAULT_RXD 512
155#define IXGBEVF_MAX_TXD 4096
156#define IXGBEVF_MIN_TXD 64
157#define IXGBEVF_MAX_RXD 4096
158#define IXGBEVF_MIN_RXD 64
159
160
161#define IXGBEVF_RXBUFFER_256 256
162#define IXGBEVF_RXBUFFER_2048 2048
163
164#define IXGBEVF_RX_HDR_SIZE IXGBEVF_RXBUFFER_256
165#define IXGBEVF_RX_BUFSZ IXGBEVF_RXBUFFER_2048
166
167#define MAXIMUM_ETHERNET_VLAN_SIZE (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
168
169#define IXGBE_TX_FLAGS_CSUM (u32)(1)
170#define IXGBE_TX_FLAGS_VLAN (u32)(1 << 1)
171#define IXGBE_TX_FLAGS_TSO (u32)(1 << 2)
172#define IXGBE_TX_FLAGS_IPV4 (u32)(1 << 3)
173#define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000
174#define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0x0000e000
175#define IXGBE_TX_FLAGS_VLAN_SHIFT 16
176
177struct ixgbevf_ring_container {
178 struct ixgbevf_ring *ring;
179 unsigned int total_bytes;
180 unsigned int total_packets;
181 u8 count;
182 u8 itr;
183};
184
185
186#define ixgbevf_for_each_ring(pos, head) \
187 for (pos = (head).ring; pos != NULL; pos = pos->next)
188
189
190
191
192struct ixgbevf_q_vector {
193 struct ixgbevf_adapter *adapter;
194
195
196
197 u16 v_idx;
198 u16 itr;
199 struct napi_struct napi;
200 struct ixgbevf_ring_container rx, tx;
201 char name[IFNAMSIZ + 9];
202#ifdef CONFIG_NET_RX_BUSY_POLL
203 unsigned int state;
204#define IXGBEVF_QV_STATE_IDLE 0
205#define IXGBEVF_QV_STATE_NAPI 1
206#define IXGBEVF_QV_STATE_POLL 2
207#define IXGBEVF_QV_STATE_DISABLED 4
208#define IXGBEVF_QV_OWNED (IXGBEVF_QV_STATE_NAPI | IXGBEVF_QV_STATE_POLL)
209#define IXGBEVF_QV_LOCKED (IXGBEVF_QV_OWNED | IXGBEVF_QV_STATE_DISABLED)
210#define IXGBEVF_QV_STATE_NAPI_YIELD 8
211#define IXGBEVF_QV_STATE_POLL_YIELD 16
212#define IXGBEVF_QV_YIELD (IXGBEVF_QV_STATE_NAPI_YIELD | \
213 IXGBEVF_QV_STATE_POLL_YIELD)
214#define IXGBEVF_QV_USER_PEND (IXGBEVF_QV_STATE_POLL | \
215 IXGBEVF_QV_STATE_POLL_YIELD)
216 spinlock_t lock;
217#endif
218};
219
220#ifdef CONFIG_NET_RX_BUSY_POLL
221static inline void ixgbevf_qv_init_lock(struct ixgbevf_q_vector *q_vector)
222{
223 spin_lock_init(&q_vector->lock);
224 q_vector->state = IXGBEVF_QV_STATE_IDLE;
225}
226
227
228static inline bool ixgbevf_qv_lock_napi(struct ixgbevf_q_vector *q_vector)
229{
230 int rc = true;
231
232 spin_lock_bh(&q_vector->lock);
233 if (q_vector->state & IXGBEVF_QV_LOCKED) {
234 WARN_ON(q_vector->state & IXGBEVF_QV_STATE_NAPI);
235 q_vector->state |= IXGBEVF_QV_STATE_NAPI_YIELD;
236 rc = false;
237#ifdef BP_EXTENDED_STATS
238 q_vector->tx.ring->stats.yields++;
239#endif
240 } else {
241
242 q_vector->state = IXGBEVF_QV_STATE_NAPI;
243 }
244 spin_unlock_bh(&q_vector->lock);
245 return rc;
246}
247
248
249static inline bool ixgbevf_qv_unlock_napi(struct ixgbevf_q_vector *q_vector)
250{
251 int rc = false;
252
253 spin_lock_bh(&q_vector->lock);
254 WARN_ON(q_vector->state & (IXGBEVF_QV_STATE_POLL |
255 IXGBEVF_QV_STATE_NAPI_YIELD));
256
257 if (q_vector->state & IXGBEVF_QV_STATE_POLL_YIELD)
258 rc = true;
259
260 q_vector->state &= IXGBEVF_QV_STATE_DISABLED;
261 spin_unlock_bh(&q_vector->lock);
262 return rc;
263}
264
265
266static inline bool ixgbevf_qv_lock_poll(struct ixgbevf_q_vector *q_vector)
267{
268 int rc = true;
269
270 spin_lock_bh(&q_vector->lock);
271 if ((q_vector->state & IXGBEVF_QV_LOCKED)) {
272 q_vector->state |= IXGBEVF_QV_STATE_POLL_YIELD;
273 rc = false;
274#ifdef BP_EXTENDED_STATS
275 q_vector->rx.ring->stats.yields++;
276#endif
277 } else {
278
279 q_vector->state |= IXGBEVF_QV_STATE_POLL;
280 }
281 spin_unlock_bh(&q_vector->lock);
282 return rc;
283}
284
285
286static inline bool ixgbevf_qv_unlock_poll(struct ixgbevf_q_vector *q_vector)
287{
288 int rc = false;
289
290 spin_lock_bh(&q_vector->lock);
291 WARN_ON(q_vector->state & (IXGBEVF_QV_STATE_NAPI));
292
293 if (q_vector->state & IXGBEVF_QV_STATE_POLL_YIELD)
294 rc = true;
295
296 q_vector->state &= IXGBEVF_QV_STATE_DISABLED;
297 spin_unlock_bh(&q_vector->lock);
298 return rc;
299}
300
301
302static inline bool ixgbevf_qv_busy_polling(struct ixgbevf_q_vector *q_vector)
303{
304 WARN_ON(!(q_vector->state & IXGBEVF_QV_OWNED));
305 return q_vector->state & IXGBEVF_QV_USER_PEND;
306}
307
308
309static inline bool ixgbevf_qv_disable(struct ixgbevf_q_vector *q_vector)
310{
311 int rc = true;
312
313 spin_lock_bh(&q_vector->lock);
314 if (q_vector->state & IXGBEVF_QV_OWNED)
315 rc = false;
316 q_vector->state |= IXGBEVF_QV_STATE_DISABLED;
317 spin_unlock_bh(&q_vector->lock);
318 return rc;
319}
320
321#endif
322
323
324
325
326#define IXGBE_MIN_RSC_ITR 24
327#define IXGBE_100K_ITR 40
328#define IXGBE_20K_ITR 200
329#define IXGBE_12K_ITR 336
330
331
332
333
334
335#define EITR_INTS_PER_SEC_TO_REG(_eitr) \
336 ((_eitr) ? (1000000000 / ((_eitr) * 256)) : 8)
337#define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG
338
339
340static inline __le32 ixgbevf_test_staterr(union ixgbe_adv_rx_desc *rx_desc,
341 const u32 stat_err_bits)
342{
343 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
344}
345
346static inline u16 ixgbevf_desc_unused(struct ixgbevf_ring *ring)
347{
348 u16 ntc = ring->next_to_clean;
349 u16 ntu = ring->next_to_use;
350
351 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1;
352}
353
354static inline void ixgbevf_write_tail(struct ixgbevf_ring *ring, u32 value)
355{
356 writel(value, ring->tail);
357}
358
359#define IXGBEVF_RX_DESC(R, i) \
360 (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i]))
361#define IXGBEVF_TX_DESC(R, i) \
362 (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i]))
363#define IXGBEVF_TX_CTXTDESC(R, i) \
364 (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i]))
365
366#define IXGBE_MAX_JUMBO_FRAME_SIZE 9728
367
368#define OTHER_VECTOR 1
369#define NON_Q_VECTORS (OTHER_VECTOR)
370
371#define MAX_MSIX_Q_VECTORS 2
372
373#define MIN_MSIX_Q_VECTORS 1
374#define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
375
376
377struct ixgbevf_adapter {
378
379 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
380
381 struct ixgbevf_q_vector *q_vector[MAX_MSIX_Q_VECTORS];
382
383
384 u16 rx_itr_setting;
385 u16 tx_itr_setting;
386
387
388 u32 eims_enable_mask;
389 u32 eims_other;
390
391
392 int num_tx_queues;
393 struct ixgbevf_ring *tx_ring[MAX_TX_QUEUES];
394 u64 restart_queue;
395 u32 tx_timeout_count;
396
397
398 int num_rx_queues;
399 struct ixgbevf_ring *rx_ring[MAX_TX_QUEUES];
400 u64 hw_csum_rx_error;
401 u64 hw_rx_no_dma_resources;
402 int num_msix_vectors;
403 u32 alloc_rx_page_failed;
404 u32 alloc_rx_buff_failed;
405
406
407
408
409 u32 flags;
410#define IXGBEVF_FLAG_RESET_REQUESTED (u32)(1)
411#define IXGBEVF_FLAG_QUEUE_RESET_REQUESTED (u32)(1 << 2)
412
413 struct msix_entry *msix_entries;
414
415
416 struct net_device *netdev;
417 struct pci_dev *pdev;
418
419
420 struct ixgbe_hw hw;
421 u16 msg_enable;
422
423 u32 eitr_param;
424
425 struct ixgbevf_hw_stats stats;
426
427 unsigned long state;
428 u64 tx_busy;
429 unsigned int tx_ring_count;
430 unsigned int rx_ring_count;
431
432#ifdef BP_EXTENDED_STATS
433 u64 bp_rx_yields;
434 u64 bp_rx_cleaned;
435 u64 bp_rx_missed;
436
437 u64 bp_tx_yields;
438 u64 bp_tx_cleaned;
439 u64 bp_tx_missed;
440#endif
441
442 u8 __iomem *io_addr;
443 u32 link_speed;
444 bool link_up;
445
446 struct timer_list service_timer;
447 struct work_struct service_task;
448
449 spinlock_t mbx_lock;
450 unsigned long last_reset;
451
452 u32 rss_key[IXGBEVF_VFRSSRK_REGS];
453 u8 rss_indir_tbl[IXGBEVF_X550_VFRETA_SIZE];
454};
455
456enum ixbgevf_state_t {
457 __IXGBEVF_TESTING,
458 __IXGBEVF_RESETTING,
459 __IXGBEVF_DOWN,
460 __IXGBEVF_DISABLED,
461 __IXGBEVF_REMOVING,
462 __IXGBEVF_SERVICE_SCHED,
463 __IXGBEVF_SERVICE_INITED,
464};
465
466enum ixgbevf_boards {
467 board_82599_vf,
468 board_X540_vf,
469 board_X550_vf,
470 board_X550EM_x_vf,
471};
472
473enum ixgbevf_xcast_modes {
474 IXGBEVF_XCAST_MODE_NONE = 0,
475 IXGBEVF_XCAST_MODE_MULTI,
476 IXGBEVF_XCAST_MODE_ALLMULTI,
477};
478
479extern const struct ixgbevf_info ixgbevf_82599_vf_info;
480extern const struct ixgbevf_info ixgbevf_X540_vf_info;
481extern const struct ixgbevf_info ixgbevf_X550_vf_info;
482extern const struct ixgbevf_info ixgbevf_X550EM_x_vf_info;
483extern const struct ixgbe_mbx_operations ixgbevf_mbx_ops;
484
485
486extern const char ixgbevf_driver_name[];
487extern const char ixgbevf_driver_version[];
488
489void ixgbevf_up(struct ixgbevf_adapter *adapter);
490void ixgbevf_down(struct ixgbevf_adapter *adapter);
491void ixgbevf_reinit_locked(struct ixgbevf_adapter *adapter);
492void ixgbevf_reset(struct ixgbevf_adapter *adapter);
493void ixgbevf_set_ethtool_ops(struct net_device *netdev);
494int ixgbevf_setup_rx_resources(struct ixgbevf_ring *);
495int ixgbevf_setup_tx_resources(struct ixgbevf_ring *);
496void ixgbevf_free_rx_resources(struct ixgbevf_ring *);
497void ixgbevf_free_tx_resources(struct ixgbevf_ring *);
498void ixgbevf_update_stats(struct ixgbevf_adapter *adapter);
499int ethtool_ioctl(struct ifreq *ifr);
500
501extern void ixgbevf_write_eitr(struct ixgbevf_q_vector *q_vector);
502
503void ixgbe_napi_add_all(struct ixgbevf_adapter *adapter);
504void ixgbe_napi_del_all(struct ixgbevf_adapter *adapter);
505
506#ifdef DEBUG
507char *ixgbevf_get_hw_dev_name(struct ixgbe_hw *hw);
508#define hw_dbg(hw, format, arg...) \
509 printk(KERN_DEBUG "%s: " format, ixgbevf_get_hw_dev_name(hw), ##arg)
510#else
511#define hw_dbg(hw, format, arg...) do {} while (0)
512#endif
513
514#endif
515