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37#ifndef _MLXSW_REG_H
38#define _MLXSW_REG_H
39
40#include <linux/string.h>
41#include <linux/bitops.h>
42#include <linux/if_vlan.h>
43
44#include "item.h"
45#include "port.h"
46
47struct mlxsw_reg_info {
48 u16 id;
49 u16 len;
50};
51
52#define MLXSW_REG(type) (&mlxsw_reg_##type)
53#define MLXSW_REG_LEN(type) MLXSW_REG(type)->len
54#define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len)
55
56
57
58
59
60#define MLXSW_REG_SGCR_ID 0x2000
61#define MLXSW_REG_SGCR_LEN 0x10
62
63static const struct mlxsw_reg_info mlxsw_reg_sgcr = {
64 .id = MLXSW_REG_SGCR_ID,
65 .len = MLXSW_REG_SGCR_LEN,
66};
67
68
69
70
71
72
73
74MLXSW_ITEM32(reg, sgcr, llb, 0x04, 0, 1);
75
76static inline void mlxsw_reg_sgcr_pack(char *payload, bool llb)
77{
78 MLXSW_REG_ZERO(sgcr, payload);
79 mlxsw_reg_sgcr_llb_set(payload, !!llb);
80}
81
82
83
84
85
86#define MLXSW_REG_SPAD_ID 0x2002
87#define MLXSW_REG_SPAD_LEN 0x10
88
89static const struct mlxsw_reg_info mlxsw_reg_spad = {
90 .id = MLXSW_REG_SPAD_ID,
91 .len = MLXSW_REG_SPAD_LEN,
92};
93
94
95
96
97
98
99
100MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6);
101
102
103
104
105
106
107
108#define MLXSW_REG_SMID_ID 0x2007
109#define MLXSW_REG_SMID_LEN 0x240
110
111static const struct mlxsw_reg_info mlxsw_reg_smid = {
112 .id = MLXSW_REG_SMID_ID,
113 .len = MLXSW_REG_SMID_LEN,
114};
115
116
117
118
119
120MLXSW_ITEM32(reg, smid, swid, 0x00, 24, 8);
121
122
123
124
125
126
127MLXSW_ITEM32(reg, smid, mid, 0x00, 0, 16);
128
129
130
131
132
133MLXSW_ITEM_BIT_ARRAY(reg, smid, port, 0x20, 0x20, 1);
134
135
136
137
138
139MLXSW_ITEM_BIT_ARRAY(reg, smid, port_mask, 0x220, 0x20, 1);
140
141static inline void mlxsw_reg_smid_pack(char *payload, u16 mid,
142 u8 port, bool set)
143{
144 MLXSW_REG_ZERO(smid, payload);
145 mlxsw_reg_smid_swid_set(payload, 0);
146 mlxsw_reg_smid_mid_set(payload, mid);
147 mlxsw_reg_smid_port_set(payload, port, set);
148 mlxsw_reg_smid_port_mask_set(payload, port, 1);
149}
150
151
152
153
154
155#define MLXSW_REG_SSPR_ID 0x2008
156#define MLXSW_REG_SSPR_LEN 0x8
157
158static const struct mlxsw_reg_info mlxsw_reg_sspr = {
159 .id = MLXSW_REG_SSPR_ID,
160 .len = MLXSW_REG_SSPR_LEN,
161};
162
163
164
165
166
167
168
169
170
171
172
173MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1);
174
175
176
177
178
179
180MLXSW_ITEM32(reg, sspr, local_port, 0x00, 16, 8);
181
182
183
184
185
186
187
188MLXSW_ITEM32(reg, sspr, sub_port, 0x00, 8, 8);
189
190
191
192
193
194
195
196
197
198MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16);
199
200static inline void mlxsw_reg_sspr_pack(char *payload, u8 local_port)
201{
202 MLXSW_REG_ZERO(sspr, payload);
203 mlxsw_reg_sspr_m_set(payload, 1);
204 mlxsw_reg_sspr_local_port_set(payload, local_port);
205 mlxsw_reg_sspr_sub_port_set(payload, 0);
206 mlxsw_reg_sspr_system_port_set(payload, local_port);
207}
208
209
210
211
212
213
214#define MLXSW_REG_SFDAT_ID 0x2009
215#define MLXSW_REG_SFDAT_LEN 0x8
216
217static const struct mlxsw_reg_info mlxsw_reg_sfdat = {
218 .id = MLXSW_REG_SFDAT_ID,
219 .len = MLXSW_REG_SFDAT_LEN,
220};
221
222
223
224
225
226MLXSW_ITEM32(reg, sfdat, swid, 0x00, 24, 8);
227
228
229
230
231
232
233
234
235MLXSW_ITEM32(reg, sfdat, age_time, 0x04, 0, 20);
236
237static inline void mlxsw_reg_sfdat_pack(char *payload, u32 age_time)
238{
239 MLXSW_REG_ZERO(sfdat, payload);
240 mlxsw_reg_sfdat_swid_set(payload, 0);
241 mlxsw_reg_sfdat_age_time_set(payload, age_time);
242}
243
244
245
246
247
248
249
250
251#define MLXSW_REG_SFD_ID 0x200A
252#define MLXSW_REG_SFD_BASE_LEN 0x10
253#define MLXSW_REG_SFD_REC_LEN 0x10
254#define MLXSW_REG_SFD_REC_MAX_COUNT 64
255#define MLXSW_REG_SFD_LEN (MLXSW_REG_SFD_BASE_LEN + \
256 MLXSW_REG_SFD_REC_LEN * MLXSW_REG_SFD_REC_MAX_COUNT)
257
258static const struct mlxsw_reg_info mlxsw_reg_sfd = {
259 .id = MLXSW_REG_SFD_ID,
260 .len = MLXSW_REG_SFD_LEN,
261};
262
263
264
265
266
267MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8);
268
269enum mlxsw_reg_sfd_op {
270
271 MLXSW_REG_SFD_OP_QUERY_DUMP = 0,
272
273 MLXSW_REG_SFD_OP_QUERY_QUERY = 1,
274
275 MLXSW_REG_SFD_OP_QUERY_QUERY_AND_CLEAR_ACTIVITY = 2,
276
277
278
279 MLXSW_REG_SFD_OP_WRITE_TEST = 0,
280
281
282
283
284 MLXSW_REG_SFD_OP_WRITE_EDIT = 1,
285
286
287
288
289
290 MLXSW_REG_SFD_OP_WRITE_REMOVE = 2,
291
292
293
294 MLXSW_REG_SFD_OP_WRITE_REMOVE_NOTIFICATION = 2,
295};
296
297
298
299
300
301MLXSW_ITEM32(reg, sfd, op, 0x04, 30, 2);
302
303
304
305
306
307
308
309
310MLXSW_ITEM32(reg, sfd, record_locator, 0x04, 0, 30);
311
312
313
314
315
316
317
318
319MLXSW_ITEM32(reg, sfd, num_rec, 0x08, 0, 8);
320
321static inline void mlxsw_reg_sfd_pack(char *payload, enum mlxsw_reg_sfd_op op,
322 u32 record_locator)
323{
324 MLXSW_REG_ZERO(sfd, payload);
325 mlxsw_reg_sfd_op_set(payload, op);
326 mlxsw_reg_sfd_record_locator_set(payload, record_locator);
327}
328
329
330
331
332
333MLXSW_ITEM32_INDEXED(reg, sfd, rec_swid, MLXSW_REG_SFD_BASE_LEN, 24, 8,
334 MLXSW_REG_SFD_REC_LEN, 0x00, false);
335
336enum mlxsw_reg_sfd_rec_type {
337 MLXSW_REG_SFD_REC_TYPE_UNICAST = 0x0,
338 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG = 0x1,
339 MLXSW_REG_SFD_REC_TYPE_MULTICAST = 0x2,
340};
341
342
343
344
345
346MLXSW_ITEM32_INDEXED(reg, sfd, rec_type, MLXSW_REG_SFD_BASE_LEN, 20, 4,
347 MLXSW_REG_SFD_REC_LEN, 0x00, false);
348
349enum mlxsw_reg_sfd_rec_policy {
350
351 MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY = 0,
352
353
354
355 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_MLAG = 1,
356
357 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_INGRESS = 3,
358};
359
360
361
362
363
364MLXSW_ITEM32_INDEXED(reg, sfd, rec_policy, MLXSW_REG_SFD_BASE_LEN, 18, 2,
365 MLXSW_REG_SFD_REC_LEN, 0x00, false);
366
367
368
369
370
371
372
373MLXSW_ITEM32_INDEXED(reg, sfd, rec_a, MLXSW_REG_SFD_BASE_LEN, 16, 1,
374 MLXSW_REG_SFD_REC_LEN, 0x00, false);
375
376
377
378
379
380MLXSW_ITEM_BUF_INDEXED(reg, sfd, rec_mac, MLXSW_REG_SFD_BASE_LEN, 6,
381 MLXSW_REG_SFD_REC_LEN, 0x02);
382
383enum mlxsw_reg_sfd_rec_action {
384
385 MLXSW_REG_SFD_REC_ACTION_NOP = 0,
386
387 MLXSW_REG_SFD_REC_ACTION_MIRROR_TO_CPU = 1,
388
389 MLXSW_REG_SFD_REC_ACTION_TRAP = 3,
390 MLXSW_REG_SFD_REC_ACTION_DISCARD_ERROR = 15,
391};
392
393
394
395
396
397
398MLXSW_ITEM32_INDEXED(reg, sfd, rec_action, MLXSW_REG_SFD_BASE_LEN, 28, 4,
399 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
400
401
402
403
404
405
406
407MLXSW_ITEM32_INDEXED(reg, sfd, uc_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8,
408 MLXSW_REG_SFD_REC_LEN, 0x08, false);
409
410
411
412
413
414
415
416
417
418
419
420MLXSW_ITEM32_INDEXED(reg, sfd, uc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
421 MLXSW_REG_SFD_REC_LEN, 0x08, false);
422
423
424
425
426
427MLXSW_ITEM32_INDEXED(reg, sfd, uc_system_port, MLXSW_REG_SFD_BASE_LEN, 0, 16,
428 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
429
430static inline void mlxsw_reg_sfd_rec_pack(char *payload, int rec_index,
431 enum mlxsw_reg_sfd_rec_type rec_type,
432 const char *mac,
433 enum mlxsw_reg_sfd_rec_action action)
434{
435 u8 num_rec = mlxsw_reg_sfd_num_rec_get(payload);
436
437 if (rec_index >= num_rec)
438 mlxsw_reg_sfd_num_rec_set(payload, rec_index + 1);
439 mlxsw_reg_sfd_rec_swid_set(payload, rec_index, 0);
440 mlxsw_reg_sfd_rec_type_set(payload, rec_index, rec_type);
441 mlxsw_reg_sfd_rec_mac_memcpy_to(payload, rec_index, mac);
442 mlxsw_reg_sfd_rec_action_set(payload, rec_index, action);
443}
444
445static inline void mlxsw_reg_sfd_uc_pack(char *payload, int rec_index,
446 enum mlxsw_reg_sfd_rec_policy policy,
447 const char *mac, u16 fid_vid,
448 enum mlxsw_reg_sfd_rec_action action,
449 u8 local_port)
450{
451 mlxsw_reg_sfd_rec_pack(payload, rec_index,
452 MLXSW_REG_SFD_REC_TYPE_UNICAST, mac, action);
453 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy);
454 mlxsw_reg_sfd_uc_sub_port_set(payload, rec_index, 0);
455 mlxsw_reg_sfd_uc_fid_vid_set(payload, rec_index, fid_vid);
456 mlxsw_reg_sfd_uc_system_port_set(payload, rec_index, local_port);
457}
458
459static inline void mlxsw_reg_sfd_uc_unpack(char *payload, int rec_index,
460 char *mac, u16 *p_fid_vid,
461 u8 *p_local_port)
462{
463 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac);
464 *p_fid_vid = mlxsw_reg_sfd_uc_fid_vid_get(payload, rec_index);
465 *p_local_port = mlxsw_reg_sfd_uc_system_port_get(payload, rec_index);
466}
467
468
469
470
471
472
473MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8,
474 MLXSW_REG_SFD_REC_LEN, 0x08, false);
475
476
477
478
479
480
481
482
483
484
485
486MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
487 MLXSW_REG_SFD_REC_LEN, 0x08, false);
488
489
490
491
492
493MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12,
494 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
495
496
497
498
499
500MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_id, MLXSW_REG_SFD_BASE_LEN, 0, 10,
501 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
502
503static inline void
504mlxsw_reg_sfd_uc_lag_pack(char *payload, int rec_index,
505 enum mlxsw_reg_sfd_rec_policy policy,
506 const char *mac, u16 fid_vid,
507 enum mlxsw_reg_sfd_rec_action action, u16 lag_vid,
508 u16 lag_id)
509{
510 mlxsw_reg_sfd_rec_pack(payload, rec_index,
511 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG,
512 mac, action);
513 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy);
514 mlxsw_reg_sfd_uc_lag_sub_port_set(payload, rec_index, 0);
515 mlxsw_reg_sfd_uc_lag_fid_vid_set(payload, rec_index, fid_vid);
516 mlxsw_reg_sfd_uc_lag_lag_vid_set(payload, rec_index, lag_vid);
517 mlxsw_reg_sfd_uc_lag_lag_id_set(payload, rec_index, lag_id);
518}
519
520static inline void mlxsw_reg_sfd_uc_lag_unpack(char *payload, int rec_index,
521 char *mac, u16 *p_vid,
522 u16 *p_lag_id)
523{
524 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac);
525 *p_vid = mlxsw_reg_sfd_uc_lag_fid_vid_get(payload, rec_index);
526 *p_lag_id = mlxsw_reg_sfd_uc_lag_lag_id_get(payload, rec_index);
527}
528
529
530
531
532
533
534
535
536MLXSW_ITEM32_INDEXED(reg, sfd, mc_pgi, MLXSW_REG_SFD_BASE_LEN, 16, 13,
537 MLXSW_REG_SFD_REC_LEN, 0x08, false);
538
539
540
541
542
543
544MLXSW_ITEM32_INDEXED(reg, sfd, mc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
545 MLXSW_REG_SFD_REC_LEN, 0x08, false);
546
547
548
549
550
551
552
553MLXSW_ITEM32_INDEXED(reg, sfd, mc_mid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
554 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
555
556static inline void
557mlxsw_reg_sfd_mc_pack(char *payload, int rec_index,
558 const char *mac, u16 fid_vid,
559 enum mlxsw_reg_sfd_rec_action action, u16 mid)
560{
561 mlxsw_reg_sfd_rec_pack(payload, rec_index,
562 MLXSW_REG_SFD_REC_TYPE_MULTICAST, mac, action);
563 mlxsw_reg_sfd_mc_pgi_set(payload, rec_index, 0x1FFF);
564 mlxsw_reg_sfd_mc_fid_vid_set(payload, rec_index, fid_vid);
565 mlxsw_reg_sfd_mc_mid_set(payload, rec_index, mid);
566}
567
568
569
570
571
572
573#define MLXSW_REG_SFN_ID 0x200B
574#define MLXSW_REG_SFN_BASE_LEN 0x10
575#define MLXSW_REG_SFN_REC_LEN 0x10
576#define MLXSW_REG_SFN_REC_MAX_COUNT 64
577#define MLXSW_REG_SFN_LEN (MLXSW_REG_SFN_BASE_LEN + \
578 MLXSW_REG_SFN_REC_LEN * MLXSW_REG_SFN_REC_MAX_COUNT)
579
580static const struct mlxsw_reg_info mlxsw_reg_sfn = {
581 .id = MLXSW_REG_SFN_ID,
582 .len = MLXSW_REG_SFN_LEN,
583};
584
585
586
587
588
589MLXSW_ITEM32(reg, sfn, swid, 0x00, 24, 8);
590
591
592
593
594
595
596
597
598
599MLXSW_ITEM32(reg, sfn, num_rec, 0x04, 0, 8);
600
601static inline void mlxsw_reg_sfn_pack(char *payload)
602{
603 MLXSW_REG_ZERO(sfn, payload);
604 mlxsw_reg_sfn_swid_set(payload, 0);
605 mlxsw_reg_sfn_num_rec_set(payload, MLXSW_REG_SFN_REC_MAX_COUNT);
606}
607
608
609
610
611
612MLXSW_ITEM32_INDEXED(reg, sfn, rec_swid, MLXSW_REG_SFN_BASE_LEN, 24, 8,
613 MLXSW_REG_SFN_REC_LEN, 0x00, false);
614
615enum mlxsw_reg_sfn_rec_type {
616
617 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC = 0x5,
618
619 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC_LAG = 0x6,
620
621 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC = 0x7,
622
623 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC_LAG = 0x8,
624};
625
626
627
628
629
630MLXSW_ITEM32_INDEXED(reg, sfn, rec_type, MLXSW_REG_SFN_BASE_LEN, 20, 4,
631 MLXSW_REG_SFN_REC_LEN, 0x00, false);
632
633
634
635
636
637MLXSW_ITEM_BUF_INDEXED(reg, sfn, rec_mac, MLXSW_REG_SFN_BASE_LEN, 6,
638 MLXSW_REG_SFN_REC_LEN, 0x02);
639
640
641
642
643
644
645MLXSW_ITEM32_INDEXED(reg, sfn, mac_sub_port, MLXSW_REG_SFN_BASE_LEN, 16, 8,
646 MLXSW_REG_SFN_REC_LEN, 0x08, false);
647
648
649
650
651
652MLXSW_ITEM32_INDEXED(reg, sfn, mac_fid, MLXSW_REG_SFN_BASE_LEN, 0, 16,
653 MLXSW_REG_SFN_REC_LEN, 0x08, false);
654
655
656
657
658
659MLXSW_ITEM32_INDEXED(reg, sfn, mac_system_port, MLXSW_REG_SFN_BASE_LEN, 0, 16,
660 MLXSW_REG_SFN_REC_LEN, 0x0C, false);
661
662static inline void mlxsw_reg_sfn_mac_unpack(char *payload, int rec_index,
663 char *mac, u16 *p_vid,
664 u8 *p_local_port)
665{
666 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac);
667 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index);
668 *p_local_port = mlxsw_reg_sfn_mac_system_port_get(payload, rec_index);
669}
670
671
672
673
674
675MLXSW_ITEM32_INDEXED(reg, sfn, mac_lag_lag_id, MLXSW_REG_SFN_BASE_LEN, 0, 10,
676 MLXSW_REG_SFN_REC_LEN, 0x0C, false);
677
678static inline void mlxsw_reg_sfn_mac_lag_unpack(char *payload, int rec_index,
679 char *mac, u16 *p_vid,
680 u16 *p_lag_id)
681{
682 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac);
683 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index);
684 *p_lag_id = mlxsw_reg_sfn_mac_lag_lag_id_get(payload, rec_index);
685}
686
687
688
689
690
691#define MLXSW_REG_SPMS_ID 0x200D
692#define MLXSW_REG_SPMS_LEN 0x404
693
694static const struct mlxsw_reg_info mlxsw_reg_spms = {
695 .id = MLXSW_REG_SPMS_ID,
696 .len = MLXSW_REG_SPMS_LEN,
697};
698
699
700
701
702
703MLXSW_ITEM32(reg, spms, local_port, 0x00, 16, 8);
704
705enum mlxsw_reg_spms_state {
706 MLXSW_REG_SPMS_STATE_NO_CHANGE,
707 MLXSW_REG_SPMS_STATE_DISCARDING,
708 MLXSW_REG_SPMS_STATE_LEARNING,
709 MLXSW_REG_SPMS_STATE_FORWARDING,
710};
711
712
713
714
715
716
717
718
719
720MLXSW_ITEM_BIT_ARRAY(reg, spms, state, 0x04, 0x400, 2);
721
722static inline void mlxsw_reg_spms_pack(char *payload, u8 local_port)
723{
724 MLXSW_REG_ZERO(spms, payload);
725 mlxsw_reg_spms_local_port_set(payload, local_port);
726}
727
728static inline void mlxsw_reg_spms_vid_pack(char *payload, u16 vid,
729 enum mlxsw_reg_spms_state state)
730{
731 mlxsw_reg_spms_state_set(payload, vid, state);
732}
733
734
735
736
737
738#define MLXSW_REG_SPVID_ID 0x200E
739#define MLXSW_REG_SPVID_LEN 0x08
740
741static const struct mlxsw_reg_info mlxsw_reg_spvid = {
742 .id = MLXSW_REG_SPVID_ID,
743 .len = MLXSW_REG_SPVID_LEN,
744};
745
746
747
748
749
750MLXSW_ITEM32(reg, spvid, local_port, 0x00, 16, 8);
751
752
753
754
755
756
757MLXSW_ITEM32(reg, spvid, sub_port, 0x00, 8, 8);
758
759
760
761
762
763MLXSW_ITEM32(reg, spvid, pvid, 0x04, 0, 12);
764
765static inline void mlxsw_reg_spvid_pack(char *payload, u8 local_port, u16 pvid)
766{
767 MLXSW_REG_ZERO(spvid, payload);
768 mlxsw_reg_spvid_local_port_set(payload, local_port);
769 mlxsw_reg_spvid_pvid_set(payload, pvid);
770}
771
772
773
774
775
776
777
778#define MLXSW_REG_SPVM_ID 0x200F
779#define MLXSW_REG_SPVM_BASE_LEN 0x04
780#define MLXSW_REG_SPVM_REC_LEN 0x04
781#define MLXSW_REG_SPVM_REC_MAX_COUNT 256
782#define MLXSW_REG_SPVM_LEN (MLXSW_REG_SPVM_BASE_LEN + \
783 MLXSW_REG_SPVM_REC_LEN * MLXSW_REG_SPVM_REC_MAX_COUNT)
784
785static const struct mlxsw_reg_info mlxsw_reg_spvm = {
786 .id = MLXSW_REG_SPVM_ID,
787 .len = MLXSW_REG_SPVM_LEN,
788};
789
790
791
792
793
794
795
796MLXSW_ITEM32(reg, spvm, pt, 0x00, 31, 1);
797
798
799
800
801
802
803MLXSW_ITEM32(reg, spvm, pte, 0x00, 30, 1);
804
805
806
807
808
809MLXSW_ITEM32(reg, spvm, local_port, 0x00, 16, 8);
810
811
812
813
814
815
816MLXSW_ITEM32(reg, spvm, sub_port, 0x00, 8, 8);
817
818
819
820
821
822MLXSW_ITEM32(reg, spvm, num_rec, 0x00, 0, 8);
823
824
825
826
827
828MLXSW_ITEM32_INDEXED(reg, spvm, rec_i,
829 MLXSW_REG_SPVM_BASE_LEN, 14, 1,
830 MLXSW_REG_SPVM_REC_LEN, 0, false);
831
832
833
834
835
836MLXSW_ITEM32_INDEXED(reg, spvm, rec_e,
837 MLXSW_REG_SPVM_BASE_LEN, 13, 1,
838 MLXSW_REG_SPVM_REC_LEN, 0, false);
839
840
841
842
843
844
845MLXSW_ITEM32_INDEXED(reg, spvm, rec_u,
846 MLXSW_REG_SPVM_BASE_LEN, 12, 1,
847 MLXSW_REG_SPVM_REC_LEN, 0, false);
848
849
850
851
852
853MLXSW_ITEM32_INDEXED(reg, spvm, rec_vid,
854 MLXSW_REG_SPVM_BASE_LEN, 0, 12,
855 MLXSW_REG_SPVM_REC_LEN, 0, false);
856
857static inline void mlxsw_reg_spvm_pack(char *payload, u8 local_port,
858 u16 vid_begin, u16 vid_end,
859 bool is_member, bool untagged)
860{
861 int size = vid_end - vid_begin + 1;
862 int i;
863
864 MLXSW_REG_ZERO(spvm, payload);
865 mlxsw_reg_spvm_local_port_set(payload, local_port);
866 mlxsw_reg_spvm_num_rec_set(payload, size);
867
868 for (i = 0; i < size; i++) {
869 mlxsw_reg_spvm_rec_i_set(payload, i, is_member);
870 mlxsw_reg_spvm_rec_e_set(payload, i, is_member);
871 mlxsw_reg_spvm_rec_u_set(payload, i, untagged);
872 mlxsw_reg_spvm_rec_vid_set(payload, i, vid_begin + i);
873 }
874}
875
876
877
878
879
880
881#define MLXSW_REG_SPAFT_ID 0x2010
882#define MLXSW_REG_SPAFT_LEN 0x08
883
884static const struct mlxsw_reg_info mlxsw_reg_spaft = {
885 .id = MLXSW_REG_SPAFT_ID,
886 .len = MLXSW_REG_SPAFT_LEN,
887};
888
889
890
891
892
893
894
895MLXSW_ITEM32(reg, spaft, local_port, 0x00, 16, 8);
896
897
898
899
900
901
902MLXSW_ITEM32(reg, spaft, sub_port, 0x00, 8, 8);
903
904
905
906
907
908MLXSW_ITEM32(reg, spaft, allow_untagged, 0x04, 31, 1);
909
910
911
912
913
914MLXSW_ITEM32(reg, spaft, allow_prio_tagged, 0x04, 30, 1);
915
916
917
918
919
920MLXSW_ITEM32(reg, spaft, allow_tagged, 0x04, 29, 1);
921
922static inline void mlxsw_reg_spaft_pack(char *payload, u8 local_port,
923 bool allow_untagged)
924{
925 MLXSW_REG_ZERO(spaft, payload);
926 mlxsw_reg_spaft_local_port_set(payload, local_port);
927 mlxsw_reg_spaft_allow_untagged_set(payload, allow_untagged);
928 mlxsw_reg_spaft_allow_prio_tagged_set(payload, true);
929 mlxsw_reg_spaft_allow_tagged_set(payload, true);
930}
931
932
933
934
935
936
937#define MLXSW_REG_SFGC_ID 0x2011
938#define MLXSW_REG_SFGC_LEN 0x10
939
940static const struct mlxsw_reg_info mlxsw_reg_sfgc = {
941 .id = MLXSW_REG_SFGC_ID,
942 .len = MLXSW_REG_SFGC_LEN,
943};
944
945enum mlxsw_reg_sfgc_type {
946 MLXSW_REG_SFGC_TYPE_BROADCAST,
947 MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST,
948 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4,
949 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6,
950 MLXSW_REG_SFGC_TYPE_RESERVED,
951 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP,
952 MLXSW_REG_SFGC_TYPE_IPV4_LINK_LOCAL,
953 MLXSW_REG_SFGC_TYPE_IPV6_ALL_HOST,
954 MLXSW_REG_SFGC_TYPE_MAX,
955};
956
957
958
959
960
961MLXSW_ITEM32(reg, sfgc, type, 0x00, 0, 4);
962
963enum mlxsw_reg_sfgc_bridge_type {
964 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID = 0,
965 MLXSW_REG_SFGC_BRIDGE_TYPE_VFID = 1,
966};
967
968
969
970
971
972
973MLXSW_ITEM32(reg, sfgc, bridge_type, 0x04, 24, 3);
974
975enum mlxsw_flood_table_type {
976 MLXSW_REG_SFGC_TABLE_TYPE_VID = 1,
977 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE = 2,
978 MLXSW_REG_SFGC_TABLE_TYPE_ANY = 0,
979 MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFEST = 3,
980 MLXSW_REG_SFGC_TABLE_TYPE_FID = 4,
981};
982
983
984
985
986
987
988
989MLXSW_ITEM32(reg, sfgc, table_type, 0x04, 16, 3);
990
991
992
993
994
995
996MLXSW_ITEM32(reg, sfgc, flood_table, 0x04, 0, 6);
997
998
999
1000
1001
1002MLXSW_ITEM32(reg, sfgc, mid, 0x08, 0, 16);
1003
1004
1005
1006
1007
1008MLXSW_ITEM32(reg, sfgc, counter_set_type, 0x0C, 24, 8);
1009
1010
1011
1012
1013
1014MLXSW_ITEM32(reg, sfgc, counter_index, 0x0C, 0, 24);
1015
1016static inline void
1017mlxsw_reg_sfgc_pack(char *payload, enum mlxsw_reg_sfgc_type type,
1018 enum mlxsw_reg_sfgc_bridge_type bridge_type,
1019 enum mlxsw_flood_table_type table_type,
1020 unsigned int flood_table)
1021{
1022 MLXSW_REG_ZERO(sfgc, payload);
1023 mlxsw_reg_sfgc_type_set(payload, type);
1024 mlxsw_reg_sfgc_bridge_type_set(payload, bridge_type);
1025 mlxsw_reg_sfgc_table_type_set(payload, table_type);
1026 mlxsw_reg_sfgc_flood_table_set(payload, flood_table);
1027 mlxsw_reg_sfgc_mid_set(payload, MLXSW_PORT_MID);
1028}
1029
1030
1031
1032
1033
1034
1035#define MLXSW_REG_SFTR_ID 0x2012
1036#define MLXSW_REG_SFTR_LEN 0x420
1037
1038static const struct mlxsw_reg_info mlxsw_reg_sftr = {
1039 .id = MLXSW_REG_SFTR_ID,
1040 .len = MLXSW_REG_SFTR_LEN,
1041};
1042
1043
1044
1045
1046
1047MLXSW_ITEM32(reg, sftr, swid, 0x00, 24, 8);
1048
1049
1050
1051
1052
1053
1054MLXSW_ITEM32(reg, sftr, flood_table, 0x00, 16, 6);
1055
1056
1057
1058
1059
1060
1061MLXSW_ITEM32(reg, sftr, index, 0x00, 0, 16);
1062
1063
1064
1065
1066
1067MLXSW_ITEM32(reg, sftr, table_type, 0x04, 16, 3);
1068
1069
1070
1071
1072
1073MLXSW_ITEM32(reg, sftr, range, 0x04, 0, 16);
1074
1075
1076
1077
1078
1079MLXSW_ITEM_BIT_ARRAY(reg, sftr, port, 0x20, 0x20, 1);
1080
1081
1082
1083
1084
1085MLXSW_ITEM_BIT_ARRAY(reg, sftr, port_mask, 0x220, 0x20, 1);
1086
1087static inline void mlxsw_reg_sftr_pack(char *payload,
1088 unsigned int flood_table,
1089 unsigned int index,
1090 enum mlxsw_flood_table_type table_type,
1091 unsigned int range, u8 port, bool set)
1092{
1093 MLXSW_REG_ZERO(sftr, payload);
1094 mlxsw_reg_sftr_swid_set(payload, 0);
1095 mlxsw_reg_sftr_flood_table_set(payload, flood_table);
1096 mlxsw_reg_sftr_index_set(payload, index);
1097 mlxsw_reg_sftr_table_type_set(payload, table_type);
1098 mlxsw_reg_sftr_range_set(payload, range);
1099 mlxsw_reg_sftr_port_set(payload, port, set);
1100 mlxsw_reg_sftr_port_mask_set(payload, port, 1);
1101}
1102
1103
1104
1105
1106
1107
1108#define MLXSW_REG_SFDF_ID 0x2013
1109#define MLXSW_REG_SFDF_LEN 0x14
1110
1111static const struct mlxsw_reg_info mlxsw_reg_sfdf = {
1112 .id = MLXSW_REG_SFDF_ID,
1113 .len = MLXSW_REG_SFDF_LEN,
1114};
1115
1116
1117
1118
1119
1120MLXSW_ITEM32(reg, sfdf, swid, 0x00, 24, 8);
1121
1122enum mlxsw_reg_sfdf_flush_type {
1123 MLXSW_REG_SFDF_FLUSH_PER_SWID,
1124 MLXSW_REG_SFDF_FLUSH_PER_FID,
1125 MLXSW_REG_SFDF_FLUSH_PER_PORT,
1126 MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID,
1127 MLXSW_REG_SFDF_FLUSH_PER_LAG,
1128 MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID,
1129};
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141MLXSW_ITEM32(reg, sfdf, flush_type, 0x04, 28, 4);
1142
1143
1144
1145
1146
1147
1148
1149MLXSW_ITEM32(reg, sfdf, flush_static, 0x04, 24, 1);
1150
1151static inline void mlxsw_reg_sfdf_pack(char *payload,
1152 enum mlxsw_reg_sfdf_flush_type type)
1153{
1154 MLXSW_REG_ZERO(sfdf, payload);
1155 mlxsw_reg_sfdf_flush_type_set(payload, type);
1156 mlxsw_reg_sfdf_flush_static_set(payload, true);
1157}
1158
1159
1160
1161
1162
1163MLXSW_ITEM32(reg, sfdf, fid, 0x0C, 0, 16);
1164
1165
1166
1167
1168
1169MLXSW_ITEM32(reg, sfdf, system_port, 0x0C, 0, 16);
1170
1171
1172
1173
1174
1175MLXSW_ITEM32(reg, sfdf, port_fid_system_port, 0x08, 0, 16);
1176
1177
1178
1179
1180
1181MLXSW_ITEM32(reg, sfdf, lag_id, 0x0C, 0, 10);
1182
1183
1184
1185
1186
1187MLXSW_ITEM32(reg, sfdf, lag_fid_lag_id, 0x08, 0, 10);
1188
1189
1190
1191
1192
1193
1194
1195#define MLXSW_REG_SLDR_ID 0x2014
1196#define MLXSW_REG_SLDR_LEN 0x0C
1197
1198static const struct mlxsw_reg_info mlxsw_reg_sldr = {
1199 .id = MLXSW_REG_SLDR_ID,
1200 .len = MLXSW_REG_SLDR_LEN,
1201};
1202
1203enum mlxsw_reg_sldr_op {
1204
1205 MLXSW_REG_SLDR_OP_LAG_CREATE,
1206 MLXSW_REG_SLDR_OP_LAG_DESTROY,
1207
1208 MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST,
1209
1210 MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST,
1211};
1212
1213
1214
1215
1216
1217MLXSW_ITEM32(reg, sldr, op, 0x00, 29, 3);
1218
1219
1220
1221
1222
1223MLXSW_ITEM32(reg, sldr, lag_id, 0x00, 0, 10);
1224
1225static inline void mlxsw_reg_sldr_lag_create_pack(char *payload, u8 lag_id)
1226{
1227 MLXSW_REG_ZERO(sldr, payload);
1228 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_CREATE);
1229 mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1230}
1231
1232static inline void mlxsw_reg_sldr_lag_destroy_pack(char *payload, u8 lag_id)
1233{
1234 MLXSW_REG_ZERO(sldr, payload);
1235 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_DESTROY);
1236 mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1237}
1238
1239
1240
1241
1242
1243
1244
1245MLXSW_ITEM32(reg, sldr, num_ports, 0x04, 24, 8);
1246
1247
1248
1249
1250
1251MLXSW_ITEM32_INDEXED(reg, sldr, system_port, 0x08, 0, 16, 4, 0, false);
1252
1253static inline void mlxsw_reg_sldr_lag_add_port_pack(char *payload, u8 lag_id,
1254 u8 local_port)
1255{
1256 MLXSW_REG_ZERO(sldr, payload);
1257 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST);
1258 mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1259 mlxsw_reg_sldr_num_ports_set(payload, 1);
1260 mlxsw_reg_sldr_system_port_set(payload, 0, local_port);
1261}
1262
1263static inline void mlxsw_reg_sldr_lag_remove_port_pack(char *payload, u8 lag_id,
1264 u8 local_port)
1265{
1266 MLXSW_REG_ZERO(sldr, payload);
1267 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST);
1268 mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1269 mlxsw_reg_sldr_num_ports_set(payload, 1);
1270 mlxsw_reg_sldr_system_port_set(payload, 0, local_port);
1271}
1272
1273
1274
1275
1276
1277
1278#define MLXSW_REG_SLCR_ID 0x2015
1279#define MLXSW_REG_SLCR_LEN 0x10
1280
1281static const struct mlxsw_reg_info mlxsw_reg_slcr = {
1282 .id = MLXSW_REG_SLCR_ID,
1283 .len = MLXSW_REG_SLCR_LEN,
1284};
1285
1286enum mlxsw_reg_slcr_pp {
1287
1288 MLXSW_REG_SLCR_PP_GLOBAL,
1289
1290 MLXSW_REG_SLCR_PP_PER_PORT,
1291};
1292
1293
1294
1295
1296
1297
1298MLXSW_ITEM32(reg, slcr, pp, 0x00, 24, 1);
1299
1300
1301
1302
1303
1304
1305
1306
1307MLXSW_ITEM32(reg, slcr, local_port, 0x00, 16, 8);
1308
1309enum mlxsw_reg_slcr_type {
1310 MLXSW_REG_SLCR_TYPE_CRC,
1311 MLXSW_REG_SLCR_TYPE_XOR,
1312 MLXSW_REG_SLCR_TYPE_RANDOM,
1313};
1314
1315
1316
1317
1318
1319MLXSW_ITEM32(reg, slcr, type, 0x00, 0, 4);
1320
1321
1322#define MLXSW_REG_SLCR_LAG_HASH_IN_PORT BIT(0)
1323
1324#define MLXSW_REG_SLCR_LAG_HASH_SMAC_IP BIT(1)
1325
1326#define MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP BIT(2)
1327#define MLXSW_REG_SLCR_LAG_HASH_SMAC \
1328 (MLXSW_REG_SLCR_LAG_HASH_SMAC_IP | \
1329 MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP)
1330
1331#define MLXSW_REG_SLCR_LAG_HASH_DMAC_IP BIT(3)
1332
1333#define MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP BIT(4)
1334#define MLXSW_REG_SLCR_LAG_HASH_DMAC \
1335 (MLXSW_REG_SLCR_LAG_HASH_DMAC_IP | \
1336 MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP)
1337
1338#define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP BIT(5)
1339
1340#define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP BIT(6)
1341#define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE \
1342 (MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP | \
1343 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP)
1344
1345#define MLXSW_REG_SLCR_LAG_HASH_VLANID_IP BIT(7)
1346
1347#define MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP BIT(8)
1348#define MLXSW_REG_SLCR_LAG_HASH_VLANID \
1349 (MLXSW_REG_SLCR_LAG_HASH_VLANID_IP | \
1350 MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP)
1351
1352#define MLXSW_REG_SLCR_LAG_HASH_SIP BIT(9)
1353
1354#define MLXSW_REG_SLCR_LAG_HASH_DIP BIT(10)
1355
1356#define MLXSW_REG_SLCR_LAG_HASH_SPORT BIT(11)
1357
1358#define MLXSW_REG_SLCR_LAG_HASH_DPORT BIT(12)
1359
1360#define MLXSW_REG_SLCR_LAG_HASH_IPPROTO BIT(13)
1361
1362#define MLXSW_REG_SLCR_LAG_HASH_FLOWLABEL BIT(14)
1363
1364#define MLXSW_REG_SLCR_LAG_HASH_FCOE_SID BIT(15)
1365
1366#define MLXSW_REG_SLCR_LAG_HASH_FCOE_DID BIT(16)
1367
1368#define MLXSW_REG_SLCR_LAG_HASH_FCOE_OXID BIT(17)
1369
1370#define MLXSW_REG_SLCR_LAG_HASH_ROCE_DQP BIT(19)
1371
1372
1373
1374
1375
1376
1377
1378
1379MLXSW_ITEM32(reg, slcr, lag_hash, 0x04, 0, 20);
1380
1381static inline void mlxsw_reg_slcr_pack(char *payload, u16 lag_hash)
1382{
1383 MLXSW_REG_ZERO(slcr, payload);
1384 mlxsw_reg_slcr_pp_set(payload, MLXSW_REG_SLCR_PP_GLOBAL);
1385 mlxsw_reg_slcr_type_set(payload, MLXSW_REG_SLCR_TYPE_XOR);
1386 mlxsw_reg_slcr_lag_hash_set(payload, lag_hash);
1387}
1388
1389
1390
1391
1392
1393
1394#define MLXSW_REG_SLCOR_ID 0x2016
1395#define MLXSW_REG_SLCOR_LEN 0x10
1396
1397static const struct mlxsw_reg_info mlxsw_reg_slcor = {
1398 .id = MLXSW_REG_SLCOR_ID,
1399 .len = MLXSW_REG_SLCOR_LEN,
1400};
1401
1402enum mlxsw_reg_slcor_col {
1403
1404 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT,
1405 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED,
1406 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_DISABLED,
1407 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT,
1408};
1409
1410
1411
1412
1413
1414MLXSW_ITEM32(reg, slcor, col, 0x00, 30, 2);
1415
1416
1417
1418
1419
1420
1421MLXSW_ITEM32(reg, slcor, local_port, 0x00, 16, 8);
1422
1423
1424
1425
1426
1427MLXSW_ITEM32(reg, slcor, lag_id, 0x00, 0, 10);
1428
1429
1430
1431
1432
1433
1434MLXSW_ITEM32(reg, slcor, port_index, 0x04, 0, 10);
1435
1436static inline void mlxsw_reg_slcor_pack(char *payload,
1437 u8 local_port, u16 lag_id,
1438 enum mlxsw_reg_slcor_col col)
1439{
1440 MLXSW_REG_ZERO(slcor, payload);
1441 mlxsw_reg_slcor_col_set(payload, col);
1442 mlxsw_reg_slcor_local_port_set(payload, local_port);
1443 mlxsw_reg_slcor_lag_id_set(payload, lag_id);
1444}
1445
1446static inline void mlxsw_reg_slcor_port_add_pack(char *payload,
1447 u8 local_port, u16 lag_id,
1448 u8 port_index)
1449{
1450 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1451 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT);
1452 mlxsw_reg_slcor_port_index_set(payload, port_index);
1453}
1454
1455static inline void mlxsw_reg_slcor_port_remove_pack(char *payload,
1456 u8 local_port, u16 lag_id)
1457{
1458 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1459 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT);
1460}
1461
1462static inline void mlxsw_reg_slcor_col_enable_pack(char *payload,
1463 u8 local_port, u16 lag_id)
1464{
1465 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1466 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED);
1467}
1468
1469static inline void mlxsw_reg_slcor_col_disable_pack(char *payload,
1470 u8 local_port, u16 lag_id)
1471{
1472 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1473 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED);
1474}
1475
1476
1477
1478
1479
1480#define MLXSW_REG_SPMLR_ID 0x2018
1481#define MLXSW_REG_SPMLR_LEN 0x8
1482
1483static const struct mlxsw_reg_info mlxsw_reg_spmlr = {
1484 .id = MLXSW_REG_SPMLR_ID,
1485 .len = MLXSW_REG_SPMLR_LEN,
1486};
1487
1488
1489
1490
1491
1492MLXSW_ITEM32(reg, spmlr, local_port, 0x00, 16, 8);
1493
1494
1495
1496
1497
1498
1499MLXSW_ITEM32(reg, spmlr, sub_port, 0x00, 8, 8);
1500
1501enum mlxsw_reg_spmlr_learn_mode {
1502 MLXSW_REG_SPMLR_LEARN_MODE_DISABLE = 0,
1503 MLXSW_REG_SPMLR_LEARN_MODE_ENABLE = 2,
1504 MLXSW_REG_SPMLR_LEARN_MODE_SEC = 3,
1505};
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518MLXSW_ITEM32(reg, spmlr, learn_mode, 0x04, 30, 2);
1519
1520static inline void mlxsw_reg_spmlr_pack(char *payload, u8 local_port,
1521 enum mlxsw_reg_spmlr_learn_mode mode)
1522{
1523 MLXSW_REG_ZERO(spmlr, payload);
1524 mlxsw_reg_spmlr_local_port_set(payload, local_port);
1525 mlxsw_reg_spmlr_sub_port_set(payload, 0);
1526 mlxsw_reg_spmlr_learn_mode_set(payload, mode);
1527}
1528
1529
1530
1531
1532
1533
1534#define MLXSW_REG_SVFA_ID 0x201C
1535#define MLXSW_REG_SVFA_LEN 0x10
1536
1537static const struct mlxsw_reg_info mlxsw_reg_svfa = {
1538 .id = MLXSW_REG_SVFA_ID,
1539 .len = MLXSW_REG_SVFA_LEN,
1540};
1541
1542
1543
1544
1545
1546MLXSW_ITEM32(reg, svfa, swid, 0x00, 24, 8);
1547
1548
1549
1550
1551
1552
1553
1554MLXSW_ITEM32(reg, svfa, local_port, 0x00, 16, 8);
1555
1556enum mlxsw_reg_svfa_mt {
1557 MLXSW_REG_SVFA_MT_VID_TO_FID,
1558 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID,
1559};
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569MLXSW_ITEM32(reg, svfa, mapping_table, 0x00, 8, 3);
1570
1571
1572
1573
1574
1575
1576
1577
1578MLXSW_ITEM32(reg, svfa, v, 0x00, 0, 1);
1579
1580
1581
1582
1583
1584MLXSW_ITEM32(reg, svfa, fid, 0x04, 16, 16);
1585
1586
1587
1588
1589
1590MLXSW_ITEM32(reg, svfa, vid, 0x04, 0, 12);
1591
1592
1593
1594
1595
1596
1597
1598MLXSW_ITEM32(reg, svfa, counter_set_type, 0x08, 24, 8);
1599
1600
1601
1602
1603
1604
1605
1606MLXSW_ITEM32(reg, svfa, counter_index, 0x08, 0, 24);
1607
1608static inline void mlxsw_reg_svfa_pack(char *payload, u8 local_port,
1609 enum mlxsw_reg_svfa_mt mt, bool valid,
1610 u16 fid, u16 vid)
1611{
1612 MLXSW_REG_ZERO(svfa, payload);
1613 local_port = mt == MLXSW_REG_SVFA_MT_VID_TO_FID ? 0 : local_port;
1614 mlxsw_reg_svfa_swid_set(payload, 0);
1615 mlxsw_reg_svfa_local_port_set(payload, local_port);
1616 mlxsw_reg_svfa_mapping_table_set(payload, mt);
1617 mlxsw_reg_svfa_v_set(payload, valid);
1618 mlxsw_reg_svfa_fid_set(payload, fid);
1619 mlxsw_reg_svfa_vid_set(payload, vid);
1620}
1621
1622
1623
1624
1625
1626#define MLXSW_REG_SVPE_ID 0x201E
1627#define MLXSW_REG_SVPE_LEN 0x4
1628
1629static const struct mlxsw_reg_info mlxsw_reg_svpe = {
1630 .id = MLXSW_REG_SVPE_ID,
1631 .len = MLXSW_REG_SVPE_LEN,
1632};
1633
1634
1635
1636
1637
1638
1639
1640MLXSW_ITEM32(reg, svpe, local_port, 0x00, 16, 8);
1641
1642
1643
1644
1645
1646
1647
1648MLXSW_ITEM32(reg, svpe, vp_en, 0x00, 8, 1);
1649
1650static inline void mlxsw_reg_svpe_pack(char *payload, u8 local_port,
1651 bool enable)
1652{
1653 MLXSW_REG_ZERO(svpe, payload);
1654 mlxsw_reg_svpe_local_port_set(payload, local_port);
1655 mlxsw_reg_svpe_vp_en_set(payload, enable);
1656}
1657
1658
1659
1660
1661
1662#define MLXSW_REG_SFMR_ID 0x201F
1663#define MLXSW_REG_SFMR_LEN 0x18
1664
1665static const struct mlxsw_reg_info mlxsw_reg_sfmr = {
1666 .id = MLXSW_REG_SFMR_ID,
1667 .len = MLXSW_REG_SFMR_LEN,
1668};
1669
1670enum mlxsw_reg_sfmr_op {
1671 MLXSW_REG_SFMR_OP_CREATE_FID,
1672 MLXSW_REG_SFMR_OP_DESTROY_FID,
1673};
1674
1675
1676
1677
1678
1679
1680
1681MLXSW_ITEM32(reg, sfmr, op, 0x00, 24, 4);
1682
1683
1684
1685
1686
1687MLXSW_ITEM32(reg, sfmr, fid, 0x00, 0, 16);
1688
1689
1690
1691
1692
1693
1694
1695MLXSW_ITEM32(reg, sfmr, fid_offset, 0x08, 0, 16);
1696
1697
1698
1699
1700
1701
1702
1703
1704MLXSW_ITEM32(reg, sfmr, vtfp, 0x0C, 31, 1);
1705
1706
1707
1708
1709
1710
1711
1712MLXSW_ITEM32(reg, sfmr, nve_tunnel_flood_ptr, 0x0C, 0, 24);
1713
1714
1715
1716
1717
1718
1719
1720
1721MLXSW_ITEM32(reg, sfmr, vv, 0x10, 31, 1);
1722
1723
1724
1725
1726
1727
1728
1729MLXSW_ITEM32(reg, sfmr, vni, 0x10, 0, 24);
1730
1731static inline void mlxsw_reg_sfmr_pack(char *payload,
1732 enum mlxsw_reg_sfmr_op op, u16 fid,
1733 u16 fid_offset)
1734{
1735 MLXSW_REG_ZERO(sfmr, payload);
1736 mlxsw_reg_sfmr_op_set(payload, op);
1737 mlxsw_reg_sfmr_fid_set(payload, fid);
1738 mlxsw_reg_sfmr_fid_offset_set(payload, fid_offset);
1739 mlxsw_reg_sfmr_vtfp_set(payload, false);
1740 mlxsw_reg_sfmr_vv_set(payload, false);
1741}
1742
1743
1744
1745
1746
1747#define MLXSW_REG_SPVMLR_ID 0x2020
1748#define MLXSW_REG_SPVMLR_BASE_LEN 0x04
1749#define MLXSW_REG_SPVMLR_REC_LEN 0x04
1750#define MLXSW_REG_SPVMLR_REC_MAX_COUNT 256
1751#define MLXSW_REG_SPVMLR_LEN (MLXSW_REG_SPVMLR_BASE_LEN + \
1752 MLXSW_REG_SPVMLR_REC_LEN * \
1753 MLXSW_REG_SPVMLR_REC_MAX_COUNT)
1754
1755static const struct mlxsw_reg_info mlxsw_reg_spvmlr = {
1756 .id = MLXSW_REG_SPVMLR_ID,
1757 .len = MLXSW_REG_SPVMLR_LEN,
1758};
1759
1760
1761
1762
1763
1764
1765
1766MLXSW_ITEM32(reg, spvmlr, local_port, 0x00, 16, 8);
1767
1768
1769
1770
1771
1772MLXSW_ITEM32(reg, spvmlr, num_rec, 0x00, 0, 8);
1773
1774
1775
1776
1777
1778
1779MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_learn_enable, MLXSW_REG_SPVMLR_BASE_LEN,
1780 31, 1, MLXSW_REG_SPVMLR_REC_LEN, 0x00, false);
1781
1782
1783
1784
1785
1786MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_vid, MLXSW_REG_SPVMLR_BASE_LEN, 0, 12,
1787 MLXSW_REG_SPVMLR_REC_LEN, 0x00, false);
1788
1789static inline void mlxsw_reg_spvmlr_pack(char *payload, u8 local_port,
1790 u16 vid_begin, u16 vid_end,
1791 bool learn_enable)
1792{
1793 int num_rec = vid_end - vid_begin + 1;
1794 int i;
1795
1796 WARN_ON(num_rec < 1 || num_rec > MLXSW_REG_SPVMLR_REC_MAX_COUNT);
1797
1798 MLXSW_REG_ZERO(spvmlr, payload);
1799 mlxsw_reg_spvmlr_local_port_set(payload, local_port);
1800 mlxsw_reg_spvmlr_num_rec_set(payload, num_rec);
1801
1802 for (i = 0; i < num_rec; i++) {
1803 mlxsw_reg_spvmlr_rec_learn_enable_set(payload, i, learn_enable);
1804 mlxsw_reg_spvmlr_rec_vid_set(payload, i, vid_begin + i);
1805 }
1806}
1807
1808
1809
1810
1811
1812#define MLXSW_REG_PMLP_ID 0x5002
1813#define MLXSW_REG_PMLP_LEN 0x40
1814
1815static const struct mlxsw_reg_info mlxsw_reg_pmlp = {
1816 .id = MLXSW_REG_PMLP_ID,
1817 .len = MLXSW_REG_PMLP_LEN,
1818};
1819
1820
1821
1822
1823
1824
1825MLXSW_ITEM32(reg, pmlp, rxtx, 0x00, 31, 1);
1826
1827
1828
1829
1830
1831MLXSW_ITEM32(reg, pmlp, local_port, 0x00, 16, 8);
1832
1833
1834
1835
1836
1837
1838
1839
1840MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8);
1841
1842
1843
1844
1845
1846MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0x00, false);
1847
1848
1849
1850
1851
1852MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 2, 0x04, 0x00, false);
1853
1854
1855
1856
1857
1858
1859MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 2, 0x04, 0x00, false);
1860
1861static inline void mlxsw_reg_pmlp_pack(char *payload, u8 local_port)
1862{
1863 MLXSW_REG_ZERO(pmlp, payload);
1864 mlxsw_reg_pmlp_local_port_set(payload, local_port);
1865}
1866
1867
1868
1869
1870
1871#define MLXSW_REG_PMTU_ID 0x5003
1872#define MLXSW_REG_PMTU_LEN 0x10
1873
1874static const struct mlxsw_reg_info mlxsw_reg_pmtu = {
1875 .id = MLXSW_REG_PMTU_ID,
1876 .len = MLXSW_REG_PMTU_LEN,
1877};
1878
1879
1880
1881
1882
1883MLXSW_ITEM32(reg, pmtu, local_port, 0x00, 16, 8);
1884
1885
1886
1887
1888
1889
1890
1891
1892MLXSW_ITEM32(reg, pmtu, max_mtu, 0x04, 16, 16);
1893
1894
1895
1896
1897
1898
1899
1900MLXSW_ITEM32(reg, pmtu, admin_mtu, 0x08, 16, 16);
1901
1902
1903
1904
1905
1906
1907
1908
1909MLXSW_ITEM32(reg, pmtu, oper_mtu, 0x0C, 16, 16);
1910
1911static inline void mlxsw_reg_pmtu_pack(char *payload, u8 local_port,
1912 u16 new_mtu)
1913{
1914 MLXSW_REG_ZERO(pmtu, payload);
1915 mlxsw_reg_pmtu_local_port_set(payload, local_port);
1916 mlxsw_reg_pmtu_max_mtu_set(payload, 0);
1917 mlxsw_reg_pmtu_admin_mtu_set(payload, new_mtu);
1918 mlxsw_reg_pmtu_oper_mtu_set(payload, 0);
1919}
1920
1921
1922
1923
1924
1925
1926
1927
1928#define MLXSW_REG_PTYS_ID 0x5004
1929#define MLXSW_REG_PTYS_LEN 0x40
1930
1931static const struct mlxsw_reg_info mlxsw_reg_ptys = {
1932 .id = MLXSW_REG_PTYS_ID,
1933 .len = MLXSW_REG_PTYS_LEN,
1934};
1935
1936
1937
1938
1939
1940MLXSW_ITEM32(reg, ptys, local_port, 0x00, 16, 8);
1941
1942#define MLXSW_REG_PTYS_PROTO_MASK_ETH BIT(2)
1943
1944
1945
1946
1947
1948
1949
1950
1951MLXSW_ITEM32(reg, ptys, proto_mask, 0x00, 0, 3);
1952
1953#define MLXSW_REG_PTYS_ETH_SPEED_SGMII BIT(0)
1954#define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX BIT(1)
1955#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 BIT(2)
1956#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 BIT(3)
1957#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR BIT(4)
1958#define MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2 BIT(5)
1959#define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 BIT(6)
1960#define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 BIT(7)
1961#define MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4 BIT(8)
1962#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR BIT(12)
1963#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR BIT(13)
1964#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR BIT(14)
1965#define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 BIT(15)
1966#define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4 BIT(16)
1967#define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 BIT(19)
1968#define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 BIT(20)
1969#define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 BIT(21)
1970#define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 BIT(22)
1971#define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4 BIT(23)
1972#define MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX BIT(24)
1973#define MLXSW_REG_PTYS_ETH_SPEED_100BASE_T BIT(25)
1974#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T BIT(26)
1975#define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR BIT(27)
1976#define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR BIT(28)
1977#define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR BIT(29)
1978#define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 BIT(30)
1979#define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2 BIT(31)
1980
1981
1982
1983
1984
1985MLXSW_ITEM32(reg, ptys, eth_proto_cap, 0x0C, 0, 32);
1986
1987
1988
1989
1990
1991MLXSW_ITEM32(reg, ptys, eth_proto_admin, 0x18, 0, 32);
1992
1993
1994
1995
1996
1997MLXSW_ITEM32(reg, ptys, eth_proto_oper, 0x24, 0, 32);
1998
1999static inline void mlxsw_reg_ptys_pack(char *payload, u8 local_port,
2000 u32 proto_admin)
2001{
2002 MLXSW_REG_ZERO(ptys, payload);
2003 mlxsw_reg_ptys_local_port_set(payload, local_port);
2004 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH);
2005 mlxsw_reg_ptys_eth_proto_admin_set(payload, proto_admin);
2006}
2007
2008static inline void mlxsw_reg_ptys_unpack(char *payload, u32 *p_eth_proto_cap,
2009 u32 *p_eth_proto_adm,
2010 u32 *p_eth_proto_oper)
2011{
2012 if (p_eth_proto_cap)
2013 *p_eth_proto_cap = mlxsw_reg_ptys_eth_proto_cap_get(payload);
2014 if (p_eth_proto_adm)
2015 *p_eth_proto_adm = mlxsw_reg_ptys_eth_proto_admin_get(payload);
2016 if (p_eth_proto_oper)
2017 *p_eth_proto_oper = mlxsw_reg_ptys_eth_proto_oper_get(payload);
2018}
2019
2020
2021
2022
2023
2024#define MLXSW_REG_PPAD_ID 0x5005
2025#define MLXSW_REG_PPAD_LEN 0x10
2026
2027static const struct mlxsw_reg_info mlxsw_reg_ppad = {
2028 .id = MLXSW_REG_PPAD_ID,
2029 .len = MLXSW_REG_PPAD_LEN,
2030};
2031
2032
2033
2034
2035
2036
2037
2038MLXSW_ITEM32(reg, ppad, single_base_mac, 0x00, 28, 1);
2039
2040
2041
2042
2043
2044MLXSW_ITEM32(reg, ppad, local_port, 0x00, 16, 8);
2045
2046
2047
2048
2049
2050
2051MLXSW_ITEM_BUF(reg, ppad, mac, 0x02, 6);
2052
2053static inline void mlxsw_reg_ppad_pack(char *payload, bool single_base_mac,
2054 u8 local_port)
2055{
2056 MLXSW_REG_ZERO(ppad, payload);
2057 mlxsw_reg_ppad_single_base_mac_set(payload, !!single_base_mac);
2058 mlxsw_reg_ppad_local_port_set(payload, local_port);
2059}
2060
2061
2062
2063
2064
2065#define MLXSW_REG_PAOS_ID 0x5006
2066#define MLXSW_REG_PAOS_LEN 0x10
2067
2068static const struct mlxsw_reg_info mlxsw_reg_paos = {
2069 .id = MLXSW_REG_PAOS_ID,
2070 .len = MLXSW_REG_PAOS_LEN,
2071};
2072
2073
2074
2075
2076
2077
2078
2079
2080MLXSW_ITEM32(reg, paos, swid, 0x00, 24, 8);
2081
2082
2083
2084
2085
2086MLXSW_ITEM32(reg, paos, local_port, 0x00, 16, 8);
2087
2088
2089
2090
2091
2092
2093
2094
2095
2096
2097MLXSW_ITEM32(reg, paos, admin_status, 0x00, 8, 4);
2098
2099
2100
2101
2102
2103
2104
2105
2106
2107MLXSW_ITEM32(reg, paos, oper_status, 0x00, 0, 4);
2108
2109
2110
2111
2112
2113MLXSW_ITEM32(reg, paos, ase, 0x04, 31, 1);
2114
2115
2116
2117
2118
2119
2120MLXSW_ITEM32(reg, paos, ee, 0x04, 30, 1);
2121
2122
2123
2124
2125
2126
2127
2128
2129MLXSW_ITEM32(reg, paos, e, 0x04, 0, 2);
2130
2131static inline void mlxsw_reg_paos_pack(char *payload, u8 local_port,
2132 enum mlxsw_port_admin_status status)
2133{
2134 MLXSW_REG_ZERO(paos, payload);
2135 mlxsw_reg_paos_swid_set(payload, 0);
2136 mlxsw_reg_paos_local_port_set(payload, local_port);
2137 mlxsw_reg_paos_admin_status_set(payload, status);
2138 mlxsw_reg_paos_oper_status_set(payload, 0);
2139 mlxsw_reg_paos_ase_set(payload, 1);
2140 mlxsw_reg_paos_ee_set(payload, 1);
2141 mlxsw_reg_paos_e_set(payload, 1);
2142}
2143
2144
2145
2146
2147
2148#define MLXSW_REG_PPCNT_ID 0x5008
2149#define MLXSW_REG_PPCNT_LEN 0x100
2150
2151static const struct mlxsw_reg_info mlxsw_reg_ppcnt = {
2152 .id = MLXSW_REG_PPCNT_ID,
2153 .len = MLXSW_REG_PPCNT_LEN,
2154};
2155
2156
2157
2158
2159
2160
2161
2162
2163
2164
2165MLXSW_ITEM32(reg, ppcnt, swid, 0x00, 24, 8);
2166
2167
2168
2169
2170
2171
2172
2173MLXSW_ITEM32(reg, ppcnt, local_port, 0x00, 16, 8);
2174
2175
2176
2177
2178
2179
2180
2181MLXSW_ITEM32(reg, ppcnt, pnat, 0x00, 14, 2);
2182
2183
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193
2194
2195
2196
2197
2198MLXSW_ITEM32(reg, ppcnt, grp, 0x00, 0, 6);
2199
2200
2201
2202
2203
2204
2205
2206MLXSW_ITEM32(reg, ppcnt, clr, 0x04, 31, 1);
2207
2208
2209
2210
2211
2212
2213
2214
2215
2216MLXSW_ITEM32(reg, ppcnt, prio_tc, 0x04, 0, 5);
2217
2218
2219
2220
2221MLXSW_ITEM64(reg, ppcnt, a_frames_transmitted_ok,
2222 0x08 + 0x00, 0, 64);
2223
2224
2225
2226
2227MLXSW_ITEM64(reg, ppcnt, a_frames_received_ok,
2228 0x08 + 0x08, 0, 64);
2229
2230
2231
2232
2233MLXSW_ITEM64(reg, ppcnt, a_frame_check_sequence_errors,
2234 0x08 + 0x10, 0, 64);
2235
2236
2237
2238
2239MLXSW_ITEM64(reg, ppcnt, a_alignment_errors,
2240 0x08 + 0x18, 0, 64);
2241
2242
2243
2244
2245MLXSW_ITEM64(reg, ppcnt, a_octets_transmitted_ok,
2246 0x08 + 0x20, 0, 64);
2247
2248
2249
2250
2251MLXSW_ITEM64(reg, ppcnt, a_octets_received_ok,
2252 0x08 + 0x28, 0, 64);
2253
2254
2255
2256
2257MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_xmitted_ok,
2258 0x08 + 0x30, 0, 64);
2259
2260
2261
2262
2263MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_xmitted_ok,
2264 0x08 + 0x38, 0, 64);
2265
2266
2267
2268
2269MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_received_ok,
2270 0x08 + 0x40, 0, 64);
2271
2272
2273
2274
2275MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_received_ok,
2276 0x08 + 0x48, 0, 64);
2277
2278
2279
2280
2281MLXSW_ITEM64(reg, ppcnt, a_in_range_length_errors,
2282 0x08 + 0x50, 0, 64);
2283
2284
2285
2286
2287MLXSW_ITEM64(reg, ppcnt, a_out_of_range_length_field,
2288 0x08 + 0x58, 0, 64);
2289
2290
2291
2292
2293MLXSW_ITEM64(reg, ppcnt, a_frame_too_long_errors,
2294 0x08 + 0x60, 0, 64);
2295
2296
2297
2298
2299MLXSW_ITEM64(reg, ppcnt, a_symbol_error_during_carrier,
2300 0x08 + 0x68, 0, 64);
2301
2302
2303
2304
2305MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_transmitted,
2306 0x08 + 0x70, 0, 64);
2307
2308
2309
2310
2311MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_received,
2312 0x08 + 0x78, 0, 64);
2313
2314
2315
2316
2317MLXSW_ITEM64(reg, ppcnt, a_unsupported_opcodes_received,
2318 0x08 + 0x80, 0, 64);
2319
2320
2321
2322
2323MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_received,
2324 0x08 + 0x88, 0, 64);
2325
2326
2327
2328
2329MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_transmitted,
2330 0x08 + 0x90, 0, 64);
2331
2332static inline void mlxsw_reg_ppcnt_pack(char *payload, u8 local_port)
2333{
2334 MLXSW_REG_ZERO(ppcnt, payload);
2335 mlxsw_reg_ppcnt_swid_set(payload, 0);
2336 mlxsw_reg_ppcnt_local_port_set(payload, local_port);
2337 mlxsw_reg_ppcnt_pnat_set(payload, 0);
2338 mlxsw_reg_ppcnt_grp_set(payload, 0);
2339 mlxsw_reg_ppcnt_clr_set(payload, 0);
2340 mlxsw_reg_ppcnt_prio_tc_set(payload, 0);
2341}
2342
2343
2344
2345
2346
2347
2348#define MLXSW_REG_PBMC_ID 0x500C
2349#define MLXSW_REG_PBMC_LEN 0x68
2350
2351static const struct mlxsw_reg_info mlxsw_reg_pbmc = {
2352 .id = MLXSW_REG_PBMC_ID,
2353 .len = MLXSW_REG_PBMC_LEN,
2354};
2355
2356
2357
2358
2359
2360MLXSW_ITEM32(reg, pbmc, local_port, 0x00, 16, 8);
2361
2362
2363
2364
2365
2366
2367MLXSW_ITEM32(reg, pbmc, xoff_timer_value, 0x04, 16, 16);
2368
2369
2370
2371
2372
2373
2374
2375MLXSW_ITEM32(reg, pbmc, xoff_refresh, 0x04, 0, 16);
2376
2377
2378
2379
2380
2381
2382
2383MLXSW_ITEM32_INDEXED(reg, pbmc, buf_lossy, 0x0C, 25, 1, 0x08, 0x00, false);
2384
2385
2386
2387
2388
2389
2390
2391
2392MLXSW_ITEM32_INDEXED(reg, pbmc, buf_epsb, 0x0C, 24, 1, 0x08, 0x00, false);
2393
2394
2395
2396
2397
2398
2399MLXSW_ITEM32_INDEXED(reg, pbmc, buf_size, 0x0C, 0, 16, 0x08, 0x00, false);
2400
2401static inline void mlxsw_reg_pbmc_pack(char *payload, u8 local_port,
2402 u16 xoff_timer_value, u16 xoff_refresh)
2403{
2404 MLXSW_REG_ZERO(pbmc, payload);
2405 mlxsw_reg_pbmc_local_port_set(payload, local_port);
2406 mlxsw_reg_pbmc_xoff_timer_value_set(payload, xoff_timer_value);
2407 mlxsw_reg_pbmc_xoff_refresh_set(payload, xoff_refresh);
2408}
2409
2410static inline void mlxsw_reg_pbmc_lossy_buffer_pack(char *payload,
2411 int buf_index,
2412 u16 size)
2413{
2414 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 1);
2415 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0);
2416 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size);
2417}
2418
2419
2420
2421
2422
2423
2424#define MLXSW_REG_PSPA_ID 0x500D
2425#define MLXSW_REG_PSPA_LEN 0x8
2426
2427static const struct mlxsw_reg_info mlxsw_reg_pspa = {
2428 .id = MLXSW_REG_PSPA_ID,
2429 .len = MLXSW_REG_PSPA_LEN,
2430};
2431
2432
2433
2434
2435
2436MLXSW_ITEM32(reg, pspa, swid, 0x00, 24, 8);
2437
2438
2439
2440
2441
2442MLXSW_ITEM32(reg, pspa, local_port, 0x00, 16, 8);
2443
2444
2445
2446
2447
2448
2449MLXSW_ITEM32(reg, pspa, sub_port, 0x00, 8, 8);
2450
2451static inline void mlxsw_reg_pspa_pack(char *payload, u8 swid, u8 local_port)
2452{
2453 MLXSW_REG_ZERO(pspa, payload);
2454 mlxsw_reg_pspa_swid_set(payload, swid);
2455 mlxsw_reg_pspa_local_port_set(payload, local_port);
2456 mlxsw_reg_pspa_sub_port_set(payload, 0);
2457}
2458
2459
2460
2461
2462
2463#define MLXSW_REG_HTGT_ID 0x7002
2464#define MLXSW_REG_HTGT_LEN 0x100
2465
2466static const struct mlxsw_reg_info mlxsw_reg_htgt = {
2467 .id = MLXSW_REG_HTGT_ID,
2468 .len = MLXSW_REG_HTGT_LEN,
2469};
2470
2471
2472
2473
2474
2475MLXSW_ITEM32(reg, htgt, swid, 0x00, 24, 8);
2476
2477#define MLXSW_REG_HTGT_PATH_TYPE_LOCAL 0x0
2478
2479
2480
2481
2482
2483MLXSW_ITEM32(reg, htgt, type, 0x00, 8, 4);
2484
2485enum mlxsw_reg_htgt_trap_group {
2486 MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
2487 MLXSW_REG_HTGT_TRAP_GROUP_RX,
2488 MLXSW_REG_HTGT_TRAP_GROUP_CTRL,
2489};
2490
2491
2492
2493
2494
2495
2496
2497MLXSW_ITEM32(reg, htgt, trap_group, 0x00, 0, 8);
2498
2499enum {
2500 MLXSW_REG_HTGT_POLICER_DISABLE,
2501 MLXSW_REG_HTGT_POLICER_ENABLE,
2502};
2503
2504
2505
2506
2507
2508MLXSW_ITEM32(reg, htgt, pide, 0x04, 15, 1);
2509
2510
2511
2512
2513
2514MLXSW_ITEM32(reg, htgt, pid, 0x04, 0, 8);
2515
2516#define MLXSW_REG_HTGT_TRAP_TO_CPU 0x0
2517
2518
2519
2520
2521
2522
2523
2524
2525
2526
2527MLXSW_ITEM32(reg, htgt, mirror_action, 0x08, 8, 2);
2528
2529
2530
2531
2532
2533MLXSW_ITEM32(reg, htgt, mirroring_agent, 0x08, 0, 3);
2534
2535
2536
2537
2538
2539
2540
2541
2542
2543
2544
2545
2546MLXSW_ITEM32(reg, htgt, priority, 0x0C, 0, 4);
2547
2548
2549
2550
2551
2552MLXSW_ITEM32(reg, htgt, local_path_cpu_tclass, 0x10, 16, 6);
2553
2554#define MLXSW_REG_HTGT_LOCAL_PATH_RDQ_EMAD 0x15
2555#define MLXSW_REG_HTGT_LOCAL_PATH_RDQ_RX 0x14
2556#define MLXSW_REG_HTGT_LOCAL_PATH_RDQ_CTRL 0x13
2557
2558
2559
2560
2561
2562MLXSW_ITEM32(reg, htgt, local_path_rdq, 0x10, 0, 6);
2563
2564static inline void mlxsw_reg_htgt_pack(char *payload,
2565 enum mlxsw_reg_htgt_trap_group group)
2566{
2567 u8 swid, rdq;
2568
2569 MLXSW_REG_ZERO(htgt, payload);
2570 switch (group) {
2571 case MLXSW_REG_HTGT_TRAP_GROUP_EMAD:
2572 swid = MLXSW_PORT_SWID_ALL_SWIDS;
2573 rdq = MLXSW_REG_HTGT_LOCAL_PATH_RDQ_EMAD;
2574 break;
2575 case MLXSW_REG_HTGT_TRAP_GROUP_RX:
2576 swid = 0;
2577 rdq = MLXSW_REG_HTGT_LOCAL_PATH_RDQ_RX;
2578 break;
2579 case MLXSW_REG_HTGT_TRAP_GROUP_CTRL:
2580 swid = 0;
2581 rdq = MLXSW_REG_HTGT_LOCAL_PATH_RDQ_CTRL;
2582 break;
2583 }
2584 mlxsw_reg_htgt_swid_set(payload, swid);
2585 mlxsw_reg_htgt_type_set(payload, MLXSW_REG_HTGT_PATH_TYPE_LOCAL);
2586 mlxsw_reg_htgt_trap_group_set(payload, group);
2587 mlxsw_reg_htgt_pide_set(payload, MLXSW_REG_HTGT_POLICER_DISABLE);
2588 mlxsw_reg_htgt_pid_set(payload, 0);
2589 mlxsw_reg_htgt_mirror_action_set(payload, MLXSW_REG_HTGT_TRAP_TO_CPU);
2590 mlxsw_reg_htgt_mirroring_agent_set(payload, 0);
2591 mlxsw_reg_htgt_priority_set(payload, 0);
2592 mlxsw_reg_htgt_local_path_cpu_tclass_set(payload, 7);
2593 mlxsw_reg_htgt_local_path_rdq_set(payload, rdq);
2594}
2595
2596
2597
2598
2599
2600#define MLXSW_REG_HPKT_ID 0x7003
2601#define MLXSW_REG_HPKT_LEN 0x10
2602
2603static const struct mlxsw_reg_info mlxsw_reg_hpkt = {
2604 .id = MLXSW_REG_HPKT_ID,
2605 .len = MLXSW_REG_HPKT_LEN,
2606};
2607
2608enum {
2609 MLXSW_REG_HPKT_ACK_NOT_REQUIRED,
2610 MLXSW_REG_HPKT_ACK_REQUIRED,
2611};
2612
2613
2614
2615
2616
2617
2618
2619
2620
2621MLXSW_ITEM32(reg, hpkt, ack, 0x00, 24, 1);
2622
2623enum mlxsw_reg_hpkt_action {
2624 MLXSW_REG_HPKT_ACTION_FORWARD,
2625 MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU,
2626 MLXSW_REG_HPKT_ACTION_MIRROR_TO_CPU,
2627 MLXSW_REG_HPKT_ACTION_DISCARD,
2628 MLXSW_REG_HPKT_ACTION_SOFT_DISCARD,
2629 MLXSW_REG_HPKT_ACTION_TRAP_AND_SOFT_DISCARD,
2630};
2631
2632
2633
2634
2635
2636
2637
2638
2639
2640
2641
2642
2643
2644
2645MLXSW_ITEM32(reg, hpkt, action, 0x00, 20, 3);
2646
2647
2648
2649
2650
2651MLXSW_ITEM32(reg, hpkt, trap_group, 0x00, 12, 6);
2652
2653
2654
2655
2656
2657
2658
2659
2660MLXSW_ITEM32(reg, hpkt, trap_id, 0x00, 0, 9);
2661
2662enum {
2663 MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT,
2664 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER,
2665 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER,
2666};
2667
2668
2669
2670
2671
2672
2673
2674
2675MLXSW_ITEM32(reg, hpkt, ctrl, 0x04, 16, 2);
2676
2677static inline void mlxsw_reg_hpkt_pack(char *payload, u8 action, u16 trap_id)
2678{
2679 enum mlxsw_reg_htgt_trap_group trap_group;
2680
2681 MLXSW_REG_ZERO(hpkt, payload);
2682 mlxsw_reg_hpkt_ack_set(payload, MLXSW_REG_HPKT_ACK_NOT_REQUIRED);
2683 mlxsw_reg_hpkt_action_set(payload, action);
2684 switch (trap_id) {
2685 case MLXSW_TRAP_ID_ETHEMAD:
2686 case MLXSW_TRAP_ID_PUDE:
2687 trap_group = MLXSW_REG_HTGT_TRAP_GROUP_EMAD;
2688 break;
2689 default:
2690 trap_group = MLXSW_REG_HTGT_TRAP_GROUP_RX;
2691 break;
2692 }
2693 mlxsw_reg_hpkt_trap_group_set(payload, trap_group);
2694 mlxsw_reg_hpkt_trap_id_set(payload, trap_id);
2695 mlxsw_reg_hpkt_ctrl_set(payload, MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT);
2696}
2697
2698
2699
2700
2701
2702#define MLXSW_REG_MFCR_ID 0x9001
2703#define MLXSW_REG_MFCR_LEN 0x08
2704
2705static const struct mlxsw_reg_info mlxsw_reg_mfcr = {
2706 .id = MLXSW_REG_MFCR_ID,
2707 .len = MLXSW_REG_MFCR_LEN,
2708};
2709
2710enum mlxsw_reg_mfcr_pwm_frequency {
2711 MLXSW_REG_MFCR_PWM_FEQ_11HZ = 0x00,
2712 MLXSW_REG_MFCR_PWM_FEQ_14_7HZ = 0x01,
2713 MLXSW_REG_MFCR_PWM_FEQ_22_1HZ = 0x02,
2714 MLXSW_REG_MFCR_PWM_FEQ_1_4KHZ = 0x40,
2715 MLXSW_REG_MFCR_PWM_FEQ_5KHZ = 0x41,
2716 MLXSW_REG_MFCR_PWM_FEQ_20KHZ = 0x42,
2717 MLXSW_REG_MFCR_PWM_FEQ_22_5KHZ = 0x43,
2718 MLXSW_REG_MFCR_PWM_FEQ_25KHZ = 0x44,
2719};
2720
2721
2722
2723
2724
2725MLXSW_ITEM32(reg, mfcr, pwm_frequency, 0x00, 0, 6);
2726
2727#define MLXSW_MFCR_TACHOS_MAX 10
2728
2729
2730
2731
2732
2733MLXSW_ITEM32(reg, mfcr, tacho_active, 0x04, 16, MLXSW_MFCR_TACHOS_MAX);
2734
2735#define MLXSW_MFCR_PWMS_MAX 5
2736
2737
2738
2739
2740
2741MLXSW_ITEM32(reg, mfcr, pwm_active, 0x04, 0, MLXSW_MFCR_PWMS_MAX);
2742
2743static inline void
2744mlxsw_reg_mfcr_pack(char *payload,
2745 enum mlxsw_reg_mfcr_pwm_frequency pwm_frequency)
2746{
2747 MLXSW_REG_ZERO(mfcr, payload);
2748 mlxsw_reg_mfcr_pwm_frequency_set(payload, pwm_frequency);
2749}
2750
2751static inline void
2752mlxsw_reg_mfcr_unpack(char *payload,
2753 enum mlxsw_reg_mfcr_pwm_frequency *p_pwm_frequency,
2754 u16 *p_tacho_active, u8 *p_pwm_active)
2755{
2756 *p_pwm_frequency = mlxsw_reg_mfcr_pwm_frequency_get(payload);
2757 *p_tacho_active = mlxsw_reg_mfcr_tacho_active_get(payload);
2758 *p_pwm_active = mlxsw_reg_mfcr_pwm_active_get(payload);
2759}
2760
2761
2762
2763
2764
2765#define MLXSW_REG_MFSC_ID 0x9002
2766#define MLXSW_REG_MFSC_LEN 0x08
2767
2768static const struct mlxsw_reg_info mlxsw_reg_mfsc = {
2769 .id = MLXSW_REG_MFSC_ID,
2770 .len = MLXSW_REG_MFSC_LEN,
2771};
2772
2773
2774
2775
2776
2777MLXSW_ITEM32(reg, mfsc, pwm, 0x00, 24, 3);
2778
2779
2780
2781
2782
2783
2784MLXSW_ITEM32(reg, mfsc, pwm_duty_cycle, 0x04, 0, 8);
2785
2786static inline void mlxsw_reg_mfsc_pack(char *payload, u8 pwm,
2787 u8 pwm_duty_cycle)
2788{
2789 MLXSW_REG_ZERO(mfsc, payload);
2790 mlxsw_reg_mfsc_pwm_set(payload, pwm);
2791 mlxsw_reg_mfsc_pwm_duty_cycle_set(payload, pwm_duty_cycle);
2792}
2793
2794
2795
2796
2797
2798
2799#define MLXSW_REG_MFSM_ID 0x9003
2800#define MLXSW_REG_MFSM_LEN 0x08
2801
2802static const struct mlxsw_reg_info mlxsw_reg_mfsm = {
2803 .id = MLXSW_REG_MFSM_ID,
2804 .len = MLXSW_REG_MFSM_LEN,
2805};
2806
2807
2808
2809
2810
2811MLXSW_ITEM32(reg, mfsm, tacho, 0x00, 24, 4);
2812
2813
2814
2815
2816
2817MLXSW_ITEM32(reg, mfsm, rpm, 0x04, 0, 16);
2818
2819static inline void mlxsw_reg_mfsm_pack(char *payload, u8 tacho)
2820{
2821 MLXSW_REG_ZERO(mfsm, payload);
2822 mlxsw_reg_mfsm_tacho_set(payload, tacho);
2823}
2824
2825
2826
2827
2828
2829
2830#define MLXSW_REG_MTCAP_ID 0x9009
2831#define MLXSW_REG_MTCAP_LEN 0x08
2832
2833static const struct mlxsw_reg_info mlxsw_reg_mtcap = {
2834 .id = MLXSW_REG_MTCAP_ID,
2835 .len = MLXSW_REG_MTCAP_LEN,
2836};
2837
2838
2839
2840
2841
2842
2843MLXSW_ITEM32(reg, mtcap, sensor_count, 0x00, 0, 7);
2844
2845
2846
2847
2848
2849
2850
2851#define MLXSW_REG_MTMP_ID 0x900A
2852#define MLXSW_REG_MTMP_LEN 0x20
2853
2854static const struct mlxsw_reg_info mlxsw_reg_mtmp = {
2855 .id = MLXSW_REG_MTMP_ID,
2856 .len = MLXSW_REG_MTMP_LEN,
2857};
2858
2859
2860
2861
2862
2863
2864
2865MLXSW_ITEM32(reg, mtmp, sensor_index, 0x00, 0, 7);
2866
2867
2868#define MLXSW_REG_MTMP_TEMP_TO_MC(val) (val * 125)
2869
2870
2871
2872
2873
2874
2875MLXSW_ITEM32(reg, mtmp, temperature, 0x04, 0, 16);
2876
2877
2878
2879
2880
2881MLXSW_ITEM32(reg, mtmp, mte, 0x08, 31, 1);
2882
2883
2884
2885
2886
2887MLXSW_ITEM32(reg, mtmp, mtr, 0x08, 30, 1);
2888
2889
2890
2891
2892
2893
2894MLXSW_ITEM32(reg, mtmp, max_temperature, 0x08, 0, 16);
2895
2896#define MLXSW_REG_MTMP_SENSOR_NAME_SIZE 8
2897
2898
2899
2900
2901
2902MLXSW_ITEM_BUF(reg, mtmp, sensor_name, 0x18, MLXSW_REG_MTMP_SENSOR_NAME_SIZE);
2903
2904static inline void mlxsw_reg_mtmp_pack(char *payload, u8 sensor_index,
2905 bool max_temp_enable,
2906 bool max_temp_reset)
2907{
2908 MLXSW_REG_ZERO(mtmp, payload);
2909 mlxsw_reg_mtmp_sensor_index_set(payload, sensor_index);
2910 mlxsw_reg_mtmp_mte_set(payload, max_temp_enable);
2911 mlxsw_reg_mtmp_mtr_set(payload, max_temp_reset);
2912}
2913
2914static inline void mlxsw_reg_mtmp_unpack(char *payload, unsigned int *p_temp,
2915 unsigned int *p_max_temp,
2916 char *sensor_name)
2917{
2918 u16 temp;
2919
2920 if (p_temp) {
2921 temp = mlxsw_reg_mtmp_temperature_get(payload);
2922 *p_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp);
2923 }
2924 if (p_max_temp) {
2925 temp = mlxsw_reg_mtmp_max_temperature_get(payload);
2926 *p_max_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp);
2927 }
2928 if (sensor_name)
2929 mlxsw_reg_mtmp_sensor_name_memcpy_from(payload, sensor_name);
2930}
2931
2932
2933
2934
2935
2936#define MLXSW_REG_MLCR_ID 0x902B
2937#define MLXSW_REG_MLCR_LEN 0x0C
2938
2939static const struct mlxsw_reg_info mlxsw_reg_mlcr = {
2940 .id = MLXSW_REG_MLCR_ID,
2941 .len = MLXSW_REG_MLCR_LEN,
2942};
2943
2944
2945
2946
2947
2948MLXSW_ITEM32(reg, mlcr, local_port, 0x00, 16, 8);
2949
2950#define MLXSW_REG_MLCR_DURATION_MAX 0xFFFF
2951
2952
2953
2954
2955
2956
2957
2958MLXSW_ITEM32(reg, mlcr, beacon_duration, 0x04, 0, 16);
2959
2960
2961
2962
2963
2964
2965MLXSW_ITEM32(reg, mlcr, beacon_remain, 0x08, 0, 16);
2966
2967static inline void mlxsw_reg_mlcr_pack(char *payload, u8 local_port,
2968 bool active)
2969{
2970 MLXSW_REG_ZERO(mlcr, payload);
2971 mlxsw_reg_mlcr_local_port_set(payload, local_port);
2972 mlxsw_reg_mlcr_beacon_duration_set(payload, active ?
2973 MLXSW_REG_MLCR_DURATION_MAX : 0);
2974}
2975
2976
2977
2978
2979
2980#define MLXSW_REG_SBPR_ID 0xB001
2981#define MLXSW_REG_SBPR_LEN 0x14
2982
2983static const struct mlxsw_reg_info mlxsw_reg_sbpr = {
2984 .id = MLXSW_REG_SBPR_ID,
2985 .len = MLXSW_REG_SBPR_LEN,
2986};
2987
2988enum mlxsw_reg_sbpr_dir {
2989 MLXSW_REG_SBPR_DIR_INGRESS,
2990 MLXSW_REG_SBPR_DIR_EGRESS,
2991};
2992
2993
2994
2995
2996
2997MLXSW_ITEM32(reg, sbpr, dir, 0x00, 24, 2);
2998
2999
3000
3001
3002
3003MLXSW_ITEM32(reg, sbpr, pool, 0x00, 0, 4);
3004
3005
3006
3007
3008
3009MLXSW_ITEM32(reg, sbpr, size, 0x04, 0, 24);
3010
3011enum mlxsw_reg_sbpr_mode {
3012 MLXSW_REG_SBPR_MODE_STATIC,
3013 MLXSW_REG_SBPR_MODE_DYNAMIC,
3014};
3015
3016
3017
3018
3019
3020MLXSW_ITEM32(reg, sbpr, mode, 0x08, 0, 4);
3021
3022static inline void mlxsw_reg_sbpr_pack(char *payload, u8 pool,
3023 enum mlxsw_reg_sbpr_dir dir,
3024 enum mlxsw_reg_sbpr_mode mode, u32 size)
3025{
3026 MLXSW_REG_ZERO(sbpr, payload);
3027 mlxsw_reg_sbpr_pool_set(payload, pool);
3028 mlxsw_reg_sbpr_dir_set(payload, dir);
3029 mlxsw_reg_sbpr_mode_set(payload, mode);
3030 mlxsw_reg_sbpr_size_set(payload, size);
3031}
3032
3033
3034
3035
3036
3037
3038
3039#define MLXSW_REG_SBCM_ID 0xB002
3040#define MLXSW_REG_SBCM_LEN 0x28
3041
3042static const struct mlxsw_reg_info mlxsw_reg_sbcm = {
3043 .id = MLXSW_REG_SBCM_ID,
3044 .len = MLXSW_REG_SBCM_LEN,
3045};
3046
3047
3048
3049
3050
3051
3052
3053MLXSW_ITEM32(reg, sbcm, local_port, 0x00, 16, 8);
3054
3055
3056
3057
3058
3059
3060
3061
3062
3063MLXSW_ITEM32(reg, sbcm, pg_buff, 0x00, 8, 6);
3064
3065enum mlxsw_reg_sbcm_dir {
3066 MLXSW_REG_SBCM_DIR_INGRESS,
3067 MLXSW_REG_SBCM_DIR_EGRESS,
3068};
3069
3070
3071
3072
3073
3074MLXSW_ITEM32(reg, sbcm, dir, 0x00, 0, 2);
3075
3076
3077
3078
3079
3080MLXSW_ITEM32(reg, sbcm, min_buff, 0x18, 0, 24);
3081
3082
3083
3084
3085
3086
3087
3088
3089
3090
3091
3092
3093MLXSW_ITEM32(reg, sbcm, max_buff, 0x1C, 0, 24);
3094
3095
3096
3097
3098
3099MLXSW_ITEM32(reg, sbcm, pool, 0x24, 0, 4);
3100
3101static inline void mlxsw_reg_sbcm_pack(char *payload, u8 local_port, u8 pg_buff,
3102 enum mlxsw_reg_sbcm_dir dir,
3103 u32 min_buff, u32 max_buff, u8 pool)
3104{
3105 MLXSW_REG_ZERO(sbcm, payload);
3106 mlxsw_reg_sbcm_local_port_set(payload, local_port);
3107 mlxsw_reg_sbcm_pg_buff_set(payload, pg_buff);
3108 mlxsw_reg_sbcm_dir_set(payload, dir);
3109 mlxsw_reg_sbcm_min_buff_set(payload, min_buff);
3110 mlxsw_reg_sbcm_max_buff_set(payload, max_buff);
3111 mlxsw_reg_sbcm_pool_set(payload, pool);
3112}
3113
3114
3115
3116
3117
3118
3119
3120#define MLXSW_REG_SBPM_ID 0xB003
3121#define MLXSW_REG_SBPM_LEN 0x28
3122
3123static const struct mlxsw_reg_info mlxsw_reg_sbpm = {
3124 .id = MLXSW_REG_SBPM_ID,
3125 .len = MLXSW_REG_SBPM_LEN,
3126};
3127
3128
3129
3130
3131
3132
3133
3134MLXSW_ITEM32(reg, sbpm, local_port, 0x00, 16, 8);
3135
3136
3137
3138
3139
3140MLXSW_ITEM32(reg, sbpm, pool, 0x00, 8, 4);
3141
3142enum mlxsw_reg_sbpm_dir {
3143 MLXSW_REG_SBPM_DIR_INGRESS,
3144 MLXSW_REG_SBPM_DIR_EGRESS,
3145};
3146
3147
3148
3149
3150
3151MLXSW_ITEM32(reg, sbpm, dir, 0x00, 0, 2);
3152
3153
3154
3155
3156
3157MLXSW_ITEM32(reg, sbpm, min_buff, 0x18, 0, 24);
3158
3159
3160
3161
3162
3163
3164
3165
3166
3167
3168
3169
3170MLXSW_ITEM32(reg, sbpm, max_buff, 0x1C, 0, 24);
3171
3172static inline void mlxsw_reg_sbpm_pack(char *payload, u8 local_port, u8 pool,
3173 enum mlxsw_reg_sbpm_dir dir,
3174 u32 min_buff, u32 max_buff)
3175{
3176 MLXSW_REG_ZERO(sbpm, payload);
3177 mlxsw_reg_sbpm_local_port_set(payload, local_port);
3178 mlxsw_reg_sbpm_pool_set(payload, pool);
3179 mlxsw_reg_sbpm_dir_set(payload, dir);
3180 mlxsw_reg_sbpm_min_buff_set(payload, min_buff);
3181 mlxsw_reg_sbpm_max_buff_set(payload, max_buff);
3182}
3183
3184
3185
3186
3187
3188
3189
3190#define MLXSW_REG_SBMM_ID 0xB004
3191#define MLXSW_REG_SBMM_LEN 0x28
3192
3193static const struct mlxsw_reg_info mlxsw_reg_sbmm = {
3194 .id = MLXSW_REG_SBMM_ID,
3195 .len = MLXSW_REG_SBMM_LEN,
3196};
3197
3198
3199
3200
3201
3202MLXSW_ITEM32(reg, sbmm, prio, 0x00, 8, 4);
3203
3204
3205
3206
3207
3208MLXSW_ITEM32(reg, sbmm, min_buff, 0x18, 0, 24);
3209
3210
3211
3212
3213
3214
3215
3216
3217
3218
3219
3220
3221MLXSW_ITEM32(reg, sbmm, max_buff, 0x1C, 0, 24);
3222
3223
3224
3225
3226
3227MLXSW_ITEM32(reg, sbmm, pool, 0x24, 0, 4);
3228
3229static inline void mlxsw_reg_sbmm_pack(char *payload, u8 prio, u32 min_buff,
3230 u32 max_buff, u8 pool)
3231{
3232 MLXSW_REG_ZERO(sbmm, payload);
3233 mlxsw_reg_sbmm_prio_set(payload, prio);
3234 mlxsw_reg_sbmm_min_buff_set(payload, min_buff);
3235 mlxsw_reg_sbmm_max_buff_set(payload, max_buff);
3236 mlxsw_reg_sbmm_pool_set(payload, pool);
3237}
3238
3239static inline const char *mlxsw_reg_id_str(u16 reg_id)
3240{
3241 switch (reg_id) {
3242 case MLXSW_REG_SGCR_ID:
3243 return "SGCR";
3244 case MLXSW_REG_SPAD_ID:
3245 return "SPAD";
3246 case MLXSW_REG_SMID_ID:
3247 return "SMID";
3248 case MLXSW_REG_SSPR_ID:
3249 return "SSPR";
3250 case MLXSW_REG_SFDAT_ID:
3251 return "SFDAT";
3252 case MLXSW_REG_SFD_ID:
3253 return "SFD";
3254 case MLXSW_REG_SFN_ID:
3255 return "SFN";
3256 case MLXSW_REG_SPMS_ID:
3257 return "SPMS";
3258 case MLXSW_REG_SPVID_ID:
3259 return "SPVID";
3260 case MLXSW_REG_SPVM_ID:
3261 return "SPVM";
3262 case MLXSW_REG_SPAFT_ID:
3263 return "SPAFT";
3264 case MLXSW_REG_SFGC_ID:
3265 return "SFGC";
3266 case MLXSW_REG_SFTR_ID:
3267 return "SFTR";
3268 case MLXSW_REG_SFDF_ID:
3269 return "SFDF";
3270 case MLXSW_REG_SLDR_ID:
3271 return "SLDR";
3272 case MLXSW_REG_SLCR_ID:
3273 return "SLCR";
3274 case MLXSW_REG_SLCOR_ID:
3275 return "SLCOR";
3276 case MLXSW_REG_SPMLR_ID:
3277 return "SPMLR";
3278 case MLXSW_REG_SVFA_ID:
3279 return "SVFA";
3280 case MLXSW_REG_SVPE_ID:
3281 return "SVPE";
3282 case MLXSW_REG_SFMR_ID:
3283 return "SFMR";
3284 case MLXSW_REG_SPVMLR_ID:
3285 return "SPVMLR";
3286 case MLXSW_REG_PMLP_ID:
3287 return "PMLP";
3288 case MLXSW_REG_PMTU_ID:
3289 return "PMTU";
3290 case MLXSW_REG_PTYS_ID:
3291 return "PTYS";
3292 case MLXSW_REG_PPAD_ID:
3293 return "PPAD";
3294 case MLXSW_REG_PAOS_ID:
3295 return "PAOS";
3296 case MLXSW_REG_PPCNT_ID:
3297 return "PPCNT";
3298 case MLXSW_REG_PBMC_ID:
3299 return "PBMC";
3300 case MLXSW_REG_PSPA_ID:
3301 return "PSPA";
3302 case MLXSW_REG_HTGT_ID:
3303 return "HTGT";
3304 case MLXSW_REG_HPKT_ID:
3305 return "HPKT";
3306 case MLXSW_REG_MFCR_ID:
3307 return "MFCR";
3308 case MLXSW_REG_MFSC_ID:
3309 return "MFSC";
3310 case MLXSW_REG_MFSM_ID:
3311 return "MFSM";
3312 case MLXSW_REG_MTCAP_ID:
3313 return "MTCAP";
3314 case MLXSW_REG_MTMP_ID:
3315 return "MTMP";
3316 case MLXSW_REG_MLCR_ID:
3317 return "MLCR";
3318 case MLXSW_REG_SBPR_ID:
3319 return "SBPR";
3320 case MLXSW_REG_SBCM_ID:
3321 return "SBCM";
3322 case MLXSW_REG_SBPM_ID:
3323 return "SBPM";
3324 case MLXSW_REG_SBMM_ID:
3325 return "SBMM";
3326 default:
3327 return "*UNKNOWN*";
3328 }
3329}
3330
3331
3332
3333
3334
3335#define MLXSW_REG_PUDE_LEN 0x10
3336
3337
3338
3339
3340
3341MLXSW_ITEM32(reg, pude, swid, 0x00, 24, 8);
3342
3343
3344
3345
3346
3347MLXSW_ITEM32(reg, pude, local_port, 0x00, 16, 8);
3348
3349
3350
3351
3352
3353
3354
3355
3356
3357
3358MLXSW_ITEM32(reg, pude, admin_status, 0x00, 8, 4);
3359
3360
3361
3362
3363
3364
3365
3366
3367
3368MLXSW_ITEM32(reg, pude, oper_status, 0x00, 0, 4);
3369
3370#endif
3371