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10#ifndef _SR9800_H
11#define _SR9800_H
12
13
14
15
16#define SR_CMD_SET_SW_MII 0x06
17
18#define SR_CMD_READ_MII_REG 0x07
19
20#define SR_CMD_WRITE_MII_REG 0x08
21
22#define SR_CMD_SET_HW_MII 0x0a
23
24#define SR_CMD_READ_EEPROM 0x0b
25
26#define SR_CMD_WRITE_EEPROM 0x0c
27
28#define SR_CMD_WRITE_ENABLE 0x0d
29
30#define SR_CMD_WRITE_DISABLE 0x0e
31
32#define SR_CMD_READ_RX_CTL 0x0f
33#define SR_RX_CTL_PRO (1 << 0)
34#define SR_RX_CTL_AMALL (1 << 1)
35#define SR_RX_CTL_SEP (1 << 2)
36#define SR_RX_CTL_AB (1 << 3)
37#define SR_RX_CTL_AM (1 << 4)
38#define SR_RX_CTL_AP (1 << 5)
39#define SR_RX_CTL_ARP (1 << 6)
40#define SR_RX_CTL_SO (1 << 7)
41#define SR_RX_CTL_RH1M (1 << 8)
42#define SR_RX_CTL_RH2M (1 << 9)
43#define SR_RX_CTL_RH3M (1 << 10)
44
45#define SR_CMD_WRITE_RX_CTL 0x10
46
47#define SR_CMD_READ_IPG012 0x11
48
49#define SR_CMD_WRITE_IPG012 0x12
50
51#define SR_CMD_READ_NODE_ID 0x13
52
53#define SR_CMD_WRITE_NODE_ID 0x14
54
55#define SR_CMD_READ_MULTI_FILTER 0x15
56
57#define SR_CMD_WRITE_MULTI_FILTER 0x16
58
59#define SR_CMD_READ_PHY_ID 0x19
60
61#define SR_CMD_READ_MEDIUM_STATUS 0x1a
62#define SR_MONITOR_LINK (1 << 1)
63#define SR_MONITOR_MAGIC (1 << 2)
64#define SR_MONITOR_HSFS (1 << 4)
65
66#define SR_CMD_WRITE_MEDIUM_MODE 0x1b
67#define SR_MEDIUM_GM (1 << 0)
68#define SR_MEDIUM_FD (1 << 1)
69#define SR_MEDIUM_AC (1 << 2)
70#define SR_MEDIUM_ENCK (1 << 3)
71#define SR_MEDIUM_RFC (1 << 4)
72#define SR_MEDIUM_TFC (1 << 5)
73#define SR_MEDIUM_JFE (1 << 6)
74#define SR_MEDIUM_PF (1 << 7)
75#define SR_MEDIUM_RE (1 << 8)
76#define SR_MEDIUM_PS (1 << 9)
77#define SR_MEDIUM_RSV (1 << 10)
78#define SR_MEDIUM_SBP (1 << 11)
79#define SR_MEDIUM_SM (1 << 12)
80
81#define SR_CMD_READ_MONITOR_MODE 0x1c
82
83#define SR_CMD_WRITE_MONITOR_MODE 0x1d
84
85#define SR_CMD_READ_GPIOS 0x1e
86#define SR_GPIO_GPO0EN (1 << 0)
87#define SR_GPIO_GPO_0 (1 << 1)
88#define SR_GPIO_GPO1EN (1 << 2)
89#define SR_GPIO_GPO_1 (1 << 3)
90#define SR_GPIO_GPO2EN (1 << 4)
91#define SR_GPIO_GPO_2 (1 << 5)
92#define SR_GPIO_RESERVED (1 << 6)
93#define SR_GPIO_RSE (1 << 7)
94
95#define SR_CMD_WRITE_GPIOS 0x1f
96
97#define SR_CMD_SW_RESET 0x20
98#define SR_SWRESET_CLEAR 0x00
99#define SR_SWRESET_RR (1 << 0)
100#define SR_SWRESET_RT (1 << 1)
101#define SR_SWRESET_PRTE (1 << 2)
102#define SR_SWRESET_PRL (1 << 3)
103#define SR_SWRESET_BZ (1 << 4)
104#define SR_SWRESET_IPRL (1 << 5)
105#define SR_SWRESET_IPPD (1 << 6)
106
107#define SR_CMD_SW_PHY_STATUS 0x21
108
109#define SR_CMD_SW_PHY_SELECT 0x22
110
111#define SR_CMD_BULKIN_SIZE 0x2A
112
113#define SR_CMD_LED_MUX 0x70
114#define SR_LED_MUX_TX_ACTIVE (1 << 0)
115#define SR_LED_MUX_RX_ACTIVE (1 << 1)
116#define SR_LED_MUX_COLLISION (1 << 2)
117#define SR_LED_MUX_DUP_COL (1 << 3)
118#define SR_LED_MUX_DUP (1 << 4)
119#define SR_LED_MUX_SPEED (1 << 5)
120#define SR_LED_MUX_LINK_ACTIVE (1 << 6)
121#define SR_LED_MUX_LINK (1 << 7)
122
123
124#define SR_REQ_RD_REG (USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE)
125#define SR_REQ_WR_REG (USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE)
126
127
128#define SR_MCAST_FILTER_SIZE 8
129#define SR_MAX_MCAST 64
130
131
132#define SR9800_IPG0_DEFAULT 0x15
133#define SR9800_IPG1_DEFAULT 0x0c
134#define SR9800_IPG2_DEFAULT 0x12
135
136
137#define SR9800_MEDIUM_DEFAULT \
138 (SR_MEDIUM_FD | SR_MEDIUM_RFC | \
139 SR_MEDIUM_TFC | SR_MEDIUM_PS | \
140 SR_MEDIUM_AC | SR_MEDIUM_RE)
141
142
143#define SR_DEFAULT_RX_CTL \
144 (SR_RX_CTL_SO | SR_RX_CTL_AB | SR_RX_CTL_RH1M)
145
146
147#define SR_EEPROM_MAGIC 0xdeadbeef
148#define SR9800_EEPROM_LEN 0xff
149
150
151#define DRIVER_VERSION "11-Nov-2013"
152#define DRIVER_NAME "CoreChips"
153#define DRIVER_FLAG \
154 (FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR | FLAG_MULTI_PACKET)
155
156
157#define SR9800_MAX_BULKIN_2K 0
158#define SR9800_MAX_BULKIN_4K 1
159#define SR9800_MAX_BULKIN_6K 2
160#define SR9800_MAX_BULKIN_8K 3
161#define SR9800_MAX_BULKIN_16K 4
162#define SR9800_MAX_BULKIN_20K 5
163#define SR9800_MAX_BULKIN_24K 6
164#define SR9800_MAX_BULKIN_32K 7
165
166struct {unsigned short size, byte_cnt, threshold; } SR9800_BULKIN_SIZE[] = {
167
168 {2048, 0x8000, 0x8001},
169
170 {4096, 0x8100, 0x8147},
171
172 {6144, 0x8200, 0x81EB},
173
174 {8192, 0x8300, 0x83D7},
175
176 {16384, 0x8400, 0x851E},
177
178 {20480, 0x8500, 0x8666},
179
180 {24576, 0x8600, 0x87AE},
181
182 {32768, 0x8700, 0x8A3D},
183};
184
185
186struct sr_data {
187 u8 multi_filter[SR_MCAST_FILTER_SIZE];
188 u8 mac_addr[ETH_ALEN];
189 u8 phymode;
190 u8 ledmode;
191 u8 eeprom_len;
192};
193
194struct sr9800_int_data {
195 __le16 res1;
196 u8 link;
197 __le16 res2;
198 u8 status;
199 __le16 res3;
200} __packed;
201
202#endif
203