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15#ifndef __MT76_REGS_H
16#define __MT76_REGS_H
17
18#include <linux/bitops.h>
19
20#ifndef GENMASK
21#define GENMASK(h, l) (((U32_C(1) << ((h) - (l) + 1)) - 1) << (l))
22#endif
23
24#define MT_ASIC_VERSION 0x0000
25
26#define MT76XX_REV_E3 0x22
27#define MT76XX_REV_E4 0x33
28
29#define MT_CMB_CTRL 0x0020
30#define MT_CMB_CTRL_XTAL_RDY BIT(22)
31#define MT_CMB_CTRL_PLL_LD BIT(23)
32
33#define MT_EFUSE_CTRL 0x0024
34#define MT_EFUSE_CTRL_AOUT GENMASK(5, 0)
35#define MT_EFUSE_CTRL_MODE GENMASK(7, 6)
36#define MT_EFUSE_CTRL_LDO_OFF_TIME GENMASK(13, 8)
37#define MT_EFUSE_CTRL_LDO_ON_TIME GENMASK(15, 14)
38#define MT_EFUSE_CTRL_AIN GENMASK(25, 16)
39#define MT_EFUSE_CTRL_KICK BIT(30)
40#define MT_EFUSE_CTRL_SEL BIT(31)
41
42#define MT_EFUSE_DATA_BASE 0x0028
43#define MT_EFUSE_DATA(_n) (MT_EFUSE_DATA_BASE + ((_n) << 2))
44
45#define MT_COEXCFG0 0x0040
46#define MT_COEXCFG0_COEX_EN BIT(0)
47
48#define MT_WLAN_FUN_CTRL 0x0080
49#define MT_WLAN_FUN_CTRL_WLAN_EN BIT(0)
50#define MT_WLAN_FUN_CTRL_WLAN_CLK_EN BIT(1)
51#define MT_WLAN_FUN_CTRL_WLAN_RESET_RF BIT(2)
52
53#define MT_WLAN_FUN_CTRL_WLAN_RESET BIT(3)
54#define MT_WLAN_FUN_CTRL_CSR_F20M_CKEN BIT(3)
55
56#define MT_WLAN_FUN_CTRL_PCIE_CLK_REQ BIT(4)
57#define MT_WLAN_FUN_CTRL_FRC_WL_ANT_SEL BIT(5)
58#define MT_WLAN_FUN_CTRL_INV_ANT_SEL BIT(6)
59#define MT_WLAN_FUN_CTRL_WAKE_HOST BIT(7)
60
61#define MT_WLAN_FUN_CTRL_THERM_RST BIT(8)
62#define MT_WLAN_FUN_CTRL_THERM_CKEN BIT(9)
63
64#define MT_WLAN_FUN_CTRL_GPIO_IN GENMASK(15, 8)
65#define MT_WLAN_FUN_CTRL_GPIO_OUT GENMASK(23, 16)
66#define MT_WLAN_FUN_CTRL_GPIO_OUT_EN GENMASK(31, 24)
67
68#define MT_XO_CTRL0 0x0100
69#define MT_XO_CTRL1 0x0104
70#define MT_XO_CTRL2 0x0108
71#define MT_XO_CTRL3 0x010c
72#define MT_XO_CTRL4 0x0110
73
74#define MT_XO_CTRL5 0x0114
75#define MT_XO_CTRL5_C2_VAL GENMASK(14, 8)
76
77#define MT_XO_CTRL6 0x0118
78#define MT_XO_CTRL6_C2_CTRL GENMASK(14, 8)
79
80#define MT_XO_CTRL7 0x011c
81
82#define MT_WLAN_MTC_CTRL 0x10148
83#define MT_WLAN_MTC_CTRL_MTCMOS_PWR_UP BIT(0)
84#define MT_WLAN_MTC_CTRL_PWR_ACK BIT(12)
85#define MT_WLAN_MTC_CTRL_PWR_ACK_S BIT(13)
86#define MT_WLAN_MTC_CTRL_BBP_MEM_PD GENMASK(19, 16)
87#define MT_WLAN_MTC_CTRL_PBF_MEM_PD BIT(20)
88#define MT_WLAN_MTC_CTRL_FCE_MEM_PD BIT(21)
89#define MT_WLAN_MTC_CTRL_TSO_MEM_PD BIT(22)
90#define MT_WLAN_MTC_CTRL_BBP_MEM_RB BIT(24)
91#define MT_WLAN_MTC_CTRL_PBF_MEM_RB BIT(25)
92#define MT_WLAN_MTC_CTRL_FCE_MEM_RB BIT(26)
93#define MT_WLAN_MTC_CTRL_TSO_MEM_RB BIT(27)
94#define MT_WLAN_MTC_CTRL_STATE_UP BIT(28)
95
96#define MT_INT_SOURCE_CSR 0x0200
97#define MT_INT_MASK_CSR 0x0204
98
99#define MT_INT_RX_DONE(_n) BIT(_n)
100#define MT_INT_RX_DONE_ALL GENMASK(1, 0)
101#define MT_INT_TX_DONE_ALL GENMASK(13, 4)
102#define MT_INT_TX_DONE(_n) BIT(_n + 4)
103#define MT_INT_RX_COHERENT BIT(16)
104#define MT_INT_TX_COHERENT BIT(17)
105#define MT_INT_ANY_COHERENT BIT(18)
106#define MT_INT_MCU_CMD BIT(19)
107#define MT_INT_TBTT BIT(20)
108#define MT_INT_PRE_TBTT BIT(21)
109#define MT_INT_TX_STAT BIT(22)
110#define MT_INT_AUTO_WAKEUP BIT(23)
111#define MT_INT_GPTIMER BIT(24)
112#define MT_INT_RXDELAYINT BIT(26)
113#define MT_INT_TXDELAYINT BIT(27)
114
115#define MT_WPDMA_GLO_CFG 0x0208
116#define MT_WPDMA_GLO_CFG_TX_DMA_EN BIT(0)
117#define MT_WPDMA_GLO_CFG_TX_DMA_BUSY BIT(1)
118#define MT_WPDMA_GLO_CFG_RX_DMA_EN BIT(2)
119#define MT_WPDMA_GLO_CFG_RX_DMA_BUSY BIT(3)
120#define MT_WPDMA_GLO_CFG_DMA_BURST_SIZE GENMASK(5, 4)
121#define MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE BIT(6)
122#define MT_WPDMA_GLO_CFG_BIG_ENDIAN BIT(7)
123#define MT_WPDMA_GLO_CFG_HDR_SEG_LEN GENMASK(15, 8)
124#define MT_WPDMA_GLO_CFG_CLK_GATE_DIS BIT(30)
125#define MT_WPDMA_GLO_CFG_RX_2B_OFFSET BIT(31)
126
127#define MT_WPDMA_RST_IDX 0x020c
128
129#define MT_WPDMA_DELAY_INT_CFG 0x0210
130
131#define MT_WMM_AIFSN 0x0214
132#define MT_WMM_AIFSN_MASK GENMASK(3, 0)
133#define MT_WMM_AIFSN_SHIFT(_n) ((_n) * 4)
134
135#define MT_WMM_CWMIN 0x0218
136#define MT_WMM_CWMIN_MASK GENMASK(3, 0)
137#define MT_WMM_CWMIN_SHIFT(_n) ((_n) * 4)
138
139#define MT_WMM_CWMAX 0x021c
140#define MT_WMM_CWMAX_MASK GENMASK(3, 0)
141#define MT_WMM_CWMAX_SHIFT(_n) ((_n) * 4)
142
143#define MT_WMM_TXOP_BASE 0x0220
144#define MT_WMM_TXOP(_n) (MT_WMM_TXOP_BASE + (((_n) / 2) << 2))
145#define MT_WMM_TXOP_SHIFT(_n) ((_n & 1) * 16)
146#define MT_WMM_TXOP_MASK GENMASK(15, 0)
147
148#define MT_FCE_DMA_ADDR 0x0230
149#define MT_FCE_DMA_LEN 0x0234
150
151#define MT_USB_DMA_CFG 0x238
152#define MT_USB_DMA_CFG_RX_BULK_AGG_TOUT GENMASK(7, 0)
153#define MT_USB_DMA_CFG_RX_BULK_AGG_LMT GENMASK(15, 8)
154#define MT_USB_DMA_CFG_PHY_CLR BIT(16)
155#define MT_USB_DMA_CFG_TX_CLR BIT(19)
156#define MT_USB_DMA_CFG_TXOP_HALT BIT(20)
157#define MT_USB_DMA_CFG_RX_BULK_AGG_EN BIT(21)
158#define MT_USB_DMA_CFG_RX_BULK_EN BIT(22)
159#define MT_USB_DMA_CFG_TX_BULK_EN BIT(23)
160#define MT_USB_DMA_CFG_UDMA_RX_WL_DROP BIT(25)
161#define MT_USB_DMA_CFG_EP_OUT_VALID GENMASK(29, 27)
162#define MT_USB_DMA_CFG_RX_BUSY BIT(30)
163#define MT_USB_DMA_CFG_TX_BUSY BIT(31)
164
165#define MT_TSO_CTRL 0x0250
166#define MT_HEADER_TRANS_CTRL_REG 0x0260
167
168#define MT_US_CYC_CFG 0x02a4
169#define MT_US_CYC_CNT GENMASK(7, 0)
170
171#define MT_TX_RING_BASE 0x0300
172#define MT_RX_RING_BASE 0x03c0
173#define MT_RING_SIZE 0x10
174
175#define MT_TX_HW_QUEUE_MCU 8
176#define MT_TX_HW_QUEUE_MGMT 9
177
178#define MT_PBF_SYS_CTRL 0x0400
179#define MT_PBF_SYS_CTRL_MCU_RESET BIT(0)
180#define MT_PBF_SYS_CTRL_DMA_RESET BIT(1)
181#define MT_PBF_SYS_CTRL_MAC_RESET BIT(2)
182#define MT_PBF_SYS_CTRL_PBF_RESET BIT(3)
183#define MT_PBF_SYS_CTRL_ASY_RESET BIT(4)
184
185#define MT_PBF_CFG 0x0404
186#define MT_PBF_CFG_TX0Q_EN BIT(0)
187#define MT_PBF_CFG_TX1Q_EN BIT(1)
188#define MT_PBF_CFG_TX2Q_EN BIT(2)
189#define MT_PBF_CFG_TX3Q_EN BIT(3)
190#define MT_PBF_CFG_RX0Q_EN BIT(4)
191#define MT_PBF_CFG_RX_DROP_EN BIT(8)
192
193#define MT_PBF_TX_MAX_PCNT 0x0408
194#define MT_PBF_RX_MAX_PCNT 0x040c
195
196#define MT_BCN_OFFSET_BASE 0x041c
197#define MT_BCN_OFFSET(_n) (MT_BCN_OFFSET_BASE + ((_n) << 2))
198
199#define MT_RF_CSR_CFG 0x0500
200#define MT_RF_CSR_CFG_DATA GENMASK(7, 0)
201#define MT_RF_CSR_CFG_REG_ID GENMASK(13, 8)
202#define MT_RF_CSR_CFG_REG_BANK GENMASK(17, 14)
203#define MT_RF_CSR_CFG_WR BIT(30)
204#define MT_RF_CSR_CFG_KICK BIT(31)
205
206#define MT_RF_BYPASS_0 0x0504
207#define MT_RF_BYPASS_1 0x0508
208#define MT_RF_SETTING_0 0x050c
209
210#define MT_RF_DATA_WRITE 0x0524
211
212#define MT_RF_CTRL 0x0528
213#define MT_RF_CTRL_ADDR GENMASK(11, 0)
214#define MT_RF_CTRL_WRITE BIT(12)
215#define MT_RF_CTRL_BUSY BIT(13)
216#define MT_RF_CTRL_IDX BIT(16)
217
218#define MT_RF_DATA_READ 0x052c
219
220#define MT_FCE_PSE_CTRL 0x0800
221#define MT_FCE_PARAMETERS 0x0804
222#define MT_FCE_CSO 0x0808
223
224#define MT_FCE_L2_STUFF 0x080c
225#define MT_FCE_L2_STUFF_HT_L2_EN BIT(0)
226#define MT_FCE_L2_STUFF_QOS_L2_EN BIT(1)
227#define MT_FCE_L2_STUFF_RX_STUFF_EN BIT(2)
228#define MT_FCE_L2_STUFF_TX_STUFF_EN BIT(3)
229#define MT_FCE_L2_STUFF_WR_MPDU_LEN_EN BIT(4)
230#define MT_FCE_L2_STUFF_MVINV_BSWAP BIT(5)
231#define MT_FCE_L2_STUFF_TS_CMD_QSEL_EN GENMASK(15, 8)
232#define MT_FCE_L2_STUFF_TS_LEN_EN GENMASK(23, 16)
233#define MT_FCE_L2_STUFF_OTHER_PORT GENMASK(25, 24)
234
235#define MT_FCE_WLAN_FLOW_CONTROL1 0x0824
236
237#define MT_TX_CPU_FROM_FCE_BASE_PTR 0x09a0
238#define MT_TX_CPU_FROM_FCE_MAX_COUNT 0x09a4
239#define MT_TX_CPU_FROM_FCE_CPU_DESC_IDX 0x09a8
240
241#define MT_FCE_PDMA_GLOBAL_CONF 0x09c4
242
243#define MT_PAUSE_ENABLE_CONTROL1 0x0a38
244
245#define MT_FCE_SKIP_FS 0x0a6c
246
247#define MT_MAC_CSR0 0x1000
248
249#define MT_MAC_SYS_CTRL 0x1004
250#define MT_MAC_SYS_CTRL_RESET_CSR BIT(0)
251#define MT_MAC_SYS_CTRL_RESET_BBP BIT(1)
252#define MT_MAC_SYS_CTRL_ENABLE_TX BIT(2)
253#define MT_MAC_SYS_CTRL_ENABLE_RX BIT(3)
254
255#define MT_MAC_ADDR_DW0 0x1008
256#define MT_MAC_ADDR_DW1 0x100c
257#define MT_MAC_ADDR_DW1_U2ME_MASK GENMASK(23, 16)
258
259#define MT_MAC_BSSID_DW0 0x1010
260#define MT_MAC_BSSID_DW1 0x1014
261#define MT_MAC_BSSID_DW1_ADDR GENMASK(15, 0)
262#define MT_MAC_BSSID_DW1_MBSS_MODE GENMASK(17, 16)
263#define MT_MAC_BSSID_DW1_MBEACON_N GENMASK(20, 18)
264#define MT_MAC_BSSID_DW1_MBSS_LOCAL_BIT BIT(21)
265#define MT_MAC_BSSID_DW1_MBSS_MODE_B2 BIT(22)
266#define MT_MAC_BSSID_DW1_MBEACON_N_B3 BIT(23)
267#define MT_MAC_BSSID_DW1_MBSS_IDX_BYTE GENMASK(26, 24)
268
269#define MT_MAX_LEN_CFG 0x1018
270#define MT_MAX_LEN_CFG_AMPDU GENMASK(13, 12)
271
272#define MT_BBP_CSR_CFG 0x101c
273#define MT_BBP_CSR_CFG_VAL GENMASK(7, 0)
274#define MT_BBP_CSR_CFG_REG_NUM GENMASK(15, 8)
275#define MT_BBP_CSR_CFG_READ BIT(16)
276#define MT_BBP_CSR_CFG_BUSY BIT(17)
277#define MT_BBP_CSR_CFG_PAR_DUR BIT(18)
278#define MT_BBP_CSR_CFG_RW_MODE BIT(19)
279
280#define MT_AMPDU_MAX_LEN_20M1S 0x1030
281#define MT_AMPDU_MAX_LEN_20M2S 0x1034
282#define MT_AMPDU_MAX_LEN_40M1S 0x1038
283#define MT_AMPDU_MAX_LEN_40M2S 0x103c
284#define MT_AMPDU_MAX_LEN 0x1040
285
286#define MT_WCID_DROP_BASE 0x106c
287#define MT_WCID_DROP(_n) (MT_WCID_DROP_BASE + ((_n) >> 5) * 4)
288#define MT_WCID_DROP_MASK(_n) BIT((_n) % 32)
289
290#define MT_BCN_BYPASS_MASK 0x108c
291
292#define MT_MAC_APC_BSSID_BASE 0x1090
293#define MT_MAC_APC_BSSID_L(_n) (MT_MAC_APC_BSSID_BASE + ((_n) * 8))
294#define MT_MAC_APC_BSSID_H(_n) (MT_MAC_APC_BSSID_BASE + ((_n) * 8 + 4))
295#define MT_MAC_APC_BSSID_H_ADDR GENMASK(15, 0)
296#define MT_MAC_APC_BSSID0_H_EN BIT(16)
297
298#define MT_XIFS_TIME_CFG 0x1100
299#define MT_XIFS_TIME_CFG_CCK_SIFS GENMASK(7, 0)
300#define MT_XIFS_TIME_CFG_OFDM_SIFS GENMASK(15, 8)
301#define MT_XIFS_TIME_CFG_OFDM_XIFS GENMASK(19, 16)
302#define MT_XIFS_TIME_CFG_EIFS GENMASK(28, 20)
303#define MT_XIFS_TIME_CFG_BB_RXEND_EN BIT(29)
304
305#define MT_BKOFF_SLOT_CFG 0x1104
306#define MT_BKOFF_SLOT_CFG_SLOTTIME GENMASK(7, 0)
307#define MT_BKOFF_SLOT_CFG_CC_DELAY GENMASK(11, 8)
308
309#define MT_BEACON_TIME_CFG 0x1114
310#define MT_BEACON_TIME_CFG_INTVAL GENMASK(15, 0)
311#define MT_BEACON_TIME_CFG_TIMER_EN BIT(16)
312#define MT_BEACON_TIME_CFG_SYNC_MODE GENMASK(18, 17)
313#define MT_BEACON_TIME_CFG_TBTT_EN BIT(19)
314#define MT_BEACON_TIME_CFG_BEACON_TX BIT(20)
315#define MT_BEACON_TIME_CFG_TSF_COMP GENMASK(31, 24)
316
317#define MT_TBTT_SYNC_CFG 0x1118
318#define MT_TBTT_TIMER_CFG 0x1124
319
320#define MT_INT_TIMER_CFG 0x1128
321#define MT_INT_TIMER_CFG_PRE_TBTT GENMASK(15, 0)
322#define MT_INT_TIMER_CFG_GP_TIMER GENMASK(31, 16)
323
324#define MT_INT_TIMER_EN 0x112c
325#define MT_INT_TIMER_EN_PRE_TBTT_EN BIT(0)
326#define MT_INT_TIMER_EN_GP_TIMER_EN BIT(1)
327
328#define MT_MAC_STATUS 0x1200
329#define MT_MAC_STATUS_TX BIT(0)
330#define MT_MAC_STATUS_RX BIT(1)
331
332#define MT_PWR_PIN_CFG 0x1204
333#define MT_AUX_CLK_CFG 0x120c
334
335#define MT_BB_PA_MODE_CFG0 0x1214
336#define MT_BB_PA_MODE_CFG1 0x1218
337#define MT_RF_PA_MODE_CFG0 0x121c
338#define MT_RF_PA_MODE_CFG1 0x1220
339
340#define MT_RF_PA_MODE_ADJ0 0x1228
341#define MT_RF_PA_MODE_ADJ1 0x122c
342
343#define MT_DACCLK_EN_DLY_CFG 0x1264
344
345#define MT_EDCA_CFG_BASE 0x1300
346#define MT_EDCA_CFG_AC(_n) (MT_EDCA_CFG_BASE + ((_n) << 2))
347#define MT_EDCA_CFG_TXOP GENMASK(7, 0)
348#define MT_EDCA_CFG_AIFSN GENMASK(11, 8)
349#define MT_EDCA_CFG_CWMIN GENMASK(15, 12)
350#define MT_EDCA_CFG_CWMAX GENMASK(19, 16)
351
352#define MT_TX_PWR_CFG_0 0x1314
353#define MT_TX_PWR_CFG_1 0x1318
354#define MT_TX_PWR_CFG_2 0x131c
355#define MT_TX_PWR_CFG_3 0x1320
356#define MT_TX_PWR_CFG_4 0x1324
357
358#define MT_TX_BAND_CFG 0x132c
359#define MT_TX_BAND_CFG_UPPER_40M BIT(0)
360#define MT_TX_BAND_CFG_5G BIT(1)
361#define MT_TX_BAND_CFG_2G BIT(2)
362
363#define MT_HT_FBK_TO_LEGACY 0x1384
364#define MT_TX_MPDU_ADJ_INT 0x1388
365
366#define MT_TX_PWR_CFG_7 0x13d4
367#define MT_TX_PWR_CFG_8 0x13d8
368#define MT_TX_PWR_CFG_9 0x13dc
369
370#define MT_TX_SW_CFG0 0x1330
371#define MT_TX_SW_CFG1 0x1334
372#define MT_TX_SW_CFG2 0x1338
373
374#define MT_TXOP_CTRL_CFG 0x1340
375#define MT_TXOP_TRUN_EN GENMASK(5, 0)
376#define MT_TXOP_EXT_CCA_DLY GENMASK(15, 8)
377#define MT_TXOP_CTRL
378
379#define MT_TX_RTS_CFG 0x1344
380#define MT_TX_RTS_CFG_RETRY_LIMIT GENMASK(7, 0)
381#define MT_TX_RTS_CFG_THRESH GENMASK(23, 8)
382#define MT_TX_RTS_FALLBACK BIT(24)
383
384#define MT_TX_TIMEOUT_CFG 0x1348
385#define MT_TX_RETRY_CFG 0x134c
386#define MT_TX_LINK_CFG 0x1350
387#define MT_HT_FBK_CFG0 0x1354
388#define MT_HT_FBK_CFG1 0x1358
389#define MT_LG_FBK_CFG0 0x135c
390#define MT_LG_FBK_CFG1 0x1360
391
392#define MT_CCK_PROT_CFG 0x1364
393#define MT_OFDM_PROT_CFG 0x1368
394#define MT_MM20_PROT_CFG 0x136c
395#define MT_MM40_PROT_CFG 0x1370
396#define MT_GF20_PROT_CFG 0x1374
397#define MT_GF40_PROT_CFG 0x1378
398
399#define MT_PROT_RATE GENMASK(15, 0)
400#define MT_PROT_CTRL_RTS_CTS BIT(16)
401#define MT_PROT_CTRL_CTS2SELF BIT(17)
402#define MT_PROT_NAV_SHORT BIT(18)
403#define MT_PROT_NAV_LONG BIT(19)
404#define MT_PROT_TXOP_ALLOW_CCK BIT(20)
405#define MT_PROT_TXOP_ALLOW_OFDM BIT(21)
406#define MT_PROT_TXOP_ALLOW_MM20 BIT(22)
407#define MT_PROT_TXOP_ALLOW_MM40 BIT(23)
408#define MT_PROT_TXOP_ALLOW_GF20 BIT(24)
409#define MT_PROT_TXOP_ALLOW_GF40 BIT(25)
410#define MT_PROT_RTS_THR_EN BIT(26)
411#define MT_PROT_RATE_CCK_11 0x0003
412#define MT_PROT_RATE_OFDM_6 0x4000
413#define MT_PROT_RATE_OFDM_24 0x4004
414#define MT_PROT_RATE_DUP_OFDM_24 0x4084
415#define MT_PROT_TXOP_ALLOW_ALL GENMASK(25, 20)
416#define MT_PROT_TXOP_ALLOW_BW20 (MT_PROT_TXOP_ALLOW_ALL & \
417 ~MT_PROT_TXOP_ALLOW_MM40 & \
418 ~MT_PROT_TXOP_ALLOW_GF40)
419
420#define MT_EXP_ACK_TIME 0x1380
421
422#define MT_TX_PWR_CFG_0_EXT 0x1390
423#define MT_TX_PWR_CFG_1_EXT 0x1394
424
425#define MT_TX_FBK_LIMIT 0x1398
426#define MT_TX_FBK_LIMIT_MPDU_FBK GENMASK(7, 0)
427#define MT_TX_FBK_LIMIT_AMPDU_FBK GENMASK(15, 8)
428#define MT_TX_FBK_LIMIT_MPDU_UP_CLEAR BIT(16)
429#define MT_TX_FBK_LIMIT_AMPDU_UP_CLEAR BIT(17)
430#define MT_TX_FBK_LIMIT_RATE_LUT BIT(18)
431
432#define MT_TX0_RF_GAIN_CORR 0x13a0
433#define MT_TX1_RF_GAIN_CORR 0x13a4
434#define MT_TX0_RF_GAIN_ATTEN 0x13a8
435
436#define MT_TX_ALC_CFG_0 0x13b0
437#define MT_TX_ALC_CFG_0_CH_INIT_0 GENMASK(5, 0)
438#define MT_TX_ALC_CFG_0_CH_INIT_1 GENMASK(13, 8)
439#define MT_TX_ALC_CFG_0_LIMIT_0 GENMASK(21, 16)
440#define MT_TX_ALC_CFG_0_LIMIT_1 GENMASK(29, 24)
441
442#define MT_TX_ALC_CFG_1 0x13b4
443#define MT_TX_ALC_CFG_1_TEMP_COMP GENMASK(5, 0)
444
445#define MT_TX_ALC_CFG_2 0x13a8
446#define MT_TX_ALC_CFG_2_TEMP_COMP GENMASK(5, 0)
447
448#define MT_TX0_BB_GAIN_ATTEN 0x13c0
449
450#define MT_TX_ALC_VGA3 0x13c8
451
452#define MT_TX_PROT_CFG6 0x13e0
453#define MT_TX_PROT_CFG7 0x13e4
454#define MT_TX_PROT_CFG8 0x13e8
455
456#define MT_PIFS_TX_CFG 0x13ec
457
458#define MT_RX_FILTR_CFG 0x1400
459
460#define MT_RX_FILTR_CFG_CRC_ERR BIT(0)
461#define MT_RX_FILTR_CFG_PHY_ERR BIT(1)
462#define MT_RX_FILTR_CFG_PROMISC BIT(2)
463#define MT_RX_FILTR_CFG_OTHER_BSS BIT(3)
464#define MT_RX_FILTR_CFG_VER_ERR BIT(4)
465#define MT_RX_FILTR_CFG_MCAST BIT(5)
466#define MT_RX_FILTR_CFG_BCAST BIT(6)
467#define MT_RX_FILTR_CFG_DUP BIT(7)
468#define MT_RX_FILTR_CFG_CFACK BIT(8)
469#define MT_RX_FILTR_CFG_CFEND BIT(9)
470#define MT_RX_FILTR_CFG_ACK BIT(10)
471#define MT_RX_FILTR_CFG_CTS BIT(11)
472#define MT_RX_FILTR_CFG_RTS BIT(12)
473#define MT_RX_FILTR_CFG_PSPOLL BIT(13)
474#define MT_RX_FILTR_CFG_BA BIT(14)
475#define MT_RX_FILTR_CFG_BAR BIT(15)
476#define MT_RX_FILTR_CFG_CTRL_RSV BIT(16)
477
478#define MT_AUTO_RSP_CFG 0x1404
479
480#define MT_AUTO_RSP_PREAMB_SHORT BIT(4)
481
482#define MT_LEGACY_BASIC_RATE 0x1408
483#define MT_HT_BASIC_RATE 0x140c
484
485#define MT_RX_PARSER_CFG 0x1418
486#define MT_RX_PARSER_RX_SET_NAV_ALL BIT(0)
487
488#define MT_EXT_CCA_CFG 0x141c
489#define MT_EXT_CCA_CFG_CCA0 GENMASK(1, 0)
490#define MT_EXT_CCA_CFG_CCA1 GENMASK(3, 2)
491#define MT_EXT_CCA_CFG_CCA2 GENMASK(5, 4)
492#define MT_EXT_CCA_CFG_CCA3 GENMASK(7, 6)
493#define MT_EXT_CCA_CFG_CCA_MASK GENMASK(11, 8)
494#define MT_EXT_CCA_CFG_ED_CCA_MASK GENMASK(15, 12)
495
496#define MT_TX_SW_CFG3 0x1478
497
498#define MT_PN_PAD_MODE 0x150c
499
500#define MT_TXOP_HLDR_ET 0x1608
501
502#define MT_PROT_AUTO_TX_CFG 0x1648
503
504#define MT_RX_STA_CNT0 0x1700
505#define MT_RX_STA_CNT1 0x1704
506#define MT_RX_STA_CNT2 0x1708
507#define MT_TX_STA_CNT0 0x170c
508#define MT_TX_STA_CNT1 0x1710
509#define MT_TX_STA_CNT2 0x1714
510
511
512
513
514
515
516
517
518
519#define MT_TX_STAT_FIFO 0x1718
520#define MT_TX_STAT_FIFO_VALID BIT(0)
521#define MT_TX_STAT_FIFO_PID_TYPE GENMASK(4, 1)
522#define MT_TX_STAT_FIFO_SUCCESS BIT(5)
523#define MT_TX_STAT_FIFO_AGGR BIT(6)
524#define MT_TX_STAT_FIFO_ACKREQ BIT(7)
525#define MT_TX_STAT_FIFO_WCID GENMASK(15, 8)
526#define MT_TX_STAT_FIFO_RATE GENMASK(31, 16)
527
528#define MT_TX_AGG_STAT 0x171c
529
530#define MT_TX_AGG_CNT_BASE0 0x1720
531
532#define MT_MPDU_DENSITY_CNT 0x1740
533
534#define MT_TX_AGG_CNT_BASE1 0x174c
535
536#define MT_TX_AGG_CNT(_id) ((_id) < 8 ? \
537 MT_TX_AGG_CNT_BASE0 + ((_id) << 2) : \
538 MT_TX_AGG_CNT_BASE1 + ((_id - 8) << 2))
539
540#define MT_TX_STAT_FIFO_EXT 0x1798
541#define MT_TX_STAT_FIFO_EXT_RETRY GENMASK(7, 0)
542
543#define MT_BBP_CORE_BASE 0x2000
544#define MT_BBP_IBI_BASE 0x2100
545#define MT_BBP_AGC_BASE 0x2300
546#define MT_BBP_TXC_BASE 0x2400
547#define MT_BBP_RXC_BASE 0x2500
548#define MT_BBP_TXO_BASE 0x2600
549#define MT_BBP_TXBE_BASE 0x2700
550#define MT_BBP_RXFE_BASE 0x2800
551#define MT_BBP_RXO_BASE 0x2900
552#define MT_BBP_DFS_BASE 0x2a00
553#define MT_BBP_TR_BASE 0x2b00
554#define MT_BBP_CAL_BASE 0x2c00
555#define MT_BBP_DSC_BASE 0x2e00
556#define MT_BBP_PFMU_BASE 0x2f00
557
558#define MT_BBP(_type, _n) (MT_BBP_##_type##_BASE + ((_n) << 2))
559
560#define MT_BBP_CORE_R1_BW GENMASK(4, 3)
561
562#define MT_BBP_AGC_R0_CTRL_CHAN GENMASK(9, 8)
563#define MT_BBP_AGC_R0_BW GENMASK(14, 12)
564
565
566#define MT_BBP_AGC_LNA_GAIN GENMASK(21, 16)
567
568
569#define MT_BBP_AGC_GAIN GENMASK(14, 8)
570
571#define MT_BBP_AGC20_RSSI0 GENMASK(7, 0)
572#define MT_BBP_AGC20_RSSI1 GENMASK(15, 8)
573
574#define MT_BBP_TXBE_R0_CTRL_CHAN GENMASK(1, 0)
575
576#define MT_WCID_ADDR_BASE 0x1800
577#define MT_WCID_ADDR(_n) (MT_WCID_ADDR_BASE + (_n) * 8)
578
579#define MT_SRAM_BASE 0x4000
580
581#define MT_WCID_KEY_BASE 0x8000
582#define MT_WCID_KEY(_n) (MT_WCID_KEY_BASE + (_n) * 32)
583
584#define MT_WCID_IV_BASE 0xa000
585#define MT_WCID_IV(_n) (MT_WCID_IV_BASE + (_n) * 8)
586
587#define MT_WCID_ATTR_BASE 0xa800
588#define MT_WCID_ATTR(_n) (MT_WCID_ATTR_BASE + (_n) * 4)
589
590#define MT_WCID_ATTR_PAIRWISE BIT(0)
591#define MT_WCID_ATTR_PKEY_MODE GENMASK(3, 1)
592#define MT_WCID_ATTR_BSS_IDX GENMASK(6, 4)
593#define MT_WCID_ATTR_RXWI_UDF GENMASK(9, 7)
594#define MT_WCID_ATTR_PKEY_MODE_EXT BIT(10)
595#define MT_WCID_ATTR_BSS_IDX_EXT BIT(11)
596#define MT_WCID_ATTR_WAPI_MCBC BIT(15)
597#define MT_WCID_ATTR_WAPI_KEYID GENMASK(31, 24)
598
599#define MT_SKEY_BASE_0 0xac00
600#define MT_SKEY_BASE_1 0xb400
601#define MT_SKEY_0(_bss, _idx) \
602 (MT_SKEY_BASE_0 + (4 * (_bss) + _idx) * 32)
603#define MT_SKEY_1(_bss, _idx) \
604 (MT_SKEY_BASE_1 + (4 * ((_bss) & 7) + _idx) * 32)
605#define MT_SKEY(_bss, _idx) \
606 ((_bss & 8) ? MT_SKEY_1(_bss, _idx) : MT_SKEY_0(_bss, _idx))
607
608#define MT_SKEY_MODE_BASE_0 0xb000
609#define MT_SKEY_MODE_BASE_1 0xb3f0
610#define MT_SKEY_MODE_0(_bss) \
611 (MT_SKEY_MODE_BASE_0 + ((_bss / 2) << 2))
612#define MT_SKEY_MODE_1(_bss) \
613 (MT_SKEY_MODE_BASE_1 + ((((_bss) & 7) / 2) << 2))
614#define MT_SKEY_MODE(_bss) \
615 ((_bss & 8) ? MT_SKEY_MODE_1(_bss) : MT_SKEY_MODE_0(_bss))
616#define MT_SKEY_MODE_MASK GENMASK(3, 0)
617#define MT_SKEY_MODE_SHIFT(_bss, _idx) (4 * ((_idx) + 4 * (_bss & 1)))
618
619#define MT_BEACON_BASE 0xc000
620
621#define MT_TEMP_SENSOR 0x1d000
622#define MT_TEMP_SENSOR_VAL GENMASK(6, 0)
623
624enum mt76_cipher_type {
625 MT_CIPHER_NONE,
626 MT_CIPHER_WEP40,
627 MT_CIPHER_WEP104,
628 MT_CIPHER_TKIP,
629 MT_CIPHER_AES_CCMP,
630 MT_CIPHER_CKIP40,
631 MT_CIPHER_CKIP104,
632 MT_CIPHER_CKIP128,
633 MT_CIPHER_WAPI,
634};
635
636#endif
637