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18#include <linux/firmware.h>
19#include "rsi_sdio.h"
20#include "rsi_common.h"
21
22
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25
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27
28
29
30static int rsi_sdio_master_access_msword(struct rsi_hw *adapter,
31 u16 ms_word)
32{
33 u8 byte;
34 u8 function = 0;
35 int status = 0;
36
37 byte = (u8)(ms_word & 0x00FF);
38
39 rsi_dbg(INIT_ZONE,
40 "%s: MASTER_ACCESS_MSBYTE:0x%x\n", __func__, byte);
41
42 status = rsi_sdio_write_register(adapter,
43 function,
44 SDIO_MASTER_ACCESS_MSBYTE,
45 &byte);
46 if (status) {
47 rsi_dbg(ERR_ZONE,
48 "%s: fail to access MASTER_ACCESS_MSBYTE\n",
49 __func__);
50 return -1;
51 }
52
53 byte = (u8)(ms_word >> 8);
54
55 rsi_dbg(INIT_ZONE, "%s:MASTER_ACCESS_LSBYTE:0x%x\n", __func__, byte);
56 status = rsi_sdio_write_register(adapter,
57 function,
58 SDIO_MASTER_ACCESS_LSBYTE,
59 &byte);
60 return status;
61}
62
63
64
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71
72
73
74
75static int rsi_copy_to_card(struct rsi_common *common,
76 const u8 *fw,
77 u32 len,
78 u32 num_blocks)
79{
80 struct rsi_hw *adapter = common->priv;
81 struct rsi_91x_sdiodev *dev =
82 (struct rsi_91x_sdiodev *)adapter->rsi_dev;
83 u32 indx, ii;
84 u32 block_size = dev->tx_blk_size;
85 u32 lsb_address;
86 __le32 data[] = { TA_HOLD_THREAD_VALUE, TA_SOFT_RST_CLR,
87 TA_PC_ZERO, TA_RELEASE_THREAD_VALUE };
88 u32 address[] = { TA_HOLD_THREAD_REG, TA_SOFT_RESET_REG,
89 TA_TH0_PC_REG, TA_RELEASE_THREAD_REG };
90 u32 base_address;
91 u16 msb_address;
92
93 base_address = TA_LOAD_ADDRESS;
94 msb_address = base_address >> 16;
95
96 for (indx = 0, ii = 0; ii < num_blocks; ii++, indx += block_size) {
97 lsb_address = ((u16) base_address | RSI_SD_REQUEST_MASTER);
98 if (rsi_sdio_write_register_multiple(adapter,
99 lsb_address,
100 (u8 *)(fw + indx),
101 block_size)) {
102 rsi_dbg(ERR_ZONE,
103 "%s: Unable to load %s blk\n", __func__,
104 FIRMWARE_RSI9113);
105 return -1;
106 }
107 rsi_dbg(INIT_ZONE, "%s: loading block: %d\n", __func__, ii);
108 base_address += block_size;
109 if ((base_address >> 16) != msb_address) {
110 msb_address += 1;
111 if (rsi_sdio_master_access_msword(adapter,
112 msb_address)) {
113 rsi_dbg(ERR_ZONE,
114 "%s: Unable to set ms word reg\n",
115 __func__);
116 return -1;
117 }
118 }
119 }
120
121 if (len % block_size) {
122 lsb_address = ((u16) base_address | RSI_SD_REQUEST_MASTER);
123 if (rsi_sdio_write_register_multiple(adapter,
124 lsb_address,
125 (u8 *)(fw + indx),
126 len % block_size)) {
127 rsi_dbg(ERR_ZONE,
128 "%s: Unable to load f/w\n", __func__);
129 return -1;
130 }
131 }
132 rsi_dbg(INIT_ZONE,
133 "%s: Succesfully loaded TA instructions\n", __func__);
134
135 if (rsi_sdio_master_access_msword(adapter, TA_BASE_ADDR)) {
136 rsi_dbg(ERR_ZONE,
137 "%s: Unable to set ms word to common reg\n",
138 __func__);
139 return -1;
140 }
141
142 for (ii = 0; ii < ARRAY_SIZE(data); ii++) {
143
144 if (rsi_sdio_write_register_multiple(adapter,
145 (address[ii] |
146 RSI_SD_REQUEST_MASTER),
147 (u8 *)&data[ii],
148 4)) {
149 rsi_dbg(ERR_ZONE,
150 "%s: Unable to hold TA threads\n", __func__);
151 return -1;
152 }
153 }
154
155 rsi_dbg(INIT_ZONE, "%s: loaded firmware\n", __func__);
156 return 0;
157}
158
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161
162
163
164
165
166
167
168static int rsi_load_ta_instructions(struct rsi_common *common)
169{
170 struct rsi_hw *adapter = common->priv;
171 struct rsi_91x_sdiodev *dev =
172 (struct rsi_91x_sdiodev *)adapter->rsi_dev;
173 u32 len;
174 u32 num_blocks;
175 const u8 *fw;
176 const struct firmware *fw_entry = NULL;
177 u32 block_size = dev->tx_blk_size;
178 int status = 0;
179 u32 base_address;
180 u16 msb_address;
181
182 if (rsi_sdio_master_access_msword(adapter, TA_BASE_ADDR)) {
183 rsi_dbg(ERR_ZONE,
184 "%s: Unable to set ms word to common reg\n",
185 __func__);
186 return -1;
187 }
188 base_address = TA_LOAD_ADDRESS;
189 msb_address = (base_address >> 16);
190
191 if (rsi_sdio_master_access_msword(adapter, msb_address)) {
192 rsi_dbg(ERR_ZONE,
193 "%s: Unable to set ms word reg\n", __func__);
194 return -1;
195 }
196
197 status = request_firmware(&fw_entry, FIRMWARE_RSI9113, adapter->device);
198 if (status < 0) {
199 rsi_dbg(ERR_ZONE, "%s Firmware file %s not found\n",
200 __func__, FIRMWARE_RSI9113);
201 return status;
202 }
203
204
205 fw = kmemdup(fw_entry->data, fw_entry->size, GFP_KERNEL);
206 if (!fw) {
207 status = -ENOMEM;
208 goto out;
209 }
210 len = fw_entry->size;
211
212 if (len % 4)
213 len += (4 - (len % 4));
214
215 num_blocks = (len / block_size);
216
217 rsi_dbg(INIT_ZONE, "%s: Instruction size:%d\n", __func__, len);
218 rsi_dbg(INIT_ZONE, "%s: num blocks: %d\n", __func__, num_blocks);
219
220 status = rsi_copy_to_card(common, fw, len, num_blocks);
221 kfree(fw);
222
223out:
224 release_firmware(fw_entry);
225 return status;
226}
227
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229
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231
232
233
234
235static int rsi_process_pkt(struct rsi_common *common)
236{
237 struct rsi_hw *adapter = common->priv;
238 u8 num_blks = 0;
239 u32 rcv_pkt_len = 0;
240 int status = 0;
241
242 status = rsi_sdio_read_register(adapter,
243 SDIO_RX_NUM_BLOCKS_REG,
244 &num_blks);
245
246 if (status) {
247 rsi_dbg(ERR_ZONE,
248 "%s: Failed to read pkt length from the card:\n",
249 __func__);
250 return status;
251 }
252 rcv_pkt_len = (num_blks * 256);
253
254 common->rx_data_pkt = kmalloc(rcv_pkt_len, GFP_KERNEL);
255 if (!common->rx_data_pkt) {
256 rsi_dbg(ERR_ZONE, "%s: Failed in memory allocation\n",
257 __func__);
258 return -ENOMEM;
259 }
260
261 status = rsi_sdio_host_intf_read_pkt(adapter,
262 common->rx_data_pkt,
263 rcv_pkt_len);
264 if (status) {
265 rsi_dbg(ERR_ZONE, "%s: Failed to read packet from card\n",
266 __func__);
267 goto fail;
268 }
269
270 status = rsi_read_pkt(common, rcv_pkt_len);
271
272fail:
273 kfree(common->rx_data_pkt);
274 return status;
275}
276
277
278
279
280
281
282
283
284int rsi_init_sdio_slave_regs(struct rsi_hw *adapter)
285{
286 struct rsi_91x_sdiodev *dev =
287 (struct rsi_91x_sdiodev *)adapter->rsi_dev;
288 u8 function = 0;
289 u8 byte;
290 int status = 0;
291
292 if (dev->next_read_delay) {
293 byte = dev->next_read_delay;
294 status = rsi_sdio_write_register(adapter,
295 function,
296 SDIO_NXT_RD_DELAY2,
297 &byte);
298 if (status) {
299 rsi_dbg(ERR_ZONE,
300 "%s: Failed to write SDIO_NXT_RD_DELAY2\n",
301 __func__);
302 return -1;
303 }
304 }
305
306 if (dev->sdio_high_speed_enable) {
307 rsi_dbg(INIT_ZONE, "%s: Enabling SDIO High speed\n", __func__);
308 byte = 0x3;
309
310 status = rsi_sdio_write_register(adapter,
311 function,
312 SDIO_REG_HIGH_SPEED,
313 &byte);
314 if (status) {
315 rsi_dbg(ERR_ZONE,
316 "%s: Failed to enable SDIO high speed\n",
317 __func__);
318 return -1;
319 }
320 }
321
322
323 rsi_dbg(INIT_ZONE, "%s: Initialzing SDIO read start level\n", __func__);
324 byte = 0x24;
325
326 status = rsi_sdio_write_register(adapter,
327 function,
328 SDIO_READ_START_LVL,
329 &byte);
330 if (status) {
331 rsi_dbg(ERR_ZONE,
332 "%s: Failed to write SDIO_READ_START_LVL\n", __func__);
333 return -1;
334 }
335
336 rsi_dbg(INIT_ZONE, "%s: Initialzing FIFO ctrl registers\n", __func__);
337 byte = (128 - 32);
338
339 status = rsi_sdio_write_register(adapter,
340 function,
341 SDIO_READ_FIFO_CTL,
342 &byte);
343 if (status) {
344 rsi_dbg(ERR_ZONE,
345 "%s: Failed to write SDIO_READ_FIFO_CTL\n", __func__);
346 return -1;
347 }
348
349 byte = 32;
350 status = rsi_sdio_write_register(adapter,
351 function,
352 SDIO_WRITE_FIFO_CTL,
353 &byte);
354 if (status) {
355 rsi_dbg(ERR_ZONE,
356 "%s: Failed to write SDIO_WRITE_FIFO_CTL\n", __func__);
357 return -1;
358 }
359
360 return 0;
361}
362
363
364
365
366
367
368
369void rsi_interrupt_handler(struct rsi_hw *adapter)
370{
371 struct rsi_common *common = adapter->priv;
372 struct rsi_91x_sdiodev *dev =
373 (struct rsi_91x_sdiodev *)adapter->rsi_dev;
374 int status;
375 enum sdio_interrupt_type isr_type;
376 u8 isr_status = 0;
377 u8 fw_status = 0;
378
379 dev->rx_info.sdio_int_counter++;
380
381 do {
382 mutex_lock(&common->tx_rxlock);
383 status = rsi_sdio_read_register(common->priv,
384 RSI_FN1_INT_REGISTER,
385 &isr_status);
386 if (status) {
387 rsi_dbg(ERR_ZONE,
388 "%s: Failed to Read Intr Status Register\n",
389 __func__);
390 mutex_unlock(&common->tx_rxlock);
391 return;
392 }
393
394 if (isr_status == 0) {
395 rsi_set_event(&common->tx_thread.event);
396 dev->rx_info.sdio_intr_status_zero++;
397 mutex_unlock(&common->tx_rxlock);
398 return;
399 }
400
401 rsi_dbg(ISR_ZONE, "%s: Intr_status = %x %d %d\n",
402 __func__, isr_status, (1 << MSDU_PKT_PENDING),
403 (1 << FW_ASSERT_IND));
404
405 do {
406 RSI_GET_SDIO_INTERRUPT_TYPE(isr_status, isr_type);
407
408 switch (isr_type) {
409 case BUFFER_AVAILABLE:
410 dev->rx_info.watch_bufferfull_count = 0;
411 dev->rx_info.buffer_full = false;
412 dev->rx_info.semi_buffer_full = false;
413 dev->rx_info.mgmt_buffer_full = false;
414 rsi_sdio_ack_intr(common->priv,
415 (1 << PKT_BUFF_AVAILABLE));
416 rsi_set_event(&common->tx_thread.event);
417
418 rsi_dbg(ISR_ZONE,
419 "%s: ==> BUFFER_AVAILABLE <==\n",
420 __func__);
421 dev->rx_info.buf_available_counter++;
422 break;
423
424 case FIRMWARE_ASSERT_IND:
425 rsi_dbg(ERR_ZONE,
426 "%s: ==> FIRMWARE Assert <==\n",
427 __func__);
428 status = rsi_sdio_read_register(common->priv,
429 SDIO_FW_STATUS_REG,
430 &fw_status);
431 if (status) {
432 rsi_dbg(ERR_ZONE,
433 "%s: Failed to read f/w reg\n",
434 __func__);
435 } else {
436 rsi_dbg(ERR_ZONE,
437 "%s: Firmware Status is 0x%x\n",
438 __func__ , fw_status);
439 rsi_sdio_ack_intr(common->priv,
440 (1 << FW_ASSERT_IND));
441 }
442
443 common->fsm_state = FSM_CARD_NOT_READY;
444 break;
445
446 case MSDU_PACKET_PENDING:
447 rsi_dbg(ISR_ZONE, "Pkt pending interrupt\n");
448 dev->rx_info.total_sdio_msdu_pending_intr++;
449
450 status = rsi_process_pkt(common);
451 if (status) {
452 rsi_dbg(ERR_ZONE,
453 "%s: Failed to read pkt\n",
454 __func__);
455 mutex_unlock(&common->tx_rxlock);
456 return;
457 }
458 break;
459 default:
460 rsi_sdio_ack_intr(common->priv, isr_status);
461 dev->rx_info.total_sdio_unknown_intr++;
462 isr_status = 0;
463 rsi_dbg(ISR_ZONE,
464 "Unknown Interrupt %x\n",
465 isr_status);
466 break;
467 }
468 isr_status ^= BIT(isr_type - 1);
469 } while (isr_status);
470 mutex_unlock(&common->tx_rxlock);
471 } while (1);
472}
473
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476
477
478
479
480int rsi_sdio_device_init(struct rsi_common *common)
481{
482 if (rsi_load_ta_instructions(common))
483 return -1;
484
485 if (rsi_sdio_master_access_msword(common->priv, MISC_CFG_BASE_ADDR)) {
486 rsi_dbg(ERR_ZONE, "%s: Unable to set ms word reg\n",
487 __func__);
488 return -1;
489 }
490 rsi_dbg(INIT_ZONE,
491 "%s: Setting ms word to 0x41050000\n", __func__);
492
493 return 0;
494}
495
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504
505
506int rsi_sdio_read_buffer_status_register(struct rsi_hw *adapter, u8 q_num)
507{
508 struct rsi_common *common = adapter->priv;
509 struct rsi_91x_sdiodev *dev =
510 (struct rsi_91x_sdiodev *)adapter->rsi_dev;
511 u8 buf_status = 0;
512 int status = 0;
513
514 status = rsi_sdio_read_register(common->priv,
515 RSI_DEVICE_BUFFER_STATUS_REGISTER,
516 &buf_status);
517
518 if (status) {
519 rsi_dbg(ERR_ZONE,
520 "%s: Failed to read status register\n", __func__);
521 return -1;
522 }
523
524 if (buf_status & (BIT(PKT_MGMT_BUFF_FULL))) {
525 if (!dev->rx_info.mgmt_buffer_full)
526 dev->rx_info.mgmt_buf_full_counter++;
527 dev->rx_info.mgmt_buffer_full = true;
528 } else {
529 dev->rx_info.mgmt_buffer_full = false;
530 }
531
532 if (buf_status & (BIT(PKT_BUFF_FULL))) {
533 if (!dev->rx_info.buffer_full)
534 dev->rx_info.buf_full_counter++;
535 dev->rx_info.buffer_full = true;
536 } else {
537 dev->rx_info.buffer_full = false;
538 }
539
540 if (buf_status & (BIT(PKT_BUFF_SEMI_FULL))) {
541 if (!dev->rx_info.semi_buffer_full)
542 dev->rx_info.buf_semi_full_counter++;
543 dev->rx_info.semi_buffer_full = true;
544 } else {
545 dev->rx_info.semi_buffer_full = false;
546 }
547
548 if ((q_num == MGMT_SOFT_Q) && (dev->rx_info.mgmt_buffer_full))
549 return QUEUE_FULL;
550
551 if (dev->rx_info.buffer_full)
552 return QUEUE_FULL;
553
554 return QUEUE_NOT_FULL;
555}
556
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558
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560
561
562
563
564int rsi_sdio_determine_event_timeout(struct rsi_hw *adapter)
565{
566 struct rsi_91x_sdiodev *dev =
567 (struct rsi_91x_sdiodev *)adapter->rsi_dev;
568
569
570 if (dev->rx_info.buffer_full)
571 return 2;
572
573 return EVENT_WAIT_FOREVER;
574}
575
