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21#include <linux/clk.h>
22#include <linux/completion.h>
23#include <linux/delay.h>
24#include <linux/dmaengine.h>
25#include <linux/dma-mapping.h>
26#include <linux/err.h>
27#include <linux/gpio.h>
28#include <linux/interrupt.h>
29#include <linux/io.h>
30#include <linux/irq.h>
31#include <linux/kernel.h>
32#include <linux/module.h>
33#include <linux/platform_device.h>
34#include <linux/slab.h>
35#include <linux/spi/spi.h>
36#include <linux/spi/spi_bitbang.h>
37#include <linux/types.h>
38#include <linux/of.h>
39#include <linux/of_device.h>
40#include <linux/of_gpio.h>
41
42#include <linux/platform_data/dma-imx.h>
43#include <linux/platform_data/spi-imx.h>
44
45#define DRIVER_NAME "spi_imx"
46
47#define MXC_CSPIRXDATA 0x00
48#define MXC_CSPITXDATA 0x04
49#define MXC_CSPICTRL 0x08
50#define MXC_CSPIINT 0x0c
51#define MXC_RESET 0x1c
52
53
54#define MXC_INT_RR (1 << 0)
55#define MXC_INT_TE (1 << 1)
56
57
58#define MAX_SDMA_BD_BYTES (1 << 15)
59#define IMX_DMA_TIMEOUT (msecs_to_jiffies(3000))
60struct spi_imx_config {
61 unsigned int speed_hz;
62 unsigned int bpw;
63 unsigned int mode;
64 u8 cs;
65};
66
67enum spi_imx_devtype {
68 IMX1_CSPI,
69 IMX21_CSPI,
70 IMX27_CSPI,
71 IMX31_CSPI,
72 IMX35_CSPI,
73 IMX51_ECSPI,
74};
75
76struct spi_imx_data;
77
78struct spi_imx_devtype_data {
79 void (*intctrl)(struct spi_imx_data *, int);
80 int (*config)(struct spi_imx_data *, struct spi_imx_config *);
81 void (*trigger)(struct spi_imx_data *);
82 int (*rx_available)(struct spi_imx_data *);
83 void (*reset)(struct spi_imx_data *);
84 enum spi_imx_devtype devtype;
85};
86
87struct spi_imx_data {
88 struct spi_bitbang bitbang;
89
90 struct completion xfer_done;
91 void __iomem *base;
92 struct clk *clk_per;
93 struct clk *clk_ipg;
94 unsigned long spi_clk;
95
96 unsigned int count;
97 void (*tx)(struct spi_imx_data *);
98 void (*rx)(struct spi_imx_data *);
99 void *rx_buf;
100 const void *tx_buf;
101 unsigned int txfifo;
102
103
104 unsigned int dma_is_inited;
105 unsigned int dma_finished;
106 bool usedma;
107 u32 wml;
108 struct completion dma_rx_completion;
109 struct completion dma_tx_completion;
110
111 const struct spi_imx_devtype_data *devtype_data;
112 int chipselect[0];
113};
114
115static inline int is_imx27_cspi(struct spi_imx_data *d)
116{
117 return d->devtype_data->devtype == IMX27_CSPI;
118}
119
120static inline int is_imx35_cspi(struct spi_imx_data *d)
121{
122 return d->devtype_data->devtype == IMX35_CSPI;
123}
124
125static inline int is_imx51_ecspi(struct spi_imx_data *d)
126{
127 return d->devtype_data->devtype == IMX51_ECSPI;
128}
129
130static inline unsigned spi_imx_get_fifosize(struct spi_imx_data *d)
131{
132 return is_imx51_ecspi(d) ? 64 : 8;
133}
134
135#define MXC_SPI_BUF_RX(type) \
136static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx) \
137{ \
138 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \
139 \
140 if (spi_imx->rx_buf) { \
141 *(type *)spi_imx->rx_buf = val; \
142 spi_imx->rx_buf += sizeof(type); \
143 } \
144}
145
146#define MXC_SPI_BUF_TX(type) \
147static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx) \
148{ \
149 type val = 0; \
150 \
151 if (spi_imx->tx_buf) { \
152 val = *(type *)spi_imx->tx_buf; \
153 spi_imx->tx_buf += sizeof(type); \
154 } \
155 \
156 spi_imx->count -= sizeof(type); \
157 \
158 writel(val, spi_imx->base + MXC_CSPITXDATA); \
159}
160
161MXC_SPI_BUF_RX(u8)
162MXC_SPI_BUF_TX(u8)
163MXC_SPI_BUF_RX(u16)
164MXC_SPI_BUF_TX(u16)
165MXC_SPI_BUF_RX(u32)
166MXC_SPI_BUF_TX(u32)
167
168
169
170
171static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192,
172 256, 384, 512, 768, 1024};
173
174
175static unsigned int spi_imx_clkdiv_1(unsigned int fin,
176 unsigned int fspi, unsigned int max)
177{
178 int i;
179
180 for (i = 2; i < max; i++)
181 if (fspi * mxc_clkdivs[i] >= fin)
182 return i;
183
184 return max;
185}
186
187
188static unsigned int spi_imx_clkdiv_2(unsigned int fin,
189 unsigned int fspi)
190{
191 int i, div = 4;
192
193 for (i = 0; i < 7; i++) {
194 if (fspi * div >= fin)
195 return i;
196 div <<= 1;
197 }
198
199 return 7;
200}
201
202static bool spi_imx_can_dma(struct spi_master *master, struct spi_device *spi,
203 struct spi_transfer *transfer)
204{
205 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
206
207 if (spi_imx->dma_is_inited && transfer->len >= spi_imx->wml &&
208 (transfer->len % spi_imx->wml) == 0)
209 return true;
210 return false;
211}
212
213#define MX51_ECSPI_CTRL 0x08
214#define MX51_ECSPI_CTRL_ENABLE (1 << 0)
215#define MX51_ECSPI_CTRL_XCH (1 << 2)
216#define MX51_ECSPI_CTRL_SMC (1 << 3)
217#define MX51_ECSPI_CTRL_MODE_MASK (0xf << 4)
218#define MX51_ECSPI_CTRL_POSTDIV_OFFSET 8
219#define MX51_ECSPI_CTRL_PREDIV_OFFSET 12
220#define MX51_ECSPI_CTRL_CS(cs) ((cs) << 18)
221#define MX51_ECSPI_CTRL_BL_OFFSET 20
222
223#define MX51_ECSPI_CONFIG 0x0c
224#define MX51_ECSPI_CONFIG_SCLKPHA(cs) (1 << ((cs) + 0))
225#define MX51_ECSPI_CONFIG_SCLKPOL(cs) (1 << ((cs) + 4))
226#define MX51_ECSPI_CONFIG_SBBCTRL(cs) (1 << ((cs) + 8))
227#define MX51_ECSPI_CONFIG_SSBPOL(cs) (1 << ((cs) + 12))
228#define MX51_ECSPI_CONFIG_SCLKCTL(cs) (1 << ((cs) + 20))
229
230#define MX51_ECSPI_INT 0x10
231#define MX51_ECSPI_INT_TEEN (1 << 0)
232#define MX51_ECSPI_INT_RREN (1 << 3)
233
234#define MX51_ECSPI_DMA 0x14
235#define MX51_ECSPI_DMA_TX_WML_OFFSET 0
236#define MX51_ECSPI_DMA_TX_WML_MASK 0x3F
237#define MX51_ECSPI_DMA_RX_WML_OFFSET 16
238#define MX51_ECSPI_DMA_RX_WML_MASK (0x3F << 16)
239#define MX51_ECSPI_DMA_RXT_WML_OFFSET 24
240#define MX51_ECSPI_DMA_RXT_WML_MASK (0x3F << 24)
241
242#define MX51_ECSPI_DMA_TEDEN_OFFSET 7
243#define MX51_ECSPI_DMA_RXDEN_OFFSET 23
244#define MX51_ECSPI_DMA_RXTDEN_OFFSET 31
245
246#define MX51_ECSPI_STAT 0x18
247#define MX51_ECSPI_STAT_RR (1 << 3)
248
249#define MX51_ECSPI_TESTREG 0x20
250#define MX51_ECSPI_TESTREG_LBC BIT(31)
251
252
253static unsigned int mx51_ecspi_clkdiv(unsigned int fin, unsigned int fspi,
254 unsigned int *fres)
255{
256
257
258
259
260 unsigned int pre, post;
261
262 if (unlikely(fspi > fin))
263 return 0;
264
265 post = fls(fin) - fls(fspi);
266 if (fin > fspi << post)
267 post++;
268
269
270
271 post = max(4U, post) - 4;
272 if (unlikely(post > 0xf)) {
273 pr_err("%s: cannot set clock freq: %u (base freq: %u)\n",
274 __func__, fspi, fin);
275 return 0xff;
276 }
277
278 pre = DIV_ROUND_UP(fin, fspi << post) - 1;
279
280 pr_debug("%s: fin: %u, fspi: %u, post: %u, pre: %u\n",
281 __func__, fin, fspi, post, pre);
282
283
284 *fres = (fin / (pre + 1)) >> post;
285
286 return (pre << MX51_ECSPI_CTRL_PREDIV_OFFSET) |
287 (post << MX51_ECSPI_CTRL_POSTDIV_OFFSET);
288}
289
290static void __maybe_unused mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int enable)
291{
292 unsigned val = 0;
293
294 if (enable & MXC_INT_TE)
295 val |= MX51_ECSPI_INT_TEEN;
296
297 if (enable & MXC_INT_RR)
298 val |= MX51_ECSPI_INT_RREN;
299
300 writel(val, spi_imx->base + MX51_ECSPI_INT);
301}
302
303static void __maybe_unused mx51_ecspi_trigger(struct spi_imx_data *spi_imx)
304{
305 u32 reg = readl(spi_imx->base + MX51_ECSPI_CTRL);
306
307 if (!spi_imx->usedma)
308 reg |= MX51_ECSPI_CTRL_XCH;
309 else if (!spi_imx->dma_finished)
310 reg |= MX51_ECSPI_CTRL_SMC;
311 else
312 reg &= ~MX51_ECSPI_CTRL_SMC;
313 writel(reg, spi_imx->base + MX51_ECSPI_CTRL);
314}
315
316static int __maybe_unused mx51_ecspi_config(struct spi_imx_data *spi_imx,
317 struct spi_imx_config *config)
318{
319 u32 ctrl = MX51_ECSPI_CTRL_ENABLE, cfg = 0, dma = 0;
320 u32 tx_wml_cfg, rx_wml_cfg, rxt_wml_cfg;
321 u32 clk = config->speed_hz, delay, reg;
322
323
324
325
326
327
328
329
330 ctrl |= MX51_ECSPI_CTRL_MODE_MASK;
331
332
333 ctrl |= mx51_ecspi_clkdiv(spi_imx->spi_clk, config->speed_hz, &clk);
334
335
336 ctrl |= MX51_ECSPI_CTRL_CS(config->cs);
337
338 ctrl |= (config->bpw - 1) << MX51_ECSPI_CTRL_BL_OFFSET;
339
340 cfg |= MX51_ECSPI_CONFIG_SBBCTRL(config->cs);
341
342 if (config->mode & SPI_CPHA)
343 cfg |= MX51_ECSPI_CONFIG_SCLKPHA(config->cs);
344 else
345 cfg &= ~MX51_ECSPI_CONFIG_SCLKPHA(config->cs);
346
347 if (config->mode & SPI_CPOL) {
348 cfg |= MX51_ECSPI_CONFIG_SCLKPOL(config->cs);
349 cfg |= MX51_ECSPI_CONFIG_SCLKCTL(config->cs);
350 } else {
351 cfg &= ~MX51_ECSPI_CONFIG_SCLKPOL(config->cs);
352 cfg &= ~MX51_ECSPI_CONFIG_SCLKCTL(config->cs);
353 }
354 if (config->mode & SPI_CS_HIGH)
355 cfg |= MX51_ECSPI_CONFIG_SSBPOL(config->cs);
356 else
357 cfg &= ~MX51_ECSPI_CONFIG_SSBPOL(config->cs);
358
359
360 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
361
362 reg = readl(spi_imx->base + MX51_ECSPI_TESTREG);
363 if (config->mode & SPI_LOOP)
364 reg |= MX51_ECSPI_TESTREG_LBC;
365 else
366 reg &= ~MX51_ECSPI_TESTREG_LBC;
367 writel(reg, spi_imx->base + MX51_ECSPI_TESTREG);
368
369 writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG);
370
371
372
373
374
375
376
377
378
379
380
381
382 delay = (2 * 1000000) / clk;
383 if (likely(delay < 10))
384 udelay(delay);
385 else
386 usleep_range(delay, delay + 10);
387
388
389
390
391
392 if (spi_imx->dma_is_inited) {
393 dma = readl(spi_imx->base + MX51_ECSPI_DMA);
394
395 rx_wml_cfg = spi_imx->wml << MX51_ECSPI_DMA_RX_WML_OFFSET;
396 tx_wml_cfg = spi_imx->wml << MX51_ECSPI_DMA_TX_WML_OFFSET;
397 rxt_wml_cfg = spi_imx->wml << MX51_ECSPI_DMA_RXT_WML_OFFSET;
398 dma = (dma & ~MX51_ECSPI_DMA_TX_WML_MASK
399 & ~MX51_ECSPI_DMA_RX_WML_MASK
400 & ~MX51_ECSPI_DMA_RXT_WML_MASK)
401 | rx_wml_cfg | tx_wml_cfg | rxt_wml_cfg
402 |(1 << MX51_ECSPI_DMA_TEDEN_OFFSET)
403 |(1 << MX51_ECSPI_DMA_RXDEN_OFFSET)
404 |(1 << MX51_ECSPI_DMA_RXTDEN_OFFSET);
405
406 writel(dma, spi_imx->base + MX51_ECSPI_DMA);
407 }
408
409 return 0;
410}
411
412static int __maybe_unused mx51_ecspi_rx_available(struct spi_imx_data *spi_imx)
413{
414 return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR;
415}
416
417static void __maybe_unused mx51_ecspi_reset(struct spi_imx_data *spi_imx)
418{
419
420 while (mx51_ecspi_rx_available(spi_imx))
421 readl(spi_imx->base + MXC_CSPIRXDATA);
422}
423
424#define MX31_INTREG_TEEN (1 << 0)
425#define MX31_INTREG_RREN (1 << 3)
426
427#define MX31_CSPICTRL_ENABLE (1 << 0)
428#define MX31_CSPICTRL_MASTER (1 << 1)
429#define MX31_CSPICTRL_XCH (1 << 2)
430#define MX31_CSPICTRL_POL (1 << 4)
431#define MX31_CSPICTRL_PHA (1 << 5)
432#define MX31_CSPICTRL_SSCTL (1 << 6)
433#define MX31_CSPICTRL_SSPOL (1 << 7)
434#define MX31_CSPICTRL_BC_SHIFT 8
435#define MX35_CSPICTRL_BL_SHIFT 20
436#define MX31_CSPICTRL_CS_SHIFT 24
437#define MX35_CSPICTRL_CS_SHIFT 12
438#define MX31_CSPICTRL_DR_SHIFT 16
439
440#define MX31_CSPISTATUS 0x14
441#define MX31_STATUS_RR (1 << 3)
442
443
444
445
446
447static void __maybe_unused mx31_intctrl(struct spi_imx_data *spi_imx, int enable)
448{
449 unsigned int val = 0;
450
451 if (enable & MXC_INT_TE)
452 val |= MX31_INTREG_TEEN;
453 if (enable & MXC_INT_RR)
454 val |= MX31_INTREG_RREN;
455
456 writel(val, spi_imx->base + MXC_CSPIINT);
457}
458
459static void __maybe_unused mx31_trigger(struct spi_imx_data *spi_imx)
460{
461 unsigned int reg;
462
463 reg = readl(spi_imx->base + MXC_CSPICTRL);
464 reg |= MX31_CSPICTRL_XCH;
465 writel(reg, spi_imx->base + MXC_CSPICTRL);
466}
467
468static int __maybe_unused mx31_config(struct spi_imx_data *spi_imx,
469 struct spi_imx_config *config)
470{
471 unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER;
472 int cs = spi_imx->chipselect[config->cs];
473
474 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
475 MX31_CSPICTRL_DR_SHIFT;
476
477 if (is_imx35_cspi(spi_imx)) {
478 reg |= (config->bpw - 1) << MX35_CSPICTRL_BL_SHIFT;
479 reg |= MX31_CSPICTRL_SSCTL;
480 } else {
481 reg |= (config->bpw - 1) << MX31_CSPICTRL_BC_SHIFT;
482 }
483
484 if (config->mode & SPI_CPHA)
485 reg |= MX31_CSPICTRL_PHA;
486 if (config->mode & SPI_CPOL)
487 reg |= MX31_CSPICTRL_POL;
488 if (config->mode & SPI_CS_HIGH)
489 reg |= MX31_CSPICTRL_SSPOL;
490 if (cs < 0)
491 reg |= (cs + 32) <<
492 (is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT :
493 MX31_CSPICTRL_CS_SHIFT);
494
495 writel(reg, spi_imx->base + MXC_CSPICTRL);
496
497 return 0;
498}
499
500static int __maybe_unused mx31_rx_available(struct spi_imx_data *spi_imx)
501{
502 return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR;
503}
504
505static void __maybe_unused mx31_reset(struct spi_imx_data *spi_imx)
506{
507
508 while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR)
509 readl(spi_imx->base + MXC_CSPIRXDATA);
510}
511
512#define MX21_INTREG_RR (1 << 4)
513#define MX21_INTREG_TEEN (1 << 9)
514#define MX21_INTREG_RREN (1 << 13)
515
516#define MX21_CSPICTRL_POL (1 << 5)
517#define MX21_CSPICTRL_PHA (1 << 6)
518#define MX21_CSPICTRL_SSPOL (1 << 8)
519#define MX21_CSPICTRL_XCH (1 << 9)
520#define MX21_CSPICTRL_ENABLE (1 << 10)
521#define MX21_CSPICTRL_MASTER (1 << 11)
522#define MX21_CSPICTRL_DR_SHIFT 14
523#define MX21_CSPICTRL_CS_SHIFT 19
524
525static void __maybe_unused mx21_intctrl(struct spi_imx_data *spi_imx, int enable)
526{
527 unsigned int val = 0;
528
529 if (enable & MXC_INT_TE)
530 val |= MX21_INTREG_TEEN;
531 if (enable & MXC_INT_RR)
532 val |= MX21_INTREG_RREN;
533
534 writel(val, spi_imx->base + MXC_CSPIINT);
535}
536
537static void __maybe_unused mx21_trigger(struct spi_imx_data *spi_imx)
538{
539 unsigned int reg;
540
541 reg = readl(spi_imx->base + MXC_CSPICTRL);
542 reg |= MX21_CSPICTRL_XCH;
543 writel(reg, spi_imx->base + MXC_CSPICTRL);
544}
545
546static int __maybe_unused mx21_config(struct spi_imx_data *spi_imx,
547 struct spi_imx_config *config)
548{
549 unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_MASTER;
550 int cs = spi_imx->chipselect[config->cs];
551 unsigned int max = is_imx27_cspi(spi_imx) ? 16 : 18;
552
553 reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, config->speed_hz, max) <<
554 MX21_CSPICTRL_DR_SHIFT;
555 reg |= config->bpw - 1;
556
557 if (config->mode & SPI_CPHA)
558 reg |= MX21_CSPICTRL_PHA;
559 if (config->mode & SPI_CPOL)
560 reg |= MX21_CSPICTRL_POL;
561 if (config->mode & SPI_CS_HIGH)
562 reg |= MX21_CSPICTRL_SSPOL;
563 if (cs < 0)
564 reg |= (cs + 32) << MX21_CSPICTRL_CS_SHIFT;
565
566 writel(reg, spi_imx->base + MXC_CSPICTRL);
567
568 return 0;
569}
570
571static int __maybe_unused mx21_rx_available(struct spi_imx_data *spi_imx)
572{
573 return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR;
574}
575
576static void __maybe_unused mx21_reset(struct spi_imx_data *spi_imx)
577{
578 writel(1, spi_imx->base + MXC_RESET);
579}
580
581#define MX1_INTREG_RR (1 << 3)
582#define MX1_INTREG_TEEN (1 << 8)
583#define MX1_INTREG_RREN (1 << 11)
584
585#define MX1_CSPICTRL_POL (1 << 4)
586#define MX1_CSPICTRL_PHA (1 << 5)
587#define MX1_CSPICTRL_XCH (1 << 8)
588#define MX1_CSPICTRL_ENABLE (1 << 9)
589#define MX1_CSPICTRL_MASTER (1 << 10)
590#define MX1_CSPICTRL_DR_SHIFT 13
591
592static void __maybe_unused mx1_intctrl(struct spi_imx_data *spi_imx, int enable)
593{
594 unsigned int val = 0;
595
596 if (enable & MXC_INT_TE)
597 val |= MX1_INTREG_TEEN;
598 if (enable & MXC_INT_RR)
599 val |= MX1_INTREG_RREN;
600
601 writel(val, spi_imx->base + MXC_CSPIINT);
602}
603
604static void __maybe_unused mx1_trigger(struct spi_imx_data *spi_imx)
605{
606 unsigned int reg;
607
608 reg = readl(spi_imx->base + MXC_CSPICTRL);
609 reg |= MX1_CSPICTRL_XCH;
610 writel(reg, spi_imx->base + MXC_CSPICTRL);
611}
612
613static int __maybe_unused mx1_config(struct spi_imx_data *spi_imx,
614 struct spi_imx_config *config)
615{
616 unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER;
617
618 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
619 MX1_CSPICTRL_DR_SHIFT;
620 reg |= config->bpw - 1;
621
622 if (config->mode & SPI_CPHA)
623 reg |= MX1_CSPICTRL_PHA;
624 if (config->mode & SPI_CPOL)
625 reg |= MX1_CSPICTRL_POL;
626
627 writel(reg, spi_imx->base + MXC_CSPICTRL);
628
629 return 0;
630}
631
632static int __maybe_unused mx1_rx_available(struct spi_imx_data *spi_imx)
633{
634 return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR;
635}
636
637static void __maybe_unused mx1_reset(struct spi_imx_data *spi_imx)
638{
639 writel(1, spi_imx->base + MXC_RESET);
640}
641
642static struct spi_imx_devtype_data imx1_cspi_devtype_data = {
643 .intctrl = mx1_intctrl,
644 .config = mx1_config,
645 .trigger = mx1_trigger,
646 .rx_available = mx1_rx_available,
647 .reset = mx1_reset,
648 .devtype = IMX1_CSPI,
649};
650
651static struct spi_imx_devtype_data imx21_cspi_devtype_data = {
652 .intctrl = mx21_intctrl,
653 .config = mx21_config,
654 .trigger = mx21_trigger,
655 .rx_available = mx21_rx_available,
656 .reset = mx21_reset,
657 .devtype = IMX21_CSPI,
658};
659
660static struct spi_imx_devtype_data imx27_cspi_devtype_data = {
661
662 .intctrl = mx21_intctrl,
663 .config = mx21_config,
664 .trigger = mx21_trigger,
665 .rx_available = mx21_rx_available,
666 .reset = mx21_reset,
667 .devtype = IMX27_CSPI,
668};
669
670static struct spi_imx_devtype_data imx31_cspi_devtype_data = {
671 .intctrl = mx31_intctrl,
672 .config = mx31_config,
673 .trigger = mx31_trigger,
674 .rx_available = mx31_rx_available,
675 .reset = mx31_reset,
676 .devtype = IMX31_CSPI,
677};
678
679static struct spi_imx_devtype_data imx35_cspi_devtype_data = {
680
681 .intctrl = mx31_intctrl,
682 .config = mx31_config,
683 .trigger = mx31_trigger,
684 .rx_available = mx31_rx_available,
685 .reset = mx31_reset,
686 .devtype = IMX35_CSPI,
687};
688
689static struct spi_imx_devtype_data imx51_ecspi_devtype_data = {
690 .intctrl = mx51_ecspi_intctrl,
691 .config = mx51_ecspi_config,
692 .trigger = mx51_ecspi_trigger,
693 .rx_available = mx51_ecspi_rx_available,
694 .reset = mx51_ecspi_reset,
695 .devtype = IMX51_ECSPI,
696};
697
698static const struct platform_device_id spi_imx_devtype[] = {
699 {
700 .name = "imx1-cspi",
701 .driver_data = (kernel_ulong_t) &imx1_cspi_devtype_data,
702 }, {
703 .name = "imx21-cspi",
704 .driver_data = (kernel_ulong_t) &imx21_cspi_devtype_data,
705 }, {
706 .name = "imx27-cspi",
707 .driver_data = (kernel_ulong_t) &imx27_cspi_devtype_data,
708 }, {
709 .name = "imx31-cspi",
710 .driver_data = (kernel_ulong_t) &imx31_cspi_devtype_data,
711 }, {
712 .name = "imx35-cspi",
713 .driver_data = (kernel_ulong_t) &imx35_cspi_devtype_data,
714 }, {
715 .name = "imx51-ecspi",
716 .driver_data = (kernel_ulong_t) &imx51_ecspi_devtype_data,
717 }, {
718
719 }
720};
721
722static const struct of_device_id spi_imx_dt_ids[] = {
723 { .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, },
724 { .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data, },
725 { .compatible = "fsl,imx27-cspi", .data = &imx27_cspi_devtype_data, },
726 { .compatible = "fsl,imx31-cspi", .data = &imx31_cspi_devtype_data, },
727 { .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, },
728 { .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, },
729 { }
730};
731MODULE_DEVICE_TABLE(of, spi_imx_dt_ids);
732
733static void spi_imx_chipselect(struct spi_device *spi, int is_active)
734{
735 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
736 int gpio = spi_imx->chipselect[spi->chip_select];
737 int active = is_active != BITBANG_CS_INACTIVE;
738 int dev_is_lowactive = !(spi->mode & SPI_CS_HIGH);
739
740 if (!gpio_is_valid(gpio))
741 return;
742
743 gpio_set_value(gpio, dev_is_lowactive ^ active);
744}
745
746static void spi_imx_push(struct spi_imx_data *spi_imx)
747{
748 while (spi_imx->txfifo < spi_imx_get_fifosize(spi_imx)) {
749 if (!spi_imx->count)
750 break;
751 spi_imx->tx(spi_imx);
752 spi_imx->txfifo++;
753 }
754
755 spi_imx->devtype_data->trigger(spi_imx);
756}
757
758static irqreturn_t spi_imx_isr(int irq, void *dev_id)
759{
760 struct spi_imx_data *spi_imx = dev_id;
761
762 while (spi_imx->devtype_data->rx_available(spi_imx)) {
763 spi_imx->rx(spi_imx);
764 spi_imx->txfifo--;
765 }
766
767 if (spi_imx->count) {
768 spi_imx_push(spi_imx);
769 return IRQ_HANDLED;
770 }
771
772 if (spi_imx->txfifo) {
773
774
775
776 spi_imx->devtype_data->intctrl(
777 spi_imx, MXC_INT_RR);
778 return IRQ_HANDLED;
779 }
780
781 spi_imx->devtype_data->intctrl(spi_imx, 0);
782 complete(&spi_imx->xfer_done);
783
784 return IRQ_HANDLED;
785}
786
787static int spi_imx_setupxfer(struct spi_device *spi,
788 struct spi_transfer *t)
789{
790 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
791 struct spi_imx_config config;
792
793 config.bpw = t ? t->bits_per_word : spi->bits_per_word;
794 config.speed_hz = t ? t->speed_hz : spi->max_speed_hz;
795 config.mode = spi->mode;
796 config.cs = spi->chip_select;
797
798 if (!config.speed_hz)
799 config.speed_hz = spi->max_speed_hz;
800 if (!config.bpw)
801 config.bpw = spi->bits_per_word;
802
803
804 if (config.bpw <= 8) {
805 spi_imx->rx = spi_imx_buf_rx_u8;
806 spi_imx->tx = spi_imx_buf_tx_u8;
807 } else if (config.bpw <= 16) {
808 spi_imx->rx = spi_imx_buf_rx_u16;
809 spi_imx->tx = spi_imx_buf_tx_u16;
810 } else {
811 spi_imx->rx = spi_imx_buf_rx_u32;
812 spi_imx->tx = spi_imx_buf_tx_u32;
813 }
814
815 spi_imx->devtype_data->config(spi_imx, &config);
816
817 return 0;
818}
819
820static void spi_imx_sdma_exit(struct spi_imx_data *spi_imx)
821{
822 struct spi_master *master = spi_imx->bitbang.master;
823
824 if (master->dma_rx) {
825 dma_release_channel(master->dma_rx);
826 master->dma_rx = NULL;
827 }
828
829 if (master->dma_tx) {
830 dma_release_channel(master->dma_tx);
831 master->dma_tx = NULL;
832 }
833
834 spi_imx->dma_is_inited = 0;
835}
836
837static int spi_imx_sdma_init(struct device *dev, struct spi_imx_data *spi_imx,
838 struct spi_master *master,
839 const struct resource *res)
840{
841 struct dma_slave_config slave_config = {};
842 int ret;
843
844
845 if (of_machine_is_compatible("fsl,imx6dl"))
846 return 0;
847
848 spi_imx->wml = spi_imx_get_fifosize(spi_imx) / 2;
849
850
851 master->dma_tx = dma_request_slave_channel_reason(dev, "tx");
852 if (IS_ERR(master->dma_tx)) {
853 ret = PTR_ERR(master->dma_tx);
854 dev_dbg(dev, "can't get the TX DMA channel, error %d!\n", ret);
855 master->dma_tx = NULL;
856 goto err;
857 }
858
859 slave_config.direction = DMA_MEM_TO_DEV;
860 slave_config.dst_addr = res->start + MXC_CSPITXDATA;
861 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
862 slave_config.dst_maxburst = spi_imx->wml;
863 ret = dmaengine_slave_config(master->dma_tx, &slave_config);
864 if (ret) {
865 dev_err(dev, "error in TX dma configuration.\n");
866 goto err;
867 }
868
869
870 master->dma_rx = dma_request_slave_channel_reason(dev, "rx");
871 if (IS_ERR(master->dma_rx)) {
872 ret = PTR_ERR(master->dma_rx);
873 dev_dbg(dev, "can't get the RX DMA channel, error %d\n", ret);
874 master->dma_rx = NULL;
875 goto err;
876 }
877
878 slave_config.direction = DMA_DEV_TO_MEM;
879 slave_config.src_addr = res->start + MXC_CSPIRXDATA;
880 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
881 slave_config.src_maxburst = spi_imx->wml;
882 ret = dmaengine_slave_config(master->dma_rx, &slave_config);
883 if (ret) {
884 dev_err(dev, "error in RX dma configuration.\n");
885 goto err;
886 }
887
888 init_completion(&spi_imx->dma_rx_completion);
889 init_completion(&spi_imx->dma_tx_completion);
890 master->can_dma = spi_imx_can_dma;
891 master->max_dma_len = MAX_SDMA_BD_BYTES;
892 spi_imx->bitbang.master->flags = SPI_MASTER_MUST_RX |
893 SPI_MASTER_MUST_TX;
894 spi_imx->dma_is_inited = 1;
895
896 return 0;
897err:
898 spi_imx_sdma_exit(spi_imx);
899 return ret;
900}
901
902static void spi_imx_dma_rx_callback(void *cookie)
903{
904 struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;
905
906 complete(&spi_imx->dma_rx_completion);
907}
908
909static void spi_imx_dma_tx_callback(void *cookie)
910{
911 struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;
912
913 complete(&spi_imx->dma_tx_completion);
914}
915
916static int spi_imx_dma_transfer(struct spi_imx_data *spi_imx,
917 struct spi_transfer *transfer)
918{
919 struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL;
920 int ret;
921 unsigned long timeout;
922 struct spi_master *master = spi_imx->bitbang.master;
923 struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg;
924
925 if (tx) {
926 desc_tx = dmaengine_prep_slave_sg(master->dma_tx,
927 tx->sgl, tx->nents, DMA_MEM_TO_DEV,
928 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
929 if (!desc_tx)
930 goto tx_nodma;
931
932 desc_tx->callback = spi_imx_dma_tx_callback;
933 desc_tx->callback_param = (void *)spi_imx;
934 dmaengine_submit(desc_tx);
935 }
936
937 if (rx) {
938 desc_rx = dmaengine_prep_slave_sg(master->dma_rx,
939 rx->sgl, rx->nents, DMA_DEV_TO_MEM,
940 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
941 if (!desc_rx)
942 goto rx_nodma;
943
944 desc_rx->callback = spi_imx_dma_rx_callback;
945 desc_rx->callback_param = (void *)spi_imx;
946 dmaengine_submit(desc_rx);
947 }
948
949 reinit_completion(&spi_imx->dma_rx_completion);
950 reinit_completion(&spi_imx->dma_tx_completion);
951
952
953 spi_imx->dma_finished = 0;
954
955
956
957
958
959
960
961
962
963 dma_async_issue_pending(master->dma_rx);
964 dma_async_issue_pending(master->dma_tx);
965 spi_imx->devtype_data->trigger(spi_imx);
966
967
968 timeout = wait_for_completion_timeout(&spi_imx->dma_tx_completion,
969 IMX_DMA_TIMEOUT);
970 if (!timeout) {
971 pr_warn("%s %s: I/O Error in DMA TX\n",
972 dev_driver_string(&master->dev),
973 dev_name(&master->dev));
974 dmaengine_terminate_all(master->dma_tx);
975 dmaengine_terminate_all(master->dma_rx);
976 } else {
977 timeout = wait_for_completion_timeout(
978 &spi_imx->dma_rx_completion, IMX_DMA_TIMEOUT);
979 if (!timeout) {
980 pr_warn("%s %s: I/O Error in DMA RX\n",
981 dev_driver_string(&master->dev),
982 dev_name(&master->dev));
983 spi_imx->devtype_data->reset(spi_imx);
984 dmaengine_terminate_all(master->dma_rx);
985 }
986 }
987
988 spi_imx->dma_finished = 1;
989 spi_imx->devtype_data->trigger(spi_imx);
990
991 if (!timeout)
992 ret = -ETIMEDOUT;
993 else
994 ret = transfer->len;
995
996 return ret;
997
998rx_nodma:
999 dmaengine_terminate_all(master->dma_tx);
1000tx_nodma:
1001 pr_warn_once("%s %s: DMA not available, falling back to PIO\n",
1002 dev_driver_string(&master->dev),
1003 dev_name(&master->dev));
1004 return -EAGAIN;
1005}
1006
1007static int spi_imx_pio_transfer(struct spi_device *spi,
1008 struct spi_transfer *transfer)
1009{
1010 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1011
1012 spi_imx->tx_buf = transfer->tx_buf;
1013 spi_imx->rx_buf = transfer->rx_buf;
1014 spi_imx->count = transfer->len;
1015 spi_imx->txfifo = 0;
1016
1017 reinit_completion(&spi_imx->xfer_done);
1018
1019 spi_imx_push(spi_imx);
1020
1021 spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE);
1022
1023 wait_for_completion(&spi_imx->xfer_done);
1024
1025 return transfer->len;
1026}
1027
1028static int spi_imx_transfer(struct spi_device *spi,
1029 struct spi_transfer *transfer)
1030{
1031 int ret;
1032 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1033
1034 if (spi_imx->bitbang.master->can_dma &&
1035 spi_imx_can_dma(spi_imx->bitbang.master, spi, transfer)) {
1036 spi_imx->usedma = true;
1037 ret = spi_imx_dma_transfer(spi_imx, transfer);
1038 if (ret != -EAGAIN)
1039 return ret;
1040 }
1041 spi_imx->usedma = false;
1042
1043 return spi_imx_pio_transfer(spi, transfer);
1044}
1045
1046static int spi_imx_setup(struct spi_device *spi)
1047{
1048 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1049 int gpio = spi_imx->chipselect[spi->chip_select];
1050
1051 dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__,
1052 spi->mode, spi->bits_per_word, spi->max_speed_hz);
1053
1054 if (gpio_is_valid(gpio))
1055 gpio_direction_output(gpio, spi->mode & SPI_CS_HIGH ? 0 : 1);
1056
1057 spi_imx_chipselect(spi, BITBANG_CS_INACTIVE);
1058
1059 return 0;
1060}
1061
1062static void spi_imx_cleanup(struct spi_device *spi)
1063{
1064}
1065
1066static int
1067spi_imx_prepare_message(struct spi_master *master, struct spi_message *msg)
1068{
1069 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1070 int ret;
1071
1072 ret = clk_enable(spi_imx->clk_per);
1073 if (ret)
1074 return ret;
1075
1076 ret = clk_enable(spi_imx->clk_ipg);
1077 if (ret) {
1078 clk_disable(spi_imx->clk_per);
1079 return ret;
1080 }
1081
1082 return 0;
1083}
1084
1085static int
1086spi_imx_unprepare_message(struct spi_master *master, struct spi_message *msg)
1087{
1088 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1089
1090 clk_disable(spi_imx->clk_ipg);
1091 clk_disable(spi_imx->clk_per);
1092 return 0;
1093}
1094
1095static int spi_imx_probe(struct platform_device *pdev)
1096{
1097 struct device_node *np = pdev->dev.of_node;
1098 const struct of_device_id *of_id =
1099 of_match_device(spi_imx_dt_ids, &pdev->dev);
1100 struct spi_imx_master *mxc_platform_info =
1101 dev_get_platdata(&pdev->dev);
1102 struct spi_master *master;
1103 struct spi_imx_data *spi_imx;
1104 struct resource *res;
1105 int i, ret, num_cs, irq;
1106
1107 if (!np && !mxc_platform_info) {
1108 dev_err(&pdev->dev, "can't get the platform data\n");
1109 return -EINVAL;
1110 }
1111
1112 ret = of_property_read_u32(np, "fsl,spi-num-chipselects", &num_cs);
1113 if (ret < 0) {
1114 if (mxc_platform_info)
1115 num_cs = mxc_platform_info->num_chipselect;
1116 else
1117 return ret;
1118 }
1119
1120 master = spi_alloc_master(&pdev->dev,
1121 sizeof(struct spi_imx_data) + sizeof(int) * num_cs);
1122 if (!master)
1123 return -ENOMEM;
1124
1125 platform_set_drvdata(pdev, master);
1126
1127 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
1128 master->bus_num = pdev->id;
1129 master->num_chipselect = num_cs;
1130
1131 spi_imx = spi_master_get_devdata(master);
1132 spi_imx->bitbang.master = master;
1133
1134 spi_imx->devtype_data = of_id ? of_id->data :
1135 (struct spi_imx_devtype_data *)pdev->id_entry->driver_data;
1136
1137 for (i = 0; i < master->num_chipselect; i++) {
1138 int cs_gpio = of_get_named_gpio(np, "cs-gpios", i);
1139 if (!gpio_is_valid(cs_gpio) && mxc_platform_info)
1140 cs_gpio = mxc_platform_info->chipselect[i];
1141
1142 spi_imx->chipselect[i] = cs_gpio;
1143 if (!gpio_is_valid(cs_gpio))
1144 continue;
1145
1146 ret = devm_gpio_request(&pdev->dev, spi_imx->chipselect[i],
1147 DRIVER_NAME);
1148 if (ret) {
1149 dev_err(&pdev->dev, "can't get cs gpios\n");
1150 goto out_master_put;
1151 }
1152 }
1153
1154 spi_imx->bitbang.chipselect = spi_imx_chipselect;
1155 spi_imx->bitbang.setup_transfer = spi_imx_setupxfer;
1156 spi_imx->bitbang.txrx_bufs = spi_imx_transfer;
1157 spi_imx->bitbang.master->setup = spi_imx_setup;
1158 spi_imx->bitbang.master->cleanup = spi_imx_cleanup;
1159 spi_imx->bitbang.master->prepare_message = spi_imx_prepare_message;
1160 spi_imx->bitbang.master->unprepare_message = spi_imx_unprepare_message;
1161 spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1162 if (is_imx51_ecspi(spi_imx))
1163 spi_imx->bitbang.master->mode_bits |= SPI_LOOP;
1164
1165 init_completion(&spi_imx->xfer_done);
1166
1167 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1168 spi_imx->base = devm_ioremap_resource(&pdev->dev, res);
1169 if (IS_ERR(spi_imx->base)) {
1170 ret = PTR_ERR(spi_imx->base);
1171 goto out_master_put;
1172 }
1173
1174 irq = platform_get_irq(pdev, 0);
1175 if (irq < 0) {
1176 ret = irq;
1177 goto out_master_put;
1178 }
1179
1180 ret = devm_request_irq(&pdev->dev, irq, spi_imx_isr, 0,
1181 dev_name(&pdev->dev), spi_imx);
1182 if (ret) {
1183 dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret);
1184 goto out_master_put;
1185 }
1186
1187 spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1188 if (IS_ERR(spi_imx->clk_ipg)) {
1189 ret = PTR_ERR(spi_imx->clk_ipg);
1190 goto out_master_put;
1191 }
1192
1193 spi_imx->clk_per = devm_clk_get(&pdev->dev, "per");
1194 if (IS_ERR(spi_imx->clk_per)) {
1195 ret = PTR_ERR(spi_imx->clk_per);
1196 goto out_master_put;
1197 }
1198
1199 ret = clk_prepare_enable(spi_imx->clk_per);
1200 if (ret)
1201 goto out_master_put;
1202
1203 ret = clk_prepare_enable(spi_imx->clk_ipg);
1204 if (ret)
1205 goto out_put_per;
1206
1207 spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per);
1208
1209
1210
1211
1212 if (is_imx51_ecspi(spi_imx)) {
1213 ret = spi_imx_sdma_init(&pdev->dev, spi_imx, master, res);
1214 if (ret == -EPROBE_DEFER)
1215 goto out_clk_put;
1216
1217 if (ret < 0)
1218 dev_err(&pdev->dev, "dma setup error %d, use pio\n",
1219 ret);
1220 }
1221
1222 spi_imx->devtype_data->reset(spi_imx);
1223
1224 spi_imx->devtype_data->intctrl(spi_imx, 0);
1225
1226 master->dev.of_node = pdev->dev.of_node;
1227 ret = spi_bitbang_start(&spi_imx->bitbang);
1228 if (ret) {
1229 dev_err(&pdev->dev, "bitbang start failed with %d\n", ret);
1230 goto out_clk_put;
1231 }
1232
1233 dev_info(&pdev->dev, "probed\n");
1234
1235 clk_disable(spi_imx->clk_ipg);
1236 clk_disable(spi_imx->clk_per);
1237 return ret;
1238
1239out_clk_put:
1240 clk_disable_unprepare(spi_imx->clk_ipg);
1241out_put_per:
1242 clk_disable_unprepare(spi_imx->clk_per);
1243out_master_put:
1244 spi_master_put(master);
1245
1246 return ret;
1247}
1248
1249static int spi_imx_remove(struct platform_device *pdev)
1250{
1251 struct spi_master *master = platform_get_drvdata(pdev);
1252 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1253
1254 spi_bitbang_stop(&spi_imx->bitbang);
1255
1256 writel(0, spi_imx->base + MXC_CSPICTRL);
1257 clk_unprepare(spi_imx->clk_ipg);
1258 clk_unprepare(spi_imx->clk_per);
1259 spi_imx_sdma_exit(spi_imx);
1260 spi_master_put(master);
1261
1262 return 0;
1263}
1264
1265static struct platform_driver spi_imx_driver = {
1266 .driver = {
1267 .name = DRIVER_NAME,
1268 .of_match_table = spi_imx_dt_ids,
1269 },
1270 .id_table = spi_imx_devtype,
1271 .probe = spi_imx_probe,
1272 .remove = spi_imx_remove,
1273};
1274module_platform_driver(spi_imx_driver);
1275
1276MODULE_DESCRIPTION("SPI Master Controller driver");
1277MODULE_AUTHOR("Sascha Hauer, Pengutronix");
1278MODULE_LICENSE("GPL");
1279MODULE_ALIAS("platform:" DRIVER_NAME);
1280