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20#ifndef __RTL8188E_XMIT_H__
21#define __RTL8188E_XMIT_H__
22
23#define MAX_TX_AGG_PACKET_NUMBER 0xFF
24
25
26
27#define QSLT_BK 0x2
28#define QSLT_BE 0x0
29#define QSLT_VI 0x5
30#define QSLT_VO 0x7
31#define QSLT_BEACON 0x10
32#define QSLT_HIGH 0x11
33#define QSLT_MGNT 0x12
34#define QSLT_CMD 0x13
35
36
37#define SET_EARLYMODE_PKTNUM(__pAddr, __Value) \
38 SET_BITS_TO_LE_4BYTE(__pAddr, 0, 3, __Value)
39#define SET_EARLYMODE_LEN0(__pAddr, __Value) \
40 SET_BITS_TO_LE_4BYTE(__pAddr, 4, 12, __Value)
41#define SET_EARLYMODE_LEN1(__pAddr, __Value) \
42 SET_BITS_TO_LE_4BYTE(__pAddr, 16, 12, __Value)
43#define SET_EARLYMODE_LEN2_1(__pAddr, __Value) \
44 SET_BITS_TO_LE_4BYTE(__pAddr, 28, 4, __Value)
45#define SET_EARLYMODE_LEN2_2(__pAddr, __Value) \
46 SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 8, __Value)
47#define SET_EARLYMODE_LEN3(__pAddr, __Value) \
48 SET_BITS_TO_LE_4BYTE(__pAddr+4, 8, 12, __Value)
49#define SET_EARLYMODE_LEN4(__pAddr, __Value) \
50 SET_BITS_TO_LE_4BYTE(__pAddr+4, 20, 12, __Value)
51
52
53
54
55
56#define MAX_TID (15)
57
58
59#define OFFSET_SZ 0
60#define OFFSET_SHT 16
61#define BMC BIT(24)
62#define LSG BIT(26)
63#define FSG BIT(27)
64#define OWN BIT(31)
65
66
67
68#define PKT_OFFSET_SZ 0
69#define QSEL_SHT 8
70#define RATE_ID_SHT 16
71#define NAVUSEHDR BIT(20)
72#define SEC_TYPE_SHT 22
73#define PKT_OFFSET_SHT 26
74
75
76#define AGG_EN BIT(12)
77#define AGG_BK BIT(16)
78#define AMPDU_DENSITY_SHT 20
79#define ANTSEL_A BIT(24)
80#define ANTSEL_B BIT(25)
81#define TX_ANT_CCK_SHT 26
82#define TX_ANTL_SHT 28
83#define TX_ANT_HT_SHT 30
84
85
86#define SEQ_SHT 16
87#define EN_HWSEQ BIT(31)
88
89
90#define QOS BIT(6)
91#define HW_SSN BIT(7)
92#define USERATE BIT(8)
93#define DISDATAFB BIT(10)
94#define CTS_2_SELF BIT(11)
95#define RTS_EN BIT(12)
96#define HW_RTS_EN BIT(13)
97#define DATA_SHORT BIT(24)
98#define PWR_STATUS_SHT 15
99#define DATA_SC_SHT 20
100#define DATA_BW BIT(25)
101
102
103#define RTY_LMT_EN BIT(17)
104
105enum TXDESC_SC {
106 SC_DONT_CARE = 0x00,
107 SC_UPPER = 0x01,
108 SC_LOWER = 0x02,
109 SC_DUPLICATE = 0x03
110};
111
112#define SGI BIT(6)
113#define USB_TXAGG_NUM_SHT 24
114
115#define txdesc_set_ccx_sw_88e(txdesc, value) \
116 do { \
117 ((struct txdesc_88e *)(txdesc))->sw1 = (((value)>>8) & 0x0f); \
118 ((struct txdesc_88e *)(txdesc))->sw0 = ((value) & 0xff); \
119 } while (0)
120
121struct txrpt_ccx_88e {
122
123 u8 tag1:1;
124 u8 pkt_num:3;
125 u8 txdma_underflow:1;
126 u8 int_bt:1;
127 u8 int_tri:1;
128 u8 int_ccx:1;
129
130
131 u8 mac_id:6;
132 u8 pkt_ok:1;
133 u8 bmc:1;
134
135
136 u8 retry_cnt:6;
137 u8 lifetime_over:1;
138 u8 retry_over:1;
139
140
141 u8 ccx_qtime0;
142 u8 ccx_qtime1;
143
144
145 u8 final_data_rate;
146
147
148 u8 sw1:4;
149 u8 qsel:4;
150
151
152 u8 sw0;
153};
154
155#define txrpt_ccx_sw_88e(txrpt_ccx) ((txrpt_ccx)->sw0 + ((txrpt_ccx)->sw1<<8))
156#define txrpt_ccx_qtime_88e(txrpt_ccx) \
157 ((txrpt_ccx)->ccx_qtime0+((txrpt_ccx)->ccx_qtime1<<8))
158
159void rtl8188e_fill_fake_txdesc(struct adapter *padapter, u8 *pDesc,
160 u32 BufferLen, u8 IsPsPoll, u8 IsBTQosNull);
161s32 rtl8188eu_init_xmit_priv(struct adapter *padapter);
162s32 rtl8188eu_hal_xmit(struct adapter *padapter, struct xmit_frame *frame);
163s32 rtl8188eu_mgnt_xmit(struct adapter *padapter, struct xmit_frame *frame);
164s32 rtl8188eu_xmit_buf_handler(struct adapter *padapter);
165#define hal_xmit_handler rtl8188eu_xmit_buf_handler
166void rtl8188eu_xmit_tasklet(void *priv);
167s32 rtl8188eu_xmitframe_complete(struct adapter *padapter,
168 struct xmit_priv *pxmitpriv,
169 struct xmit_buf *pxmitbuf);
170
171void dump_txrpt_ccx_88e(void *buf);
172void handle_txrpt_ccx_88e(struct adapter *adapter, u8 *buf);
173
174void _dbg_dump_tx_info(struct adapter *padapter, int frame_tag,
175 struct tx_desc *ptxdesc);
176
177#endif
178