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17#if defined(CONFIG_SERIAL_XILINX_PS_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
18#define SUPPORT_SYSRQ
19#endif
20
21#include <linux/platform_device.h>
22#include <linux/serial.h>
23#include <linux/console.h>
24#include <linux/serial_core.h>
25#include <linux/slab.h>
26#include <linux/tty.h>
27#include <linux/tty_flip.h>
28#include <linux/clk.h>
29#include <linux/irq.h>
30#include <linux/io.h>
31#include <linux/of.h>
32#include <linux/module.h>
33
34#define CDNS_UART_TTY_NAME "ttyPS"
35#define CDNS_UART_NAME "xuartps"
36#define CDNS_UART_MAJOR 0
37#define CDNS_UART_MINOR 0
38#define CDNS_UART_NR_PORTS 2
39#define CDNS_UART_FIFO_SIZE 64
40#define CDNS_UART_REGISTER_SPACE 0x1000
41
42
43static int rx_trigger_level = 56;
44module_param(rx_trigger_level, uint, S_IRUGO);
45MODULE_PARM_DESC(rx_trigger_level, "Rx trigger level, 1-63 bytes");
46
47
48static int rx_timeout = 10;
49module_param(rx_timeout, uint, S_IRUGO);
50MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255");
51
52
53#define CDNS_UART_CR_OFFSET 0x00
54#define CDNS_UART_MR_OFFSET 0x04
55#define CDNS_UART_IER_OFFSET 0x08
56#define CDNS_UART_IDR_OFFSET 0x0C
57#define CDNS_UART_IMR_OFFSET 0x10
58#define CDNS_UART_ISR_OFFSET 0x14
59#define CDNS_UART_BAUDGEN_OFFSET 0x18
60#define CDNS_UART_RXTOUT_OFFSET 0x1C
61#define CDNS_UART_RXWM_OFFSET 0x20
62#define CDNS_UART_MODEMCR_OFFSET 0x24
63#define CDNS_UART_MODEMSR_OFFSET 0x28
64#define CDNS_UART_SR_OFFSET 0x2C
65#define CDNS_UART_FIFO_OFFSET 0x30
66#define CDNS_UART_BAUDDIV_OFFSET 0x34
67#define CDNS_UART_FLOWDEL_OFFSET 0x38
68#define CDNS_UART_IRRX_PWIDTH_OFFSET 0x3C
69#define CDNS_UART_IRTX_PWIDTH_OFFSET 0x40
70#define CDNS_UART_TXWM_OFFSET 0x44
71
72
73#define CDNS_UART_CR_STOPBRK 0x00000100
74#define CDNS_UART_CR_STARTBRK 0x00000080
75#define CDNS_UART_CR_TX_DIS 0x00000020
76#define CDNS_UART_CR_TX_EN 0x00000010
77#define CDNS_UART_CR_RX_DIS 0x00000008
78#define CDNS_UART_CR_RX_EN 0x00000004
79#define CDNS_UART_CR_TXRST 0x00000002
80#define CDNS_UART_CR_RXRST 0x00000001
81#define CDNS_UART_CR_RST_TO 0x00000040
82
83
84
85
86
87
88
89#define CDNS_UART_MR_CLKSEL 0x00000001
90#define CDNS_UART_MR_CHMODE_L_LOOP 0x00000200
91#define CDNS_UART_MR_CHMODE_NORM 0x00000000
92
93#define CDNS_UART_MR_STOPMODE_2_BIT 0x00000080
94#define CDNS_UART_MR_STOPMODE_1_BIT 0x00000000
95
96#define CDNS_UART_MR_PARITY_NONE 0x00000020
97#define CDNS_UART_MR_PARITY_MARK 0x00000018
98#define CDNS_UART_MR_PARITY_SPACE 0x00000010
99#define CDNS_UART_MR_PARITY_ODD 0x00000008
100#define CDNS_UART_MR_PARITY_EVEN 0x00000000
101
102#define CDNS_UART_MR_CHARLEN_6_BIT 0x00000006
103#define CDNS_UART_MR_CHARLEN_7_BIT 0x00000004
104#define CDNS_UART_MR_CHARLEN_8_BIT 0x00000000
105
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114
115
116
117#define CDNS_UART_IXR_TOUT 0x00000100
118#define CDNS_UART_IXR_PARITY 0x00000080
119#define CDNS_UART_IXR_FRAMING 0x00000040
120#define CDNS_UART_IXR_OVERRUN 0x00000020
121#define CDNS_UART_IXR_TXFULL 0x00000010
122#define CDNS_UART_IXR_TXEMPTY 0x00000008
123#define CDNS_UART_ISR_RXEMPTY 0x00000002
124#define CDNS_UART_IXR_RXTRIG 0x00000001
125#define CDNS_UART_IXR_RXFULL 0x00000004
126#define CDNS_UART_IXR_RXEMPTY 0x00000002
127#define CDNS_UART_IXR_MASK 0x00001FFF
128
129
130#define CDNS_UART_IXR_BRK 0x80000000
131
132
133
134
135
136
137#define CDNS_UART_MODEMCR_FCM 0x00000020
138#define CDNS_UART_MODEMCR_RTS 0x00000002
139#define CDNS_UART_MODEMCR_DTR 0x00000001
140
141
142
143
144
145
146
147#define CDNS_UART_SR_RXEMPTY 0x00000002
148#define CDNS_UART_SR_TXEMPTY 0x00000008
149#define CDNS_UART_SR_TXFULL 0x00000010
150#define CDNS_UART_SR_RXTRIG 0x00000001
151
152
153#define CDNS_UART_BDIV_MIN 4
154#define CDNS_UART_BDIV_MAX 255
155#define CDNS_UART_CD_MAX 65535
156
157
158
159
160
161
162
163
164
165struct cdns_uart {
166 struct uart_port *port;
167 struct clk *uartclk;
168 struct clk *pclk;
169 unsigned int baud;
170 struct notifier_block clk_rate_change_nb;
171};
172#define to_cdns_uart(_nb) container_of(_nb, struct cdns_uart, \
173 clk_rate_change_nb);
174
175
176
177
178
179
180
181
182static irqreturn_t cdns_uart_isr(int irq, void *dev_id)
183{
184 struct uart_port *port = (struct uart_port *)dev_id;
185 unsigned long flags;
186 unsigned int isrstatus, numbytes;
187 unsigned int data;
188 char status = TTY_NORMAL;
189
190 spin_lock_irqsave(&port->lock, flags);
191
192
193
194
195 isrstatus = readl(port->membase + CDNS_UART_ISR_OFFSET);
196
197
198
199
200
201
202 if (isrstatus & CDNS_UART_IXR_FRAMING) {
203 while (!(readl(port->membase + CDNS_UART_SR_OFFSET) &
204 CDNS_UART_SR_RXEMPTY)) {
205 if (!readl(port->membase + CDNS_UART_FIFO_OFFSET)) {
206 port->read_status_mask |= CDNS_UART_IXR_BRK;
207 isrstatus &= ~CDNS_UART_IXR_FRAMING;
208 }
209 }
210 writel(CDNS_UART_IXR_FRAMING,
211 port->membase + CDNS_UART_ISR_OFFSET);
212 }
213
214
215 if (isrstatus & port->ignore_status_mask & CDNS_UART_IXR_PARITY)
216 isrstatus &= ~(CDNS_UART_IXR_RXTRIG | CDNS_UART_IXR_TOUT);
217
218 isrstatus &= port->read_status_mask;
219 isrstatus &= ~port->ignore_status_mask;
220
221 if ((isrstatus & CDNS_UART_IXR_TOUT) ||
222 (isrstatus & CDNS_UART_IXR_RXTRIG)) {
223
224 while (!(readl(port->membase + CDNS_UART_SR_OFFSET) &
225 CDNS_UART_SR_RXEMPTY)) {
226 data = readl(port->membase + CDNS_UART_FIFO_OFFSET);
227
228
229 if (data && (port->read_status_mask &
230 CDNS_UART_IXR_BRK)) {
231 port->read_status_mask &= ~CDNS_UART_IXR_BRK;
232 port->icount.brk++;
233 if (uart_handle_break(port))
234 continue;
235 }
236
237#ifdef SUPPORT_SYSRQ
238
239
240
241
242 if (port->sysrq) {
243 spin_unlock(&port->lock);
244 if (uart_handle_sysrq_char(port,
245 (unsigned char)data)) {
246 spin_lock(&port->lock);
247 continue;
248 }
249 spin_lock(&port->lock);
250 }
251#endif
252
253 port->icount.rx++;
254
255 if (isrstatus & CDNS_UART_IXR_PARITY) {
256 port->icount.parity++;
257 status = TTY_PARITY;
258 } else if (isrstatus & CDNS_UART_IXR_FRAMING) {
259 port->icount.frame++;
260 status = TTY_FRAME;
261 } else if (isrstatus & CDNS_UART_IXR_OVERRUN) {
262 port->icount.overrun++;
263 }
264
265 uart_insert_char(port, isrstatus, CDNS_UART_IXR_OVERRUN,
266 data, status);
267 }
268 spin_unlock(&port->lock);
269 tty_flip_buffer_push(&port->state->port);
270 spin_lock(&port->lock);
271 }
272
273
274 if ((isrstatus & CDNS_UART_IXR_TXEMPTY) == CDNS_UART_IXR_TXEMPTY) {
275 if (uart_circ_empty(&port->state->xmit)) {
276 writel(CDNS_UART_IXR_TXEMPTY,
277 port->membase + CDNS_UART_IDR_OFFSET);
278 } else {
279 numbytes = port->fifosize;
280
281 while (numbytes--) {
282 if (uart_circ_empty(&port->state->xmit))
283 break;
284
285
286
287
288 writel(port->state->xmit.buf[
289 port->state->xmit.tail],
290 port->membase + CDNS_UART_FIFO_OFFSET);
291
292 port->icount.tx++;
293
294
295
296
297 port->state->xmit.tail =
298 (port->state->xmit.tail + 1) &
299 (UART_XMIT_SIZE - 1);
300 }
301
302 if (uart_circ_chars_pending(
303 &port->state->xmit) < WAKEUP_CHARS)
304 uart_write_wakeup(port);
305 }
306 }
307
308 writel(isrstatus, port->membase + CDNS_UART_ISR_OFFSET);
309
310
311 spin_unlock_irqrestore(&port->lock, flags);
312
313 return IRQ_HANDLED;
314}
315
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334
335
336static unsigned int cdns_uart_calc_baud_divs(unsigned int clk,
337 unsigned int baud, u32 *rbdiv, u32 *rcd, int *div8)
338{
339 u32 cd, bdiv;
340 unsigned int calc_baud;
341 unsigned int bestbaud = 0;
342 unsigned int bauderror;
343 unsigned int besterror = ~0;
344
345 if (baud < clk / ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX)) {
346 *div8 = 1;
347 clk /= 8;
348 } else {
349 *div8 = 0;
350 }
351
352 for (bdiv = CDNS_UART_BDIV_MIN; bdiv <= CDNS_UART_BDIV_MAX; bdiv++) {
353 cd = DIV_ROUND_CLOSEST(clk, baud * (bdiv + 1));
354 if (cd < 1 || cd > CDNS_UART_CD_MAX)
355 continue;
356
357 calc_baud = clk / (cd * (bdiv + 1));
358
359 if (baud > calc_baud)
360 bauderror = baud - calc_baud;
361 else
362 bauderror = calc_baud - baud;
363
364 if (besterror > bauderror) {
365 *rbdiv = bdiv;
366 *rcd = cd;
367 bestbaud = calc_baud;
368 besterror = bauderror;
369 }
370 }
371
372 if (((besterror * 100) / baud) < 3)
373 bestbaud = baud;
374
375 return bestbaud;
376}
377
378
379
380
381
382
383
384
385static unsigned int cdns_uart_set_baud_rate(struct uart_port *port,
386 unsigned int baud)
387{
388 unsigned int calc_baud;
389 u32 cd = 0, bdiv = 0;
390 u32 mreg;
391 int div8;
392 struct cdns_uart *cdns_uart = port->private_data;
393
394 calc_baud = cdns_uart_calc_baud_divs(port->uartclk, baud, &bdiv, &cd,
395 &div8);
396
397
398 mreg = readl(port->membase + CDNS_UART_MR_OFFSET);
399 if (div8)
400 mreg |= CDNS_UART_MR_CLKSEL;
401 else
402 mreg &= ~CDNS_UART_MR_CLKSEL;
403 writel(mreg, port->membase + CDNS_UART_MR_OFFSET);
404 writel(cd, port->membase + CDNS_UART_BAUDGEN_OFFSET);
405 writel(bdiv, port->membase + CDNS_UART_BAUDDIV_OFFSET);
406 cdns_uart->baud = baud;
407
408 return calc_baud;
409}
410
411#ifdef CONFIG_COMMON_CLK
412
413
414
415
416
417
418
419static int cdns_uart_clk_notifier_cb(struct notifier_block *nb,
420 unsigned long event, void *data)
421{
422 u32 ctrl_reg;
423 struct uart_port *port;
424 int locked = 0;
425 struct clk_notifier_data *ndata = data;
426 unsigned long flags = 0;
427 struct cdns_uart *cdns_uart = to_cdns_uart(nb);
428
429 port = cdns_uart->port;
430 if (port->suspended)
431 return NOTIFY_OK;
432
433 switch (event) {
434 case PRE_RATE_CHANGE:
435 {
436 u32 bdiv, cd;
437 int div8;
438
439
440
441
442
443 if (!cdns_uart_calc_baud_divs(ndata->new_rate, cdns_uart->baud,
444 &bdiv, &cd, &div8)) {
445 dev_warn(port->dev, "clock rate change rejected\n");
446 return NOTIFY_BAD;
447 }
448
449 spin_lock_irqsave(&cdns_uart->port->lock, flags);
450
451
452 ctrl_reg = readl(port->membase + CDNS_UART_CR_OFFSET);
453 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
454 writel(ctrl_reg, port->membase + CDNS_UART_CR_OFFSET);
455
456 spin_unlock_irqrestore(&cdns_uart->port->lock, flags);
457
458 return NOTIFY_OK;
459 }
460 case POST_RATE_CHANGE:
461
462
463
464
465
466 spin_lock_irqsave(&cdns_uart->port->lock, flags);
467
468 locked = 1;
469 port->uartclk = ndata->new_rate;
470
471 cdns_uart->baud = cdns_uart_set_baud_rate(cdns_uart->port,
472 cdns_uart->baud);
473
474 case ABORT_RATE_CHANGE:
475 if (!locked)
476 spin_lock_irqsave(&cdns_uart->port->lock, flags);
477
478
479 ctrl_reg = readl(port->membase + CDNS_UART_CR_OFFSET);
480 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
481 writel(ctrl_reg, port->membase + CDNS_UART_CR_OFFSET);
482
483 while (readl(port->membase + CDNS_UART_CR_OFFSET) &
484 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
485 cpu_relax();
486
487
488
489
490
491
492 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT_OFFSET);
493 ctrl_reg = readl(port->membase + CDNS_UART_CR_OFFSET);
494 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
495 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
496 writel(ctrl_reg, port->membase + CDNS_UART_CR_OFFSET);
497
498 spin_unlock_irqrestore(&cdns_uart->port->lock, flags);
499
500 return NOTIFY_OK;
501 default:
502 return NOTIFY_DONE;
503 }
504}
505#endif
506
507
508
509
510
511static void cdns_uart_start_tx(struct uart_port *port)
512{
513 unsigned int status, numbytes = port->fifosize;
514
515 if (uart_circ_empty(&port->state->xmit) || uart_tx_stopped(port))
516 return;
517
518 status = readl(port->membase + CDNS_UART_CR_OFFSET);
519
520
521
522 writel((status & ~CDNS_UART_CR_TX_DIS) | CDNS_UART_CR_TX_EN,
523 port->membase + CDNS_UART_CR_OFFSET);
524
525 while (numbytes-- && ((readl(port->membase + CDNS_UART_SR_OFFSET) &
526 CDNS_UART_SR_TXFULL)) != CDNS_UART_SR_TXFULL) {
527
528 if (uart_circ_empty(&port->state->xmit))
529 break;
530
531
532
533
534 writel(port->state->xmit.buf[port->state->xmit.tail],
535 port->membase + CDNS_UART_FIFO_OFFSET);
536 port->icount.tx++;
537
538
539
540
541 port->state->xmit.tail = (port->state->xmit.tail + 1) &
542 (UART_XMIT_SIZE - 1);
543 }
544 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_ISR_OFFSET);
545
546 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IER_OFFSET);
547
548 if (uart_circ_chars_pending(&port->state->xmit) < WAKEUP_CHARS)
549 uart_write_wakeup(port);
550}
551
552
553
554
555
556static void cdns_uart_stop_tx(struct uart_port *port)
557{
558 unsigned int regval;
559
560 regval = readl(port->membase + CDNS_UART_CR_OFFSET);
561 regval |= CDNS_UART_CR_TX_DIS;
562
563 writel(regval, port->membase + CDNS_UART_CR_OFFSET);
564}
565
566
567
568
569
570static void cdns_uart_stop_rx(struct uart_port *port)
571{
572 unsigned int regval;
573
574 regval = readl(port->membase + CDNS_UART_CR_OFFSET);
575 regval |= CDNS_UART_CR_RX_DIS;
576
577 writel(regval, port->membase + CDNS_UART_CR_OFFSET);
578}
579
580
581
582
583
584
585
586static unsigned int cdns_uart_tx_empty(struct uart_port *port)
587{
588 unsigned int status;
589
590 status = readl(port->membase + CDNS_UART_SR_OFFSET) &
591 CDNS_UART_SR_TXEMPTY;
592 return status ? TIOCSER_TEMT : 0;
593}
594
595
596
597
598
599
600
601static void cdns_uart_break_ctl(struct uart_port *port, int ctl)
602{
603 unsigned int status;
604 unsigned long flags;
605
606 spin_lock_irqsave(&port->lock, flags);
607
608 status = readl(port->membase + CDNS_UART_CR_OFFSET);
609
610 if (ctl == -1)
611 writel(CDNS_UART_CR_STARTBRK | status,
612 port->membase + CDNS_UART_CR_OFFSET);
613 else {
614 if ((status & CDNS_UART_CR_STOPBRK) == 0)
615 writel(CDNS_UART_CR_STOPBRK | status,
616 port->membase + CDNS_UART_CR_OFFSET);
617 }
618 spin_unlock_irqrestore(&port->lock, flags);
619}
620
621
622
623
624
625
626
627
628static void cdns_uart_set_termios(struct uart_port *port,
629 struct ktermios *termios, struct ktermios *old)
630{
631 unsigned int cval = 0;
632 unsigned int baud, minbaud, maxbaud;
633 unsigned long flags;
634 unsigned int ctrl_reg, mode_reg;
635
636 spin_lock_irqsave(&port->lock, flags);
637
638
639 if (!(readl(port->membase + CDNS_UART_CR_OFFSET) &
640 CDNS_UART_CR_TX_DIS)) {
641 while (!(readl(port->membase + CDNS_UART_SR_OFFSET) &
642 CDNS_UART_SR_TXEMPTY)) {
643 cpu_relax();
644 }
645 }
646
647
648 ctrl_reg = readl(port->membase + CDNS_UART_CR_OFFSET);
649 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
650 writel(ctrl_reg, port->membase + CDNS_UART_CR_OFFSET);
651
652
653
654
655
656
657 minbaud = port->uartclk /
658 ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX * 8);
659 maxbaud = port->uartclk / (CDNS_UART_BDIV_MIN + 1);
660 baud = uart_get_baud_rate(port, termios, old, minbaud, maxbaud);
661 baud = cdns_uart_set_baud_rate(port, baud);
662 if (tty_termios_baud_rate(termios))
663 tty_termios_encode_baud_rate(termios, baud, baud);
664
665
666 uart_update_timeout(port, termios->c_cflag, baud);
667
668
669 ctrl_reg = readl(port->membase + CDNS_UART_CR_OFFSET);
670 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
671 writel(ctrl_reg, port->membase + CDNS_UART_CR_OFFSET);
672
673
674
675
676
677 ctrl_reg = readl(port->membase + CDNS_UART_CR_OFFSET);
678 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
679 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
680 writel(ctrl_reg, port->membase + CDNS_UART_CR_OFFSET);
681
682 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT_OFFSET);
683
684 port->read_status_mask = CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_RXTRIG |
685 CDNS_UART_IXR_OVERRUN | CDNS_UART_IXR_TOUT;
686 port->ignore_status_mask = 0;
687
688 if (termios->c_iflag & INPCK)
689 port->read_status_mask |= CDNS_UART_IXR_PARITY |
690 CDNS_UART_IXR_FRAMING;
691
692 if (termios->c_iflag & IGNPAR)
693 port->ignore_status_mask |= CDNS_UART_IXR_PARITY |
694 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
695
696
697 if ((termios->c_cflag & CREAD) == 0)
698 port->ignore_status_mask |= CDNS_UART_IXR_RXTRIG |
699 CDNS_UART_IXR_TOUT | CDNS_UART_IXR_PARITY |
700 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
701
702 mode_reg = readl(port->membase + CDNS_UART_MR_OFFSET);
703
704
705 switch (termios->c_cflag & CSIZE) {
706 case CS6:
707 cval |= CDNS_UART_MR_CHARLEN_6_BIT;
708 break;
709 case CS7:
710 cval |= CDNS_UART_MR_CHARLEN_7_BIT;
711 break;
712 default:
713 case CS8:
714 cval |= CDNS_UART_MR_CHARLEN_8_BIT;
715 termios->c_cflag &= ~CSIZE;
716 termios->c_cflag |= CS8;
717 break;
718 }
719
720
721 if (termios->c_cflag & CSTOPB)
722 cval |= CDNS_UART_MR_STOPMODE_2_BIT;
723 else
724 cval |= CDNS_UART_MR_STOPMODE_1_BIT;
725
726 if (termios->c_cflag & PARENB) {
727
728 if (termios->c_cflag & CMSPAR) {
729 if (termios->c_cflag & PARODD)
730 cval |= CDNS_UART_MR_PARITY_MARK;
731 else
732 cval |= CDNS_UART_MR_PARITY_SPACE;
733 } else {
734 if (termios->c_cflag & PARODD)
735 cval |= CDNS_UART_MR_PARITY_ODD;
736 else
737 cval |= CDNS_UART_MR_PARITY_EVEN;
738 }
739 } else {
740 cval |= CDNS_UART_MR_PARITY_NONE;
741 }
742 cval |= mode_reg & 1;
743 writel(cval, port->membase + CDNS_UART_MR_OFFSET);
744
745 spin_unlock_irqrestore(&port->lock, flags);
746}
747
748
749
750
751
752
753
754static int cdns_uart_startup(struct uart_port *port)
755{
756 unsigned int retval = 0, status = 0;
757
758 retval = request_irq(port->irq, cdns_uart_isr, 0, CDNS_UART_NAME,
759 (void *)port);
760 if (retval)
761 return retval;
762
763
764 writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
765 port->membase + CDNS_UART_CR_OFFSET);
766
767
768
769
770 writel(CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST,
771 port->membase + CDNS_UART_CR_OFFSET);
772
773 status = readl(port->membase + CDNS_UART_CR_OFFSET);
774
775
776
777
778 writel((status & ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS))
779 | (CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN |
780 CDNS_UART_CR_STOPBRK),
781 port->membase + CDNS_UART_CR_OFFSET);
782
783
784
785
786 writel(CDNS_UART_MR_CHMODE_NORM | CDNS_UART_MR_STOPMODE_1_BIT
787 | CDNS_UART_MR_PARITY_NONE | CDNS_UART_MR_CHARLEN_8_BIT,
788 port->membase + CDNS_UART_MR_OFFSET);
789
790
791
792
793
794 writel(rx_trigger_level, port->membase + CDNS_UART_RXWM_OFFSET);
795
796
797
798
799
800 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT_OFFSET);
801
802
803 writel(readl(port->membase + CDNS_UART_ISR_OFFSET),
804 port->membase + CDNS_UART_ISR_OFFSET);
805
806
807 writel(CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_PARITY |
808 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN |
809 CDNS_UART_IXR_RXTRIG | CDNS_UART_IXR_TOUT,
810 port->membase + CDNS_UART_IER_OFFSET);
811
812 return retval;
813}
814
815
816
817
818
819static void cdns_uart_shutdown(struct uart_port *port)
820{
821 int status;
822
823
824 status = readl(port->membase + CDNS_UART_IMR_OFFSET);
825 writel(status, port->membase + CDNS_UART_IDR_OFFSET);
826
827
828 writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
829 port->membase + CDNS_UART_CR_OFFSET);
830 free_irq(port->irq, port);
831}
832
833
834
835
836
837
838
839static const char *cdns_uart_type(struct uart_port *port)
840{
841 return port->type == PORT_XUARTPS ? CDNS_UART_NAME : NULL;
842}
843
844
845
846
847
848
849
850
851static int cdns_uart_verify_port(struct uart_port *port,
852 struct serial_struct *ser)
853{
854 if (ser->type != PORT_UNKNOWN && ser->type != PORT_XUARTPS)
855 return -EINVAL;
856 if (port->irq != ser->irq)
857 return -EINVAL;
858 if (ser->io_type != UPIO_MEM)
859 return -EINVAL;
860 if (port->iobase != ser->port)
861 return -EINVAL;
862 if (ser->hub6 != 0)
863 return -EINVAL;
864 return 0;
865}
866
867
868
869
870
871
872
873
874
875static int cdns_uart_request_port(struct uart_port *port)
876{
877 if (!request_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE,
878 CDNS_UART_NAME)) {
879 return -ENOMEM;
880 }
881
882 port->membase = ioremap(port->mapbase, CDNS_UART_REGISTER_SPACE);
883 if (!port->membase) {
884 dev_err(port->dev, "Unable to map registers\n");
885 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE);
886 return -ENOMEM;
887 }
888 return 0;
889}
890
891
892
893
894
895
896
897
898static void cdns_uart_release_port(struct uart_port *port)
899{
900 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE);
901 iounmap(port->membase);
902 port->membase = NULL;
903}
904
905
906
907
908
909
910static void cdns_uart_config_port(struct uart_port *port, int flags)
911{
912 if (flags & UART_CONFIG_TYPE && cdns_uart_request_port(port) == 0)
913 port->type = PORT_XUARTPS;
914}
915
916
917
918
919
920
921
922static unsigned int cdns_uart_get_mctrl(struct uart_port *port)
923{
924 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
925}
926
927static void cdns_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
928{
929 u32 val;
930
931 val = readl(port->membase + CDNS_UART_MODEMCR_OFFSET);
932
933 val &= ~(CDNS_UART_MODEMCR_RTS | CDNS_UART_MODEMCR_DTR);
934
935 if (mctrl & TIOCM_RTS)
936 val |= CDNS_UART_MODEMCR_RTS;
937 if (mctrl & TIOCM_DTR)
938 val |= CDNS_UART_MODEMCR_DTR;
939
940 writel(val, port->membase + CDNS_UART_MODEMCR_OFFSET);
941}
942
943#ifdef CONFIG_CONSOLE_POLL
944static int cdns_uart_poll_get_char(struct uart_port *port)
945{
946 u32 imr;
947 int c;
948
949
950 imr = readl(port->membase + CDNS_UART_IMR_OFFSET);
951 writel(imr, port->membase + CDNS_UART_IDR_OFFSET);
952
953
954 if (readl(port->membase + CDNS_UART_SR_OFFSET) & CDNS_UART_SR_RXEMPTY)
955 c = NO_POLL_CHAR;
956 else
957 c = (unsigned char) readl(
958 port->membase + CDNS_UART_FIFO_OFFSET);
959
960
961 writel(imr, port->membase + CDNS_UART_IER_OFFSET);
962
963 return c;
964}
965
966static void cdns_uart_poll_put_char(struct uart_port *port, unsigned char c)
967{
968 u32 imr;
969
970
971 imr = readl(port->membase + CDNS_UART_IMR_OFFSET);
972 writel(imr, port->membase + CDNS_UART_IDR_OFFSET);
973
974
975 while (!(readl(port->membase + CDNS_UART_SR_OFFSET) &
976 CDNS_UART_SR_TXEMPTY))
977 cpu_relax();
978
979
980 writel(c, port->membase + CDNS_UART_FIFO_OFFSET);
981
982
983 while (!(readl(port->membase + CDNS_UART_SR_OFFSET) &
984 CDNS_UART_SR_TXEMPTY))
985 cpu_relax();
986
987
988 writel(imr, port->membase + CDNS_UART_IER_OFFSET);
989
990 return;
991}
992#endif
993
994static struct uart_ops cdns_uart_ops = {
995 .set_mctrl = cdns_uart_set_mctrl,
996 .get_mctrl = cdns_uart_get_mctrl,
997 .start_tx = cdns_uart_start_tx,
998 .stop_tx = cdns_uart_stop_tx,
999 .stop_rx = cdns_uart_stop_rx,
1000 .tx_empty = cdns_uart_tx_empty,
1001 .break_ctl = cdns_uart_break_ctl,
1002 .set_termios = cdns_uart_set_termios,
1003 .startup = cdns_uart_startup,
1004 .shutdown = cdns_uart_shutdown,
1005 .type = cdns_uart_type,
1006 .verify_port = cdns_uart_verify_port,
1007 .request_port = cdns_uart_request_port,
1008 .release_port = cdns_uart_release_port,
1009 .config_port = cdns_uart_config_port,
1010#ifdef CONFIG_CONSOLE_POLL
1011 .poll_get_char = cdns_uart_poll_get_char,
1012 .poll_put_char = cdns_uart_poll_put_char,
1013#endif
1014};
1015
1016static struct uart_port cdns_uart_port[CDNS_UART_NR_PORTS];
1017
1018
1019
1020
1021
1022
1023
1024static struct uart_port *cdns_uart_get_port(int id)
1025{
1026 struct uart_port *port;
1027
1028
1029 if (cdns_uart_port[id].mapbase != 0) {
1030
1031 for (id = 0; id < CDNS_UART_NR_PORTS; id++)
1032 if (cdns_uart_port[id].mapbase == 0)
1033 break;
1034 }
1035
1036 if (id >= CDNS_UART_NR_PORTS)
1037 return NULL;
1038
1039 port = &cdns_uart_port[id];
1040
1041
1042 spin_lock_init(&port->lock);
1043 port->membase = NULL;
1044 port->irq = 0;
1045 port->type = PORT_UNKNOWN;
1046 port->iotype = UPIO_MEM32;
1047 port->flags = UPF_BOOT_AUTOCONF;
1048 port->ops = &cdns_uart_ops;
1049 port->fifosize = CDNS_UART_FIFO_SIZE;
1050 port->line = id;
1051 port->dev = NULL;
1052 return port;
1053}
1054
1055#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1056
1057
1058
1059
1060static void cdns_uart_console_wait_tx(struct uart_port *port)
1061{
1062 while (!(readl(port->membase + CDNS_UART_SR_OFFSET) &
1063 CDNS_UART_SR_TXEMPTY))
1064 barrier();
1065}
1066
1067
1068
1069
1070
1071
1072static void cdns_uart_console_putchar(struct uart_port *port, int ch)
1073{
1074 cdns_uart_console_wait_tx(port);
1075 writel(ch, port->membase + CDNS_UART_FIFO_OFFSET);
1076}
1077
1078static void __init cdns_early_write(struct console *con, const char *s,
1079 unsigned n)
1080{
1081 struct earlycon_device *dev = con->data;
1082
1083 uart_console_write(&dev->port, s, n, cdns_uart_console_putchar);
1084}
1085
1086static int __init cdns_early_console_setup(struct earlycon_device *device,
1087 const char *opt)
1088{
1089 if (!device->port.membase)
1090 return -ENODEV;
1091
1092 device->con->write = cdns_early_write;
1093
1094 return 0;
1095}
1096EARLYCON_DECLARE(cdns, cdns_early_console_setup);
1097
1098
1099
1100
1101
1102
1103
1104static void cdns_uart_console_write(struct console *co, const char *s,
1105 unsigned int count)
1106{
1107 struct uart_port *port = &cdns_uart_port[co->index];
1108 unsigned long flags;
1109 unsigned int imr, ctrl;
1110 int locked = 1;
1111
1112 if (oops_in_progress)
1113 locked = spin_trylock_irqsave(&port->lock, flags);
1114 else
1115 spin_lock_irqsave(&port->lock, flags);
1116
1117
1118 imr = readl(port->membase + CDNS_UART_IMR_OFFSET);
1119 writel(imr, port->membase + CDNS_UART_IDR_OFFSET);
1120
1121
1122
1123
1124
1125 ctrl = readl(port->membase + CDNS_UART_CR_OFFSET);
1126 writel((ctrl & ~CDNS_UART_CR_TX_DIS) | CDNS_UART_CR_TX_EN,
1127 port->membase + CDNS_UART_CR_OFFSET);
1128
1129 uart_console_write(port, s, count, cdns_uart_console_putchar);
1130 cdns_uart_console_wait_tx(port);
1131
1132 writel(ctrl, port->membase + CDNS_UART_CR_OFFSET);
1133
1134
1135 writel(imr, port->membase + CDNS_UART_IER_OFFSET);
1136
1137 if (locked)
1138 spin_unlock_irqrestore(&port->lock, flags);
1139}
1140
1141
1142
1143
1144
1145
1146
1147
1148static int __init cdns_uart_console_setup(struct console *co, char *options)
1149{
1150 struct uart_port *port = &cdns_uart_port[co->index];
1151 int baud = 9600;
1152 int bits = 8;
1153 int parity = 'n';
1154 int flow = 'n';
1155
1156 if (co->index < 0 || co->index >= CDNS_UART_NR_PORTS)
1157 return -EINVAL;
1158
1159 if (!port->membase) {
1160 pr_debug("console on " CDNS_UART_TTY_NAME "%i not present\n",
1161 co->index);
1162 return -ENODEV;
1163 }
1164
1165 if (options)
1166 uart_parse_options(options, &baud, &parity, &bits, &flow);
1167
1168 return uart_set_options(port, co, baud, parity, bits, flow);
1169}
1170
1171static struct uart_driver cdns_uart_uart_driver;
1172
1173static struct console cdns_uart_console = {
1174 .name = CDNS_UART_TTY_NAME,
1175 .write = cdns_uart_console_write,
1176 .device = uart_console_device,
1177 .setup = cdns_uart_console_setup,
1178 .flags = CON_PRINTBUFFER,
1179 .index = -1,
1180 .data = &cdns_uart_uart_driver,
1181};
1182
1183
1184
1185
1186
1187
1188static int __init cdns_uart_console_init(void)
1189{
1190 register_console(&cdns_uart_console);
1191 return 0;
1192}
1193
1194console_initcall(cdns_uart_console_init);
1195
1196#endif
1197
1198static struct uart_driver cdns_uart_uart_driver = {
1199 .owner = THIS_MODULE,
1200 .driver_name = CDNS_UART_NAME,
1201 .dev_name = CDNS_UART_TTY_NAME,
1202 .major = CDNS_UART_MAJOR,
1203 .minor = CDNS_UART_MINOR,
1204 .nr = CDNS_UART_NR_PORTS,
1205#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1206 .cons = &cdns_uart_console,
1207#endif
1208};
1209
1210#ifdef CONFIG_PM_SLEEP
1211
1212
1213
1214
1215
1216
1217static int cdns_uart_suspend(struct device *device)
1218{
1219 struct uart_port *port = dev_get_drvdata(device);
1220 struct tty_struct *tty;
1221 struct device *tty_dev;
1222 int may_wake = 0;
1223
1224
1225 tty = tty_port_tty_get(&port->state->port);
1226 if (tty) {
1227 tty_dev = tty->dev;
1228 may_wake = device_may_wakeup(tty_dev);
1229 tty_kref_put(tty);
1230 }
1231
1232
1233
1234
1235
1236 uart_suspend_port(&cdns_uart_uart_driver, port);
1237 if (console_suspend_enabled && !may_wake) {
1238 struct cdns_uart *cdns_uart = port->private_data;
1239
1240 clk_disable(cdns_uart->uartclk);
1241 clk_disable(cdns_uart->pclk);
1242 } else {
1243 unsigned long flags = 0;
1244
1245 spin_lock_irqsave(&port->lock, flags);
1246
1247 while (!(readl(port->membase + CDNS_UART_SR_OFFSET) &
1248 CDNS_UART_SR_RXEMPTY))
1249 readl(port->membase + CDNS_UART_FIFO_OFFSET);
1250
1251 writel(1, port->membase + CDNS_UART_RXWM_OFFSET);
1252
1253 writel(CDNS_UART_IXR_TOUT,
1254 port->membase + CDNS_UART_IDR_OFFSET);
1255 spin_unlock_irqrestore(&port->lock, flags);
1256 }
1257
1258 return 0;
1259}
1260
1261
1262
1263
1264
1265
1266
1267static int cdns_uart_resume(struct device *device)
1268{
1269 struct uart_port *port = dev_get_drvdata(device);
1270 unsigned long flags = 0;
1271 u32 ctrl_reg;
1272 struct tty_struct *tty;
1273 struct device *tty_dev;
1274 int may_wake = 0;
1275
1276
1277 tty = tty_port_tty_get(&port->state->port);
1278 if (tty) {
1279 tty_dev = tty->dev;
1280 may_wake = device_may_wakeup(tty_dev);
1281 tty_kref_put(tty);
1282 }
1283
1284 if (console_suspend_enabled && !may_wake) {
1285 struct cdns_uart *cdns_uart = port->private_data;
1286
1287 clk_enable(cdns_uart->pclk);
1288 clk_enable(cdns_uart->uartclk);
1289
1290 spin_lock_irqsave(&port->lock, flags);
1291
1292
1293 ctrl_reg = readl(port->membase + CDNS_UART_CR_OFFSET);
1294 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
1295 writel(ctrl_reg, port->membase + CDNS_UART_CR_OFFSET);
1296 while (readl(port->membase + CDNS_UART_CR_OFFSET) &
1297 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
1298 cpu_relax();
1299
1300
1301 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT_OFFSET);
1302
1303 ctrl_reg = readl(port->membase + CDNS_UART_CR_OFFSET);
1304 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
1305 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
1306 writel(ctrl_reg, port->membase + CDNS_UART_CR_OFFSET);
1307
1308 spin_unlock_irqrestore(&port->lock, flags);
1309 } else {
1310 spin_lock_irqsave(&port->lock, flags);
1311
1312 writel(rx_trigger_level,
1313 port->membase + CDNS_UART_RXWM_OFFSET);
1314
1315 writel(CDNS_UART_IXR_TOUT,
1316 port->membase + CDNS_UART_IER_OFFSET);
1317 spin_unlock_irqrestore(&port->lock, flags);
1318 }
1319
1320 return uart_resume_port(&cdns_uart_uart_driver, port);
1321}
1322#endif
1323
1324static SIMPLE_DEV_PM_OPS(cdns_uart_dev_pm_ops, cdns_uart_suspend,
1325 cdns_uart_resume);
1326
1327
1328
1329
1330
1331
1332
1333static int cdns_uart_probe(struct platform_device *pdev)
1334{
1335 int rc, id, irq;
1336 struct uart_port *port;
1337 struct resource *res;
1338 struct cdns_uart *cdns_uart_data;
1339
1340 cdns_uart_data = devm_kzalloc(&pdev->dev, sizeof(*cdns_uart_data),
1341 GFP_KERNEL);
1342 if (!cdns_uart_data)
1343 return -ENOMEM;
1344
1345 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "pclk");
1346 if (IS_ERR(cdns_uart_data->pclk)) {
1347 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "aper_clk");
1348 if (!IS_ERR(cdns_uart_data->pclk))
1349 dev_err(&pdev->dev, "clock name 'aper_clk' is deprecated.\n");
1350 }
1351 if (IS_ERR(cdns_uart_data->pclk)) {
1352 dev_err(&pdev->dev, "pclk clock not found.\n");
1353 return PTR_ERR(cdns_uart_data->pclk);
1354 }
1355
1356 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "uart_clk");
1357 if (IS_ERR(cdns_uart_data->uartclk)) {
1358 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "ref_clk");
1359 if (!IS_ERR(cdns_uart_data->uartclk))
1360 dev_err(&pdev->dev, "clock name 'ref_clk' is deprecated.\n");
1361 }
1362 if (IS_ERR(cdns_uart_data->uartclk)) {
1363 dev_err(&pdev->dev, "uart_clk clock not found.\n");
1364 return PTR_ERR(cdns_uart_data->uartclk);
1365 }
1366
1367 rc = clk_prepare_enable(cdns_uart_data->pclk);
1368 if (rc) {
1369 dev_err(&pdev->dev, "Unable to enable pclk clock.\n");
1370 return rc;
1371 }
1372 rc = clk_prepare_enable(cdns_uart_data->uartclk);
1373 if (rc) {
1374 dev_err(&pdev->dev, "Unable to enable device clock.\n");
1375 goto err_out_clk_dis_pclk;
1376 }
1377
1378 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1379 if (!res) {
1380 rc = -ENODEV;
1381 goto err_out_clk_disable;
1382 }
1383
1384 irq = platform_get_irq(pdev, 0);
1385 if (irq <= 0) {
1386 rc = -ENXIO;
1387 goto err_out_clk_disable;
1388 }
1389
1390#ifdef CONFIG_COMMON_CLK
1391 cdns_uart_data->clk_rate_change_nb.notifier_call =
1392 cdns_uart_clk_notifier_cb;
1393 if (clk_notifier_register(cdns_uart_data->uartclk,
1394 &cdns_uart_data->clk_rate_change_nb))
1395 dev_warn(&pdev->dev, "Unable to register clock notifier.\n");
1396#endif
1397
1398 id = of_alias_get_id(pdev->dev.of_node, "serial");
1399 if (id < 0)
1400 id = 0;
1401
1402
1403 port = cdns_uart_get_port(id);
1404
1405 if (!port) {
1406 dev_err(&pdev->dev, "Cannot get uart_port structure\n");
1407 rc = -ENODEV;
1408 goto err_out_notif_unreg;
1409 } else {
1410
1411
1412
1413
1414 port->mapbase = res->start;
1415 port->irq = irq;
1416 port->dev = &pdev->dev;
1417 port->uartclk = clk_get_rate(cdns_uart_data->uartclk);
1418 port->private_data = cdns_uart_data;
1419 cdns_uart_data->port = port;
1420 platform_set_drvdata(pdev, port);
1421 rc = uart_add_one_port(&cdns_uart_uart_driver, port);
1422 if (rc) {
1423 dev_err(&pdev->dev,
1424 "uart_add_one_port() failed; err=%i\n", rc);
1425 goto err_out_notif_unreg;
1426 }
1427 return 0;
1428 }
1429
1430err_out_notif_unreg:
1431#ifdef CONFIG_COMMON_CLK
1432 clk_notifier_unregister(cdns_uart_data->uartclk,
1433 &cdns_uart_data->clk_rate_change_nb);
1434#endif
1435err_out_clk_disable:
1436 clk_disable_unprepare(cdns_uart_data->uartclk);
1437err_out_clk_dis_pclk:
1438 clk_disable_unprepare(cdns_uart_data->pclk);
1439
1440 return rc;
1441}
1442
1443
1444
1445
1446
1447
1448
1449static int cdns_uart_remove(struct platform_device *pdev)
1450{
1451 struct uart_port *port = platform_get_drvdata(pdev);
1452 struct cdns_uart *cdns_uart_data = port->private_data;
1453 int rc;
1454
1455
1456#ifdef CONFIG_COMMON_CLK
1457 clk_notifier_unregister(cdns_uart_data->uartclk,
1458 &cdns_uart_data->clk_rate_change_nb);
1459#endif
1460 rc = uart_remove_one_port(&cdns_uart_uart_driver, port);
1461 port->mapbase = 0;
1462 clk_disable_unprepare(cdns_uart_data->uartclk);
1463 clk_disable_unprepare(cdns_uart_data->pclk);
1464 return rc;
1465}
1466
1467
1468static const struct of_device_id cdns_uart_of_match[] = {
1469 { .compatible = "xlnx,xuartps", },
1470 { .compatible = "cdns,uart-r1p8", },
1471 {}
1472};
1473MODULE_DEVICE_TABLE(of, cdns_uart_of_match);
1474
1475static struct platform_driver cdns_uart_platform_driver = {
1476 .probe = cdns_uart_probe,
1477 .remove = cdns_uart_remove,
1478 .driver = {
1479 .name = CDNS_UART_NAME,
1480 .of_match_table = cdns_uart_of_match,
1481 .pm = &cdns_uart_dev_pm_ops,
1482 },
1483};
1484
1485static int __init cdns_uart_init(void)
1486{
1487 int retval = 0;
1488
1489
1490 retval = uart_register_driver(&cdns_uart_uart_driver);
1491 if (retval)
1492 return retval;
1493
1494
1495 retval = platform_driver_register(&cdns_uart_platform_driver);
1496 if (retval)
1497 uart_unregister_driver(&cdns_uart_uart_driver);
1498
1499 return retval;
1500}
1501
1502static void __exit cdns_uart_exit(void)
1503{
1504
1505 platform_driver_unregister(&cdns_uart_platform_driver);
1506
1507
1508 uart_unregister_driver(&cdns_uart_uart_driver);
1509}
1510
1511module_init(cdns_uart_init);
1512module_exit(cdns_uart_exit);
1513
1514MODULE_DESCRIPTION("Driver for Cadence UART");
1515MODULE_AUTHOR("Xilinx Inc.");
1516MODULE_LICENSE("GPL");
1517