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35#include <linux/module.h>
36#include <linux/moduleparam.h>
37#include <linux/kernel.h>
38#include <linux/sched.h>
39#include <linux/errno.h>
40#include <linux/string.h>
41#include <linux/interrupt.h>
42#include <linux/slab.h>
43#include <linux/mm.h>
44#include <linux/fb.h>
45#include <linux/delay.h>
46#include <linux/init.h>
47#include <linux/ioport.h>
48#include <linux/cpufreq.h>
49#include <linux/platform_device.h>
50#include <linux/dma-mapping.h>
51#include <linux/clk.h>
52#include <linux/err.h>
53#include <linux/completion.h>
54#include <linux/mutex.h>
55#include <linux/kthread.h>
56#include <linux/freezer.h>
57#include <linux/console.h>
58#include <linux/of_graph.h>
59#include <video/of_display_timing.h>
60#include <video/videomode.h>
61
62#include <mach/hardware.h>
63#include <asm/io.h>
64#include <asm/irq.h>
65#include <asm/div64.h>
66#include <mach/bitfield.h>
67#include <linux/platform_data/video-pxafb.h>
68
69
70
71
72#define DEBUG_VAR 1
73
74#include "pxafb.h"
75
76
77#define LCCR0_INVALID_CONFIG_MASK (LCCR0_OUM | LCCR0_BM | LCCR0_QDM |\
78 LCCR0_DIS | LCCR0_EFM | LCCR0_IUM |\
79 LCCR0_SFM | LCCR0_LDM | LCCR0_ENB)
80
81#define LCCR3_INVALID_CONFIG_MASK (LCCR3_HSP | LCCR3_VSP |\
82 LCCR3_PCD | LCCR3_BPP(0xf))
83
84static int pxafb_activate_var(struct fb_var_screeninfo *var,
85 struct pxafb_info *);
86static void set_ctrlr_state(struct pxafb_info *fbi, u_int state);
87static void setup_base_frame(struct pxafb_info *fbi,
88 struct fb_var_screeninfo *var, int branch);
89static int setup_frame_dma(struct pxafb_info *fbi, int dma, int pal,
90 unsigned long offset, size_t size);
91
92static unsigned long video_mem_size = 0;
93
94static inline unsigned long
95lcd_readl(struct pxafb_info *fbi, unsigned int off)
96{
97 return __raw_readl(fbi->mmio_base + off);
98}
99
100static inline void
101lcd_writel(struct pxafb_info *fbi, unsigned int off, unsigned long val)
102{
103 __raw_writel(val, fbi->mmio_base + off);
104}
105
106static inline void pxafb_schedule_work(struct pxafb_info *fbi, u_int state)
107{
108 unsigned long flags;
109
110 local_irq_save(flags);
111
112
113
114
115
116
117
118
119
120
121 if (fbi->task_state == C_ENABLE && state == C_REENABLE)
122 state = (u_int) -1;
123 if (fbi->task_state == C_DISABLE && state == C_ENABLE)
124 state = C_REENABLE;
125
126 if (state != (u_int)-1) {
127 fbi->task_state = state;
128 schedule_work(&fbi->task);
129 }
130 local_irq_restore(flags);
131}
132
133static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
134{
135 chan &= 0xffff;
136 chan >>= 16 - bf->length;
137 return chan << bf->offset;
138}
139
140static int
141pxafb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
142 u_int trans, struct fb_info *info)
143{
144 struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
145 u_int val;
146
147 if (regno >= fbi->palette_size)
148 return 1;
149
150 if (fbi->fb.var.grayscale) {
151 fbi->palette_cpu[regno] = ((blue >> 8) & 0x00ff);
152 return 0;
153 }
154
155 switch (fbi->lccr4 & LCCR4_PAL_FOR_MASK) {
156 case LCCR4_PAL_FOR_0:
157 val = ((red >> 0) & 0xf800);
158 val |= ((green >> 5) & 0x07e0);
159 val |= ((blue >> 11) & 0x001f);
160 fbi->palette_cpu[regno] = val;
161 break;
162 case LCCR4_PAL_FOR_1:
163 val = ((red << 8) & 0x00f80000);
164 val |= ((green >> 0) & 0x0000fc00);
165 val |= ((blue >> 8) & 0x000000f8);
166 ((u32 *)(fbi->palette_cpu))[regno] = val;
167 break;
168 case LCCR4_PAL_FOR_2:
169 val = ((red << 8) & 0x00fc0000);
170 val |= ((green >> 0) & 0x0000fc00);
171 val |= ((blue >> 8) & 0x000000fc);
172 ((u32 *)(fbi->palette_cpu))[regno] = val;
173 break;
174 case LCCR4_PAL_FOR_3:
175 val = ((red << 8) & 0x00ff0000);
176 val |= ((green >> 0) & 0x0000ff00);
177 val |= ((blue >> 8) & 0x000000ff);
178 ((u32 *)(fbi->palette_cpu))[regno] = val;
179 break;
180 }
181
182 return 0;
183}
184
185static int
186pxafb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
187 u_int trans, struct fb_info *info)
188{
189 struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
190 unsigned int val;
191 int ret = 1;
192
193
194
195
196
197
198
199 if (fbi->cmap_inverse) {
200 red = 0xffff - red;
201 green = 0xffff - green;
202 blue = 0xffff - blue;
203 }
204
205
206
207
208
209 if (fbi->fb.var.grayscale)
210 red = green = blue = (19595 * red + 38470 * green +
211 7471 * blue) >> 16;
212
213 switch (fbi->fb.fix.visual) {
214 case FB_VISUAL_TRUECOLOR:
215
216
217
218
219 if (regno < 16) {
220 u32 *pal = fbi->fb.pseudo_palette;
221
222 val = chan_to_field(red, &fbi->fb.var.red);
223 val |= chan_to_field(green, &fbi->fb.var.green);
224 val |= chan_to_field(blue, &fbi->fb.var.blue);
225
226 pal[regno] = val;
227 ret = 0;
228 }
229 break;
230
231 case FB_VISUAL_STATIC_PSEUDOCOLOR:
232 case FB_VISUAL_PSEUDOCOLOR:
233 ret = pxafb_setpalettereg(regno, red, green, blue, trans, info);
234 break;
235 }
236
237 return ret;
238}
239
240
241static inline int var_to_depth(struct fb_var_screeninfo *var)
242{
243 return var->red.length + var->green.length +
244 var->blue.length + var->transp.length;
245}
246
247
248static int pxafb_var_to_bpp(struct fb_var_screeninfo *var)
249{
250 int bpp = -EINVAL;
251
252 switch (var->bits_per_pixel) {
253 case 1: bpp = 0; break;
254 case 2: bpp = 1; break;
255 case 4: bpp = 2; break;
256 case 8: bpp = 3; break;
257 case 16: bpp = 4; break;
258 case 24:
259 switch (var_to_depth(var)) {
260 case 18: bpp = 6; break;
261 case 19: bpp = 8; break;
262 case 24: bpp = 9; break;
263 }
264 break;
265 case 32:
266 switch (var_to_depth(var)) {
267 case 18: bpp = 5; break;
268 case 19: bpp = 7; break;
269 case 25: bpp = 10; break;
270 }
271 break;
272 }
273 return bpp;
274}
275
276
277
278
279
280
281
282
283
284
285
286
287static uint32_t pxafb_var_to_lccr3(struct fb_var_screeninfo *var)
288{
289 int bpp = pxafb_var_to_bpp(var);
290 uint32_t lccr3;
291
292 if (bpp < 0)
293 return 0;
294
295 lccr3 = LCCR3_BPP(bpp);
296
297 switch (var_to_depth(var)) {
298 case 16: lccr3 |= var->transp.length ? LCCR3_PDFOR_3 : 0; break;
299 case 18: lccr3 |= LCCR3_PDFOR_3; break;
300 case 24: lccr3 |= var->transp.length ? LCCR3_PDFOR_2 : LCCR3_PDFOR_3;
301 break;
302 case 19:
303 case 25: lccr3 |= LCCR3_PDFOR_0; break;
304 }
305 return lccr3;
306}
307
308#define SET_PIXFMT(v, r, g, b, t) \
309({ \
310 (v)->transp.offset = (t) ? (r) + (g) + (b) : 0; \
311 (v)->transp.length = (t) ? (t) : 0; \
312 (v)->blue.length = (b); (v)->blue.offset = 0; \
313 (v)->green.length = (g); (v)->green.offset = (b); \
314 (v)->red.length = (r); (v)->red.offset = (b) + (g); \
315})
316
317
318
319
320static void pxafb_set_pixfmt(struct fb_var_screeninfo *var, int depth)
321{
322 if (depth == 0)
323 depth = var->bits_per_pixel;
324
325 if (var->bits_per_pixel < 16) {
326
327 var->red.offset = 0; var->red.length = 8;
328 var->green.offset = 0; var->green.length = 8;
329 var->blue.offset = 0; var->blue.length = 8;
330 var->transp.offset = 0; var->transp.length = 8;
331 }
332
333 switch (depth) {
334 case 16: var->transp.length ?
335 SET_PIXFMT(var, 5, 5, 5, 1) :
336 SET_PIXFMT(var, 5, 6, 5, 0); break;
337 case 18: SET_PIXFMT(var, 6, 6, 6, 0); break;
338 case 19: SET_PIXFMT(var, 6, 6, 6, 1); break;
339 case 24: var->transp.length ?
340 SET_PIXFMT(var, 8, 8, 7, 1) :
341 SET_PIXFMT(var, 8, 8, 8, 0); break;
342 case 25: SET_PIXFMT(var, 8, 8, 8, 1); break;
343 }
344}
345
346#ifdef CONFIG_CPU_FREQ
347
348
349
350
351
352
353static unsigned int pxafb_display_dma_period(struct fb_var_screeninfo *var)
354{
355
356
357
358
359 return var->pixclock * 8 * 16 / var->bits_per_pixel;
360}
361#endif
362
363
364
365
366
367static struct pxafb_mode_info *pxafb_getmode(struct pxafb_mach_info *mach,
368 struct fb_var_screeninfo *var)
369{
370 struct pxafb_mode_info *mode = NULL;
371 struct pxafb_mode_info *modelist = mach->modes;
372 unsigned int best_x = 0xffffffff, best_y = 0xffffffff;
373 unsigned int i;
374
375 for (i = 0; i < mach->num_modes; i++) {
376 if (modelist[i].xres >= var->xres &&
377 modelist[i].yres >= var->yres &&
378 modelist[i].xres < best_x &&
379 modelist[i].yres < best_y &&
380 modelist[i].bpp >= var->bits_per_pixel) {
381 best_x = modelist[i].xres;
382 best_y = modelist[i].yres;
383 mode = &modelist[i];
384 }
385 }
386
387 return mode;
388}
389
390static void pxafb_setmode(struct fb_var_screeninfo *var,
391 struct pxafb_mode_info *mode)
392{
393 var->xres = mode->xres;
394 var->yres = mode->yres;
395 var->bits_per_pixel = mode->bpp;
396 var->pixclock = mode->pixclock;
397 var->hsync_len = mode->hsync_len;
398 var->left_margin = mode->left_margin;
399 var->right_margin = mode->right_margin;
400 var->vsync_len = mode->vsync_len;
401 var->upper_margin = mode->upper_margin;
402 var->lower_margin = mode->lower_margin;
403 var->sync = mode->sync;
404 var->grayscale = mode->cmap_greyscale;
405 var->transp.length = mode->transparency;
406
407
408 pxafb_set_pixfmt(var, mode->depth);
409}
410
411static int pxafb_adjust_timing(struct pxafb_info *fbi,
412 struct fb_var_screeninfo *var)
413{
414 int line_length;
415
416 var->xres = max_t(int, var->xres, MIN_XRES);
417 var->yres = max_t(int, var->yres, MIN_YRES);
418
419 if (!(fbi->lccr0 & LCCR0_LCDT)) {
420 clamp_val(var->hsync_len, 1, 64);
421 clamp_val(var->vsync_len, 1, 64);
422 clamp_val(var->left_margin, 1, 255);
423 clamp_val(var->right_margin, 1, 255);
424 clamp_val(var->upper_margin, 1, 255);
425 clamp_val(var->lower_margin, 1, 255);
426 }
427
428
429 line_length = var->xres * var->bits_per_pixel / 8;
430 line_length = ALIGN(line_length, 4);
431 var->xres = line_length * 8 / var->bits_per_pixel;
432
433
434 var->xres_virtual = var->xres;
435
436 if (var->accel_flags & FB_ACCELF_TEXT)
437 var->yres_virtual = fbi->fb.fix.smem_len / line_length;
438 else
439 var->yres_virtual = max(var->yres_virtual, var->yres);
440
441
442 if (var->xres > MAX_XRES || var->yres > MAX_YRES)
443 return -EINVAL;
444
445 if (var->yres > var->yres_virtual)
446 return -EINVAL;
447
448 return 0;
449}
450
451
452
453
454
455
456
457
458
459
460static int pxafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
461{
462 struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
463 struct pxafb_mach_info *inf = fbi->inf;
464 int err;
465
466 if (inf->fixed_modes) {
467 struct pxafb_mode_info *mode;
468
469 mode = pxafb_getmode(inf, var);
470 if (!mode)
471 return -EINVAL;
472 pxafb_setmode(var, mode);
473 }
474
475
476 err = pxafb_var_to_bpp(var);
477 if (err < 0)
478 return err;
479
480 pxafb_set_pixfmt(var, var_to_depth(var));
481
482 err = pxafb_adjust_timing(fbi, var);
483 if (err)
484 return err;
485
486#ifdef CONFIG_CPU_FREQ
487 pr_debug("pxafb: dma period = %d ps\n",
488 pxafb_display_dma_period(var));
489#endif
490
491 return 0;
492}
493
494
495
496
497
498static int pxafb_set_par(struct fb_info *info)
499{
500 struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
501 struct fb_var_screeninfo *var = &info->var;
502
503 if (var->bits_per_pixel >= 16)
504 fbi->fb.fix.visual = FB_VISUAL_TRUECOLOR;
505 else if (!fbi->cmap_static)
506 fbi->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
507 else {
508
509
510
511
512
513 fbi->fb.fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR;
514 }
515
516 fbi->fb.fix.line_length = var->xres_virtual *
517 var->bits_per_pixel / 8;
518 if (var->bits_per_pixel >= 16)
519 fbi->palette_size = 0;
520 else
521 fbi->palette_size = var->bits_per_pixel == 1 ?
522 4 : 1 << var->bits_per_pixel;
523
524 fbi->palette_cpu = (u16 *)&fbi->dma_buff->palette[0];
525
526 if (fbi->fb.var.bits_per_pixel >= 16)
527 fb_dealloc_cmap(&fbi->fb.cmap);
528 else
529 fb_alloc_cmap(&fbi->fb.cmap, 1<<fbi->fb.var.bits_per_pixel, 0);
530
531 pxafb_activate_var(var, fbi);
532
533 return 0;
534}
535
536static int pxafb_pan_display(struct fb_var_screeninfo *var,
537 struct fb_info *info)
538{
539 struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
540 struct fb_var_screeninfo newvar;
541 int dma = DMA_MAX + DMA_BASE;
542
543 if (fbi->state != C_ENABLE)
544 return 0;
545
546
547
548
549 memcpy(&newvar, &fbi->fb.var, sizeof(newvar));
550 newvar.xoffset = var->xoffset;
551 newvar.yoffset = var->yoffset;
552 newvar.vmode &= ~FB_VMODE_YWRAP;
553 newvar.vmode |= var->vmode & FB_VMODE_YWRAP;
554
555 setup_base_frame(fbi, &newvar, 1);
556
557 if (fbi->lccr0 & LCCR0_SDS)
558 lcd_writel(fbi, FBR1, fbi->fdadr[dma + 1] | 0x1);
559
560 lcd_writel(fbi, FBR0, fbi->fdadr[dma] | 0x1);
561 return 0;
562}
563
564
565
566
567
568
569
570static int pxafb_blank(int blank, struct fb_info *info)
571{
572 struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
573 int i;
574
575 switch (blank) {
576 case FB_BLANK_POWERDOWN:
577 case FB_BLANK_VSYNC_SUSPEND:
578 case FB_BLANK_HSYNC_SUSPEND:
579 case FB_BLANK_NORMAL:
580 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
581 fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
582 for (i = 0; i < fbi->palette_size; i++)
583 pxafb_setpalettereg(i, 0, 0, 0, 0, info);
584
585 pxafb_schedule_work(fbi, C_DISABLE);
586
587 break;
588
589 case FB_BLANK_UNBLANK:
590
591 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
592 fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
593 fb_set_cmap(&fbi->fb.cmap, info);
594 pxafb_schedule_work(fbi, C_ENABLE);
595 }
596 return 0;
597}
598
599static struct fb_ops pxafb_ops = {
600 .owner = THIS_MODULE,
601 .fb_check_var = pxafb_check_var,
602 .fb_set_par = pxafb_set_par,
603 .fb_pan_display = pxafb_pan_display,
604 .fb_setcolreg = pxafb_setcolreg,
605 .fb_fillrect = cfb_fillrect,
606 .fb_copyarea = cfb_copyarea,
607 .fb_imageblit = cfb_imageblit,
608 .fb_blank = pxafb_blank,
609};
610
611#ifdef CONFIG_FB_PXA_OVERLAY
612static void overlay1fb_setup(struct pxafb_layer *ofb)
613{
614 int size = ofb->fb.fix.line_length * ofb->fb.var.yres_virtual;
615 unsigned long start = ofb->video_mem_phys;
616 setup_frame_dma(ofb->fbi, DMA_OV1, PAL_NONE, start, size);
617}
618
619
620
621
622static void overlay1fb_enable(struct pxafb_layer *ofb)
623{
624 int enabled = lcd_readl(ofb->fbi, OVL1C1) & OVLxC1_OEN;
625 uint32_t fdadr1 = ofb->fbi->fdadr[DMA_OV1] | (enabled ? 0x1 : 0);
626
627 lcd_writel(ofb->fbi, enabled ? FBR1 : FDADR1, fdadr1);
628 lcd_writel(ofb->fbi, OVL1C2, ofb->control[1]);
629 lcd_writel(ofb->fbi, OVL1C1, ofb->control[0] | OVLxC1_OEN);
630}
631
632static void overlay1fb_disable(struct pxafb_layer *ofb)
633{
634 uint32_t lccr5;
635
636 if (!(lcd_readl(ofb->fbi, OVL1C1) & OVLxC1_OEN))
637 return;
638
639 lccr5 = lcd_readl(ofb->fbi, LCCR5);
640
641 lcd_writel(ofb->fbi, OVL1C1, ofb->control[0] & ~OVLxC1_OEN);
642
643 lcd_writel(ofb->fbi, LCSR1, LCSR1_BS(1));
644 lcd_writel(ofb->fbi, LCCR5, lccr5 & ~LCSR1_BS(1));
645 lcd_writel(ofb->fbi, FBR1, ofb->fbi->fdadr[DMA_OV1] | 0x3);
646
647 if (wait_for_completion_timeout(&ofb->branch_done, 1 * HZ) == 0)
648 pr_warning("%s: timeout disabling overlay1\n", __func__);
649
650 lcd_writel(ofb->fbi, LCCR5, lccr5);
651}
652
653static void overlay2fb_setup(struct pxafb_layer *ofb)
654{
655 int size, div = 1, pfor = NONSTD_TO_PFOR(ofb->fb.var.nonstd);
656 unsigned long start[3] = { ofb->video_mem_phys, 0, 0 };
657
658 if (pfor == OVERLAY_FORMAT_RGB || pfor == OVERLAY_FORMAT_YUV444_PACKED) {
659 size = ofb->fb.fix.line_length * ofb->fb.var.yres_virtual;
660 setup_frame_dma(ofb->fbi, DMA_OV2_Y, -1, start[0], size);
661 } else {
662 size = ofb->fb.var.xres_virtual * ofb->fb.var.yres_virtual;
663 switch (pfor) {
664 case OVERLAY_FORMAT_YUV444_PLANAR: div = 1; break;
665 case OVERLAY_FORMAT_YUV422_PLANAR: div = 2; break;
666 case OVERLAY_FORMAT_YUV420_PLANAR: div = 4; break;
667 }
668 start[1] = start[0] + size;
669 start[2] = start[1] + size / div;
670 setup_frame_dma(ofb->fbi, DMA_OV2_Y, -1, start[0], size);
671 setup_frame_dma(ofb->fbi, DMA_OV2_Cb, -1, start[1], size / div);
672 setup_frame_dma(ofb->fbi, DMA_OV2_Cr, -1, start[2], size / div);
673 }
674}
675
676static void overlay2fb_enable(struct pxafb_layer *ofb)
677{
678 int pfor = NONSTD_TO_PFOR(ofb->fb.var.nonstd);
679 int enabled = lcd_readl(ofb->fbi, OVL2C1) & OVLxC1_OEN;
680 uint32_t fdadr2 = ofb->fbi->fdadr[DMA_OV2_Y] | (enabled ? 0x1 : 0);
681 uint32_t fdadr3 = ofb->fbi->fdadr[DMA_OV2_Cb] | (enabled ? 0x1 : 0);
682 uint32_t fdadr4 = ofb->fbi->fdadr[DMA_OV2_Cr] | (enabled ? 0x1 : 0);
683
684 if (pfor == OVERLAY_FORMAT_RGB || pfor == OVERLAY_FORMAT_YUV444_PACKED)
685 lcd_writel(ofb->fbi, enabled ? FBR2 : FDADR2, fdadr2);
686 else {
687 lcd_writel(ofb->fbi, enabled ? FBR2 : FDADR2, fdadr2);
688 lcd_writel(ofb->fbi, enabled ? FBR3 : FDADR3, fdadr3);
689 lcd_writel(ofb->fbi, enabled ? FBR4 : FDADR4, fdadr4);
690 }
691 lcd_writel(ofb->fbi, OVL2C2, ofb->control[1]);
692 lcd_writel(ofb->fbi, OVL2C1, ofb->control[0] | OVLxC1_OEN);
693}
694
695static void overlay2fb_disable(struct pxafb_layer *ofb)
696{
697 uint32_t lccr5;
698
699 if (!(lcd_readl(ofb->fbi, OVL2C1) & OVLxC1_OEN))
700 return;
701
702 lccr5 = lcd_readl(ofb->fbi, LCCR5);
703
704 lcd_writel(ofb->fbi, OVL2C1, ofb->control[0] & ~OVLxC1_OEN);
705
706 lcd_writel(ofb->fbi, LCSR1, LCSR1_BS(2));
707 lcd_writel(ofb->fbi, LCCR5, lccr5 & ~LCSR1_BS(2));
708 lcd_writel(ofb->fbi, FBR2, ofb->fbi->fdadr[DMA_OV2_Y] | 0x3);
709 lcd_writel(ofb->fbi, FBR3, ofb->fbi->fdadr[DMA_OV2_Cb] | 0x3);
710 lcd_writel(ofb->fbi, FBR4, ofb->fbi->fdadr[DMA_OV2_Cr] | 0x3);
711
712 if (wait_for_completion_timeout(&ofb->branch_done, 1 * HZ) == 0)
713 pr_warning("%s: timeout disabling overlay2\n", __func__);
714}
715
716static struct pxafb_layer_ops ofb_ops[] = {
717 [0] = {
718 .enable = overlay1fb_enable,
719 .disable = overlay1fb_disable,
720 .setup = overlay1fb_setup,
721 },
722 [1] = {
723 .enable = overlay2fb_enable,
724 .disable = overlay2fb_disable,
725 .setup = overlay2fb_setup,
726 },
727};
728
729static int overlayfb_open(struct fb_info *info, int user)
730{
731 struct pxafb_layer *ofb = container_of(info, struct pxafb_layer, fb);
732
733
734 if (user == 0)
735 return -ENODEV;
736
737 if (ofb->usage++ == 0) {
738
739 console_lock();
740 fb_blank(&ofb->fbi->fb, FB_BLANK_UNBLANK);
741 console_unlock();
742 }
743
744 return 0;
745}
746
747static int overlayfb_release(struct fb_info *info, int user)
748{
749 struct pxafb_layer *ofb = container_of(info, struct pxafb_layer, fb);
750
751 if (ofb->usage == 1) {
752 ofb->ops->disable(ofb);
753 ofb->fb.var.height = -1;
754 ofb->fb.var.width = -1;
755 ofb->fb.var.xres = ofb->fb.var.xres_virtual = 0;
756 ofb->fb.var.yres = ofb->fb.var.yres_virtual = 0;
757
758 ofb->usage--;
759 }
760 return 0;
761}
762
763static int overlayfb_check_var(struct fb_var_screeninfo *var,
764 struct fb_info *info)
765{
766 struct pxafb_layer *ofb = container_of(info, struct pxafb_layer, fb);
767 struct fb_var_screeninfo *base_var = &ofb->fbi->fb.var;
768 int xpos, ypos, pfor, bpp;
769
770 xpos = NONSTD_TO_XPOS(var->nonstd);
771 ypos = NONSTD_TO_YPOS(var->nonstd);
772 pfor = NONSTD_TO_PFOR(var->nonstd);
773
774 bpp = pxafb_var_to_bpp(var);
775 if (bpp < 0)
776 return -EINVAL;
777
778
779 if (ofb->id == OVERLAY1 && pfor != 0)
780 return -EINVAL;
781
782
783 switch (pfor) {
784 case OVERLAY_FORMAT_RGB:
785 bpp = pxafb_var_to_bpp(var);
786 if (bpp < 0)
787 return -EINVAL;
788
789 pxafb_set_pixfmt(var, var_to_depth(var));
790 break;
791 case OVERLAY_FORMAT_YUV444_PACKED: bpp = 24; break;
792 case OVERLAY_FORMAT_YUV444_PLANAR: bpp = 8; break;
793 case OVERLAY_FORMAT_YUV422_PLANAR: bpp = 4; break;
794 case OVERLAY_FORMAT_YUV420_PLANAR: bpp = 2; break;
795 default:
796 return -EINVAL;
797 }
798
799
800 if ((xpos * bpp) % 32)
801 return -EINVAL;
802
803
804 var->xres = roundup(var->xres * bpp, 32) / bpp;
805
806 if ((xpos + var->xres > base_var->xres) ||
807 (ypos + var->yres > base_var->yres))
808 return -EINVAL;
809
810 var->xres_virtual = var->xres;
811 var->yres_virtual = max(var->yres, var->yres_virtual);
812 return 0;
813}
814
815static int overlayfb_check_video_memory(struct pxafb_layer *ofb)
816{
817 struct fb_var_screeninfo *var = &ofb->fb.var;
818 int pfor = NONSTD_TO_PFOR(var->nonstd);
819 int size, bpp = 0;
820
821 switch (pfor) {
822 case OVERLAY_FORMAT_RGB: bpp = var->bits_per_pixel; break;
823 case OVERLAY_FORMAT_YUV444_PACKED: bpp = 24; break;
824 case OVERLAY_FORMAT_YUV444_PLANAR: bpp = 24; break;
825 case OVERLAY_FORMAT_YUV422_PLANAR: bpp = 16; break;
826 case OVERLAY_FORMAT_YUV420_PLANAR: bpp = 12; break;
827 }
828
829 ofb->fb.fix.line_length = var->xres_virtual * bpp / 8;
830
831 size = PAGE_ALIGN(ofb->fb.fix.line_length * var->yres_virtual);
832
833 if (ofb->video_mem) {
834 if (ofb->video_mem_size >= size)
835 return 0;
836 }
837 return -EINVAL;
838}
839
840static int overlayfb_set_par(struct fb_info *info)
841{
842 struct pxafb_layer *ofb = container_of(info, struct pxafb_layer, fb);
843 struct fb_var_screeninfo *var = &info->var;
844 int xpos, ypos, pfor, bpp, ret;
845
846 ret = overlayfb_check_video_memory(ofb);
847 if (ret)
848 return ret;
849
850 bpp = pxafb_var_to_bpp(var);
851 xpos = NONSTD_TO_XPOS(var->nonstd);
852 ypos = NONSTD_TO_YPOS(var->nonstd);
853 pfor = NONSTD_TO_PFOR(var->nonstd);
854
855 ofb->control[0] = OVLxC1_PPL(var->xres) | OVLxC1_LPO(var->yres) |
856 OVLxC1_BPP(bpp);
857 ofb->control[1] = OVLxC2_XPOS(xpos) | OVLxC2_YPOS(ypos);
858
859 if (ofb->id == OVERLAY2)
860 ofb->control[1] |= OVL2C2_PFOR(pfor);
861
862 ofb->ops->setup(ofb);
863 ofb->ops->enable(ofb);
864 return 0;
865}
866
867static struct fb_ops overlay_fb_ops = {
868 .owner = THIS_MODULE,
869 .fb_open = overlayfb_open,
870 .fb_release = overlayfb_release,
871 .fb_check_var = overlayfb_check_var,
872 .fb_set_par = overlayfb_set_par,
873};
874
875static void init_pxafb_overlay(struct pxafb_info *fbi, struct pxafb_layer *ofb,
876 int id)
877{
878 sprintf(ofb->fb.fix.id, "overlay%d", id + 1);
879
880 ofb->fb.fix.type = FB_TYPE_PACKED_PIXELS;
881 ofb->fb.fix.xpanstep = 0;
882 ofb->fb.fix.ypanstep = 1;
883
884 ofb->fb.var.activate = FB_ACTIVATE_NOW;
885 ofb->fb.var.height = -1;
886 ofb->fb.var.width = -1;
887 ofb->fb.var.vmode = FB_VMODE_NONINTERLACED;
888
889 ofb->fb.fbops = &overlay_fb_ops;
890 ofb->fb.flags = FBINFO_FLAG_DEFAULT;
891 ofb->fb.node = -1;
892 ofb->fb.pseudo_palette = NULL;
893
894 ofb->id = id;
895 ofb->ops = &ofb_ops[id];
896 ofb->usage = 0;
897 ofb->fbi = fbi;
898 init_completion(&ofb->branch_done);
899}
900
901static inline int pxafb_overlay_supported(void)
902{
903 if (cpu_is_pxa27x() || cpu_is_pxa3xx())
904 return 1;
905
906 return 0;
907}
908
909static int pxafb_overlay_map_video_memory(struct pxafb_info *pxafb,
910 struct pxafb_layer *ofb)
911{
912
913
914
915 ofb->video_mem = alloc_pages_exact(PAGE_ALIGN(pxafb->video_mem_size),
916 GFP_KERNEL | __GFP_ZERO);
917 if (ofb->video_mem == NULL)
918 return -ENOMEM;
919
920 ofb->video_mem_phys = virt_to_phys(ofb->video_mem);
921 ofb->video_mem_size = PAGE_ALIGN(pxafb->video_mem_size);
922
923 mutex_lock(&ofb->fb.mm_lock);
924 ofb->fb.fix.smem_start = ofb->video_mem_phys;
925 ofb->fb.fix.smem_len = pxafb->video_mem_size;
926 mutex_unlock(&ofb->fb.mm_lock);
927
928 ofb->fb.screen_base = ofb->video_mem;
929
930 return 0;
931}
932
933static void pxafb_overlay_init(struct pxafb_info *fbi)
934{
935 int i, ret;
936
937 if (!pxafb_overlay_supported())
938 return;
939
940 for (i = 0; i < 2; i++) {
941 struct pxafb_layer *ofb = &fbi->overlay[i];
942 init_pxafb_overlay(fbi, ofb, i);
943 ret = register_framebuffer(&ofb->fb);
944 if (ret) {
945 dev_err(fbi->dev, "failed to register overlay %d\n", i);
946 continue;
947 }
948 ret = pxafb_overlay_map_video_memory(fbi, ofb);
949 if (ret) {
950 dev_err(fbi->dev,
951 "failed to map video memory for overlay %d\n",
952 i);
953 unregister_framebuffer(&ofb->fb);
954 continue;
955 }
956 ofb->registered = 1;
957 }
958
959
960 lcd_writel(fbi, LCCR5, ~0);
961
962 pr_info("PXA Overlay driver loaded successfully!\n");
963}
964
965static void pxafb_overlay_exit(struct pxafb_info *fbi)
966{
967 int i;
968
969 if (!pxafb_overlay_supported())
970 return;
971
972 for (i = 0; i < 2; i++) {
973 struct pxafb_layer *ofb = &fbi->overlay[i];
974 if (ofb->registered) {
975 if (ofb->video_mem)
976 free_pages_exact(ofb->video_mem,
977 ofb->video_mem_size);
978 unregister_framebuffer(&ofb->fb);
979 }
980 }
981}
982#else
983static inline void pxafb_overlay_init(struct pxafb_info *fbi) {}
984static inline void pxafb_overlay_exit(struct pxafb_info *fbi) {}
985#endif
986
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993
994
995
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997
998
999
1000
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1003
1004
1005
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1009
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1012
1013
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1015
1016
1017static inline unsigned int get_pcd(struct pxafb_info *fbi,
1018 unsigned int pixclock)
1019{
1020 unsigned long long pcd;
1021
1022
1023
1024
1025 pcd = (unsigned long long)(clk_get_rate(fbi->clk) / 10000);
1026 pcd *= pixclock;
1027 do_div(pcd, 100000000 * 2);
1028
1029
1030 return (unsigned int)pcd;
1031}
1032
1033
1034
1035
1036
1037
1038
1039static inline void set_hsync_time(struct pxafb_info *fbi, unsigned int pcd)
1040{
1041 unsigned long htime;
1042
1043 if ((pcd == 0) || (fbi->fb.var.hsync_len == 0)) {
1044 fbi->hsync_time = 0;
1045 return;
1046 }
1047
1048 htime = clk_get_rate(fbi->clk) / (pcd * fbi->fb.var.hsync_len);
1049
1050 fbi->hsync_time = htime;
1051}
1052
1053unsigned long pxafb_get_hsync_time(struct device *dev)
1054{
1055 struct pxafb_info *fbi = dev_get_drvdata(dev);
1056
1057
1058 if (!fbi || (fbi->state != C_ENABLE))
1059 return 0;
1060
1061 return fbi->hsync_time;
1062}
1063EXPORT_SYMBOL(pxafb_get_hsync_time);
1064
1065static int setup_frame_dma(struct pxafb_info *fbi, int dma, int pal,
1066 unsigned long start, size_t size)
1067{
1068 struct pxafb_dma_descriptor *dma_desc, *pal_desc;
1069 unsigned int dma_desc_off, pal_desc_off;
1070
1071 if (dma < 0 || dma >= DMA_MAX * 2)
1072 return -EINVAL;
1073
1074 dma_desc = &fbi->dma_buff->dma_desc[dma];
1075 dma_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[dma]);
1076
1077 dma_desc->fsadr = start;
1078 dma_desc->fidr = 0;
1079 dma_desc->ldcmd = size;
1080
1081 if (pal < 0 || pal >= PAL_MAX * 2) {
1082 dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
1083 fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off;
1084 } else {
1085 pal_desc = &fbi->dma_buff->pal_desc[pal];
1086 pal_desc_off = offsetof(struct pxafb_dma_buff, pal_desc[pal]);
1087
1088 pal_desc->fsadr = fbi->dma_buff_phys + pal * PALETTE_SIZE;
1089 pal_desc->fidr = 0;
1090
1091 if ((fbi->lccr4 & LCCR4_PAL_FOR_MASK) == LCCR4_PAL_FOR_0)
1092 pal_desc->ldcmd = fbi->palette_size * sizeof(u16);
1093 else
1094 pal_desc->ldcmd = fbi->palette_size * sizeof(u32);
1095
1096 pal_desc->ldcmd |= LDCMD_PAL;
1097
1098
1099 pal_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
1100 dma_desc->fdadr = fbi->dma_buff_phys + pal_desc_off;
1101 fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off;
1102 }
1103
1104 return 0;
1105}
1106
1107static void setup_base_frame(struct pxafb_info *fbi,
1108 struct fb_var_screeninfo *var,
1109 int branch)
1110{
1111 struct fb_fix_screeninfo *fix = &fbi->fb.fix;
1112 int nbytes, dma, pal, bpp = var->bits_per_pixel;
1113 unsigned long offset;
1114
1115 dma = DMA_BASE + (branch ? DMA_MAX : 0);
1116 pal = (bpp >= 16) ? PAL_NONE : PAL_BASE + (branch ? PAL_MAX : 0);
1117
1118 nbytes = fix->line_length * var->yres;
1119 offset = fix->line_length * var->yoffset + fbi->video_mem_phys;
1120
1121 if (fbi->lccr0 & LCCR0_SDS) {
1122 nbytes = nbytes / 2;
1123 setup_frame_dma(fbi, dma + 1, PAL_NONE, offset + nbytes, nbytes);
1124 }
1125
1126 setup_frame_dma(fbi, dma, pal, offset, nbytes);
1127}
1128
1129#ifdef CONFIG_FB_PXA_SMARTPANEL
1130static int setup_smart_dma(struct pxafb_info *fbi)
1131{
1132 struct pxafb_dma_descriptor *dma_desc;
1133 unsigned long dma_desc_off, cmd_buff_off;
1134
1135 dma_desc = &fbi->dma_buff->dma_desc[DMA_CMD];
1136 dma_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[DMA_CMD]);
1137 cmd_buff_off = offsetof(struct pxafb_dma_buff, cmd_buff);
1138
1139 dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
1140 dma_desc->fsadr = fbi->dma_buff_phys + cmd_buff_off;
1141 dma_desc->fidr = 0;
1142 dma_desc->ldcmd = fbi->n_smart_cmds * sizeof(uint16_t);
1143
1144 fbi->fdadr[DMA_CMD] = dma_desc->fdadr;
1145 return 0;
1146}
1147
1148int pxafb_smart_flush(struct fb_info *info)
1149{
1150 struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
1151 uint32_t prsr;
1152 int ret = 0;
1153
1154
1155 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
1156
1157
1158
1159
1160
1161
1162 while (fbi->n_smart_cmds & 1)
1163 fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_NOOP;
1164
1165 fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_INTERRUPT;
1166 fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_WAIT_FOR_VSYNC;
1167 setup_smart_dma(fbi);
1168
1169
1170 prsr = lcd_readl(fbi, PRSR) | PRSR_ST_OK | PRSR_CON_NT;
1171 lcd_writel(fbi, PRSR, prsr);
1172
1173
1174 lcd_writel(fbi, CMDCR, 0x0001);
1175
1176
1177 lcd_writel(fbi, LCCR5, LCCR5_IUM(6));
1178
1179 lcd_writel(fbi, LCCR1, fbi->reg_lccr1);
1180 lcd_writel(fbi, LCCR2, fbi->reg_lccr2);
1181 lcd_writel(fbi, LCCR3, fbi->reg_lccr3);
1182 lcd_writel(fbi, LCCR4, fbi->reg_lccr4);
1183 lcd_writel(fbi, FDADR0, fbi->fdadr[0]);
1184 lcd_writel(fbi, FDADR6, fbi->fdadr[6]);
1185
1186
1187 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 | LCCR0_ENB);
1188
1189 if (wait_for_completion_timeout(&fbi->command_done, HZ/2) == 0) {
1190 pr_warning("%s: timeout waiting for command done\n",
1191 __func__);
1192 ret = -ETIMEDOUT;
1193 }
1194
1195
1196 prsr = lcd_readl(fbi, PRSR) & ~(PRSR_ST_OK | PRSR_CON_NT);
1197 lcd_writel(fbi, PRSR, prsr);
1198 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
1199 lcd_writel(fbi, FDADR6, 0);
1200 fbi->n_smart_cmds = 0;
1201 return ret;
1202}
1203
1204int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int n_cmds)
1205{
1206 int i;
1207 struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
1208
1209 for (i = 0; i < n_cmds; i++, cmds++) {
1210
1211 if ((*cmds & 0xff00) == SMART_CMD_DELAY) {
1212 pxafb_smart_flush(info);
1213 mdelay(*cmds & 0xff);
1214 continue;
1215 }
1216
1217
1218 if (fbi->n_smart_cmds == CMD_BUFF_SIZE - 8)
1219 pxafb_smart_flush(info);
1220
1221 fbi->smart_cmds[fbi->n_smart_cmds++] = *cmds;
1222 }
1223
1224 return 0;
1225}
1226
1227static unsigned int __smart_timing(unsigned time_ns, unsigned long lcd_clk)
1228{
1229 unsigned int t = (time_ns * (lcd_clk / 1000000) / 1000);
1230 return (t == 0) ? 1 : t;
1231}
1232
1233static void setup_smart_timing(struct pxafb_info *fbi,
1234 struct fb_var_screeninfo *var)
1235{
1236 struct pxafb_mach_info *inf = fbi->inf;
1237 struct pxafb_mode_info *mode = &inf->modes[0];
1238 unsigned long lclk = clk_get_rate(fbi->clk);
1239 unsigned t1, t2, t3, t4;
1240
1241 t1 = max(mode->a0csrd_set_hld, mode->a0cswr_set_hld);
1242 t2 = max(mode->rd_pulse_width, mode->wr_pulse_width);
1243 t3 = mode->op_hold_time;
1244 t4 = mode->cmd_inh_time;
1245
1246 fbi->reg_lccr1 =
1247 LCCR1_DisWdth(var->xres) |
1248 LCCR1_BegLnDel(__smart_timing(t1, lclk)) |
1249 LCCR1_EndLnDel(__smart_timing(t2, lclk)) |
1250 LCCR1_HorSnchWdth(__smart_timing(t3, lclk));
1251
1252 fbi->reg_lccr2 = LCCR2_DisHght(var->yres);
1253 fbi->reg_lccr3 = fbi->lccr3 | LCCR3_PixClkDiv(__smart_timing(t4, lclk));
1254 fbi->reg_lccr3 |= (var->sync & FB_SYNC_HOR_HIGH_ACT) ? LCCR3_HSP : 0;
1255 fbi->reg_lccr3 |= (var->sync & FB_SYNC_VERT_HIGH_ACT) ? LCCR3_VSP : 0;
1256
1257
1258 fbi->reg_cmdcr = 1;
1259}
1260
1261static int pxafb_smart_thread(void *arg)
1262{
1263 struct pxafb_info *fbi = arg;
1264 struct pxafb_mach_info *inf = fbi->inf;
1265
1266 if (!inf->smart_update) {
1267 pr_err("%s: not properly initialized, thread terminated\n",
1268 __func__);
1269 return -EINVAL;
1270 }
1271
1272 pr_debug("%s(): task starting\n", __func__);
1273
1274 set_freezable();
1275 while (!kthread_should_stop()) {
1276
1277 if (try_to_freeze())
1278 continue;
1279
1280 mutex_lock(&fbi->ctrlr_lock);
1281
1282 if (fbi->state == C_ENABLE) {
1283 inf->smart_update(&fbi->fb);
1284 complete(&fbi->refresh_done);
1285 }
1286
1287 mutex_unlock(&fbi->ctrlr_lock);
1288
1289 set_current_state(TASK_INTERRUPTIBLE);
1290 schedule_timeout(msecs_to_jiffies(30));
1291 }
1292
1293 pr_debug("%s(): task ending\n", __func__);
1294 return 0;
1295}
1296
1297static int pxafb_smart_init(struct pxafb_info *fbi)
1298{
1299 if (!(fbi->lccr0 & LCCR0_LCDT))
1300 return 0;
1301
1302 fbi->smart_cmds = (uint16_t *) fbi->dma_buff->cmd_buff;
1303 fbi->n_smart_cmds = 0;
1304
1305 init_completion(&fbi->command_done);
1306 init_completion(&fbi->refresh_done);
1307
1308 fbi->smart_thread = kthread_run(pxafb_smart_thread, fbi,
1309 "lcd_refresh");
1310 if (IS_ERR(fbi->smart_thread)) {
1311 pr_err("%s: unable to create kernel thread\n", __func__);
1312 return PTR_ERR(fbi->smart_thread);
1313 }
1314
1315 return 0;
1316}
1317#else
1318static inline int pxafb_smart_init(struct pxafb_info *fbi) { return 0; }
1319#endif
1320
1321static void setup_parallel_timing(struct pxafb_info *fbi,
1322 struct fb_var_screeninfo *var)
1323{
1324 unsigned int lines_per_panel, pcd = get_pcd(fbi, var->pixclock);
1325
1326 fbi->reg_lccr1 =
1327 LCCR1_DisWdth(var->xres) +
1328 LCCR1_HorSnchWdth(var->hsync_len) +
1329 LCCR1_BegLnDel(var->left_margin) +
1330 LCCR1_EndLnDel(var->right_margin);
1331
1332
1333
1334
1335
1336 lines_per_panel = var->yres;
1337 if ((fbi->lccr0 & LCCR0_SDS) == LCCR0_Dual)
1338 lines_per_panel /= 2;
1339
1340 fbi->reg_lccr2 =
1341 LCCR2_DisHght(lines_per_panel) +
1342 LCCR2_VrtSnchWdth(var->vsync_len) +
1343 LCCR2_BegFrmDel(var->upper_margin) +
1344 LCCR2_EndFrmDel(var->lower_margin);
1345
1346 fbi->reg_lccr3 = fbi->lccr3 |
1347 (var->sync & FB_SYNC_HOR_HIGH_ACT ?
1348 LCCR3_HorSnchH : LCCR3_HorSnchL) |
1349 (var->sync & FB_SYNC_VERT_HIGH_ACT ?
1350 LCCR3_VrtSnchH : LCCR3_VrtSnchL);
1351
1352 if (pcd) {
1353 fbi->reg_lccr3 |= LCCR3_PixClkDiv(pcd);
1354 set_hsync_time(fbi, pcd);
1355 }
1356}
1357
1358
1359
1360
1361
1362
1363static int pxafb_activate_var(struct fb_var_screeninfo *var,
1364 struct pxafb_info *fbi)
1365{
1366 u_long flags;
1367
1368
1369 local_irq_save(flags);
1370
1371#ifdef CONFIG_FB_PXA_SMARTPANEL
1372 if (fbi->lccr0 & LCCR0_LCDT)
1373 setup_smart_timing(fbi, var);
1374 else
1375#endif
1376 setup_parallel_timing(fbi, var);
1377
1378 setup_base_frame(fbi, var, 0);
1379
1380 fbi->reg_lccr0 = fbi->lccr0 |
1381 (LCCR0_LDM | LCCR0_SFM | LCCR0_IUM | LCCR0_EFM |
1382 LCCR0_QDM | LCCR0_BM | LCCR0_OUM);
1383
1384 fbi->reg_lccr3 |= pxafb_var_to_lccr3(var);
1385
1386 fbi->reg_lccr4 = lcd_readl(fbi, LCCR4) & ~LCCR4_PAL_FOR_MASK;
1387 fbi->reg_lccr4 |= (fbi->lccr4 & LCCR4_PAL_FOR_MASK);
1388 local_irq_restore(flags);
1389
1390
1391
1392
1393
1394 if ((lcd_readl(fbi, LCCR0) != fbi->reg_lccr0) ||
1395 (lcd_readl(fbi, LCCR1) != fbi->reg_lccr1) ||
1396 (lcd_readl(fbi, LCCR2) != fbi->reg_lccr2) ||
1397 (lcd_readl(fbi, LCCR3) != fbi->reg_lccr3) ||
1398 (lcd_readl(fbi, LCCR4) != fbi->reg_lccr4) ||
1399 (lcd_readl(fbi, FDADR0) != fbi->fdadr[0]) ||
1400 ((fbi->lccr0 & LCCR0_SDS) &&
1401 (lcd_readl(fbi, FDADR1) != fbi->fdadr[1])))
1402 pxafb_schedule_work(fbi, C_REENABLE);
1403
1404 return 0;
1405}
1406
1407
1408
1409
1410
1411
1412
1413static inline void __pxafb_backlight_power(struct pxafb_info *fbi, int on)
1414{
1415 pr_debug("pxafb: backlight o%s\n", on ? "n" : "ff");
1416
1417 if (fbi->backlight_power)
1418 fbi->backlight_power(on);
1419}
1420
1421static inline void __pxafb_lcd_power(struct pxafb_info *fbi, int on)
1422{
1423 pr_debug("pxafb: LCD power o%s\n", on ? "n" : "ff");
1424
1425 if (fbi->lcd_power)
1426 fbi->lcd_power(on, &fbi->fb.var);
1427}
1428
1429static void pxafb_enable_controller(struct pxafb_info *fbi)
1430{
1431 pr_debug("pxafb: Enabling LCD controller\n");
1432 pr_debug("fdadr0 0x%08x\n", (unsigned int) fbi->fdadr[0]);
1433 pr_debug("fdadr1 0x%08x\n", (unsigned int) fbi->fdadr[1]);
1434 pr_debug("reg_lccr0 0x%08x\n", (unsigned int) fbi->reg_lccr0);
1435 pr_debug("reg_lccr1 0x%08x\n", (unsigned int) fbi->reg_lccr1);
1436 pr_debug("reg_lccr2 0x%08x\n", (unsigned int) fbi->reg_lccr2);
1437 pr_debug("reg_lccr3 0x%08x\n", (unsigned int) fbi->reg_lccr3);
1438
1439
1440 clk_prepare_enable(fbi->clk);
1441
1442 if (fbi->lccr0 & LCCR0_LCDT)
1443 return;
1444
1445
1446 lcd_writel(fbi, LCCR4, fbi->reg_lccr4);
1447 lcd_writel(fbi, LCCR3, fbi->reg_lccr3);
1448 lcd_writel(fbi, LCCR2, fbi->reg_lccr2);
1449 lcd_writel(fbi, LCCR1, fbi->reg_lccr1);
1450 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
1451
1452 lcd_writel(fbi, FDADR0, fbi->fdadr[0]);
1453 if (fbi->lccr0 & LCCR0_SDS)
1454 lcd_writel(fbi, FDADR1, fbi->fdadr[1]);
1455 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 | LCCR0_ENB);
1456}
1457
1458static void pxafb_disable_controller(struct pxafb_info *fbi)
1459{
1460 uint32_t lccr0;
1461
1462#ifdef CONFIG_FB_PXA_SMARTPANEL
1463 if (fbi->lccr0 & LCCR0_LCDT) {
1464 wait_for_completion_timeout(&fbi->refresh_done,
1465 msecs_to_jiffies(200));
1466 return;
1467 }
1468#endif
1469
1470
1471 lcd_writel(fbi, LCSR, 0xffffffff);
1472
1473 lccr0 = lcd_readl(fbi, LCCR0) & ~LCCR0_LDM;
1474 lcd_writel(fbi, LCCR0, lccr0);
1475 lcd_writel(fbi, LCCR0, lccr0 | LCCR0_DIS);
1476
1477 wait_for_completion_timeout(&fbi->disable_done, msecs_to_jiffies(200));
1478
1479
1480 clk_disable_unprepare(fbi->clk);
1481}
1482
1483
1484
1485
1486static irqreturn_t pxafb_handle_irq(int irq, void *dev_id)
1487{
1488 struct pxafb_info *fbi = dev_id;
1489 unsigned int lccr0, lcsr;
1490
1491 lcsr = lcd_readl(fbi, LCSR);
1492 if (lcsr & LCSR_LDD) {
1493 lccr0 = lcd_readl(fbi, LCCR0);
1494 lcd_writel(fbi, LCCR0, lccr0 | LCCR0_LDM);
1495 complete(&fbi->disable_done);
1496 }
1497
1498#ifdef CONFIG_FB_PXA_SMARTPANEL
1499 if (lcsr & LCSR_CMD_INT)
1500 complete(&fbi->command_done);
1501#endif
1502 lcd_writel(fbi, LCSR, lcsr);
1503
1504#ifdef CONFIG_FB_PXA_OVERLAY
1505 {
1506 unsigned int lcsr1 = lcd_readl(fbi, LCSR1);
1507 if (lcsr1 & LCSR1_BS(1))
1508 complete(&fbi->overlay[0].branch_done);
1509
1510 if (lcsr1 & LCSR1_BS(2))
1511 complete(&fbi->overlay[1].branch_done);
1512
1513 lcd_writel(fbi, LCSR1, lcsr1);
1514 }
1515#endif
1516 return IRQ_HANDLED;
1517}
1518
1519
1520
1521
1522
1523
1524static void set_ctrlr_state(struct pxafb_info *fbi, u_int state)
1525{
1526 u_int old_state;
1527
1528 mutex_lock(&fbi->ctrlr_lock);
1529
1530 old_state = fbi->state;
1531
1532
1533
1534
1535 if (old_state == C_STARTUP && state == C_REENABLE)
1536 state = C_ENABLE;
1537
1538 switch (state) {
1539 case C_DISABLE_CLKCHANGE:
1540
1541
1542
1543
1544 if (old_state != C_DISABLE && old_state != C_DISABLE_PM) {
1545 fbi->state = state;
1546
1547 pxafb_disable_controller(fbi);
1548 }
1549 break;
1550
1551 case C_DISABLE_PM:
1552 case C_DISABLE:
1553
1554
1555
1556 if (old_state != C_DISABLE) {
1557 fbi->state = state;
1558 __pxafb_backlight_power(fbi, 0);
1559 __pxafb_lcd_power(fbi, 0);
1560 if (old_state != C_DISABLE_CLKCHANGE)
1561 pxafb_disable_controller(fbi);
1562 }
1563 break;
1564
1565 case C_ENABLE_CLKCHANGE:
1566
1567
1568
1569
1570 if (old_state == C_DISABLE_CLKCHANGE) {
1571 fbi->state = C_ENABLE;
1572 pxafb_enable_controller(fbi);
1573
1574 }
1575 break;
1576
1577 case C_REENABLE:
1578
1579
1580
1581
1582
1583 if (old_state == C_ENABLE) {
1584 __pxafb_lcd_power(fbi, 0);
1585 pxafb_disable_controller(fbi);
1586 pxafb_enable_controller(fbi);
1587 __pxafb_lcd_power(fbi, 1);
1588 }
1589 break;
1590
1591 case C_ENABLE_PM:
1592
1593
1594
1595
1596
1597 if (old_state != C_DISABLE_PM)
1598 break;
1599
1600
1601 case C_ENABLE:
1602
1603
1604
1605
1606 if (old_state != C_ENABLE) {
1607 fbi->state = C_ENABLE;
1608 pxafb_enable_controller(fbi);
1609 __pxafb_lcd_power(fbi, 1);
1610 __pxafb_backlight_power(fbi, 1);
1611 }
1612 break;
1613 }
1614 mutex_unlock(&fbi->ctrlr_lock);
1615}
1616
1617
1618
1619
1620
1621static void pxafb_task(struct work_struct *work)
1622{
1623 struct pxafb_info *fbi =
1624 container_of(work, struct pxafb_info, task);
1625 u_int state = xchg(&fbi->task_state, -1);
1626
1627 set_ctrlr_state(fbi, state);
1628}
1629
1630#ifdef CONFIG_CPU_FREQ
1631
1632
1633
1634
1635
1636
1637
1638static int
1639pxafb_freq_transition(struct notifier_block *nb, unsigned long val, void *data)
1640{
1641 struct pxafb_info *fbi = TO_INF(nb, freq_transition);
1642
1643 u_int pcd;
1644
1645 switch (val) {
1646 case CPUFREQ_PRECHANGE:
1647#ifdef CONFIG_FB_PXA_OVERLAY
1648 if (!(fbi->overlay[0].usage || fbi->overlay[1].usage))
1649#endif
1650 set_ctrlr_state(fbi, C_DISABLE_CLKCHANGE);
1651 break;
1652
1653 case CPUFREQ_POSTCHANGE:
1654 pcd = get_pcd(fbi, fbi->fb.var.pixclock);
1655 set_hsync_time(fbi, pcd);
1656 fbi->reg_lccr3 = (fbi->reg_lccr3 & ~0xff) |
1657 LCCR3_PixClkDiv(pcd);
1658 set_ctrlr_state(fbi, C_ENABLE_CLKCHANGE);
1659 break;
1660 }
1661 return 0;
1662}
1663
1664static int
1665pxafb_freq_policy(struct notifier_block *nb, unsigned long val, void *data)
1666{
1667 struct pxafb_info *fbi = TO_INF(nb, freq_policy);
1668 struct fb_var_screeninfo *var = &fbi->fb.var;
1669 struct cpufreq_policy *policy = data;
1670
1671 switch (val) {
1672 case CPUFREQ_ADJUST:
1673 pr_debug("min dma period: %d ps, "
1674 "new clock %d kHz\n", pxafb_display_dma_period(var),
1675 policy->max);
1676
1677 break;
1678 }
1679 return 0;
1680}
1681#endif
1682
1683#ifdef CONFIG_PM
1684
1685
1686
1687
1688static int pxafb_suspend(struct device *dev)
1689{
1690 struct pxafb_info *fbi = dev_get_drvdata(dev);
1691
1692 set_ctrlr_state(fbi, C_DISABLE_PM);
1693 return 0;
1694}
1695
1696static int pxafb_resume(struct device *dev)
1697{
1698 struct pxafb_info *fbi = dev_get_drvdata(dev);
1699
1700 set_ctrlr_state(fbi, C_ENABLE_PM);
1701 return 0;
1702}
1703
1704static const struct dev_pm_ops pxafb_pm_ops = {
1705 .suspend = pxafb_suspend,
1706 .resume = pxafb_resume,
1707};
1708#endif
1709
1710static int pxafb_init_video_memory(struct pxafb_info *fbi)
1711{
1712 int size = PAGE_ALIGN(fbi->video_mem_size);
1713
1714 fbi->video_mem = alloc_pages_exact(size, GFP_KERNEL | __GFP_ZERO);
1715 if (fbi->video_mem == NULL)
1716 return -ENOMEM;
1717
1718 fbi->video_mem_phys = virt_to_phys(fbi->video_mem);
1719 fbi->video_mem_size = size;
1720
1721 fbi->fb.fix.smem_start = fbi->video_mem_phys;
1722 fbi->fb.fix.smem_len = fbi->video_mem_size;
1723 fbi->fb.screen_base = fbi->video_mem;
1724
1725 return fbi->video_mem ? 0 : -ENOMEM;
1726}
1727
1728static void pxafb_decode_mach_info(struct pxafb_info *fbi,
1729 struct pxafb_mach_info *inf)
1730{
1731 unsigned int lcd_conn = inf->lcd_conn;
1732 struct pxafb_mode_info *m;
1733 int i;
1734
1735 fbi->cmap_inverse = inf->cmap_inverse;
1736 fbi->cmap_static = inf->cmap_static;
1737 fbi->lccr4 = inf->lccr4;
1738
1739 switch (lcd_conn & LCD_TYPE_MASK) {
1740 case LCD_TYPE_MONO_STN:
1741 fbi->lccr0 = LCCR0_CMS;
1742 break;
1743 case LCD_TYPE_MONO_DSTN:
1744 fbi->lccr0 = LCCR0_CMS | LCCR0_SDS;
1745 break;
1746 case LCD_TYPE_COLOR_STN:
1747 fbi->lccr0 = 0;
1748 break;
1749 case LCD_TYPE_COLOR_DSTN:
1750 fbi->lccr0 = LCCR0_SDS;
1751 break;
1752 case LCD_TYPE_COLOR_TFT:
1753 fbi->lccr0 = LCCR0_PAS;
1754 break;
1755 case LCD_TYPE_SMART_PANEL:
1756 fbi->lccr0 = LCCR0_LCDT | LCCR0_PAS;
1757 break;
1758 default:
1759
1760 fbi->lccr0 = inf->lccr0;
1761 fbi->lccr3 = inf->lccr3;
1762 goto decode_mode;
1763 }
1764
1765 if (lcd_conn == LCD_MONO_STN_8BPP)
1766 fbi->lccr0 |= LCCR0_DPD;
1767
1768 fbi->lccr0 |= (lcd_conn & LCD_ALTERNATE_MAPPING) ? LCCR0_LDDALT : 0;
1769
1770 fbi->lccr3 = LCCR3_Acb((inf->lcd_conn >> 10) & 0xff);
1771 fbi->lccr3 |= (lcd_conn & LCD_BIAS_ACTIVE_LOW) ? LCCR3_OEP : 0;
1772 fbi->lccr3 |= (lcd_conn & LCD_PCLK_EDGE_FALL) ? LCCR3_PCP : 0;
1773
1774decode_mode:
1775 pxafb_setmode(&fbi->fb.var, &inf->modes[0]);
1776
1777
1778
1779
1780
1781
1782 for (i = 0, m = &inf->modes[0]; i < inf->num_modes; i++, m++)
1783 fbi->video_mem_size = max_t(size_t, fbi->video_mem_size,
1784 m->xres * m->yres * m->bpp / 8);
1785
1786 if (inf->video_mem_size > fbi->video_mem_size)
1787 fbi->video_mem_size = inf->video_mem_size;
1788
1789 if (video_mem_size > fbi->video_mem_size)
1790 fbi->video_mem_size = video_mem_size;
1791}
1792
1793static struct pxafb_info *pxafb_init_fbinfo(struct device *dev,
1794 struct pxafb_mach_info *inf)
1795{
1796 struct pxafb_info *fbi;
1797 void *addr;
1798
1799
1800 fbi = kmalloc(sizeof(struct pxafb_info) + sizeof(u32) * 16, GFP_KERNEL);
1801 if (!fbi)
1802 return NULL;
1803
1804 memset(fbi, 0, sizeof(struct pxafb_info));
1805 fbi->dev = dev;
1806 fbi->inf = inf;
1807
1808 fbi->clk = clk_get(dev, NULL);
1809 if (IS_ERR(fbi->clk)) {
1810 kfree(fbi);
1811 return NULL;
1812 }
1813
1814 strcpy(fbi->fb.fix.id, PXA_NAME);
1815
1816 fbi->fb.fix.type = FB_TYPE_PACKED_PIXELS;
1817 fbi->fb.fix.type_aux = 0;
1818 fbi->fb.fix.xpanstep = 0;
1819 fbi->fb.fix.ypanstep = 1;
1820 fbi->fb.fix.ywrapstep = 0;
1821 fbi->fb.fix.accel = FB_ACCEL_NONE;
1822
1823 fbi->fb.var.nonstd = 0;
1824 fbi->fb.var.activate = FB_ACTIVATE_NOW;
1825 fbi->fb.var.height = -1;
1826 fbi->fb.var.width = -1;
1827 fbi->fb.var.accel_flags = FB_ACCELF_TEXT;
1828 fbi->fb.var.vmode = FB_VMODE_NONINTERLACED;
1829
1830 fbi->fb.fbops = &pxafb_ops;
1831 fbi->fb.flags = FBINFO_DEFAULT;
1832 fbi->fb.node = -1;
1833
1834 addr = fbi;
1835 addr = addr + sizeof(struct pxafb_info);
1836 fbi->fb.pseudo_palette = addr;
1837
1838 fbi->state = C_STARTUP;
1839 fbi->task_state = (u_char)-1;
1840
1841 pxafb_decode_mach_info(fbi, inf);
1842
1843#ifdef CONFIG_FB_PXA_OVERLAY
1844
1845 if (pxafb_overlay_supported())
1846 fbi->lccr0 |= LCCR0_OUC;
1847#endif
1848
1849 init_waitqueue_head(&fbi->ctrlr_wait);
1850 INIT_WORK(&fbi->task, pxafb_task);
1851 mutex_init(&fbi->ctrlr_lock);
1852 init_completion(&fbi->disable_done);
1853
1854 return fbi;
1855}
1856
1857#ifdef CONFIG_FB_PXA_PARAMETERS
1858static int parse_opt_mode(struct device *dev, const char *this_opt,
1859 struct pxafb_mach_info *inf)
1860{
1861 const char *name = this_opt+5;
1862 unsigned int namelen = strlen(name);
1863 int res_specified = 0, bpp_specified = 0;
1864 unsigned int xres = 0, yres = 0, bpp = 0;
1865 int yres_specified = 0;
1866 int i;
1867 for (i = namelen-1; i >= 0; i--) {
1868 switch (name[i]) {
1869 case '-':
1870 namelen = i;
1871 if (!bpp_specified && !yres_specified) {
1872 bpp = simple_strtoul(&name[i+1], NULL, 0);
1873 bpp_specified = 1;
1874 } else
1875 goto done;
1876 break;
1877 case 'x':
1878 if (!yres_specified) {
1879 yres = simple_strtoul(&name[i+1], NULL, 0);
1880 yres_specified = 1;
1881 } else
1882 goto done;
1883 break;
1884 case '0' ... '9':
1885 break;
1886 default:
1887 goto done;
1888 }
1889 }
1890 if (i < 0 && yres_specified) {
1891 xres = simple_strtoul(name, NULL, 0);
1892 res_specified = 1;
1893 }
1894done:
1895 if (res_specified) {
1896 dev_info(dev, "overriding resolution: %dx%d\n", xres, yres);
1897 inf->modes[0].xres = xres; inf->modes[0].yres = yres;
1898 }
1899 if (bpp_specified)
1900 switch (bpp) {
1901 case 1:
1902 case 2:
1903 case 4:
1904 case 8:
1905 case 16:
1906 inf->modes[0].bpp = bpp;
1907 dev_info(dev, "overriding bit depth: %d\n", bpp);
1908 break;
1909 default:
1910 dev_err(dev, "Depth %d is not valid\n", bpp);
1911 return -EINVAL;
1912 }
1913 return 0;
1914}
1915
1916static int parse_opt(struct device *dev, char *this_opt,
1917 struct pxafb_mach_info *inf)
1918{
1919 struct pxafb_mode_info *mode = &inf->modes[0];
1920 char s[64];
1921
1922 s[0] = '\0';
1923
1924 if (!strncmp(this_opt, "vmem:", 5)) {
1925 video_mem_size = memparse(this_opt + 5, NULL);
1926 } else if (!strncmp(this_opt, "mode:", 5)) {
1927 return parse_opt_mode(dev, this_opt, inf);
1928 } else if (!strncmp(this_opt, "pixclock:", 9)) {
1929 mode->pixclock = simple_strtoul(this_opt+9, NULL, 0);
1930 sprintf(s, "pixclock: %ld\n", mode->pixclock);
1931 } else if (!strncmp(this_opt, "left:", 5)) {
1932 mode->left_margin = simple_strtoul(this_opt+5, NULL, 0);
1933 sprintf(s, "left: %u\n", mode->left_margin);
1934 } else if (!strncmp(this_opt, "right:", 6)) {
1935 mode->right_margin = simple_strtoul(this_opt+6, NULL, 0);
1936 sprintf(s, "right: %u\n", mode->right_margin);
1937 } else if (!strncmp(this_opt, "upper:", 6)) {
1938 mode->upper_margin = simple_strtoul(this_opt+6, NULL, 0);
1939 sprintf(s, "upper: %u\n", mode->upper_margin);
1940 } else if (!strncmp(this_opt, "lower:", 6)) {
1941 mode->lower_margin = simple_strtoul(this_opt+6, NULL, 0);
1942 sprintf(s, "lower: %u\n", mode->lower_margin);
1943 } else if (!strncmp(this_opt, "hsynclen:", 9)) {
1944 mode->hsync_len = simple_strtoul(this_opt+9, NULL, 0);
1945 sprintf(s, "hsynclen: %u\n", mode->hsync_len);
1946 } else if (!strncmp(this_opt, "vsynclen:", 9)) {
1947 mode->vsync_len = simple_strtoul(this_opt+9, NULL, 0);
1948 sprintf(s, "vsynclen: %u\n", mode->vsync_len);
1949 } else if (!strncmp(this_opt, "hsync:", 6)) {
1950 if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1951 sprintf(s, "hsync: Active Low\n");
1952 mode->sync &= ~FB_SYNC_HOR_HIGH_ACT;
1953 } else {
1954 sprintf(s, "hsync: Active High\n");
1955 mode->sync |= FB_SYNC_HOR_HIGH_ACT;
1956 }
1957 } else if (!strncmp(this_opt, "vsync:", 6)) {
1958 if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1959 sprintf(s, "vsync: Active Low\n");
1960 mode->sync &= ~FB_SYNC_VERT_HIGH_ACT;
1961 } else {
1962 sprintf(s, "vsync: Active High\n");
1963 mode->sync |= FB_SYNC_VERT_HIGH_ACT;
1964 }
1965 } else if (!strncmp(this_opt, "dpc:", 4)) {
1966 if (simple_strtoul(this_opt+4, NULL, 0) == 0) {
1967 sprintf(s, "double pixel clock: false\n");
1968 inf->lccr3 &= ~LCCR3_DPC;
1969 } else {
1970 sprintf(s, "double pixel clock: true\n");
1971 inf->lccr3 |= LCCR3_DPC;
1972 }
1973 } else if (!strncmp(this_opt, "outputen:", 9)) {
1974 if (simple_strtoul(this_opt+9, NULL, 0) == 0) {
1975 sprintf(s, "output enable: active low\n");
1976 inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnL;
1977 } else {
1978 sprintf(s, "output enable: active high\n");
1979 inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnH;
1980 }
1981 } else if (!strncmp(this_opt, "pixclockpol:", 12)) {
1982 if (simple_strtoul(this_opt+12, NULL, 0) == 0) {
1983 sprintf(s, "pixel clock polarity: falling edge\n");
1984 inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixFlEdg;
1985 } else {
1986 sprintf(s, "pixel clock polarity: rising edge\n");
1987 inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixRsEdg;
1988 }
1989 } else if (!strncmp(this_opt, "color", 5)) {
1990 inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Color;
1991 } else if (!strncmp(this_opt, "mono", 4)) {
1992 inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Mono;
1993 } else if (!strncmp(this_opt, "active", 6)) {
1994 inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Act;
1995 } else if (!strncmp(this_opt, "passive", 7)) {
1996 inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Pas;
1997 } else if (!strncmp(this_opt, "single", 6)) {
1998 inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Sngl;
1999 } else if (!strncmp(this_opt, "dual", 4)) {
2000 inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Dual;
2001 } else if (!strncmp(this_opt, "4pix", 4)) {
2002 inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_4PixMono;
2003 } else if (!strncmp(this_opt, "8pix", 4)) {
2004 inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_8PixMono;
2005 } else {
2006 dev_err(dev, "unknown option: %s\n", this_opt);
2007 return -EINVAL;
2008 }
2009
2010 if (s[0] != '\0')
2011 dev_info(dev, "override %s", s);
2012
2013 return 0;
2014}
2015
2016static int pxafb_parse_options(struct device *dev, char *options,
2017 struct pxafb_mach_info *inf)
2018{
2019 char *this_opt;
2020 int ret;
2021
2022 if (!options || !*options)
2023 return 0;
2024
2025 dev_dbg(dev, "options are \"%s\"\n", options ? options : "null");
2026
2027
2028 while ((this_opt = strsep(&options, ",")) != NULL) {
2029 ret = parse_opt(dev, this_opt, inf);
2030 if (ret)
2031 return ret;
2032 }
2033 return 0;
2034}
2035
2036static char g_options[256] = "";
2037
2038#ifndef MODULE
2039static int __init pxafb_setup_options(void)
2040{
2041 char *options = NULL;
2042
2043 if (fb_get_options("pxafb", &options))
2044 return -ENODEV;
2045
2046 if (options)
2047 strlcpy(g_options, options, sizeof(g_options));
2048
2049 return 0;
2050}
2051#else
2052#define pxafb_setup_options() (0)
2053
2054module_param_string(options, g_options, sizeof(g_options), 0);
2055MODULE_PARM_DESC(options, "LCD parameters (see Documentation/fb/pxafb.txt)");
2056#endif
2057
2058#else
2059#define pxafb_parse_options(...) (0)
2060#define pxafb_setup_options() (0)
2061#endif
2062
2063#ifdef DEBUG_VAR
2064
2065
2066static void pxafb_check_options(struct device *dev, struct pxafb_mach_info *inf)
2067{
2068 if (inf->lcd_conn)
2069 return;
2070
2071 if (inf->lccr0 & LCCR0_INVALID_CONFIG_MASK)
2072 dev_warn(dev, "machine LCCR0 setting contains "
2073 "illegal bits: %08x\n",
2074 inf->lccr0 & LCCR0_INVALID_CONFIG_MASK);
2075 if (inf->lccr3 & LCCR3_INVALID_CONFIG_MASK)
2076 dev_warn(dev, "machine LCCR3 setting contains "
2077 "illegal bits: %08x\n",
2078 inf->lccr3 & LCCR3_INVALID_CONFIG_MASK);
2079 if (inf->lccr0 & LCCR0_DPD &&
2080 ((inf->lccr0 & LCCR0_PAS) != LCCR0_Pas ||
2081 (inf->lccr0 & LCCR0_SDS) != LCCR0_Sngl ||
2082 (inf->lccr0 & LCCR0_CMS) != LCCR0_Mono))
2083 dev_warn(dev, "Double Pixel Data (DPD) mode is "
2084 "only valid in passive mono"
2085 " single panel mode\n");
2086 if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Act &&
2087 (inf->lccr0 & LCCR0_SDS) == LCCR0_Dual)
2088 dev_warn(dev, "Dual panel only valid in passive mode\n");
2089 if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Pas &&
2090 (inf->modes->upper_margin || inf->modes->lower_margin))
2091 dev_warn(dev, "Upper and lower margins must be 0 in "
2092 "passive mode\n");
2093}
2094#else
2095#define pxafb_check_options(...) do {} while (0)
2096#endif
2097
2098#if defined(CONFIG_OF)
2099static const char * const lcd_types[] = {
2100 "unknown", "mono-stn", "mono-dstn", "color-stn", "color-dstn",
2101 "color-tft", "smart-panel", NULL
2102};
2103
2104static int of_get_pxafb_display(struct device *dev, struct device_node *disp,
2105 struct pxafb_mach_info *info, u32 bus_width)
2106{
2107 struct display_timings *timings;
2108 struct videomode vm;
2109 int i, ret = -EINVAL;
2110 const char *s;
2111
2112 ret = of_property_read_string(disp, "lcd-type", &s);
2113 if (ret)
2114 s = "color-tft";
2115
2116 for (i = 0; lcd_types[i]; i++)
2117 if (!strcmp(s, lcd_types[i]))
2118 break;
2119 if (!i || !lcd_types[i]) {
2120 dev_err(dev, "lcd-type %s is unknown\n", s);
2121 return -EINVAL;
2122 }
2123 info->lcd_conn |= LCD_CONN_TYPE(i);
2124 info->lcd_conn |= LCD_CONN_WIDTH(bus_width);
2125
2126 timings = of_get_display_timings(disp);
2127 if (!timings)
2128 goto out;
2129
2130 ret = -ENOMEM;
2131 info->modes = kmalloc_array(timings->num_timings,
2132 sizeof(info->modes[0]), GFP_KERNEL);
2133 if (!info->modes)
2134 goto out;
2135 info->num_modes = timings->num_timings;
2136
2137 for (i = 0; i < timings->num_timings; i++) {
2138 ret = videomode_from_timings(timings, &vm, i);
2139 if (ret) {
2140 dev_err(dev, "videomode_from_timings %d failed: %d\n",
2141 i, ret);
2142 goto out;
2143 }
2144 if (vm.flags & DISPLAY_FLAGS_PIXDATA_POSEDGE)
2145 info->lcd_conn |= LCD_PCLK_EDGE_RISE;
2146 if (vm.flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
2147 info->lcd_conn |= LCD_PCLK_EDGE_FALL;
2148 if (vm.flags & DISPLAY_FLAGS_DE_HIGH)
2149 info->lcd_conn |= LCD_BIAS_ACTIVE_HIGH;
2150 if (vm.flags & DISPLAY_FLAGS_DE_LOW)
2151 info->lcd_conn |= LCD_BIAS_ACTIVE_LOW;
2152 if (vm.flags & DISPLAY_FLAGS_HSYNC_HIGH)
2153 info->modes[i].sync |= FB_SYNC_HOR_HIGH_ACT;
2154 if (vm.flags & DISPLAY_FLAGS_VSYNC_HIGH)
2155 info->modes[i].sync |= FB_SYNC_VERT_HIGH_ACT;
2156
2157 info->modes[i].pixclock = 1000000000UL / (vm.pixelclock / 1000);
2158 info->modes[i].xres = vm.hactive;
2159 info->modes[i].yres = vm.vactive;
2160 info->modes[i].hsync_len = vm.hsync_len;
2161 info->modes[i].left_margin = vm.hback_porch;
2162 info->modes[i].right_margin = vm.hfront_porch;
2163 info->modes[i].vsync_len = vm.vsync_len;
2164 info->modes[i].upper_margin = vm.vback_porch;
2165 info->modes[i].lower_margin = vm.vfront_porch;
2166 }
2167 ret = 0;
2168
2169out:
2170 display_timings_release(timings);
2171 return ret;
2172}
2173
2174static int of_get_pxafb_mode_info(struct device *dev,
2175 struct pxafb_mach_info *info)
2176{
2177 struct device_node *display, *np;
2178 u32 bus_width;
2179 int ret, i;
2180
2181 np = of_graph_get_next_endpoint(dev->of_node, NULL);
2182 if (!np) {
2183 dev_err(dev, "could not find endpoint\n");
2184 return -EINVAL;
2185 }
2186 ret = of_property_read_u32(np, "bus-width", &bus_width);
2187 if (ret) {
2188 dev_err(dev, "no bus-width specified: %d\n", ret);
2189 return ret;
2190 }
2191
2192 display = of_graph_get_remote_port_parent(np);
2193 of_node_put(np);
2194 if (!display) {
2195 dev_err(dev, "no display defined\n");
2196 return -EINVAL;
2197 }
2198
2199 ret = of_get_pxafb_display(dev, display, info, bus_width);
2200 of_node_put(display);
2201 if (ret)
2202 return ret;
2203
2204 for (i = 0; i < info->num_modes; i++)
2205 info->modes[i].bpp = bus_width;
2206
2207 return 0;
2208}
2209
2210static struct pxafb_mach_info *of_pxafb_of_mach_info(struct device *dev)
2211{
2212 int ret;
2213 struct pxafb_mach_info *info;
2214
2215 if (!dev->of_node)
2216 return NULL;
2217 info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
2218 if (!info)
2219 return ERR_PTR(-ENOMEM);
2220 ret = of_get_pxafb_mode_info(dev, info);
2221 if (ret) {
2222 kfree(info->modes);
2223 return ERR_PTR(ret);
2224 }
2225
2226
2227
2228
2229
2230
2231 return info;
2232}
2233#else
2234static struct pxafb_mach_info *of_pxafb_of_mach_info(struct device *dev)
2235{
2236 return NULL;
2237}
2238#endif
2239
2240static int pxafb_probe(struct platform_device *dev)
2241{
2242 struct pxafb_info *fbi;
2243 struct pxafb_mach_info *inf, *pdata;
2244 struct resource *r;
2245 int i, irq, ret;
2246
2247 dev_dbg(&dev->dev, "pxafb_probe\n");
2248
2249 ret = -ENOMEM;
2250 pdata = dev_get_platdata(&dev->dev);
2251 inf = devm_kmalloc(&dev->dev, sizeof(*inf), GFP_KERNEL);
2252 if (!inf)
2253 goto failed;
2254
2255 if (pdata) {
2256 *inf = *pdata;
2257 inf->modes =
2258 devm_kmalloc_array(&dev->dev, pdata->num_modes,
2259 sizeof(inf->modes[0]), GFP_KERNEL);
2260 if (!inf->modes)
2261 goto failed;
2262 for (i = 0; i < inf->num_modes; i++)
2263 inf->modes[i] = pdata->modes[i];
2264 }
2265
2266 if (!pdata)
2267 inf = of_pxafb_of_mach_info(&dev->dev);
2268 if (IS_ERR_OR_NULL(inf))
2269 goto failed;
2270
2271 ret = pxafb_parse_options(&dev->dev, g_options, inf);
2272 if (ret < 0)
2273 goto failed;
2274
2275 pxafb_check_options(&dev->dev, inf);
2276
2277 dev_dbg(&dev->dev, "got a %dx%dx%d LCD\n",
2278 inf->modes->xres,
2279 inf->modes->yres,
2280 inf->modes->bpp);
2281 if (inf->modes->xres == 0 ||
2282 inf->modes->yres == 0 ||
2283 inf->modes->bpp == 0) {
2284 dev_err(&dev->dev, "Invalid resolution or bit depth\n");
2285 ret = -EINVAL;
2286 goto failed;
2287 }
2288
2289 fbi = pxafb_init_fbinfo(&dev->dev, inf);
2290 if (!fbi) {
2291
2292 dev_err(&dev->dev, "Failed to initialize framebuffer device\n");
2293 ret = -ENOMEM;
2294 goto failed;
2295 }
2296
2297 if (cpu_is_pxa3xx() && inf->acceleration_enabled)
2298 fbi->fb.fix.accel = FB_ACCEL_PXA3XX;
2299
2300 fbi->backlight_power = inf->pxafb_backlight_power;
2301 fbi->lcd_power = inf->pxafb_lcd_power;
2302
2303 r = platform_get_resource(dev, IORESOURCE_MEM, 0);
2304 if (r == NULL) {
2305 dev_err(&dev->dev, "no I/O memory resource defined\n");
2306 ret = -ENODEV;
2307 goto failed_fbi;
2308 }
2309
2310 r = request_mem_region(r->start, resource_size(r), dev->name);
2311 if (r == NULL) {
2312 dev_err(&dev->dev, "failed to request I/O memory\n");
2313 ret = -EBUSY;
2314 goto failed_fbi;
2315 }
2316
2317 fbi->mmio_base = ioremap(r->start, resource_size(r));
2318 if (fbi->mmio_base == NULL) {
2319 dev_err(&dev->dev, "failed to map I/O memory\n");
2320 ret = -EBUSY;
2321 goto failed_free_res;
2322 }
2323
2324 fbi->dma_buff_size = PAGE_ALIGN(sizeof(struct pxafb_dma_buff));
2325 fbi->dma_buff = dma_alloc_coherent(fbi->dev, fbi->dma_buff_size,
2326 &fbi->dma_buff_phys, GFP_KERNEL);
2327 if (fbi->dma_buff == NULL) {
2328 dev_err(&dev->dev, "failed to allocate memory for DMA\n");
2329 ret = -ENOMEM;
2330 goto failed_free_io;
2331 }
2332
2333 ret = pxafb_init_video_memory(fbi);
2334 if (ret) {
2335 dev_err(&dev->dev, "Failed to allocate video RAM: %d\n", ret);
2336 ret = -ENOMEM;
2337 goto failed_free_dma;
2338 }
2339
2340 irq = platform_get_irq(dev, 0);
2341 if (irq < 0) {
2342 dev_err(&dev->dev, "no IRQ defined\n");
2343 ret = -ENODEV;
2344 goto failed_free_mem;
2345 }
2346
2347 ret = request_irq(irq, pxafb_handle_irq, 0, "LCD", fbi);
2348 if (ret) {
2349 dev_err(&dev->dev, "request_irq failed: %d\n", ret);
2350 ret = -EBUSY;
2351 goto failed_free_mem;
2352 }
2353
2354 ret = pxafb_smart_init(fbi);
2355 if (ret) {
2356 dev_err(&dev->dev, "failed to initialize smartpanel\n");
2357 goto failed_free_irq;
2358 }
2359
2360
2361
2362
2363
2364 ret = pxafb_check_var(&fbi->fb.var, &fbi->fb);
2365 if (ret) {
2366 dev_err(&dev->dev, "failed to get suitable mode\n");
2367 goto failed_free_irq;
2368 }
2369
2370 ret = pxafb_set_par(&fbi->fb);
2371 if (ret) {
2372 dev_err(&dev->dev, "Failed to set parameters\n");
2373 goto failed_free_irq;
2374 }
2375
2376 platform_set_drvdata(dev, fbi);
2377
2378 ret = register_framebuffer(&fbi->fb);
2379 if (ret < 0) {
2380 dev_err(&dev->dev,
2381 "Failed to register framebuffer device: %d\n", ret);
2382 goto failed_free_cmap;
2383 }
2384
2385 pxafb_overlay_init(fbi);
2386
2387#ifdef CONFIG_CPU_FREQ
2388 fbi->freq_transition.notifier_call = pxafb_freq_transition;
2389 fbi->freq_policy.notifier_call = pxafb_freq_policy;
2390 cpufreq_register_notifier(&fbi->freq_transition,
2391 CPUFREQ_TRANSITION_NOTIFIER);
2392 cpufreq_register_notifier(&fbi->freq_policy,
2393 CPUFREQ_POLICY_NOTIFIER);
2394#endif
2395
2396
2397
2398
2399 set_ctrlr_state(fbi, C_ENABLE);
2400
2401 return 0;
2402
2403failed_free_cmap:
2404 if (fbi->fb.cmap.len)
2405 fb_dealloc_cmap(&fbi->fb.cmap);
2406failed_free_irq:
2407 free_irq(irq, fbi);
2408failed_free_mem:
2409 free_pages_exact(fbi->video_mem, fbi->video_mem_size);
2410failed_free_dma:
2411 dma_free_coherent(&dev->dev, fbi->dma_buff_size,
2412 fbi->dma_buff, fbi->dma_buff_phys);
2413failed_free_io:
2414 iounmap(fbi->mmio_base);
2415failed_free_res:
2416 release_mem_region(r->start, resource_size(r));
2417failed_fbi:
2418 clk_put(fbi->clk);
2419 kfree(fbi);
2420failed:
2421 return ret;
2422}
2423
2424static int pxafb_remove(struct platform_device *dev)
2425{
2426 struct pxafb_info *fbi = platform_get_drvdata(dev);
2427 struct resource *r;
2428 int irq;
2429 struct fb_info *info;
2430
2431 if (!fbi)
2432 return 0;
2433
2434 info = &fbi->fb;
2435
2436 pxafb_overlay_exit(fbi);
2437 unregister_framebuffer(info);
2438
2439 pxafb_disable_controller(fbi);
2440
2441 if (fbi->fb.cmap.len)
2442 fb_dealloc_cmap(&fbi->fb.cmap);
2443
2444 irq = platform_get_irq(dev, 0);
2445 free_irq(irq, fbi);
2446
2447 free_pages_exact(fbi->video_mem, fbi->video_mem_size);
2448
2449 dma_free_writecombine(&dev->dev, fbi->dma_buff_size,
2450 fbi->dma_buff, fbi->dma_buff_phys);
2451
2452 iounmap(fbi->mmio_base);
2453
2454 r = platform_get_resource(dev, IORESOURCE_MEM, 0);
2455 release_mem_region(r->start, resource_size(r));
2456
2457 clk_put(fbi->clk);
2458 kfree(fbi);
2459
2460 return 0;
2461}
2462
2463static const struct of_device_id pxafb_of_dev_id[] = {
2464 { .compatible = "marvell,pxa270-lcdc", },
2465 { .compatible = "marvell,pxa300-lcdc", },
2466 { .compatible = "marvell,pxa2xx-lcdc", },
2467 { }
2468};
2469MODULE_DEVICE_TABLE(of, pxafb_of_dev_id);
2470
2471static struct platform_driver pxafb_driver = {
2472 .probe = pxafb_probe,
2473 .remove = pxafb_remove,
2474 .driver = {
2475 .name = "pxa2xx-fb",
2476 .of_match_table = pxafb_of_dev_id,
2477#ifdef CONFIG_PM
2478 .pm = &pxafb_pm_ops,
2479#endif
2480 },
2481};
2482
2483static int __init pxafb_init(void)
2484{
2485 if (pxafb_setup_options())
2486 return -EINVAL;
2487
2488 return platform_driver_register(&pxafb_driver);
2489}
2490
2491static void __exit pxafb_exit(void)
2492{
2493 platform_driver_unregister(&pxafb_driver);
2494}
2495
2496module_init(pxafb_init);
2497module_exit(pxafb_exit);
2498
2499MODULE_DESCRIPTION("loadable framebuffer driver for PXA");
2500MODULE_LICENSE("GPL");
2501