LXR linux/drivers/watchdog/w83627hf

   1/*
   2 *      w83627hf/thf WDT driver
   3 *
   4 *      (c) Copyright 2013 Guenter Roeck
   5 *              converted to watchdog infrastructure
   6 *
   7 *      (c) Copyright 2007 Vlad Drukker <vlad@storewiz.com>
   8 *              added support for W83627THF.
   9 *
  10 *      (c) Copyright 2003,2007 Pádraig Brady <P@draigBrady.com>
  11 *
  12 *      Based on advantechwdt.c which is based on wdt.c.
  13 *      Original copyright messages:
  14 *
  15 *      (c) Copyright 2000-2001 Marek Michalkiewicz <marekm@linux.org.pl>
  16 *
  17 *      (c) Copyright 1996 Alan Cox <alan@lxorguk.ukuu.org.uk>,
  18 *                                              All Rights Reserved.
  19 *
  20 *      This program is free software; you can redistribute it and/or
  21 *      modify it under the terms of the GNU General Public License
  22 *      as published by the Free Software Foundation; either version
  23 *      2 of the License, or (at your option) any later version.
  24 *
  25 *      Neither Alan Cox nor CymruNet Ltd. admit liability nor provide
  26 *      warranty for any of this software. This material is provided
  27 *      "AS-IS" and at no charge.
  28 *
  29 *      (c) Copyright 1995    Alan Cox <alan@lxorguk.ukuu.org.uk>
  30 */
  31
  32#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  33
  34#include <linux/module.h>
  35#include <linux/moduleparam.h>
  36#include <linux/types.h>
  37#include <linux/watchdog.h>
  38#include <linux/ioport.h>
  39#include <linux/init.h>
  40#include <linux/io.h>
  41
  42#define WATCHDOG_NAME "w83627hf/thf/hg/dhg WDT"
  43#define WATCHDOG_TIMEOUT 60             /* 60 sec default timeout */
  44
  45static int wdt_io;
  46static int cr_wdt_timeout;      /* WDT timeout register */
  47static int cr_wdt_control;      /* WDT control register */
  48
  49enum chips { w83627hf, w83627s, w83697hf, w83697ug, w83637hf, w83627thf,
  50             w83687thf, w83627ehf, w83627dhg, w83627uhg, w83667hg, w83627dhg_p,
  51             w83667hg_b, nct6775, nct6776, nct6779, nct6791, nct6792 };
  52
  53static int timeout;                     /* in seconds */
  54module_param(timeout, int, 0);
  55MODULE_PARM_DESC(timeout,
  56                "Watchdog timeout in seconds. 1 <= timeout <= 255, default="
  57                                __MODULE_STRING(WATCHDOG_TIMEOUT) ".");
  58
  59static bool nowayout = WATCHDOG_NOWAYOUT;
  60module_param(nowayout, bool, 0);
  61MODULE_PARM_DESC(nowayout,
  62                "Watchdog cannot be stopped once started (default="
  63                                __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
  64
  65static int early_disable;
  66module_param(early_disable, int, 0);
  67MODULE_PARM_DESC(early_disable, "Disable watchdog at boot time (default=0)");
  68
  69/*
  70 *      Kernel methods.
  71 */
  72
  73#define WDT_EFER (wdt_io+0)   /* Extended Function Enable Registers */
  74#define WDT_EFIR (wdt_io+0)   /* Extended Function Index Register
  75                                                        (same as EFER) */
  76#define WDT_EFDR (WDT_EFIR+1) /* Extended Function Data Register */
  77
  78#define W83627HF_LD_WDT         0x08
  79
  80#define W83627HF_ID             0x52
  81#define W83627S_ID              0x59
  82#define W83697HF_ID             0x60
  83#define W83697UG_ID             0x68
  84#define W83637HF_ID             0x70
  85#define W83627THF_ID            0x82
  86#define W83687THF_ID            0x85
  87#define W83627EHF_ID            0x88
  88#define W83627DHG_ID            0xa0
  89#define W83627UHG_ID            0xa2
  90#define W83667HG_ID             0xa5
  91#define W83627DHG_P_ID          0xb0
  92#define W83667HG_B_ID           0xb3
  93#define NCT6775_ID              0xb4
  94#define NCT6776_ID              0xc3
  95#define NCT6779_ID              0xc5
  96#define NCT6791_ID              0xc8
  97#define NCT6792_ID              0xc9
  98
  99#define W83627HF_WDT_TIMEOUT    0xf6
 100#define W83697HF_WDT_TIMEOUT    0xf4
 101
 102#define W83627HF_WDT_CONTROL    0xf5
 103#define W83697HF_WDT_CONTROL    0xf3
 104
 105static void superio_outb(int reg, int val)
 106{
 107        outb(reg, WDT_EFER);
 108        outb(val, WDT_EFDR);
 109}
 110
 111static inline int superio_inb(int reg)
 112{
 113        outb(reg, WDT_EFER);
 114        return inb(WDT_EFDR);
 115}
 116
 117static int superio_enter(void)
 118{
 119        if (!request_muxed_region(wdt_io, 2, WATCHDOG_NAME))
 120                return -EBUSY;
 121
 122        outb_p(0x87, WDT_EFER); /* Enter extended function mode */
 123        outb_p(0x87, WDT_EFER); /* Again according to manual */
 124
 125        return 0;
 126}
 127
 128static void superio_select(int ld)
 129{
 130        superio_outb(0x07, ld);
 131}
 132
 133static void superio_exit(void)
 134{
 135        outb_p(0xAA, WDT_EFER); /* Leave extended function mode */
 136        release_region(wdt_io, 2);
 137}
 138
 139static int w83627hf_init(struct watchdog_device *wdog, enum chips chip)
 140{
 141        int ret;
 142        unsigned char t;
 143
 144        ret = superio_enter();
 145        if (ret)
 146                return ret;
 147
 148        superio_select(W83627HF_LD_WDT);
 149
 150        /* set CR30 bit 0 to activate GPIO2 */
 151        t = superio_inb(0x30);
 152        if (!(t & 0x01))
 153                superio_outb(0x30, t | 0x01);
 154
 155        switch (chip) {
 156        case w83627hf:
 157        case w83627s:
 158                t = superio_inb(0x2B) & ~0x10;
 159                superio_outb(0x2B, t); /* set GPIO24 to WDT0 */
 160                break;
 161        case w83697hf:
 162                /* Set pin 119 to WDTO# mode (= CR29, WDT0) */
 163                t = superio_inb(0x29) & ~0x60;
 164                t |= 0x20;
 165                superio_outb(0x29, t);
 166                break;
 167        case w83697ug:
 168                /* Set pin 118 to WDTO# mode */
 169                t = superio_inb(0x2b) & ~0x04;
 170                superio_outb(0x2b, t);
 171                break;
 172        case w83627thf:
 173                t = (superio_inb(0x2B) & ~0x08) | 0x04;
 174                superio_outb(0x2B, t); /* set GPIO3 to WDT0 */
 175                break;
 176        case w83627dhg:
 177        case w83627dhg_p:
 178                t = superio_inb(0x2D) & ~0x01; /* PIN77 -> WDT0# */
 179                superio_outb(0x2D, t); /* set GPIO5 to WDT0 */
 180                t = superio_inb(cr_wdt_control);
 181                t |= 0x02;      /* enable the WDTO# output low pulse
 182                                 * to the KBRST# pin */
 183                superio_outb(cr_wdt_control, t);
 184                break;
 185        case w83637hf:
 186                break;
 187        case w83687thf:
 188                t = superio_inb(0x2C) & ~0x80; /* PIN47 -> WDT0# */
 189                superio_outb(0x2C, t);
 190                break;
 191        case w83627ehf:
 192        case w83627uhg:
 193        case w83667hg:
 194        case w83667hg_b:
 195        case nct6775:
 196        case nct6776:
 197        case nct6779:
 198        case nct6791:
 199        case nct6792:
 200                /*
 201                 * These chips have a fixed WDTO# output pin (W83627UHG),
 202                 * or support more than one WDTO# output pin.
 203                 * Don't touch its configuration, and hope the BIOS
 204                 * does the right thing.
 205                 */
 206                t = superio_inb(cr_wdt_control);
 207                t |= 0x02;      /* enable the WDTO# output low pulse
 208                                 * to the KBRST# pin */
 209                superio_outb(cr_wdt_control, t);
 210                break;
 211        default:
 212                break;
 213        }
 214
 215        t = superio_inb(cr_wdt_timeout);
 216        if (t != 0) {
 217                if (early_disable) {
 218                        pr_warn("Stopping previously enabled watchdog until userland kicks in\n");
 219                        superio_outb(cr_wdt_timeout, 0);
 220                } else {
 221                        pr_info("Watchdog already running. Resetting timeout to %d sec\n",
 222                                wdog->timeout);
 223                        superio_outb(cr_wdt_timeout, wdog->timeout);
 224                }
 225        }
 226
 227        /* set second mode & disable keyboard turning off watchdog */
 228        t = superio_inb(cr_wdt_control) & ~0x0C;
 229        superio_outb(cr_wdt_control, t);
 230
 231        /* reset trigger, disable keyboard & mouse turning off watchdog */
 232        t = superio_inb(0xF7) & ~0xD0;
 233        superio_outb(0xF7, t);
 234
 235        superio_exit();
 236
 237        return 0;
 238}
 239
 240static int wdt_set_time(unsigned int timeout)
 241{
 242        int ret;
 243
 244        ret = superio_enter();
 245        if (ret)
 246                return ret;
 247
 248        superio_select(W83627HF_LD_WDT);
 249        superio_outb(cr_wdt_timeout, timeout);
 250        superio_exit();
 251
 252        return 0;
 253}
 254
 255static int wdt_start(struct watchdog_device *wdog)
 256{
 257        return wdt_set_time(wdog->timeout);
 258}
 259
 260static int wdt_stop(struct watchdog_device *wdog)
 261{
 262        return wdt_set_time(0);
 263}
 264
 265static int wdt_set_timeout(struct watchdog_device *wdog, unsigned int timeout)
 266{
 267        wdog->timeout = timeout;
 268
 269        return 0;
 270}
 271
 272static unsigned int wdt_get_time(struct watchdog_device *wdog)
 273{
 274        unsigned int timeleft;
 275        int ret;
 276
 277        ret = superio_enter();
 278        if (ret)
 279                return 0;
 280
 281        superio_select(W83627HF_LD_WDT);
 282        timeleft = superio_inb(cr_wdt_timeout);
 283        superio_exit();
 284
 285        return timeleft;
 286}
 287
 288/*
 289 *      Kernel Interfaces
 290 */
 291
 292static struct watchdog_info wdt_info = {
 293        .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
 294        .identity = "W83627HF Watchdog",
 295};
 296
 297static struct watchdog_ops wdt_ops = {
 298        .owner = THIS_MODULE,
 299        .start = wdt_start,
 300        .stop = wdt_stop,
 301        .set_timeout = wdt_set_timeout,
 302        .get_timeleft = wdt_get_time,
 303};
 304
 305static struct watchdog_device wdt_dev = {
 306        .info = &wdt_info,
 307        .ops = &wdt_ops,
 308        .timeout = WATCHDOG_TIMEOUT,
 309        .min_timeout = 1,
 310        .max_timeout = 255,
 311};
 312
 313/*
 314 *      The WDT needs to learn about soft shutdowns in order to
 315 *      turn the timebomb registers off.
 316 */
 317
 318static int wdt_find(int addr)
 319{
 320        u8 val;
 321        int ret;
 322
 323        cr_wdt_timeout = W83627HF_WDT_TIMEOUT;
 324        cr_wdt_control = W83627HF_WDT_CONTROL;
 325
 326        ret = superio_enter();
 327        if (ret)
 328                return ret;
 329        superio_select(W83627HF_LD_WDT);
 330        val = superio_inb(0x20);
 331        switch (val) {
 332        case W83627HF_ID:
 333                ret = w83627hf;
 334                break;
 335        case W83627S_ID:
 336                ret = w83627s;
 337                break;
 338        case W83697HF_ID:
 339                ret = w83697hf;
 340                cr_wdt_timeout = W83697HF_WDT_TIMEOUT;
 341                cr_wdt_control = W83697HF_WDT_CONTROL;
 342                break;
 343        case W83697UG_ID:
 344                ret = w83697ug;
 345                cr_wdt_timeout = W83697HF_WDT_TIMEOUT;
 346                cr_wdt_control = W83697HF_WDT_CONTROL;
 347                break;
 348        case W83637HF_ID:
 349                ret = w83637hf;
 350                break;
 351        case W83627THF_ID:
 352                ret = w83627thf;
 353                break;
 354        case W83687THF_ID:
 355                ret = w83687thf;
 356                break;
 357        case W83627EHF_ID:
 358                ret = w83627ehf;
 359                break;
 360        case W83627DHG_ID:
 361                ret = w83627dhg;
 362                break;
 363        case W83627DHG_P_ID:
 364                ret = w83627dhg_p;
 365                break;
 366        case W83627UHG_ID:
 367                ret = w83627uhg;
 368                break;
 369        case W83667HG_ID:
 370                ret = w83667hg;
 371                break;
 372        case W83667HG_B_ID:
 373                ret = w83667hg_b;
 374                break;
 375        case NCT6775_ID:
 376                ret = nct6775;
 377                break;
 378        case NCT6776_ID:
 379                ret = nct6776;
 380                break;
 381        case NCT6779_ID:
 382                ret = nct6779;
 383                break;
 384        case NCT6791_ID:
 385                ret = nct6791;
 386                break;
 387        case NCT6792_ID:
 388                ret = nct6792;
 389                break;
 390        case 0xff:
 391                ret = -ENODEV;
 392                break;
 393        default:
 394                ret = -ENODEV;
 395                pr_err("Unsupported chip ID: 0x%02x\n", val);
 396                break;
 397        }
 398        superio_exit();
 399        return ret;
 400}
 401
 402static int __init wdt_init(void)
 403{
 404        int ret;
 405        int chip;
 406        const char * const chip_name[] = {
 407                "W83627HF",
 408                "W83627S",
 409                "W83697HF",
 410                "W83697UG",
 411                "W83637HF",
 412                "W83627THF",
 413                "W83687THF",
 414                "W83627EHF",
 415                "W83627DHG",
 416                "W83627UHG",
 417                "W83667HG",
 418                "W83667DHG-P",
 419                "W83667HG-B",
 420                "NCT6775",
 421                "NCT6776",
 422                "NCT6779",
 423                "NCT6791",
 424                "NCT6792",
 425        };
 426
 427        wdt_io = 0x2e;
 428        chip = wdt_find(0x2e);
 429        if (chip < 0) {
 430                wdt_io = 0x4e;
 431                chip = wdt_find(0x4e);
 432                if (chip < 0)
 433                        return chip;
 434        }
 435
 436        pr_info("WDT driver for %s Super I/O chip initialising\n",
 437                chip_name[chip]);
 438
 439        watchdog_init_timeout(&wdt_dev, timeout, NULL);
 440        watchdog_set_nowayout(&wdt_dev, nowayout);
 441        watchdog_stop_on_reboot(&wdt_dev);
 442
 443        ret = w83627hf_init(&wdt_dev, chip);
 444        if (ret) {
 445                pr_err("failed to initialize watchdog (err=%d)\n", ret);
 446                return ret;
 447        }
 448
 449        ret = watchdog_register_device(&wdt_dev);
 450        if (ret)
 451                return ret;
 452
 453        pr_info("initialized. timeout=%d sec (nowayout=%d)\n",
 454                wdt_dev.timeout, nowayout);
 455
 456        return ret;
 457}
 458
 459static void __exit wdt_exit(void)
 460{
 461        watchdog_unregister_device(&wdt_dev);
 462}
 463
 464module_init(wdt_init);
 465module_exit(wdt_exit);
 466
 467MODULE_LICENSE("GPL");
 468MODULE_AUTHOR("Pádraig  Brady <P@draigBrady.com>");
 469MODULE_DESCRIPTION("w83627hf/thf WDT driver");
 470