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22#ifndef _UAPI__SOUND_EMU10K1_H
23#define _UAPI__SOUND_EMU10K1_H
24
25#include <linux/types.h>
26#include <sound/asound.h>
27
28
29
30
31
32#define EMU10K1_CARD_CREATIVE 0x00000000
33#define EMU10K1_CARD_EMUAPS 0x00000001
34
35#define EMU10K1_FX8010_PCM_COUNT 8
36
37
38
39
40
41
42#define __EMU10K1_DECLARE_BITMAP(name,bits) \
43 unsigned long name[(bits) / (sizeof(unsigned long) * 8)]
44
45
46#define iMAC0 0x00
47#define iMAC1 0x01
48#define iMAC2 0x02
49#define iMAC3 0x03
50#define iMACINT0 0x04
51#define iMACINT1 0x05
52#define iACC3 0x06
53#define iMACMV 0x07
54#define iANDXOR 0x08
55#define iTSTNEG 0x09
56#define iLIMITGE 0x0a
57#define iLIMITLT 0x0b
58#define iLOG 0x0c
59#define iEXP 0x0d
60#define iINTERP 0x0e
61#define iSKIP 0x0f
62
63
64#define FXBUS(x) (0x00 + (x))
65#define EXTIN(x) (0x10 + (x))
66#define EXTOUT(x) (0x20 + (x))
67#define FXBUS2(x) (0x30 + (x))
68
69
70#define C_00000000 0x40
71#define C_00000001 0x41
72#define C_00000002 0x42
73#define C_00000003 0x43
74#define C_00000004 0x44
75#define C_00000008 0x45
76#define C_00000010 0x46
77#define C_00000020 0x47
78#define C_00000100 0x48
79#define C_00010000 0x49
80#define C_00080000 0x4a
81#define C_10000000 0x4b
82#define C_20000000 0x4c
83#define C_40000000 0x4d
84#define C_80000000 0x4e
85#define C_7fffffff 0x4f
86#define C_ffffffff 0x50
87#define C_fffffffe 0x51
88#define C_c0000000 0x52
89#define C_4f1bbcdc 0x53
90#define C_5a7ef9db 0x54
91#define C_00100000 0x55
92#define GPR_ACCU 0x56
93#define GPR_COND 0x57
94#define GPR_NOISE0 0x58
95#define GPR_NOISE1 0x59
96#define GPR_IRQ 0x5a
97#define GPR_DBAC 0x5b
98#define GPR(x) (FXGPREGBASE + (x))
99#define ITRAM_DATA(x) (TANKMEMDATAREGBASE + 0x00 + (x))
100#define ETRAM_DATA(x) (TANKMEMDATAREGBASE + 0x80 + (x))
101#define ITRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x00 + (x))
102#define ETRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x80 + (x))
103
104#define A_ITRAM_DATA(x) (TANKMEMDATAREGBASE + 0x00 + (x))
105#define A_ETRAM_DATA(x) (TANKMEMDATAREGBASE + 0xc0 + (x))
106#define A_ITRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x00 + (x))
107#define A_ETRAM_ADDR(x) (TANKMEMADDRREGBASE + 0xc0 + (x))
108#define A_ITRAM_CTL(x) (A_TANKMEMCTLREGBASE + 0x00 + (x))
109#define A_ETRAM_CTL(x) (A_TANKMEMCTLREGBASE + 0xc0 + (x))
110
111#define A_FXBUS(x) (0x00 + (x))
112#define A_EXTIN(x) (0x40 + (x))
113#define A_P16VIN(x) (0x50 + (x))
114#define A_EXTOUT(x) (0x60 + (x))
115#define A_FXBUS2(x) (0x80 + (x))
116#define A_EMU32OUTH(x) (0xa0 + (x))
117#define A_EMU32OUTL(x) (0xb0 + (x))
118#define A3_EMU32IN(x) (0x160 + (x))
119#define A3_EMU32OUT(x) (0x1E0 + (x))
120#define A_GPR(x) (A_FXGPREGBASE + (x))
121
122
123#define CC_REG_NORMALIZED C_00000001
124#define CC_REG_BORROW C_00000002
125#define CC_REG_MINUS C_00000004
126#define CC_REG_ZERO C_00000008
127#define CC_REG_SATURATE C_00000010
128#define CC_REG_NONZERO C_00000100
129
130
131#define FXBUS_PCM_LEFT 0x00
132#define FXBUS_PCM_RIGHT 0x01
133#define FXBUS_PCM_LEFT_REAR 0x02
134#define FXBUS_PCM_RIGHT_REAR 0x03
135#define FXBUS_MIDI_LEFT 0x04
136#define FXBUS_MIDI_RIGHT 0x05
137#define FXBUS_PCM_CENTER 0x06
138#define FXBUS_PCM_LFE 0x07
139#define FXBUS_PCM_LEFT_FRONT 0x08
140#define FXBUS_PCM_RIGHT_FRONT 0x09
141#define FXBUS_MIDI_REVERB 0x0c
142#define FXBUS_MIDI_CHORUS 0x0d
143#define FXBUS_PCM_LEFT_SIDE 0x0e
144#define FXBUS_PCM_RIGHT_SIDE 0x0f
145#define FXBUS_PT_LEFT 0x14
146#define FXBUS_PT_RIGHT 0x15
147
148
149#define EXTIN_AC97_L 0x00
150#define EXTIN_AC97_R 0x01
151#define EXTIN_SPDIF_CD_L 0x02
152#define EXTIN_SPDIF_CD_R 0x03
153#define EXTIN_ZOOM_L 0x04
154#define EXTIN_ZOOM_R 0x05
155#define EXTIN_TOSLINK_L 0x06
156#define EXTIN_TOSLINK_R 0x07
157#define EXTIN_LINE1_L 0x08
158#define EXTIN_LINE1_R 0x09
159#define EXTIN_COAX_SPDIF_L 0x0a
160#define EXTIN_COAX_SPDIF_R 0x0b
161#define EXTIN_LINE2_L 0x0c
162#define EXTIN_LINE2_R 0x0d
163
164
165#define EXTOUT_AC97_L 0x00
166#define EXTOUT_AC97_R 0x01
167#define EXTOUT_TOSLINK_L 0x02
168#define EXTOUT_TOSLINK_R 0x03
169#define EXTOUT_AC97_CENTER 0x04
170#define EXTOUT_AC97_LFE 0x05
171#define EXTOUT_HEADPHONE_L 0x06
172#define EXTOUT_HEADPHONE_R 0x07
173#define EXTOUT_REAR_L 0x08
174#define EXTOUT_REAR_R 0x09
175#define EXTOUT_ADC_CAP_L 0x0a
176#define EXTOUT_ADC_CAP_R 0x0b
177#define EXTOUT_MIC_CAP 0x0c
178#define EXTOUT_AC97_REAR_L 0x0d
179#define EXTOUT_AC97_REAR_R 0x0e
180#define EXTOUT_ACENTER 0x11
181#define EXTOUT_ALFE 0x12
182
183
184#define A_EXTIN_AC97_L 0x00
185#define A_EXTIN_AC97_R 0x01
186#define A_EXTIN_SPDIF_CD_L 0x02
187#define A_EXTIN_SPDIF_CD_R 0x03
188#define A_EXTIN_OPT_SPDIF_L 0x04
189#define A_EXTIN_OPT_SPDIF_R 0x05
190#define A_EXTIN_LINE2_L 0x08
191#define A_EXTIN_LINE2_R 0x09
192#define A_EXTIN_ADC_L 0x0a
193#define A_EXTIN_ADC_R 0x0b
194#define A_EXTIN_AUX2_L 0x0c
195#define A_EXTIN_AUX2_R 0x0d
196
197
198#define A_EXTOUT_FRONT_L 0x00
199#define A_EXTOUT_FRONT_R 0x01
200#define A_EXTOUT_CENTER 0x02
201#define A_EXTOUT_LFE 0x03
202#define A_EXTOUT_HEADPHONE_L 0x04
203#define A_EXTOUT_HEADPHONE_R 0x05
204#define A_EXTOUT_REAR_L 0x06
205#define A_EXTOUT_REAR_R 0x07
206#define A_EXTOUT_AFRONT_L 0x08
207#define A_EXTOUT_AFRONT_R 0x09
208#define A_EXTOUT_ACENTER 0x0a
209#define A_EXTOUT_ALFE 0x0b
210#define A_EXTOUT_ASIDE_L 0x0c
211#define A_EXTOUT_ASIDE_R 0x0d
212#define A_EXTOUT_AREAR_L 0x0e
213#define A_EXTOUT_AREAR_R 0x0f
214#define A_EXTOUT_AC97_L 0x10
215#define A_EXTOUT_AC97_R 0x11
216#define A_EXTOUT_ADC_CAP_L 0x16
217#define A_EXTOUT_ADC_CAP_R 0x17
218#define A_EXTOUT_MIC_CAP 0x18
219
220
221#define A_C_00000000 0xc0
222#define A_C_00000001 0xc1
223#define A_C_00000002 0xc2
224#define A_C_00000003 0xc3
225#define A_C_00000004 0xc4
226#define A_C_00000008 0xc5
227#define A_C_00000010 0xc6
228#define A_C_00000020 0xc7
229#define A_C_00000100 0xc8
230#define A_C_00010000 0xc9
231#define A_C_00000800 0xca
232#define A_C_10000000 0xcb
233#define A_C_20000000 0xcc
234#define A_C_40000000 0xcd
235#define A_C_80000000 0xce
236#define A_C_7fffffff 0xcf
237#define A_C_ffffffff 0xd0
238#define A_C_fffffffe 0xd1
239#define A_C_c0000000 0xd2
240#define A_C_4f1bbcdc 0xd3
241#define A_C_5a7ef9db 0xd4
242#define A_C_00100000 0xd5
243#define A_GPR_ACCU 0xd6
244#define A_GPR_COND 0xd7
245#define A_GPR_NOISE0 0xd8
246#define A_GPR_NOISE1 0xd9
247#define A_GPR_IRQ 0xda
248#define A_GPR_DBAC 0xdb
249#define A_GPR_DBACE 0xde
250
251
252#define EMU10K1_DBG_ZC 0x80000000
253#define EMU10K1_DBG_SATURATION_OCCURED 0x02000000
254#define EMU10K1_DBG_SATURATION_ADDR 0x01ff0000
255#define EMU10K1_DBG_SINGLE_STEP 0x00008000
256#define EMU10K1_DBG_STEP 0x00004000
257#define EMU10K1_DBG_CONDITION_CODE 0x00003e00
258#define EMU10K1_DBG_SINGLE_STEP_ADDR 0x000001ff
259
260
261#ifndef __KERNEL__
262#define TANKMEMADDRREG_ADDR_MASK 0x000fffff
263#define TANKMEMADDRREG_CLEAR 0x00800000
264#define TANKMEMADDRREG_ALIGN 0x00400000
265#define TANKMEMADDRREG_WRITE 0x00200000
266#define TANKMEMADDRREG_READ 0x00100000
267#endif
268
269struct snd_emu10k1_fx8010_info {
270 unsigned int internal_tram_size;
271 unsigned int external_tram_size;
272 char fxbus_names[16][32];
273 char extin_names[16][32];
274 char extout_names[32][32];
275 unsigned int gpr_controls;
276};
277
278#define EMU10K1_GPR_TRANSLATION_NONE 0
279#define EMU10K1_GPR_TRANSLATION_TABLE100 1
280#define EMU10K1_GPR_TRANSLATION_BASS 2
281#define EMU10K1_GPR_TRANSLATION_TREBLE 3
282#define EMU10K1_GPR_TRANSLATION_ONOFF 4
283
284struct snd_emu10k1_fx8010_control_gpr {
285 struct snd_ctl_elem_id id;
286 unsigned int vcount;
287 unsigned int count;
288 unsigned short gpr[32];
289 unsigned int value[32];
290 unsigned int min;
291 unsigned int max;
292 unsigned int translation;
293 const unsigned int *tlv;
294};
295
296
297struct snd_emu10k1_fx8010_control_old_gpr {
298 struct snd_ctl_elem_id id;
299 unsigned int vcount;
300 unsigned int count;
301 unsigned short gpr[32];
302 unsigned int value[32];
303 unsigned int min;
304 unsigned int max;
305 unsigned int translation;
306};
307
308struct snd_emu10k1_fx8010_code {
309 char name[128];
310
311 __EMU10K1_DECLARE_BITMAP(gpr_valid, 0x200);
312 __u32 __user *gpr_map;
313
314 unsigned int gpr_add_control_count;
315 struct snd_emu10k1_fx8010_control_gpr __user *gpr_add_controls;
316
317 unsigned int gpr_del_control_count;
318 struct snd_ctl_elem_id __user *gpr_del_controls;
319
320 unsigned int gpr_list_control_count;
321 unsigned int gpr_list_control_total;
322 struct snd_emu10k1_fx8010_control_gpr __user *gpr_list_controls;
323
324 __EMU10K1_DECLARE_BITMAP(tram_valid, 0x100);
325 __u32 __user *tram_data_map;
326 __u32 __user *tram_addr_map;
327
328 __EMU10K1_DECLARE_BITMAP(code_valid, 1024);
329 __u32 __user *code;
330};
331
332struct snd_emu10k1_fx8010_tram {
333 unsigned int address;
334 unsigned int size;
335 unsigned int *samples;
336
337};
338
339struct snd_emu10k1_fx8010_pcm_rec {
340 unsigned int substream;
341 unsigned int res1;
342 unsigned int channels;
343 unsigned int tram_start;
344 unsigned int buffer_size;
345 unsigned short gpr_size;
346 unsigned short gpr_ptr;
347 unsigned short gpr_count;
348 unsigned short gpr_tmpcount;
349 unsigned short gpr_trigger;
350 unsigned short gpr_running;
351 unsigned char pad;
352 unsigned char etram[32];
353 unsigned int res2;
354};
355
356#define SNDRV_EMU10K1_VERSION SNDRV_PROTOCOL_VERSION(1, 0, 1)
357
358#define SNDRV_EMU10K1_IOCTL_INFO _IOR ('H', 0x10, struct snd_emu10k1_fx8010_info)
359#define SNDRV_EMU10K1_IOCTL_CODE_POKE _IOW ('H', 0x11, struct snd_emu10k1_fx8010_code)
360#define SNDRV_EMU10K1_IOCTL_CODE_PEEK _IOWR('H', 0x12, struct snd_emu10k1_fx8010_code)
361#define SNDRV_EMU10K1_IOCTL_TRAM_SETUP _IOW ('H', 0x20, int)
362#define SNDRV_EMU10K1_IOCTL_TRAM_POKE _IOW ('H', 0x21, struct snd_emu10k1_fx8010_tram)
363#define SNDRV_EMU10K1_IOCTL_TRAM_PEEK _IOWR('H', 0x22, struct snd_emu10k1_fx8010_tram)
364#define SNDRV_EMU10K1_IOCTL_PCM_POKE _IOW ('H', 0x30, struct snd_emu10k1_fx8010_pcm_rec)
365#define SNDRV_EMU10K1_IOCTL_PCM_PEEK _IOWR('H', 0x31, struct snd_emu10k1_fx8010_pcm_rec)
366#define SNDRV_EMU10K1_IOCTL_PVERSION _IOR ('H', 0x40, int)
367#define SNDRV_EMU10K1_IOCTL_STOP _IO ('H', 0x80)
368#define SNDRV_EMU10K1_IOCTL_CONTINUE _IO ('H', 0x81)
369#define SNDRV_EMU10K1_IOCTL_ZERO_TRAM_COUNTER _IO ('H', 0x82)
370#define SNDRV_EMU10K1_IOCTL_SINGLE_STEP _IOW ('H', 0x83, int)
371#define SNDRV_EMU10K1_IOCTL_DBG_READ _IOR ('H', 0x84, int)
372
373
374typedef struct snd_emu10k1_fx8010_info emu10k1_fx8010_info_t;
375typedef struct snd_emu10k1_fx8010_control_gpr emu10k1_fx8010_control_gpr_t;
376typedef struct snd_emu10k1_fx8010_code emu10k1_fx8010_code_t;
377typedef struct snd_emu10k1_fx8010_tram emu10k1_fx8010_tram_t;
378typedef struct snd_emu10k1_fx8010_pcm_rec emu10k1_fx8010_pcm_t;
379
380#endif
381