LXR linux/sound/soc/ux500/ux500_msp

   1/*
   2 * Copyright (C) ST-Ericsson SA 2012
   3 *
   4 * Author: Ola Lilja <ola.o.lilja@stericsson.com>,
   5 *         Roger Nilsson <roger.xr.nilsson@stericsson.com>
   6 *         for ST-Ericsson.
   7 *
   8 * License terms:
   9 *
  10 * This program is free software; you can redistribute it and/or modify
  11 * it under the terms of the GNU General Public License version 2 as published
  12 * by the Free Software Foundation.
  13 */
  14
  15#ifndef UX500_msp_dai_H
  16#define UX500_msp_dai_H
  17
  18#include <linux/types.h>
  19#include <linux/spinlock.h>
  20
  21#include "ux500_msp_i2s.h"
  22
  23#define UX500_NBR_OF_DAI        4
  24
  25#define UX500_I2S_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |   \
  26                        SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
  27
  28#define UX500_I2S_FORMATS (SNDRV_PCM_FMTBIT_S16_LE)
  29
  30#define FRAME_PER_SINGLE_SLOT_8_KHZ             31
  31#define FRAME_PER_SINGLE_SLOT_16_KHZ    124
  32#define FRAME_PER_SINGLE_SLOT_44_1_KHZ  63
  33#define FRAME_PER_SINGLE_SLOT_48_KHZ    49
  34#define FRAME_PER_2_SLOTS                               31
  35#define FRAME_PER_8_SLOTS                               138
  36#define FRAME_PER_16_SLOTS                              277
  37
  38#define UX500_MSP_INTERNAL_CLOCK_FREQ  40000000
  39#define UX500_MSP1_INTERNAL_CLOCK_FREQ UX500_MSP_INTERNAL_CLOCK_FREQ
  40
  41#define UX500_MSP_MIN_CHANNELS          1
  42#define UX500_MSP_MAX_CHANNELS          8
  43
  44#define PLAYBACK_CONFIGURED             1
  45#define CAPTURE_CONFIGURED              2
  46
  47enum ux500_msp_clock_id {
  48        UX500_MSP_MASTER_CLOCK,
  49};
  50
  51struct ux500_msp_i2s_drvdata {
  52        struct ux500_msp *msp;
  53        struct regulator *reg_vape;
  54        unsigned int fmt;
  55        unsigned int tx_mask;
  56        unsigned int rx_mask;
  57        int slots;
  58        int slot_width;
  59
  60        /* Clocks */
  61        unsigned int master_clk;
  62        struct clk *clk;
  63        struct clk *pclk;
  64
  65        /* Regulators */
  66        int vape_opp_constraint;
  67};
  68
  69int ux500_msp_dai_set_data_delay(struct snd_soc_dai *dai, int delay);
  70
  71#endif
  72