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11#include <linux/init.h>
12#include <linux/platform_device.h>
13#include <linux/gpio.h>
14#include <linux/irq.h>
15#include <linux/regulator/fixed.h>
16#include <linux/regulator/machine.h>
17#include <linux/spi/spi.h>
18#include <linux/spi/flash.h>
19#include <linux/io.h>
20#include <linux/mfd/tmio.h>
21#include <linux/mmc/host.h>
22#include <linux/mmc/sh_mmcif.h>
23#include <linux/mmc/sh_mobile_sdhi.h>
24#include <linux/sh_eth.h>
25#include <linux/sh_intc.h>
26#include <linux/usb/renesas_usbhs.h>
27#include <cpu/sh7757.h>
28#include <asm/heartbeat.h>
29
30static struct resource heartbeat_resource = {
31 .start = 0xffec005c,
32 .end = 0xffec005c,
33 .flags = IORESOURCE_MEM | IORESOURCE_MEM_8BIT,
34};
35
36static unsigned char heartbeat_bit_pos[] = { 0, 1, 2, 3 };
37
38static struct heartbeat_data heartbeat_data = {
39 .bit_pos = heartbeat_bit_pos,
40 .nr_bits = ARRAY_SIZE(heartbeat_bit_pos),
41 .flags = HEARTBEAT_INVERTED,
42};
43
44static struct platform_device heartbeat_device = {
45 .name = "heartbeat",
46 .id = -1,
47 .dev = {
48 .platform_data = &heartbeat_data,
49 },
50 .num_resources = 1,
51 .resource = &heartbeat_resource,
52};
53
54
55#define GBECONT 0xffc10100
56#define GBECONT_RMII1 BIT(17)
57#define GBECONT_RMII0 BIT(16)
58static void sh7757_eth_set_mdio_gate(void *addr)
59{
60 if (((unsigned long)addr & 0x00000fff) < 0x0800)
61 writel(readl(GBECONT) | GBECONT_RMII0, GBECONT);
62 else
63 writel(readl(GBECONT) | GBECONT_RMII1, GBECONT);
64}
65
66static struct resource sh_eth0_resources[] = {
67 {
68 .start = 0xfef00000,
69 .end = 0xfef001ff,
70 .flags = IORESOURCE_MEM,
71 }, {
72 .start = evt2irq(0xc80),
73 .end = evt2irq(0xc80),
74 .flags = IORESOURCE_IRQ,
75 },
76};
77
78static struct sh_eth_plat_data sh7757_eth0_pdata = {
79 .phy = 1,
80 .edmac_endian = EDMAC_LITTLE_ENDIAN,
81 .set_mdio_gate = sh7757_eth_set_mdio_gate,
82};
83
84static struct platform_device sh7757_eth0_device = {
85 .name = "sh7757-ether",
86 .resource = sh_eth0_resources,
87 .id = 0,
88 .num_resources = ARRAY_SIZE(sh_eth0_resources),
89 .dev = {
90 .platform_data = &sh7757_eth0_pdata,
91 },
92};
93
94static struct resource sh_eth1_resources[] = {
95 {
96 .start = 0xfef00800,
97 .end = 0xfef009ff,
98 .flags = IORESOURCE_MEM,
99 }, {
100 .start = evt2irq(0xc80),
101 .end = evt2irq(0xc80),
102 .flags = IORESOURCE_IRQ,
103 },
104};
105
106static struct sh_eth_plat_data sh7757_eth1_pdata = {
107 .phy = 1,
108 .edmac_endian = EDMAC_LITTLE_ENDIAN,
109 .set_mdio_gate = sh7757_eth_set_mdio_gate,
110};
111
112static struct platform_device sh7757_eth1_device = {
113 .name = "sh7757-ether",
114 .resource = sh_eth1_resources,
115 .id = 1,
116 .num_resources = ARRAY_SIZE(sh_eth1_resources),
117 .dev = {
118 .platform_data = &sh7757_eth1_pdata,
119 },
120};
121
122static void sh7757_eth_giga_set_mdio_gate(void *addr)
123{
124 if (((unsigned long)addr & 0x00000fff) < 0x0800) {
125 gpio_set_value(GPIO_PTT4, 1);
126 writel(readl(GBECONT) & ~GBECONT_RMII0, GBECONT);
127 } else {
128 gpio_set_value(GPIO_PTT4, 0);
129 writel(readl(GBECONT) & ~GBECONT_RMII1, GBECONT);
130 }
131}
132
133static struct resource sh_eth_giga0_resources[] = {
134 {
135 .start = 0xfee00000,
136 .end = 0xfee007ff,
137 .flags = IORESOURCE_MEM,
138 }, {
139
140 .start = 0xfee01800,
141 .end = 0xfee01fff,
142 .flags = IORESOURCE_MEM,
143 }, {
144 .start = evt2irq(0x2960),
145 .end = evt2irq(0x2960),
146 .flags = IORESOURCE_IRQ,
147 },
148};
149
150static struct sh_eth_plat_data sh7757_eth_giga0_pdata = {
151 .phy = 18,
152 .edmac_endian = EDMAC_LITTLE_ENDIAN,
153 .set_mdio_gate = sh7757_eth_giga_set_mdio_gate,
154 .phy_interface = PHY_INTERFACE_MODE_RGMII_ID,
155};
156
157static struct platform_device sh7757_eth_giga0_device = {
158 .name = "sh7757-gether",
159 .resource = sh_eth_giga0_resources,
160 .id = 2,
161 .num_resources = ARRAY_SIZE(sh_eth_giga0_resources),
162 .dev = {
163 .platform_data = &sh7757_eth_giga0_pdata,
164 },
165};
166
167static struct resource sh_eth_giga1_resources[] = {
168 {
169 .start = 0xfee00800,
170 .end = 0xfee00fff,
171 .flags = IORESOURCE_MEM,
172 }, {
173
174 .start = 0xfee01800,
175 .end = 0xfee01fff,
176 .flags = IORESOURCE_MEM,
177 }, {
178 .start = evt2irq(0x2980),
179 .end = evt2irq(0x2980),
180 .flags = IORESOURCE_IRQ,
181 },
182};
183
184static struct sh_eth_plat_data sh7757_eth_giga1_pdata = {
185 .phy = 19,
186 .edmac_endian = EDMAC_LITTLE_ENDIAN,
187 .set_mdio_gate = sh7757_eth_giga_set_mdio_gate,
188 .phy_interface = PHY_INTERFACE_MODE_RGMII_ID,
189};
190
191static struct platform_device sh7757_eth_giga1_device = {
192 .name = "sh7757-gether",
193 .resource = sh_eth_giga1_resources,
194 .id = 3,
195 .num_resources = ARRAY_SIZE(sh_eth_giga1_resources),
196 .dev = {
197 .platform_data = &sh7757_eth_giga1_pdata,
198 },
199};
200
201
202static struct regulator_consumer_supply fixed3v3_power_consumers[] =
203{
204 REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
205 REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
206 REGULATOR_SUPPLY("vmmc", "sh_mmcif.0"),
207 REGULATOR_SUPPLY("vqmmc", "sh_mmcif.0"),
208};
209
210
211static struct resource sh_mmcif_resources[] = {
212 [0] = {
213 .start = 0xffcb0000,
214 .end = 0xffcb00ff,
215 .flags = IORESOURCE_MEM,
216 },
217 [1] = {
218 .start = evt2irq(0x1c60),
219 .flags = IORESOURCE_IRQ,
220 },
221 [2] = {
222 .start = evt2irq(0x1c80),
223 .flags = IORESOURCE_IRQ,
224 },
225};
226
227static struct sh_mmcif_plat_data sh_mmcif_plat = {
228 .sup_pclk = 0x0f,
229 .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA |
230 MMC_CAP_NONREMOVABLE,
231 .ocr = MMC_VDD_32_33 | MMC_VDD_33_34,
232 .slave_id_tx = SHDMA_SLAVE_MMCIF_TX,
233 .slave_id_rx = SHDMA_SLAVE_MMCIF_RX,
234};
235
236static struct platform_device sh_mmcif_device = {
237 .name = "sh_mmcif",
238 .id = 0,
239 .dev = {
240 .platform_data = &sh_mmcif_plat,
241 },
242 .num_resources = ARRAY_SIZE(sh_mmcif_resources),
243 .resource = sh_mmcif_resources,
244};
245
246
247static struct tmio_mmc_data sdhi_info = {
248 .chan_priv_tx = (void *)SHDMA_SLAVE_SDHI_TX,
249 .chan_priv_rx = (void *)SHDMA_SLAVE_SDHI_RX,
250 .capabilities = MMC_CAP_SD_HIGHSPEED,
251};
252
253static struct resource sdhi_resources[] = {
254 [0] = {
255 .start = 0xffe50000,
256 .end = 0xffe500ff,
257 .flags = IORESOURCE_MEM,
258 },
259 [1] = {
260 .start = evt2irq(0x480),
261 .flags = IORESOURCE_IRQ,
262 },
263};
264
265static struct platform_device sdhi_device = {
266 .name = "sh_mobile_sdhi",
267 .num_resources = ARRAY_SIZE(sdhi_resources),
268 .resource = sdhi_resources,
269 .id = 0,
270 .dev = {
271 .platform_data = &sdhi_info,
272 },
273};
274
275static int usbhs0_get_id(struct platform_device *pdev)
276{
277 return USBHS_GADGET;
278}
279
280static struct renesas_usbhs_platform_info usb0_data = {
281 .platform_callback = {
282 .get_id = usbhs0_get_id,
283 },
284 .driver_param = {
285 .buswait_bwait = 5,
286 }
287};
288
289static struct resource usb0_resources[] = {
290 [0] = {
291 .start = 0xfe450000,
292 .end = 0xfe4501ff,
293 .flags = IORESOURCE_MEM,
294 },
295 [1] = {
296 .start = evt2irq(0x840),
297 .end = evt2irq(0x840),
298 .flags = IORESOURCE_IRQ,
299 },
300};
301
302static struct platform_device usb0_device = {
303 .name = "renesas_usbhs",
304 .id = 0,
305 .dev = {
306 .platform_data = &usb0_data,
307 },
308 .num_resources = ARRAY_SIZE(usb0_resources),
309 .resource = usb0_resources,
310};
311
312static struct platform_device *sh7757lcr_devices[] __initdata = {
313 &heartbeat_device,
314 &sh7757_eth0_device,
315 &sh7757_eth1_device,
316 &sh7757_eth_giga0_device,
317 &sh7757_eth_giga1_device,
318 &sh_mmcif_device,
319 &sdhi_device,
320 &usb0_device,
321};
322
323static struct flash_platform_data spi_flash_data = {
324 .name = "m25p80",
325 .type = "m25px64",
326};
327
328static struct spi_board_info spi_board_info[] = {
329 {
330 .modalias = "m25p80",
331 .max_speed_hz = 25000000,
332 .bus_num = 0,
333 .chip_select = 1,
334 .platform_data = &spi_flash_data,
335 },
336};
337
338static int __init sh7757lcr_devices_setup(void)
339{
340 regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers,
341 ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
342
343
344 gpio_request(GPIO_FN_ET0_MDC, NULL);
345 gpio_request(GPIO_FN_ET0_MDIO, NULL);
346 gpio_request(GPIO_FN_ET1_MDC, NULL);
347 gpio_request(GPIO_FN_ET1_MDIO, NULL);
348
349
350 gpio_request(GPIO_FN_ON_NRE, NULL);
351 gpio_request(GPIO_FN_ON_NWE, NULL);
352 gpio_request(GPIO_FN_ON_NWP, NULL);
353 gpio_request(GPIO_FN_ON_NCE0, NULL);
354 gpio_request(GPIO_FN_ON_R_B0, NULL);
355 gpio_request(GPIO_FN_ON_ALE, NULL);
356 gpio_request(GPIO_FN_ON_CLE, NULL);
357
358 gpio_request(GPIO_FN_ON_DQ7, NULL);
359 gpio_request(GPIO_FN_ON_DQ6, NULL);
360 gpio_request(GPIO_FN_ON_DQ5, NULL);
361 gpio_request(GPIO_FN_ON_DQ4, NULL);
362 gpio_request(GPIO_FN_ON_DQ3, NULL);
363 gpio_request(GPIO_FN_ON_DQ2, NULL);
364 gpio_request(GPIO_FN_ON_DQ1, NULL);
365 gpio_request(GPIO_FN_ON_DQ0, NULL);
366
367
368 gpio_request(GPIO_FN_IRQ8, NULL);
369 gpio_request(GPIO_FN_IRQ7, NULL);
370 gpio_request(GPIO_FN_IRQ6, NULL);
371 gpio_request(GPIO_FN_IRQ5, NULL);
372 gpio_request(GPIO_FN_IRQ4, NULL);
373 gpio_request(GPIO_FN_IRQ3, NULL);
374 gpio_request(GPIO_FN_IRQ2, NULL);
375 gpio_request(GPIO_FN_IRQ1, NULL);
376 gpio_request(GPIO_FN_IRQ0, NULL);
377
378
379 gpio_request(GPIO_FN_SP0_MOSI, NULL);
380 gpio_request(GPIO_FN_SP0_MISO, NULL);
381 gpio_request(GPIO_FN_SP0_SCK, NULL);
382 gpio_request(GPIO_FN_SP0_SCK_FB, NULL);
383 gpio_request(GPIO_FN_SP0_SS0, NULL);
384 gpio_request(GPIO_FN_SP0_SS1, NULL);
385 gpio_request(GPIO_FN_SP0_SS2, NULL);
386 gpio_request(GPIO_FN_SP0_SS3, NULL);
387
388
389 gpio_request(GPIO_FN_RMII0_CRS_DV, NULL);
390 gpio_request(GPIO_FN_RMII0_TXD1, NULL);
391 gpio_request(GPIO_FN_RMII0_TXD0, NULL);
392 gpio_request(GPIO_FN_RMII0_TXEN, NULL);
393 gpio_request(GPIO_FN_RMII0_REFCLK, NULL);
394 gpio_request(GPIO_FN_RMII0_RXD1, NULL);
395 gpio_request(GPIO_FN_RMII0_RXD0, NULL);
396 gpio_request(GPIO_FN_RMII0_RX_ER, NULL);
397 gpio_request(GPIO_FN_RMII1_CRS_DV, NULL);
398 gpio_request(GPIO_FN_RMII1_TXD1, NULL);
399 gpio_request(GPIO_FN_RMII1_TXD0, NULL);
400 gpio_request(GPIO_FN_RMII1_TXEN, NULL);
401 gpio_request(GPIO_FN_RMII1_REFCLK, NULL);
402 gpio_request(GPIO_FN_RMII1_RXD1, NULL);
403 gpio_request(GPIO_FN_RMII1_RXD0, NULL);
404 gpio_request(GPIO_FN_RMII1_RX_ER, NULL);
405
406
407 gpio_request(GPIO_FN_MMCCLK, NULL);
408 gpio_request(GPIO_FN_MMCCMD, NULL);
409 gpio_request(GPIO_FN_MMCDAT7, NULL);
410 gpio_request(GPIO_FN_MMCDAT6, NULL);
411 gpio_request(GPIO_FN_MMCDAT5, NULL);
412 gpio_request(GPIO_FN_MMCDAT4, NULL);
413 gpio_request(GPIO_FN_MMCDAT3, NULL);
414 gpio_request(GPIO_FN_MMCDAT2, NULL);
415 gpio_request(GPIO_FN_MMCDAT1, NULL);
416 gpio_request(GPIO_FN_MMCDAT0, NULL);
417
418
419 gpio_request(GPIO_FN_SERIRQ, NULL);
420 gpio_request(GPIO_FN_LPCPD, NULL);
421 gpio_request(GPIO_FN_LDRQ, NULL);
422 gpio_request(GPIO_FN_WP, NULL);
423 gpio_request(GPIO_FN_FMS0, NULL);
424 gpio_request(GPIO_FN_LAD3, NULL);
425 gpio_request(GPIO_FN_LAD2, NULL);
426 gpio_request(GPIO_FN_LAD1, NULL);
427 gpio_request(GPIO_FN_LAD0, NULL);
428 gpio_request(GPIO_FN_LFRAME, NULL);
429 gpio_request(GPIO_FN_LRESET, NULL);
430 gpio_request(GPIO_FN_LCLK, NULL);
431 gpio_request(GPIO_FN_LGPIO7, NULL);
432 gpio_request(GPIO_FN_LGPIO6, NULL);
433 gpio_request(GPIO_FN_LGPIO5, NULL);
434 gpio_request(GPIO_FN_LGPIO4, NULL);
435
436
437 gpio_request(GPIO_FN_SP1_MOSI, NULL);
438 gpio_request(GPIO_FN_SP1_MISO, NULL);
439 gpio_request(GPIO_FN_SP1_SCK, NULL);
440 gpio_request(GPIO_FN_SP1_SCK_FB, NULL);
441 gpio_request(GPIO_FN_SP1_SS0, NULL);
442 gpio_request(GPIO_FN_SP1_SS1, NULL);
443
444
445 gpio_request(GPIO_FN_SD_WP, NULL);
446 gpio_request(GPIO_FN_SD_CD, NULL);
447 gpio_request(GPIO_FN_SD_CLK, NULL);
448 gpio_request(GPIO_FN_SD_CMD, NULL);
449 gpio_request(GPIO_FN_SD_D3, NULL);
450 gpio_request(GPIO_FN_SD_D2, NULL);
451 gpio_request(GPIO_FN_SD_D1, NULL);
452 gpio_request(GPIO_FN_SD_D0, NULL);
453
454
455 gpio_request(GPIO_FN_RTS3, NULL);
456 gpio_request(GPIO_FN_CTS3, NULL);
457 gpio_request(GPIO_FN_TXD3, NULL);
458 gpio_request(GPIO_FN_RXD3, NULL);
459 gpio_request(GPIO_FN_RTS4, NULL);
460 gpio_request(GPIO_FN_RXD4, NULL);
461 gpio_request(GPIO_FN_TXD4, NULL);
462 gpio_request(GPIO_FN_CTS4, NULL);
463
464
465 gpio_request(GPIO_FN_COM2_TXD, NULL);
466 gpio_request(GPIO_FN_COM2_RXD, NULL);
467 gpio_request(GPIO_FN_COM2_RTS, NULL);
468 gpio_request(GPIO_FN_COM2_CTS, NULL);
469 gpio_request(GPIO_FN_COM2_DTR, NULL);
470 gpio_request(GPIO_FN_COM2_DSR, NULL);
471 gpio_request(GPIO_FN_COM2_DCD, NULL);
472 gpio_request(GPIO_FN_COM2_RI, NULL);
473 gpio_request(GPIO_FN_RAC_RXD, NULL);
474 gpio_request(GPIO_FN_RAC_RTS, NULL);
475 gpio_request(GPIO_FN_RAC_CTS, NULL);
476 gpio_request(GPIO_FN_RAC_DTR, NULL);
477 gpio_request(GPIO_FN_RAC_DSR, NULL);
478 gpio_request(GPIO_FN_RAC_DCD, NULL);
479 gpio_request(GPIO_FN_RAC_TXD, NULL);
480 gpio_request(GPIO_FN_COM1_TXD, NULL);
481 gpio_request(GPIO_FN_COM1_RXD, NULL);
482 gpio_request(GPIO_FN_COM1_RTS, NULL);
483 gpio_request(GPIO_FN_COM1_CTS, NULL);
484
485 writeb(0x10, 0xfe470000);
486
487
488 gpio_request(GPIO_FN_SDA7, NULL);
489 gpio_request(GPIO_FN_SCL7, NULL);
490 gpio_request(GPIO_FN_SDA6, NULL);
491 gpio_request(GPIO_FN_SCL6, NULL);
492 gpio_request(GPIO_FN_SDA5, NULL);
493 gpio_request(GPIO_FN_SCL5, NULL);
494 gpio_request(GPIO_FN_SDA4, NULL);
495 gpio_request(GPIO_FN_SCL4, NULL);
496 gpio_request(GPIO_FN_SDA3, NULL);
497 gpio_request(GPIO_FN_SCL3, NULL);
498 gpio_request(GPIO_FN_SDA2, NULL);
499 gpio_request(GPIO_FN_SCL2, NULL);
500 gpio_request(GPIO_FN_SDA1, NULL);
501 gpio_request(GPIO_FN_SCL1, NULL);
502 gpio_request(GPIO_FN_SDA0, NULL);
503 gpio_request(GPIO_FN_SCL0, NULL);
504
505
506 gpio_request(GPIO_FN_VBUS_EN, NULL);
507 gpio_request(GPIO_FN_VBUS_OC, NULL);
508
509
510 gpio_request(GPIO_FN_SGPIO1_CLK, NULL);
511 gpio_request(GPIO_FN_SGPIO1_LOAD, NULL);
512 gpio_request(GPIO_FN_SGPIO1_DI, NULL);
513 gpio_request(GPIO_FN_SGPIO1_DO, NULL);
514 gpio_request(GPIO_FN_SGPIO0_CLK, NULL);
515 gpio_request(GPIO_FN_SGPIO0_LOAD, NULL);
516 gpio_request(GPIO_FN_SGPIO0_DI, NULL);
517 gpio_request(GPIO_FN_SGPIO0_DO, NULL);
518
519
520 gpio_request(GPIO_FN_SUB_CLKIN, NULL);
521
522
523 gpio_request(GPIO_FN_STATUS1, NULL);
524 gpio_request(GPIO_FN_STATUS0, NULL);
525
526
527 gpio_request(GPIO_FN_PWMX1, NULL);
528 gpio_request(GPIO_FN_PWMX0, NULL);
529
530
531 gpio_request(GPIO_FN_R_SPI_MOSI, NULL);
532 gpio_request(GPIO_FN_R_SPI_MISO, NULL);
533 gpio_request(GPIO_FN_R_SPI_RSPCK, NULL);
534 gpio_request(GPIO_FN_R_SPI_SSL0, NULL);
535 gpio_request(GPIO_FN_R_SPI_SSL1, NULL);
536
537
538 gpio_request(GPIO_FN_EVENT7, NULL);
539 gpio_request(GPIO_FN_EVENT6, NULL);
540 gpio_request(GPIO_FN_EVENT5, NULL);
541 gpio_request(GPIO_FN_EVENT4, NULL);
542 gpio_request(GPIO_FN_EVENT3, NULL);
543 gpio_request(GPIO_FN_EVENT2, NULL);
544 gpio_request(GPIO_FN_EVENT1, NULL);
545 gpio_request(GPIO_FN_EVENT0, NULL);
546
547
548 gpio_request(GPIO_PTU3, NULL);
549 gpio_direction_output(GPIO_PTU3, 1);
550 gpio_request(GPIO_PTU2, NULL);
551 gpio_direction_output(GPIO_PTU2, 1);
552 gpio_request(GPIO_PTU1, NULL);
553 gpio_direction_output(GPIO_PTU1, 1);
554 gpio_request(GPIO_PTU0, NULL);
555 gpio_direction_output(GPIO_PTU0, 1);
556
557
558 gpio_request(GPIO_PTT4, NULL);
559 gpio_direction_output(GPIO_PTT4, 1);
560
561
562 gpio_request(GPIO_PTT7, NULL);
563 gpio_direction_output(GPIO_PTT7, 0);
564 gpio_request(GPIO_PTT6, NULL);
565 gpio_direction_output(GPIO_PTT6, 0);
566 gpio_request(GPIO_PTT5, NULL);
567 gpio_direction_output(GPIO_PTT5, 1);
568
569
570 spi_register_board_info(spi_board_info,
571 ARRAY_SIZE(spi_board_info));
572
573
574 return platform_add_devices(sh7757lcr_devices,
575 ARRAY_SIZE(sh7757lcr_devices));
576}
577arch_initcall(sh7757lcr_devices_setup);
578
579
580void __init init_sh7757lcr_IRQ(void)
581{
582 plat_irq_setup_pins(IRQ_MODE_IRQ7654);
583 plat_irq_setup_pins(IRQ_MODE_IRQ3210);
584}
585
586
587static void __init sh7757lcr_setup(char **cmdline_p)
588{
589 printk(KERN_INFO "Renesas R0P7757LC0012RL support.\n");
590}
591
592static int sh7757lcr_mode_pins(void)
593{
594 int value = 0;
595
596
597
598
599
600 value |= MODE_PIN0;
601
602 return value;
603}
604
605
606static struct sh_machine_vector mv_sh7757lcr __initmv = {
607 .mv_name = "SH7757LCR",
608 .mv_setup = sh7757lcr_setup,
609 .mv_init_irq = init_sh7757lcr_IRQ,
610 .mv_mode_pins = sh7757lcr_mode_pins,
611};
612
613
