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21#ifndef __MTIP32XX_H__
22#define __MTIP32XX_H__
23
24#include <linux/spinlock.h>
25#include <linux/rwsem.h>
26#include <linux/ata.h>
27#include <linux/interrupt.h>
28#include <linux/genhd.h>
29
30
31#define PCI_SUBSYSTEM_DEVICEID 0x2E
32
33
34#define PCIE_CONFIG_EXT_DEVICE_CONTROL_OFFSET 0x48
35
36
37#define MTIP_SEC_ERASE_MODE 0x2
38
39
40#define MTIP_MAX_RETRIES 2
41
42
43#define MTIP_NCQ_CMD_TIMEOUT_MS 15000
44#define MTIP_IOCTL_CMD_TIMEOUT_MS 5000
45#define MTIP_INT_CMD_TIMEOUT_MS 5000
46#define MTIP_QUIESCE_IO_TIMEOUT_MS (MTIP_NCQ_CMD_TIMEOUT_MS * \
47 (MTIP_MAX_RETRIES + 1))
48
49
50#define MTIP_TIMEOUT_CHECK_PERIOD 500
51
52
53#define MTIP_FTL_REBUILD_OFFSET 142
54#define MTIP_FTL_REBUILD_MAGIC 0xED51
55#define MTIP_FTL_REBUILD_TIMEOUT_MS 2400000
56
57
58#define MTIP_MAX_UNALIGNED_SLOTS 2
59
60
61#define MTIP_TAG_BIT(tag) (tag & 0x1F)
62
63
64
65
66
67
68#define MTIP_TAG_INDEX(tag) (tag >> 5)
69
70
71
72
73
74#define MTIP_MAX_SG 504
75
76
77
78
79
80#define MTIP_MAX_SLOT_GROUPS 8
81
82
83#define MTIP_TAG_INTERNAL 0
84
85
86#define PCI_VENDOR_ID_MICRON 0x1344
87#define P320H_DEVICE_ID 0x5150
88#define P320M_DEVICE_ID 0x5151
89#define P320S_DEVICE_ID 0x5152
90#define P325M_DEVICE_ID 0x5153
91#define P420H_DEVICE_ID 0x5160
92#define P420M_DEVICE_ID 0x5161
93#define P425M_DEVICE_ID 0x5163
94
95
96#define MTIP_DRV_NAME "mtip32xx"
97#define MTIP_DRV_VERSION "1.3.1"
98
99
100#define MTIP_MAX_MINORS 16
101
102
103#define MTIP_MAX_COMMAND_SLOTS (MTIP_MAX_SLOT_GROUPS * 32)
104
105
106
107
108
109
110
111
112
113#define U32_PER_LONG (sizeof(long) / sizeof(u32))
114#define SLOTBITS_IN_LONGS ((MTIP_MAX_SLOT_GROUPS + \
115 (U32_PER_LONG-1))/U32_PER_LONG)
116
117
118#define MTIP_ABAR 5
119
120#ifdef DEBUG
121 #define dbg_printk(format, arg...) \
122 printk(pr_fmt(format), ##arg);
123#else
124 #define dbg_printk(format, arg...)
125#endif
126
127#define MTIP_DFS_MAX_BUF_SIZE 1024
128
129#define __force_bit2int (unsigned int __force)
130
131enum {
132
133 MTIP_PF_IC_ACTIVE_BIT = 0,
134 MTIP_PF_EH_ACTIVE_BIT = 1,
135 MTIP_PF_SE_ACTIVE_BIT = 2,
136 MTIP_PF_DM_ACTIVE_BIT = 3,
137 MTIP_PF_TO_ACTIVE_BIT = 9,
138 MTIP_PF_PAUSE_IO = ((1 << MTIP_PF_IC_ACTIVE_BIT) |
139 (1 << MTIP_PF_EH_ACTIVE_BIT) |
140 (1 << MTIP_PF_SE_ACTIVE_BIT) |
141 (1 << MTIP_PF_DM_ACTIVE_BIT) |
142 (1 << MTIP_PF_TO_ACTIVE_BIT)),
143
144 MTIP_PF_SVC_THD_ACTIVE_BIT = 4,
145 MTIP_PF_ISSUE_CMDS_BIT = 5,
146 MTIP_PF_REBUILD_BIT = 6,
147 MTIP_PF_SVC_THD_STOP_BIT = 8,
148
149 MTIP_PF_SVC_THD_WORK = ((1 << MTIP_PF_EH_ACTIVE_BIT) |
150 (1 << MTIP_PF_ISSUE_CMDS_BIT) |
151 (1 << MTIP_PF_REBUILD_BIT) |
152 (1 << MTIP_PF_SVC_THD_STOP_BIT) |
153 (1 << MTIP_PF_TO_ACTIVE_BIT)),
154
155
156 MTIP_DDF_SEC_LOCK_BIT = 0,
157 MTIP_DDF_REMOVE_PENDING_BIT = 1,
158 MTIP_DDF_OVER_TEMP_BIT = 2,
159 MTIP_DDF_WRITE_PROTECT_BIT = 3,
160 MTIP_DDF_CLEANUP_BIT = 5,
161 MTIP_DDF_RESUME_BIT = 6,
162 MTIP_DDF_INIT_DONE_BIT = 7,
163 MTIP_DDF_REBUILD_FAILED_BIT = 8,
164 MTIP_DDF_REMOVAL_BIT = 9,
165
166 MTIP_DDF_STOP_IO = ((1 << MTIP_DDF_REMOVE_PENDING_BIT) |
167 (1 << MTIP_DDF_SEC_LOCK_BIT) |
168 (1 << MTIP_DDF_OVER_TEMP_BIT) |
169 (1 << MTIP_DDF_WRITE_PROTECT_BIT) |
170 (1 << MTIP_DDF_REBUILD_FAILED_BIT)),
171
172};
173
174struct smart_attr {
175 u8 attr_id;
176 u16 flags;
177 u8 cur;
178 u8 worst;
179 u32 data;
180 u8 res[3];
181} __packed;
182
183struct mtip_work {
184 struct work_struct work;
185 void *port;
186 int cpu_binding;
187 u32 completed;
188} ____cacheline_aligned_in_smp;
189
190#define DEFINE_HANDLER(group) \
191 void mtip_workq_sdbf##group(struct work_struct *work) \
192 { \
193 struct mtip_work *w = (struct mtip_work *) work; \
194 mtip_workq_sdbfx(w->port, group, w->completed); \
195 }
196
197#define MTIP_TRIM_TIMEOUT_MS 240000
198#define MTIP_MAX_TRIM_ENTRIES 8
199#define MTIP_MAX_TRIM_ENTRY_LEN 0xfff8
200
201struct mtip_trim_entry {
202 u32 lba;
203 u16 rsvd;
204 u16 range;
205} __packed;
206
207struct mtip_trim {
208
209 struct mtip_trim_entry entry[MTIP_MAX_TRIM_ENTRIES];
210} __packed;
211
212
213struct host_to_dev_fis {
214
215
216
217
218
219
220
221
222
223
224
225 unsigned char type;
226 unsigned char opts;
227 unsigned char command;
228 unsigned char features;
229
230 union {
231 unsigned char lba_low;
232 unsigned char sector;
233 };
234 union {
235 unsigned char lba_mid;
236 unsigned char cyl_low;
237 };
238 union {
239 unsigned char lba_hi;
240 unsigned char cyl_hi;
241 };
242 union {
243 unsigned char device;
244 unsigned char head;
245 };
246
247 union {
248 unsigned char lba_low_ex;
249 unsigned char sector_ex;
250 };
251 union {
252 unsigned char lba_mid_ex;
253 unsigned char cyl_low_ex;
254 };
255 union {
256 unsigned char lba_hi_ex;
257 unsigned char cyl_hi_ex;
258 };
259 unsigned char features_ex;
260
261 unsigned char sect_count;
262 unsigned char sect_cnt_ex;
263 unsigned char res2;
264 unsigned char control;
265
266 unsigned int res3;
267};
268
269
270struct mtip_cmd_hdr {
271
272
273
274
275
276
277
278
279
280 unsigned int opts;
281
282 union {
283 unsigned int byte_count;
284 unsigned int status;
285 };
286
287
288
289
290 unsigned int ctba;
291
292
293
294
295 unsigned int ctbau;
296
297 unsigned int res[4];
298};
299
300
301struct mtip_cmd_sg {
302
303
304
305
306
307 unsigned int dba;
308
309
310
311
312 unsigned int dba_upper;
313
314 unsigned int reserved;
315
316
317
318
319
320
321 unsigned int info;
322};
323struct mtip_port;
324
325
326struct mtip_cmd {
327
328 struct mtip_cmd_hdr *command_header;
329
330 dma_addr_t command_header_dma;
331
332 void *command;
333
334 dma_addr_t command_dma;
335
336 void *comp_data;
337
338
339
340
341 void (*comp_func)(struct mtip_port *port,
342 int tag,
343 struct mtip_cmd *cmd,
344 int status);
345
346 int scatter_ents;
347
348 int unaligned;
349
350 struct scatterlist sg[MTIP_MAX_SG];
351
352 int retries;
353
354 int direction;
355};
356
357
358struct mtip_port {
359
360 struct driver_data *dd;
361
362
363
364
365 unsigned long identify_valid;
366
367 void __iomem *mmio;
368
369 void __iomem *s_active[MTIP_MAX_SLOT_GROUPS];
370
371 void __iomem *completed[MTIP_MAX_SLOT_GROUPS];
372
373 void __iomem *cmd_issue[MTIP_MAX_SLOT_GROUPS];
374
375
376
377
378 void *command_list;
379
380
381
382
383 dma_addr_t command_list_dma;
384
385
386
387
388 void *rxfis;
389
390
391
392
393 dma_addr_t rxfis_dma;
394
395
396
397 void *block1;
398
399
400
401 dma_addr_t block1_dma;
402
403
404
405
406 u16 *identify;
407
408
409
410
411 dma_addr_t identify_dma;
412
413
414
415
416 u16 *sector_buffer;
417
418
419
420
421 dma_addr_t sector_buffer_dma;
422
423 u16 *log_buf;
424 dma_addr_t log_buf_dma;
425
426 u8 *smart_buf;
427 dma_addr_t smart_buf_dma;
428
429
430
431
432
433 unsigned long cmds_to_issue[SLOTBITS_IN_LONGS];
434
435 wait_queue_head_t svc_wait;
436
437
438
439
440 unsigned long flags;
441
442
443
444 unsigned long ic_pause_timer;
445
446
447 struct semaphore cmd_slot_unal;
448
449
450 spinlock_t cmd_issue_lock[MTIP_MAX_SLOT_GROUPS];
451};
452
453
454
455
456
457
458struct driver_data {
459 void __iomem *mmio;
460
461 int major;
462
463 int instance;
464
465 struct gendisk *disk;
466
467 struct pci_dev *pdev;
468
469 struct request_queue *queue;
470
471 struct blk_mq_tag_set tags;
472
473 struct mtip_port *port;
474
475 unsigned product_type;
476
477 unsigned slot_groups;
478
479 unsigned long index;
480
481 unsigned long dd_flag;
482
483 struct task_struct *mtip_svc_handler;
484
485 struct dentry *dfs_node;
486
487 bool trim_supp;
488
489 bool sr;
490
491 int numa_node;
492
493 char workq_name[32];
494
495 struct workqueue_struct *isr_workq;
496
497 atomic_t irq_workers_active;
498
499 struct mtip_work work[MTIP_MAX_SLOT_GROUPS];
500
501 int isr_binding;
502
503 struct block_device *bdev;
504
505 struct list_head online_list;
506
507 struct list_head remove_list;
508
509 int unal_qdepth;
510};
511
512#endif
513