/*
 * Copyright © 2008 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 * Authors:
 *    Eric Anholt <eric@anholt.net>
 *    Keith Packard <keithp@keithp.com>
 *
 */

#include <linux/seq_file.h>
#include <linux/circ_buf.h>
#include <linux/ctype.h>
#include <linux/debugfs.h>
#include <linux/slab.h>
#include <linux/export.h>
#include <linux/list_sort.h>
#include <asm/msr-index.h>
#include <drm/drmP.h>
#include "intel_drv.h"
#include "intel_ringbuffer.h"
#include <drm/i915_drm.h>
#include "i915_drv.h"

enum {
        ACTIVE_LIST,
        INACTIVE_LIST,
        PINNED_LIST,
};

/* As the drm_debugfs_init() routines are called before dev->dev_private is
 * allocated we need to hook into the minor for release. */
static int
drm_add_fake_info_node(struct drm_minor *minor,
                       struct dentry *ent,
                       const void *key)
{
        struct drm_info_node *node;

        node = kmalloc(sizeof(*node), GFP_KERNEL);
        if (node == NULL) {
                debugfs_remove(ent);
                return -ENOMEM;
        }

        node->minor = minor;
        node->dent = ent;
        node->info_ent = (void *) key;

        mutex_lock(&minor->debugfs_lock);
        list_add(&node->list, &minor->debugfs_list);
        mutex_unlock(&minor->debugfs_lock);

        return 0;
}

static int i915_capabilities(struct seq_file *m, void *data)
{
        struct drm_info_node *node = m->private;
        struct drm_device *dev = node->minor->dev;
        const struct intel_device_info *info = INTEL_INFO(dev);

        seq_printf(m, "gen: %d\n", info->gen);
        seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
#define PRINT_FLAG(x)  seq_printf(m, #x ": %s\n", yesno(info->x))
#define SEP_SEMICOLON ;
        DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
#undef PRINT_FLAG
#undef SEP_SEMICOLON

        return 0;
}

static const char *get_pin_flag(struct drm_i915_gem_object *obj)
{
        if (obj->pin_display)
                return "p";
        else
                return " ";
}

static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
{
        switch (obj->tiling_mode) {
        default:
        case I915_TILING_NONE: return " ";
        case I915_TILING_X: return "X";
        case I915_TILING_Y: return "Y";
        }
}

static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
{
        return i915_gem_obj_to_ggtt(obj) ? "g" : " ";
}

static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
{
        u64 size = 0;
        struct i915_vma *vma;

        list_for_each_entry(vma, &obj->vma_list, obj_link) {
                if (vma->is_ggtt && drm_mm_node_allocated(&vma->node))
                        size += vma->node.size;
        }

        return size;
}

static void
describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
{
        struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
        struct intel_engine_cs *ring;
        struct i915_vma *vma;
        int pin_count = 0;
        int i;

        seq_printf(m, "%pK: %s%s%s%s %8zdKiB %02x %02x [ ",
                   &obj->base,
                   obj->active ? "*" : " ",
                   get_pin_flag(obj),
                   get_tiling_flag(obj),
                   get_global_flag(obj),
                   obj->base.size / 1024,
                   obj->base.read_domains,
                   obj->base.write_domain);
        for_each_ring(ring, dev_priv, i)
                seq_printf(m, "%x ",
                                i915_gem_request_get_seqno(obj->last_read_req[i]));
        seq_printf(m, "] %x %x%s%s%s",
                   i915_gem_request_get_seqno(obj->last_write_req),
                   i915_gem_request_get_seqno(obj->last_fenced_req),
                   i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
                   obj->dirty ? " dirty" : "",
                   obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
        if (obj->base.name)
                seq_printf(m, " (name: %d)", obj->base.name);
        list_for_each_entry(vma, &obj->vma_list, obj_link) {
                if (vma->pin_count > 0)
                        pin_count++;
        }
        seq_printf(m, " (pinned x %d)", pin_count);
        if (obj->pin_display)
                seq_printf(m, " (display)");
        if (obj->fence_reg != I915_FENCE_REG_NONE)
                seq_printf(m, " (fence: %d)", obj->fence_reg);
        list_for_each_entry(vma, &obj->vma_list, obj_link) {
                seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
                           vma->is_ggtt ? "g" : "pp",
                           vma->node.start, vma->node.size);
                if (vma->is_ggtt)
                        seq_printf(m, ", type: %u", vma->ggtt_view.type);
                seq_puts(m, ")");
        }
        if (obj->stolen)
                seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
        if (obj->pin_display || obj->fault_mappable) {
                char s[3], *t = s;
                if (obj->pin_display)
                        *t++ = 'p';
                if (obj->fault_mappable)
                        *t++ = 'f';
                *t = '\0';
                seq_printf(m, " (%s mappable)", s);
        }
        if (obj->last_write_req != NULL)
                seq_printf(m, " (%s)",
                           i915_gem_request_get_ring(obj->last_write_req)->name);
        if (obj->frontbuffer_bits)
                seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
}

static void describe_ctx(struct seq_file *m, struct intel_context *ctx)
{
        seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i');
        seq_putc(m, ctx->remap_slice ? 'R' : 'r');
        seq_putc(m, ' ');
}

static int i915_gem_object_list_info(struct seq_file *m, void *data)
{
        struct drm_info_node *node = m->private;
        uintptr_t list = (uintptr_t) node->info_ent->data;
        struct list_head *head;
        struct drm_device *dev = node->minor->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct i915_address_space *vm = &dev_priv->gtt.base;
        struct i915_vma *vma;
        u64 total_obj_size, total_gtt_size;
        int count, ret;

        ret = mutex_lock_interruptible(&dev->struct_mutex);
        if (ret)
                return ret;

        /* FIXME: the user of this interface might want more than just GGTT */
        switch (list) {
        case ACTIVE_LIST:
                seq_puts(m, "Active:\n");
                head = &vm->active_list;
                break;
        case INACTIVE_LIST:
                seq_puts(m, "Inactive:\n");
                head = &vm->inactive_list;
                break;
        default:
                mutex_unlock(&dev->struct_mutex);
                return -EINVAL;
        }

        total_obj_size = total_gtt_size = count = 0;
        list_for_each_entry(vma, head, vm_link) {
                seq_printf(m, "   ");
                describe_obj(m, vma->obj);
                seq_printf(m, "\n");
                total_obj_size += vma->obj->base.size;
                total_gtt_size += vma->node.size;
                count++;
        }
        mutex_unlock(&dev->struct_mutex);

        seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
                   count, total_obj_size, total_gtt_size);
        return 0;
}

static int obj_rank_by_stolen(void *priv,
                              struct list_head *A, struct list_head *B)
{
        struct drm_i915_gem_object *a =
                container_of(A, struct drm_i915_gem_object, obj_exec_link);
        struct drm_i915_gem_object *b =
                container_of(B, struct drm_i915_gem_object, obj_exec_link);

        if (a->stolen->start < b->stolen->start)
                return -1;
        if (a->stolen->start > b->stolen->start)
                return 1;
        return 0;
}

static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
{
        struct drm_info_node *node = m->private;
        struct drm_device *dev = node->minor->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct drm_i915_gem_object *obj;
        u64 total_obj_size, total_gtt_size;
        LIST_HEAD(stolen);
        int count, ret;

        ret = mutex_lock_interruptible(&dev->struct_mutex);
        if (ret)
                return ret;

        total_obj_size = total_gtt_size = count = 0;
        list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
                if (obj->stolen == NULL)
                        continue;

                list_add(&obj->obj_exec_link, &stolen);

                total_obj_size += obj->base.size;
                total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
                count++;
        }
        list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
                if (obj->stolen == NULL)
                        continue;

                list_add(&obj->obj_exec_link, &stolen);

                total_obj_size += obj->base.size;
                count++;
        }
        list_sort(NULL, &stolen, obj_rank_by_stolen);
        seq_puts(m, "Stolen:\n");
        while (!list_empty(&stolen)) {
                obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
                seq_puts(m, "   ");
                describe_obj(m, obj);
                seq_putc(m, '\n');
                list_del_init(&obj->obj_exec_link);
        }
        mutex_unlock(&dev->struct_mutex);

        seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
                   count, total_obj_size, total_gtt_size);
        return 0;
}

#define count_objects(list, member) do { \
        list_for_each_entry(obj, list, member) { \
                size += i915_gem_obj_total_ggtt_size(obj); \
                ++count; \
                if (obj->map_and_fenceable) { \
                        mappable_size += i915_gem_obj_ggtt_size(obj); \
                        ++mappable_count; \
                } \
        } \
} while (0)

struct file_stats {
        struct drm_i915_file_private *file_priv;
        unsigned long count;
        u64 total, unbound;
        u64 global, shared;
        u64 active, inactive;
};

static int per_file_stats(int id, void *ptr, void *data)
{
        struct drm_i915_gem_object *obj = ptr;
        struct file_stats *stats = data;
        struct i915_vma *vma;

        stats->count++;
        stats->total += obj->base.size;

        if (obj->base.name || obj->base.dma_buf)
                stats->shared += obj->base.size;

        if (USES_FULL_PPGTT(obj->base.dev)) {
                list_for_each_entry(vma, &obj->vma_list, obj_link) {
                        struct i915_hw_ppgtt *ppgtt;

                        if (!drm_mm_node_allocated(&vma->node))
                                continue;

                        if (vma->is_ggtt) {
                                stats->global += obj->base.size;
                                continue;
                        }

                        ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
                        if (ppgtt->file_priv != stats->file_priv)
                                continue;

                        if (obj->active) /* XXX per-vma statistic */
                                stats->active += obj->base.size;
                        else
                                stats->inactive += obj->base.size;

                        return 0;
                }
        } else {
                if (i915_gem_obj_ggtt_bound(obj)) {
                        stats->global += obj->base.size;
                        if (obj->active)
                                stats->active += obj->base.size;
                        else
                                stats->inactive += obj->base.size;
                        return 0;
                }
        }

        if (!list_empty(&obj->global_list))
                stats->unbound += obj->base.size;

        return 0;
}

#define print_file_stats(m, name, stats) do { \
        if (stats.count) \
                seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
                           name, \
                           stats.count, \
                           stats.total, \
                           stats.active, \
                           stats.inactive, \
                           stats.global, \
                           stats.shared, \
                           stats.unbound); \
} while (0)

static void print_batch_pool_stats(struct seq_file *m,
                                   struct drm_i915_private *dev_priv)
{
        struct drm_i915_gem_object *obj;
        struct file_stats stats;
        struct intel_engine_cs *ring;
        int i, j;

        memset(&stats, 0, sizeof(stats));

        for_each_ring(ring, dev_priv, i) {
                for (j = 0; j < ARRAY_SIZE(ring->batch_pool.cache_list); j++) {
                        list_for_each_entry(obj,
                                            &ring->batch_pool.cache_list[j],
                                            batch_pool_link)
                                per_file_stats(0, obj, &stats);
                }
        }

        print_file_stats(m, "[k]batch pool", stats);
}

#define count_vmas(list, member) do { \
        list_for_each_entry(vma, list, member) { \
                size += i915_gem_obj_total_ggtt_size(vma->obj); \
                ++count; \
                if (vma->obj->map_and_fenceable) { \
                        mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
                        ++mappable_count; \
                } \
        } \
} while (0)

static int i915_gem_object_info(struct seq_file *m, void* data)
{
        struct drm_info_node *node = m->private;
        struct drm_device *dev = node->minor->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        u32 count, mappable_count, purgeable_count;
        u64 size, mappable_size, purgeable_size;
        struct drm_i915_gem_object *obj;
        struct i915_address_space *vm = &dev_priv->gtt.base;
        struct drm_file *file;
        struct i915_vma *vma;
        int ret;

        ret = mutex_lock_interruptible(&dev->struct_mutex);
        if (ret)
                return ret;

        seq_printf(m, "%u objects, %zu bytes\n",
                   dev_priv->mm.object_count,
                   dev_priv->mm.object_memory);

        size = count = mappable_size = mappable_count = 0;
        count_objects(&dev_priv->mm.bound_list, global_list);
        seq_printf(m, "%u [%u] objects, %llu [%llu] bytes in gtt\n",
                   count, mappable_count, size, mappable_size);

        size = count = mappable_size = mappable_count = 0;
        count_vmas(&vm->active_list, vm_link);
        seq_printf(m, "  %u [%u] active objects, %llu [%llu] bytes\n",
                   count, mappable_count, size, mappable_size);

        size = count = mappable_size = mappable_count = 0;
        count_vmas(&vm->inactive_list, vm_link);
        seq_printf(m, "  %u [%u] inactive objects, %llu [%llu] bytes\n",
                   count, mappable_count, size, mappable_size);

        size = count = purgeable_size = purgeable_count = 0;
        list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
                size += obj->base.size, ++count;
                if (obj->madv == I915_MADV_DONTNEED)
                        purgeable_size += obj->base.size, ++purgeable_count;
        }
        seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);

        size = count = mappable_size = mappable_count = 0;
        list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
                if (obj->fault_mappable) {
                        size += i915_gem_obj_ggtt_size(obj);
                        ++count;
                }
                if (obj->pin_display) {
                        mappable_size += i915_gem_obj_ggtt_size(obj);
                        ++mappable_count;
                }
                if (obj->madv == I915_MADV_DONTNEED) {
                        purgeable_size += obj->base.size;
                        ++purgeable_count;
                }
        }
        seq_printf(m, "%u purgeable objects, %llu bytes\n",
                   purgeable_count, purgeable_size);
        seq_printf(m, "%u pinned mappable objects, %llu bytes\n",
                   mappable_count, mappable_size);
        seq_printf(m, "%u fault mappable objects, %llu bytes\n",
                   count, size);

        seq_printf(m, "%llu [%llu] gtt total\n",
                   dev_priv->gtt.base.total,
                   (u64)dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);

        seq_putc(m, '\n');
        print_batch_pool_stats(m, dev_priv);
        list_for_each_entry_reverse(file, &dev->filelist, lhead) {
                struct file_stats stats;
                struct task_struct *task;

                memset(&stats, 0, sizeof(stats));
                stats.file_priv = file->driver_priv;
                spin_lock(&file->table_lock);
                idr_for_each(&file->object_idr, per_file_stats, &stats);
                spin_unlock(&file->table_lock);
                /*
                 * Although we have a valid reference on file->pid, that does
                 * not guarantee that the task_struct who called get_pid() is
                 * still alive (e.g. get_pid(current) => fork() => exit()).
                 * Therefore, we need to protect this ->comm access using RCU.
                 */
                rcu_read_lock();
                task = pid_task(file->pid, PIDTYPE_PID);
                print_file_stats(m, task ? task->comm : "<unknown>", stats);
                rcu_read_unlock();
        }

        mutex_unlock(&dev->struct_mutex);

        return 0;
}

static int i915_gem_gtt_info(struct seq_file *m, void *data)
{
        struct drm_info_node *node = m->private;
        struct drm_device *dev = node->minor->dev;
        uintptr_t list = (uintptr_t) node->info_ent->data;
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct drm_i915_gem_object *obj;
        u64 total_obj_size, total_gtt_size;
        int count, ret;

        ret = mutex_lock_interruptible(&dev->struct_mutex);
        if (ret)
                return ret;

        total_obj_size = total_gtt_size = count = 0;
        list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
                if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
                        continue;

                seq_puts(m, "   ");
                describe_obj(m, obj);
                seq_putc(m, '\n');
                total_obj_size += obj->base.size;
                total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
                count++;
        }

        mutex_unlock(&dev->struct_mutex);

        seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
                   count, total_obj_size, total_gtt_size);

        return 0;
}

static int i915_gem_pageflip_info(struct seq_file *m, void *data)
{
        struct drm_info_node *node = m->private;
        struct drm_device *dev = node->minor->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct intel_crtc *crtc;
        int ret;

        ret = mutex_lock_interruptible(&dev->struct_mutex);
        if (ret)
                return ret;

        for_each_intel_crtc(dev, crtc) {
                const char pipe = pipe_name(crtc->pipe);
                const char plane = plane_name(crtc->plane);
                struct intel_unpin_work *work;

                spin_lock_irq(&dev->event_lock);
                work = crtc->unpin_work;
                if (work == NULL) {
                        seq_printf(m, "No flip due on pipe %c (plane %c)\n",
                                   pipe, plane);
                } else {
                        u32 addr;

                        if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
                                seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
                                           pipe, plane);
                        } else {
                                seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
                                           pipe, plane);
                        }
                        if (work->flip_queued_req) {
                                struct intel_engine_cs *ring =
                                        i915_gem_request_get_ring(work->flip_queued_req);

                                seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
                                           ring->name,
                                           i915_gem_request_get_seqno(work->flip_queued_req),
                                           dev_priv->next_seqno,
                                           ring->get_seqno(ring, true),
                                           i915_gem_request_completed(work->flip_queued_req, true));
                        } else
                                seq_printf(m, "Flip not associated with any ring\n");
                        seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
                                   work->flip_queued_vblank,
                                   work->flip_ready_vblank,
                                   drm_crtc_vblank_count(&crtc->base));
                        if (work->enable_stall_check)
                                seq_puts(m, "Stall check enabled, ");
                        else
                                seq_puts(m, "Stall check waiting for page flip ioctl, ");
                        seq_printf(m, "%d prepares\n", atomic_read(&work->pending));

                        if (INTEL_INFO(dev)->gen >= 4)
                                addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
                        else
                                addr = I915_READ(DSPADDR(crtc->plane));
                        seq_printf(m, "Current scanout address 0x%08x\n", addr);

                        if (work->pending_flip_obj) {
                                seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
                                seq_printf(m, "MMIO update completed? %d\n",  addr == work->gtt_offset);
                        }
                }
                spin_unlock_irq(&dev->event_lock);
        }

        mutex_unlock(&dev->struct_mutex);

        return 0;
}

static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
{
        struct drm_info_node *node = m->private;
        struct drm_device *dev = node->minor->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct drm_i915_gem_object *obj;
        struct intel_engine_cs *ring;
        int total = 0;
        int ret, i, j;

        ret = mutex_lock_interruptible(&dev->struct_mutex);
        if (ret)
                return ret;

        for_each_ring(ring, dev_priv, i) {
                for (j = 0; j < ARRAY_SIZE(ring->batch_pool.cache_list); j++) {
                        int count;

                        count = 0;
                        list_for_each_entry(obj,
                                            &ring->batch_pool.cache_list[j],
                                            batch_pool_link)
                                count++;
                        seq_printf(m, "%s cache[%d]: %d objects\n",
                                   ring->name, j, count);

                        list_for_each_entry(obj,
                                            &ring->batch_pool.cache_list[j],
                                            batch_pool_link) {
                                seq_puts(m, "   ");
                                describe_obj(m, obj);
                                seq_putc(m, '\n');
                        }

                        total += count;
                }
        }

        seq_printf(m, "total: %d\n", total);

        mutex_unlock(&dev->struct_mutex);

        return 0;
}

static int i915_gem_request_info(struct seq_file *m, void *data)
{
        struct drm_info_node *node = m->private;
        struct drm_device *dev = node->minor->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct intel_engine_cs *ring;
        struct drm_i915_gem_request *req;
        int ret, any, i;

        ret = mutex_lock_interruptible(&dev->struct_mutex);
        if (ret)
                return ret;

        any = 0;
        for_each_ring(ring, dev_priv, i) {
                int count;

                count = 0;
                list_for_each_entry(req, &ring->request_list, list)
                        count++;
                if (count == 0)
                        continue;

                seq_printf(m, "%s requests: %d\n", ring->name, count);
                list_for_each_entry(req, &ring->request_list, list) {
                        struct task_struct *task;

                        rcu_read_lock();
                        task = NULL;
                        if (req->pid)
                                task = pid_task(req->pid, PIDTYPE_PID);
                        seq_printf(m, "    %x @ %d: %s [%d]\n",
                                   req->seqno,
                                   (int) (jiffies - req->emitted_jiffies),
                                   task ? task->comm : "<unknown>",
                                   task ? task->pid : -1);
                        rcu_read_unlock();
                }

                any++;
        }
        mutex_unlock(&dev->struct_mutex);

        if (any == 0)
                seq_puts(m, "No requests\n");

        return 0;
}

static void i915_ring_seqno_info(struct seq_file *m,
                                 struct intel_engine_cs *ring)
{
        if (ring->get_seqno) {
                seq_printf(m, "Current sequence (%s): %x\n",
                           ring->name, ring->get_seqno(ring, false));
        }
}

static int i915_gem_seqno_info(struct seq_file *m, void *data)
{
        struct drm_info_node *node = m->private;
        struct drm_device *dev = node->minor->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct intel_engine_cs *ring;
        int ret, i;

        ret = mutex_lock_interruptible(&dev->struct_mutex);
        if (ret)
                return ret;
        intel_runtime_pm_get(dev_priv);

        for_each_ring(ring, dev_priv, i)
                i915_ring_seqno_info(m, ring);

        intel_runtime_pm_put(dev_priv);
        mutex_unlock(&dev->struct_mutex);

        return 0;
}


static int i915_interrupt_info(struct seq_file *m, void *data)
{
        struct drm_info_node *node = m->private;
        struct drm_device *dev = node->minor->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct intel_engine_cs *ring;
        int ret, i, pipe;

        ret = mutex_lock_interruptible(&dev->struct_mutex);
        if (ret)
                return ret;
        intel_runtime_pm_get(dev_priv);

        if (IS_CHERRYVIEW(dev)) {
                seq_printf(m, "Master Interrupt Control:\t%08x\n",
                           I915_READ(GEN8_MASTER_IRQ));

                seq_printf(m, "Display IER:\t%08x\n",
                           I915_READ(VLV_IER));
                seq_printf(m, "Display IIR:\t%08x\n",
                           I915_READ(VLV_IIR));
                seq_printf(m, "Display IIR_RW:\t%08x\n",
                           I915_READ(VLV_IIR_RW));
                seq_printf(m, "Display IMR:\t%08x\n",
                           I915_READ(VLV_IMR));
                for_each_pipe(dev_priv, pipe)
                        seq_printf(m, "Pipe %c stat:\t%08x\n",
                                   pipe_name(pipe),
                                   I915_READ(PIPESTAT(pipe)));

                seq_printf(m, "Port hotplug:\t%08x\n",
                           I915_READ(PORT_HOTPLUG_EN));
                seq_printf(m, "DPFLIPSTAT:\t%08x\n",
                           I915_READ(VLV_DPFLIPSTAT));
                seq_printf(m, "DPINVGTT:\t%08x\n",
                           I915_READ(DPINVGTT));

                for (i = 0; i < 4; i++) {
                        seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
                                   i, I915_READ(GEN8_GT_IMR(i)));
                        seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
                                   i, I915_READ(GEN8_GT_IIR(i)));
                        seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
                                   i, I915_READ(GEN8_GT_IER(i)));
                }

                seq_printf(m, "PCU interrupt mask:\t%08x\n",
                           I915_READ(GEN8_PCU_IMR));
                seq_printf(m, "PCU interrupt identity:\t%08x\n",
                           I915_READ(GEN8_PCU_IIR));
                seq_printf(m, "PCU interrupt enable:\t%08x\n",
                           I915_READ(GEN8_PCU_IER));
        } else if (INTEL_INFO(dev)->gen >= 8) {
                seq_printf(m, "Master Interrupt Control:\t%08x\n",
                           I915_READ(GEN8_MASTER_IRQ));

                for (i = 0; i < 4; i++) {
                        seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
                                   i, I915_READ(GEN8_GT_IMR(i)));
                        seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
                                   i, I915_READ(GEN8_GT_IIR(i)));
                        seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
                                   i, I915_READ(GEN8_GT_IER(i)));
                }

                for_each_pipe(dev_priv, pipe) {
                        enum intel_display_power_domain power_domain;

                        power_domain = POWER_DOMAIN_PIPE(pipe);
                        if (!intel_display_power_get_if_enabled(dev_priv,
                                                                power_domain)) {
                                seq_printf(m, "Pipe %c power disabled\n",
                                           pipe_name(pipe));
                                continue;
                        }
                        seq_printf(m, "Pipe %c IMR:\t%08x\n",
                                   pipe_name(pipe),
                                   I915_READ(GEN8_DE_PIPE_IMR(pipe)));
                        seq_printf(m, "Pipe %c IIR:\t%08x\n",
                                   pipe_name(pipe),
                                   I915_READ(GEN8_DE_PIPE_IIR(pipe)));
                        seq_printf(m, "Pipe %c IER:\t%08x\n",
                                   pipe_name(pipe),
                                   I915_READ(GEN8_DE_PIPE_IER(pipe)));

                        intel_display_power_put(dev_priv, power_domain);
                }

                seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
                           I915_READ(GEN8_DE_PORT_IMR));
                seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
                           I915_READ(GEN8_DE_PORT_IIR));
                seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
                           I915_READ(GEN8_DE_PORT_IER));

                seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
                           I915_READ(GEN8_DE_MISC_IMR));
                seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
                           I915_READ(GEN8_DE_MISC_IIR));
                seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
                           I915_READ(GEN8_DE_MISC_IER));

                seq_printf(m, "PCU interrupt mask:\t%08x\n",
                           I915_READ(GEN8_PCU_IMR));
                seq_printf(m, "PCU interrupt identity:\t%08x\n",
                           I915_READ(GEN8_PCU_IIR));
                seq_printf(m, "PCU interrupt enable:\t%08x\n",
                           I915_READ(GEN8_PCU_IER));
        } else if (IS_VALLEYVIEW(dev)) {
                seq_printf(m, "Display IER:\t%08x\n",
                           I915_READ(VLV_IER));
                seq_printf(m, "Display IIR:\t%08x\n",
                           I915_READ(VLV_IIR));
                seq_printf(m, "Display IIR_RW:\t%08x\n",
                           I915_READ(VLV_IIR_RW));
                seq_printf(m, "Display IMR:\t%08x\n",
                           I915_READ(VLV_IMR));
                for_each_pipe(dev_priv, pipe)
                        seq_printf(m, "Pipe %c stat:\t%08x\n",
                                   pipe_name(pipe),
                                   I915_READ(PIPESTAT(pipe)));

                seq_printf(m, "Master IER:\t%08x\n",
                           I915_READ(VLV_MASTER_IER));

                seq_printf(m, "Render IER:\t%08x\n",
                           I915_READ(GTIER));
                seq_printf(m, "Render IIR:\t%08x\n",
                           I915_READ(GTIIR));
                seq_printf(m, "Render IMR:\t%08x\n",
                           I915_READ(GTIMR));

                seq_printf(m, "PM IER:\t\t%08x\n",
                           I915_READ(GEN6_PMIER));
                seq_printf(m, "PM IIR:\t\t%08x\n",
                           I915_READ(GEN6_PMIIR));
                seq_printf(m, "PM IMR:\t\t%08x\n",
                           I915_READ(GEN6_PMIMR));

                seq_printf(m, "Port hotplug:\t%08x\n",
                           I915_READ(PORT_HOTPLUG_EN));
                seq_printf(m, "DPFLIPSTAT:\t%08x\n",
                           I915_READ(VLV_DPFLIPSTAT));
                seq_printf(m, "DPINVGTT:\t%08x\n",
                           I915_READ(DPINVGTT));

        } else if (!HAS_PCH_SPLIT(dev)) {
                seq_printf(m, "Interrupt enable:    %08x\n",
                           I915_READ(IER));
                seq_printf(m, "Interrupt identity:  %08x\n",
                           I915_READ(IIR));
                seq_printf(m, "Interrupt mask:      %08x\n",
                           I915_READ(IMR));
                for_each_pipe(dev_priv, pipe)
                        seq_printf(m, "Pipe %c stat:         %08x\n",
                                   pipe_name(pipe),
                                   I915_READ(PIPESTAT(pipe)));
        } else {
                seq_printf(m, "North Display Interrupt enable:          %08x\n",
                           I915_READ(DEIER));
                seq_printf(m, "North Display Interrupt identity:        %08x\n",
                           I915_READ(DEIIR));
                seq_printf(m, "North Display Interrupt mask:            %08x\n",
                           I915_READ(DEIMR));
                seq_printf(m, "South Display Interrupt enable:          %08x\n",
                           I915_READ(SDEIER));
                seq_printf(m, "South Display Interrupt identity:        %08x\n",
                           I915_READ(SDEIIR));
                seq_printf(m, "South Display Interrupt mask:            %08x\n",
                           I915_READ(SDEIMR));
                seq_printf(m, "Graphics Interrupt enable:               %08x\n",
                           I915_READ(GTIER));
                seq_printf(m, "Graphics Interrupt identity:             %08x\n",
                           I915_READ(GTIIR));
                seq_printf(m, "Graphics Interrupt mask:         %08x\n",
                           I915_READ(GTIMR));
        }
        for_each_ring(ring, dev_priv, i) {
                if (INTEL_INFO(dev)->gen >= 6) {
                        seq_printf(m,
                                   "Graphics Interrupt mask (%s):       %08x\n",
                                   ring->name, I915_READ_IMR(ring));
                }
                i915_ring_seqno_info(m, ring);
        }
        intel_runtime_pm_put(dev_priv);
        mutex_unlock(&dev->struct_mutex);

        return 0;
}

static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
{
        struct drm_info_node *node = m->private;
        struct drm_device *dev = node->minor->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        int i, ret;

        ret = mutex_lock_interruptible(&dev->struct_mutex);
        if (ret)
                return ret;

        seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
        for (i = 0; i < dev_priv->num_fence_regs; i++) {
                struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;

                seq_printf(m, "Fence %d, pin count = %d, object = ",
                           i, dev_priv->fence_regs[i].pin_count);
                if (obj == NULL)
                        seq_puts(m, "unused");
                else
                        describe_obj(m, obj);
                seq_putc(m, '\n');
        }

        mutex_unlock(&dev->struct_mutex);
        return 0;
}

static int i915_hws_info(struct seq_file *m, void *data)
{
        struct drm_info_node *node = m->private;
        struct drm_device *dev = node->minor->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct intel_engine_cs *ring;
        const u32 *hws;
        int i;

        ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
        hws = ring->status_page.page_addr;
        if (hws == NULL)
                return 0;

        for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
                seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
                           i * 4,
                           hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
        }
        return 0;
}

static ssize_t
i915_error_state_write(struct file *filp,
                       const char __user *ubuf,
                       size_t cnt,
                       loff_t *ppos)
{
        struct i915_error_state_file_priv *error_priv = filp->private_data;
        struct drm_device *dev = error_priv->dev;
        int ret;

        DRM_DEBUG_DRIVER("Resetting error state\n");

        ret = mutex_lock_interruptible(&dev->struct_mutex);
        if (ret)
                return ret;

        i915_destroy_error_state(dev);
        mutex_unlock(&dev->struct_mutex);

        return cnt;
}

static int i915_error_state_open(struct inode *inode, struct file *file)
{
        struct drm_device *dev = inode->i_private;
        struct i915_error_state_file_priv *error_priv;

        error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
        if (!error_priv)
                return -ENOMEM;

        error_priv->dev = dev;

        i915_error_state_get(dev, error_priv);

        file->private_data = error_priv;

        return 0;
}

static int i915_error_state_release(struct inode *inode, struct file *file)
{
        struct i915_error_state_file_priv *error_priv = file->private_data;

        i915_error_state_put(error_priv);
        kfree(error_priv);

        return 0;
}

static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
                                     size_t count, loff_t *pos)
{
        struct i915_error_state_file_priv *error_priv = file->private_data;
        struct drm_i915_error_state_buf error_str;
        loff_t tmp_pos = 0;
        ssize_t ret_count = 0;
        int ret;

        ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
        if (ret)
                return ret;

        ret = i915_error_state_to_str(&error_str, error_priv);
        if (ret)
                goto out;

        ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
                                            error_str.buf,
                                            error_str.bytes);

        if (ret_count < 0)
                ret = ret_count;
        else
                *pos = error_str.start + ret_count;
out:
        i915_error_state_buf_release(&error_str);
        return ret ?: ret_count;
}

static const struct file_operations i915_error_state_fops = {
        .owner = THIS_MODULE,
        .open = i915_error_state_open,
        .read = i915_error_state_read,
        .write = i915_error_state_write,
        .llseek = default_llseek,
        .release = i915_error_state_release,
};

static int
i915_next_seqno_get(void *data, u64 *val)
{
        struct drm_device *dev = data;
        struct drm_i915_private *dev_priv = dev->dev_private;
        int ret;

        ret = mutex_lock_interruptible(&dev->struct_mutex);
        if (ret)
                return ret;

        *val = dev_priv->next_seqno;
        mutex_unlock(&dev->struct_mutex);

        return 0;
}

static int
i915_next_seqno_set(void *data, u64 val)
{
        struct drm_device *dev = data;
        int ret;

        ret = mutex_lock_interruptible(&dev->struct_mutex);
        if (ret)
                return ret;

        ret = i915_gem_set_seqno(dev, val);
        mutex_unlock(&dev->struct_mutex);

        return ret;
}

DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
                        i915_next_seqno_get, i915_next_seqno_set,
                        "0x%llx\n");

static int i915_frequency_info(struct seq_file *m, void *unused)
{
        struct drm_info_node *node = m->private;
        struct drm_device *dev = node->minor->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        int ret = 0;

        intel_runtime_pm_get(dev_priv);

        flush_delayed_work(&dev_priv->rps.delayed_resume_work);

        if (IS_GEN5(dev)) {
                u16 rgvswctl = I915_READ16(MEMSWCTL);
                u16 rgvstat = I915_READ16(MEMSTAT_ILK);

                seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
                seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
                seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
                           MEMSTAT_VID_SHIFT);
                seq_printf(m, "Current P-state: %d\n",
                           (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
        } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
                u32 freq_sts;

                mutex_lock(&dev_priv->rps.hw_lock);
                freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
                seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
                seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);

                seq_printf(m, "actual GPU freq: %d MHz\n",
                           intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));

                seq_printf(m, "current GPU freq: %d MHz\n",
                           intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));

                seq_printf(m, "max GPU freq: %d MHz\n",
                           intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));

                seq_printf(m, "min GPU freq: %d MHz\n",
                           intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));

                seq_printf(m, "idle GPU freq: %d MHz\n",
                           intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));

                seq_printf(m,
                           "efficient (RPe) frequency: %d MHz\n",
                           intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
                mutex_unlock(&dev_priv->rps.hw_lock);
        } else if (INTEL_INFO(dev)->gen >= 6) {
                u32 rp_state_limits;
                u32 gt_perf_status;
                u32 rp_state_cap;
                u32 rpmodectl, rpinclimit, rpdeclimit;
                u32 rpstat, cagf, reqf;
                u32 rpupei, rpcurup, rpprevup;
                u32 rpdownei, rpcurdown, rpprevdown;
                u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
                int max_freq;

                rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
                if (IS_BROXTON(dev)) {
                        rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
                        gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
                } else {
                        rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
                        gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
                }

                /* RPSTAT1 is in the GT power well */
                ret = mutex_lock_interruptible(&dev->struct_mutex);
                if (ret)
                        goto out;

                intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);

                reqf = I915_READ(GEN6_RPNSWREQ);
                if (IS_GEN9(dev))
                        reqf >>= 23;
                else {
                        reqf &= ~GEN6_TURBO_DISABLE;
                        if (IS_HASWELL(dev) || IS_BROADWELL(dev))
                                reqf >>= 24;
                        else
                                reqf >>= 25;
                }
                reqf = intel_gpu_freq(dev_priv, reqf);

                rpmodectl = I915_READ(GEN6_RP_CONTROL);
                rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
                rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);

                rpstat = I915_READ(GEN6_RPSTAT1);
                rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
                rpcurup = I915_READ(GEN6_RP_CUR_UP);
                rpprevup = I915_READ(GEN6_RP_PREV_UP);
                rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
                rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
                rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
                if (IS_GEN9(dev))
                        cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
                else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
                        cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
                else
                        cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
                cagf = intel_gpu_freq(dev_priv, cagf);

                intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
                mutex_unlock(&dev->struct_mutex);

                if (IS_GEN6(dev) || IS_GEN7(dev)) {
                        pm_ier = I915_READ(GEN6_PMIER);
                        pm_imr = I915_READ(GEN6_PMIMR);
                        pm_isr = I915_READ(GEN6_PMISR);
                        pm_iir = I915_READ(GEN6_PMIIR);
                        pm_mask = I915_READ(GEN6_PMINTRMSK);
                } else {
                        pm_ier = I915_READ(GEN8_GT_IER(2));
                        pm_imr = I915_READ(GEN8_GT_IMR(2));
                        pm_isr = I915_READ(GEN8_GT_ISR(2));
                        pm_iir = I915_READ(GEN8_GT_IIR(2));
                        pm_mask = I915_READ(GEN6_PMINTRMSK);
                }
                seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
                           pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
                seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
                seq_printf(m, "Render p-state ratio: %d\n",
                           (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8);
                seq_printf(m, "Render p-state VID: %d\n",
                           gt_perf_status & 0xff);
                seq_printf(m, "Render p-state limit: %d\n",
                           rp_state_limits & 0xff);
                seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
                seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
                seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
                seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
                seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
                seq_printf(m, "CAGF: %dMHz\n", cagf);
                seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
                           GEN6_CURICONT_MASK);
                seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
                           GEN6_CURBSYTAVG_MASK);
                seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
                           GEN6_CURBSYTAVG_MASK);
                seq_printf(m, "Up threshold: %d%%\n",
                           dev_priv->rps.up_threshold);

                seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
                           GEN6_CURIAVG_MASK);
                seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
                           GEN6_CURBSYTAVG_MASK);
                seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
                           GEN6_CURBSYTAVG_MASK);
                seq_printf(m, "Down threshold: %d%%\n",
                           dev_priv->rps.down_threshold);

                max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 0 :
                            rp_state_cap >> 16) & 0xff;
                max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
                             GEN9_FREQ_SCALER : 1);
                seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
                           intel_gpu_freq(dev_priv, max_freq));

                max_freq = (rp_state_cap & 0xff00) >> 8;
                max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
                             GEN9_FREQ_SCALER : 1);
                seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
                           intel_gpu_freq(dev_priv, max_freq));

                max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 16 :
                            rp_state_cap >> 0) & 0xff;
                max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
                             GEN9_FREQ_SCALER : 1);
                seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
                           intel_gpu_freq(dev_priv, max_freq));
                seq_printf(m, "Max overclocked frequency: %dMHz\n",
                           intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));

                seq_printf(m, "Current freq: %d MHz\n",
                           intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
                seq_printf(m, "Actual freq: %d MHz\n", cagf);
                seq_printf(m, "Idle freq: %d MHz\n",
                           intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
                seq_printf(m, "Min freq: %d MHz\n",
                           intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
                seq_printf(m, "Max freq: %d MHz\n",
                           intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
                seq_printf(m,
                           "efficient (RPe) frequency: %d MHz\n",
                           intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
        } else {
                seq_puts(m, "no P-state info available\n");
        }

        seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk_freq);
        seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
        seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);

out:
        intel_runtime_pm_put(dev_priv);
        return ret;
}

static int i915_hangcheck_info(struct seq_file *m, void *unused)
{
        struct drm_info_node *node = m->private;
        struct drm_device *dev = node->minor->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct intel_engine_cs *ring;
        u64 acthd[I915_NUM_RINGS];
        u32 seqno[I915_NUM_RINGS];
        u32 instdone[I915_NUM_INSTDONE_REG];
        int i, j;

        if (!i915.enable_hangcheck) {
                seq_printf(m, "Hangcheck disabled\n");
                return 0;
        }

        intel_runtime_pm_get(dev_priv);

        for_each_ring(ring, dev_priv, i) {
                seqno[i] = ring->get_seqno(ring, false);
                acthd[i] = intel_ring_get_active_head(ring);
        }

        i915_get_extra_instdone(dev, instdone);

        intel_runtime_pm_put(dev_priv);

        if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
                seq_printf(m, "Hangcheck active, fires in %dms\n",
                           jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
                                            jiffies));
        } else
                seq_printf(m, "Hangcheck inactive\n");

        for_each_ring(ring, dev_priv, i) {
                seq_printf(m, "%s:\n", ring->name);
                seq_printf(m, "\tseqno = %x [current %x]\n",
                           ring->hangcheck.seqno, seqno[i]);
                seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
                           (long long)ring->hangcheck.acthd,
                           (long long)acthd[i]);
                seq_printf(m, "\tmax ACTHD = 0x%08llx\n",
                           (long long)ring->hangcheck.max_acthd);
                seq_printf(m, "\tscore = %d\n", ring->hangcheck.score);
                seq_printf(m, "\taction = %d\n", ring->hangcheck.action);

                if (ring->id == RCS) {
                        seq_puts(m, "\tinstdone read =");

                        for (j = 0; j < I915_NUM_INSTDONE_REG; j++)
                                seq_printf(m, " 0x%08x", instdone[j]);

                        seq_puts(m, "\n\tinstdone accu =");

                        for (j = 0; j < I915_NUM_INSTDONE_REG; j++)
                                seq_printf(m, " 0x%08x",
                                           ring->hangcheck.instdone[j]);

                        seq_puts(m, "\n");
                }
        }

        return 0;
}

static int ironlake_drpc_info(struct seq_file *m)
{
        struct drm_info_node *node = m->private;
        struct drm_device *dev = node->minor->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        u32 rgvmodectl, rstdbyctl;
        u16 crstandvid;
        int ret;

        ret = mutex_lock_interruptible(&dev->struct_mutex);
        if (ret)
                return ret;
        intel_runtime_pm_get(dev_priv);

        rgvmodectl = I915_READ(MEMMODECTL);
        rstdbyctl = I915_READ(RSTDBYCTL);
        crstandvid = I915_READ16(CRSTANDVID);

        intel_runtime_pm_put(dev_priv);
        mutex_unlock(&dev->struct_mutex);

        seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
        seq_printf(m, "Boost freq: %d\n",
                   (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
                   MEMMODE_BOOST_FREQ_SHIFT);
        seq_printf(m, "HW control enabled: %s\n",
                   yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
        seq_printf(m, "SW control enabled: %s\n",
                   yesno(rgvmodectl & MEMMODE_SWMODE_EN));
        seq_printf(m, "Gated voltage change: %s\n",
                   yesno(rgvmodectl & MEMMODE_RCLK_GATE));
        seq_printf(m, "Starting frequency: P%d\n",
                   (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
        seq_printf(m, "Max P-state: P%d\n",
                   (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
        seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
        seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
        seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
        seq_printf(m, "Render standby enabled: %s\n",
                   yesno(!(rstdbyctl & RCX_SW_EXIT)));
        seq_puts(m, "Current RS state: ");
        switch (rstdbyctl & RSX_STATUS_MASK) {
        case RSX_STATUS_ON:
                seq_puts(m, "on\n");
                break;
        case RSX_STATUS_RC1:
                seq_puts(m, "RC1\n");
                break;
        case RSX_STATUS_RC1E:
                seq_puts(m, "RC1E\n");
                break;
        case RSX_STATUS_RS1:
                seq_puts(m, "RS1\n");
                break;
        case RSX_STATUS_RS2:
                seq_puts(m, "RS2 (RC6)\n");
                break;
        case RSX_STATUS_RS3:
                seq_puts(m, "RC3 (RC6+)\n");
                break;
        default:
                seq_puts(m, "unknown\n");
                break;
        }

        return 0;
}

static int i915_forcewake_domains(struct seq_file *m, void *data)
{
        struct drm_info_node *node = m->private;
        struct drm_device *dev = node->minor->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct intel_uncore_forcewake_domain *fw_domain;
        int i;

        spin_lock_irq(&dev_priv->uncore.lock);
        for_each_fw_domain(fw_domain, dev_priv, i) {
                seq_printf(m, "%s.wake_count = %u\n",
                           intel_uncore_forcewake_domain_to_str(i),
                           fw_domain->wake_count);
        }
        spin_unlock_irq(&dev_priv->uncore.lock);

        return 0;
}

static int vlv_drpc_info(struct seq_file *m)
{
        struct drm_info_node *node = m->private;
        struct drm_device *dev = node->minor->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        u32 rpmodectl1, rcctl1, pw_status;

        intel_runtime_pm_get(dev_priv);

        pw_status = I915_READ(VLV_GTLC_PW_STATUS);
        rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
        rcctl1 = I915_READ(GEN6_RC_CONTROL);

        intel_runtime_pm_put(dev_priv);

        seq_printf(m, "Video Turbo Mode: %s\n",
                   yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
        seq_printf(m, "Turbo enabled: %s\n",
                   yesno(rpmodectl1 & GEN6_RP_ENABLE));
        seq_printf(m, "HW control enabled: %s\n",
                   yesno(rpmodectl1 & GEN6_RP_ENABLE));
        seq_printf(m, "SW control enabled: %s\n",
                   yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
                          GEN6_RP_MEDIA_SW_MODE));
        seq_printf(m, "RC6 Enabled: %s\n",
                   yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
                                        GEN6_RC_CTL_EI_MODE(1))));
        seq_printf(m, "Render Power Well: %s\n",
                   (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
        seq_printf(m, "Media Power Well: %s\n",
                   (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");

        seq_printf(m, "Render RC6 residency since boot: %u\n",
                   I915_READ(VLV_GT_RENDER_RC6));
        seq_printf(m, "Media RC6 residency since boot: %u\n",
                   I915_READ(VLV_GT_MEDIA_RC6));

        return i915_forcewake_domains(m, NULL);
}

static int gen6_drpc_info(struct seq_file *m)
{
        struct drm_info_node *node = m->private;
        struct drm_device *dev = node->minor->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
        unsigned forcewake_count;
        int count = 0, ret;

        ret = mutex_lock_interruptible(&dev->struct_mutex);
        if (ret)
                return ret;
        intel_runtime_pm_get(dev_priv);

        spin_lock_irq(&dev_priv->uncore.lock);
        forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
        spin_unlock_irq(&dev_priv->uncore.lock);

        if (forcewake_count) {
                seq_puts(m, "RC information inaccurate because somebody "
                            "holds a forcewake reference \n");
        } else {
                /* NB: we cannot use forcewake, else we read the wrong values */
                while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
                        udelay(10);
                seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
        }

        gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS);
        trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);

        rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
        rcctl1 = I915_READ(GEN6_RC_CONTROL);
        mutex_unlock(&dev->struct_mutex);
        mutex_lock(&dev_priv->rps.hw_lock);
        sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
        mutex_unlock(&dev_priv->rps.hw_lock);

        intel_runtime_pm_put(dev_priv);

        seq_printf(m, "Video Turbo Mode: %s\n",
                   yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
        seq_printf(m, "HW control enabled: %s\n",
                   yesno(rpmodectl1 & GEN6_RP_ENABLE));
        seq_printf(m, "SW control enabled: %s\n",
                   yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
                          GEN6_RP_MEDIA_SW_MODE));
        seq_printf(m, "RC1e Enabled: %s\n",
                   yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
        seq_printf(m, "RC6 Enabled: %s\n",
                   yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
        seq_printf(m, "Deep RC6 Enabled: %s\n",
                   yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
        seq_printf(m, "Deepest RC6 Enabled: %s\n",
                   yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
        seq_puts(m, "Current RC state: ");
        switch (gt_core_status & GEN6_RCn_MASK) {
        case GEN6_RC0:
                if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
                        seq_puts(m, "Core Power Down\n");
                else
                        seq_puts(m, "on\n");
                break;
        case GEN6_RC3:
                seq_puts(m, "RC3\n");
                break;
        case GEN6_RC6:
                seq_puts(m, "RC6\n");
                break;
        case GEN6_RC7:
                seq_puts(m, "RC7\n");
                break;
        default:
                seq_puts(m, "Unknown\n");
                break;
        }

        seq_printf(m, "Core Power Down: %s\n",
                   yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));

        /* Not exactly sure what this is */
        seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
                   I915_READ(GEN6_GT_GFX_RC6_LOCKED));
        seq_printf(m, "RC6 residency since boot: %u\n",
                   I915_READ(GEN6_GT_GFX_RC6));
        seq_printf(m, "RC6+ residency since boot: %u\n",
                   I915_READ(GEN6_GT_GFX_RC6p));
        seq_printf(m, "RC6++ residency since boot: %u\n",
                   I915_READ(GEN6_GT_GFX_RC6pp));

        seq_printf(m, "RC6   voltage: %dmV\n",
                   GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
        seq_printf(m, "RC6+  voltage: %dmV\n",
                   GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
        seq_printf(m, "RC6++ voltage: %dmV\n",
                   GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
        return 0;
}

static int i915_drpc_info(struct seq_file *m, void *unused)
{
        struct drm_info_node *node = m->private;
        struct drm_device *dev = node->minor->dev;

        if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
                return vlv_drpc_info(m);
        else if (INTEL_INFO(dev)->gen >= 6)
                return gen6_drpc_info(m);
        else
                return ironlake_drpc_info(m);
}

static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
{
        struct drm_info_node *node = m->private;
        struct drm_device *dev = node->minor->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;

        seq_printf(m, "FB tracking busy bits: 0x%08x\n",
                   dev_priv->fb_tracking.busy_bits);

        seq_printf(m, "FB tracking flip bits: 0x%08x\n",
                   dev_priv->fb_tracking.flip_bits);

        return 0;
}

static int i915_fbc_status(struct seq_file *m, void *unused)
{
        struct drm_info_node *node = m->private;
        struct drm_device *dev = node->minor->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;

        if (!HAS_FBC(dev)) {
                seq_puts(m, "FBC unsupported on this chipset\n");
                return 0;
        }

        intel_runtime_pm_get(dev_priv);
        mutex_lock(&dev_priv->fbc.lock);

        if (intel_fbc_is_active(dev_priv))
                seq_puts(m, "FBC enabled\n");
        else
                seq_printf(m, "FBC disabled: %s\n",
                           dev_priv->fbc.no_fbc_reason);

        if (INTEL_INFO(dev_priv)->gen >= 7)
                seq_printf(m, "Compressing: %s\n",
                           yesno(I915_READ(FBC_STATUS2) &
                                 FBC_COMPRESSION_MASK));

        mutex_unlock(&dev_priv->fbc.lock);
        intel_runtime_pm_put(dev_priv);

        return 0;
}

static int i915_fbc_fc_get(void *data, u64 *val)
{
        struct drm_device *dev = data;
        struct drm_i915_private *dev_priv = dev->dev_private;

        if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
                return -ENODEV;

        *val = dev_priv->fbc.false_color;

        return 0;
}

static int i915_fbc_fc_set(void *data, u64 val)
{
        struct drm_device *dev = data;
        struct drm_i915_private *dev_priv = dev->dev_private;
        u32 reg;

        if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
                return -ENODEV;

        mutex_lock(&dev_priv->fbc.lock);

        reg = I915_READ(ILK_DPFC_CONTROL);
        dev_priv->fbc.false_color = val;

        I915_WRITE(ILK_DPFC_CONTROL, val ?
                   (reg | FBC_CTL_FALSE_COLOR) :
                   (reg & ~FBC_CTL_FALSE_COLOR));

        mutex_unlock(&dev_priv->fbc.lock);
        return 0;
}

DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
                        i915_fbc_fc_get, i915_fbc_fc_set,
                        "%llu\n");

static int i915_ips_status(struct seq_file *m, void *unused)
{
        struct drm_info_node *node = m->private;
        struct drm_device *dev = node->minor->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;

        if (!HAS_IPS(dev)) {
                seq_puts(m, "not supported\n");
                return 0;
        }

        intel_runtime_pm_get(dev_priv);

        seq_printf(m, "Enabled by kernel parameter: %s\n",
                   yesno(i915.enable_ips));

        if (INTEL_INFO(dev)->gen >= 8) {
                seq_puts(m, "Currently: unknown\n");
        } else {
                if (I915_READ(IPS_CTL) & IPS_ENABLE)
                        seq_puts(m, "Currently: enabled\n");
                else
                        seq_puts(m, "Currently: disabled\n");
        }

        intel_runtime_pm_put(dev_priv);

        return 0;
}

static int i915_sr_status(struct seq_file *m, void *unused)
{
        struct drm_info_node *node = m->private;
        struct drm_device *dev = node->minor->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        bool sr_enabled = false;

        intel_runtime_pm_get(dev_priv);

        if (HAS_PCH_SPLIT(dev))
                sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
        else if (IS_CRESTLINE(dev) || IS_G4X(dev) ||
                 IS_I945G(dev) || IS_I945GM(dev))
                sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
        else if (IS_I915GM(dev))
                sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
        else if (IS_PINEVIEW(dev))
                sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
        else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
                sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;

        intel_runtime_pm_put(dev_priv);

        seq_printf(m, "self-refresh: %s\n",
                   sr_enabled ? "enabled" : "disabled");

        return 0;
}

static int i915_emon_status(struct seq_file *m, void *unused)
{
        struct drm_info_node *node = m->private;
        struct drm_device *dev = node->minor->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        unsigned long temp, chipset, gfx;
        int ret;

        if (!IS_GEN5(dev))
                return -ENODEV;

        ret = mutex_lock_interruptible(&dev->struct_mutex);
        if (ret)
                return ret;

        temp = i915_mch_val(dev_priv);
        chipset = i915_chipset_val(dev_priv);
        gfx = i915_gfx_val(dev_priv);
        mutex_unlock(&dev->struct_mutex);

        seq_printf(m, "GMCH temp: %ld\n", temp);
        seq_printf(m, "Chipset power: %ld\n", chipset);
        seq_printf(m, "GFX power: %ld\n", gfx);
        seq_printf(m, "Total power: %ld\n", chipset + gfx);

        return 0;
}

static int i915_ring_freq_table(struct seq_file *m, void *unused)
{
        struct drm_info_node *node = m->private;
        struct drm_device *dev = node->minor->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        int ret = 0;
        int gpu_freq, ia_freq;
        unsigned int max_gpu_freq, min_gpu_freq;

        if (!HAS_CORE_RING_FREQ(dev)) {
                seq_puts(m, "unsupported on this chipset\n");
                return 0;
        }

        intel_runtime_pm_get(dev_priv);

        flush_delayed_work(&dev_priv->rps.delayed_resume_work);

        ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
        if (ret)
                goto out;

        if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
                /* Convert GT frequency to 50 HZ units */
                min_gpu_freq =
                        dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
                max_gpu_freq =
                        dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER;
        } else {
                min_gpu_freq = dev_priv->rps.min_freq_softlimit;
                max_gpu_freq = dev_priv->rps.max_freq_softlimit;
        }

        seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");

        for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
                ia_freq = gpu_freq;
                sandybridge_pcode_read(dev_priv,
                                       GEN6_PCODE_READ_MIN_FREQ_TABLE,
                                       &ia_freq);
                seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
                           intel_gpu_freq(dev_priv, (gpu_freq *
                                (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
                                 GEN9_FREQ_SCALER : 1))),
                           ((ia_freq >> 0) & 0xff) * 100,
                           ((ia_freq >> 8) & 0xff) * 100);
        }

        mutex_unlock(&dev_priv->rps.hw_lock);

out:
        intel_runtime_pm_put(dev_priv);
        return ret;
}

static int i915_opregion(struct seq_file *m, void *unused)
{
        struct drm_info_node *node = m->private;
        struct drm_device *dev = node->minor->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct intel_opregion *opregion = &dev_priv->opregion;
        int ret;

        ret = mutex_lock_interruptible(&dev->struct_mutex);
        if (ret)
                goto out;

        if (opregion->header)
                seq_write(m, opregion->header, OPREGION_SIZE);

        mutex_unlock(&dev->struct_mutex);

out:
        return 0;
}

static int i915_vbt(struct seq_file *m, void *unused)
{
        struct drm_info_node *node = m->private;
        struct drm_device *dev = node->minor->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct intel_opregion *opregion = &dev_priv->opregion;

        if (opregion->vbt)
                seq_write(m, opregion->vbt, opregion->vbt_size);

        return 0;
}

static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
{
        struct drm_info_node *node = m->private;
        struct drm_device *dev = node->minor->dev;
        struct intel_framebuffer *fbdev_fb = NULL;
        struct drm_framebuffer *drm_fb;

#ifdef CONFIG_DRM_FBDEV_EMULATION
       if (to_i915(dev)->fbdev) {
               fbdev_fb = to_intel_framebuffer(to_i915(dev)->fbdev->helper.fb);

               seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
                         fbdev_fb->base.width,
                         fbdev_fb->base.height,
                         fbdev_fb->base.depth,
                         fbdev_fb->base.bits_per_pixel,
                         fbdev_fb->base.modifier[0],
                         atomic_read(&fbdev_fb->base.refcount.refcount));
               describe_obj(m, fbdev_fb->obj);
               seq_putc(m, '\n');
       }
#endif

        mutex_lock(&dev->mode_config.fb_lock);
        drm_for_each_fb(drm_fb, dev) {
                struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
                if (fb == fbdev_fb)
                        continue;

                seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
                           fb->base.width,
                           fb->base.height,
                           fb->base.depth,
                           fb->base.bits_per_pixel,
                           fb->base.modifier[0],
                           atomic_read(&fb->base.refcount.refcount));
                describe_obj(m, fb->obj);
                seq_putc(m, '\n');
        }
        mutex_unlock(&dev->mode_config.fb_lock);

        return 0;
}

static void describe_ctx_ringbuf(struct seq_file *m,
                                 struct intel_ringbuffer *ringbuf)
{
        seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
                   ringbuf->space, ringbuf->head, ringbuf->tail,
                   ringbuf->last_retired_head);
}

static int i915_context_status(struct seq_file *m, void *unused)
{
        struct drm_info_node *node = m->private;
        struct drm_device *dev = node->minor->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct intel_engine_cs *ring;
        struct intel_context *ctx;
        int ret, i;

        ret = mutex_lock_interruptible(&dev->struct_mutex);
        if (ret)
                return ret;

        list_for_each_entry(ctx, &dev_priv->context_list, link) {
                if (!i915.enable_execlists &&
                    ctx->legacy_hw_ctx.rcs_state == NULL)
                        continue;

                seq_puts(m, "HW context ");
                describe_ctx(m, ctx);
                if (ctx == dev_priv->kernel_context)
                        seq_printf(m, "(kernel context) ");

                if (i915.enable_execlists) {
                        seq_putc(m, '\n');
                        for_each_ring(ring, dev_priv, i) {
                                struct drm_i915_gem_object *ctx_obj =
                                        ctx->engine[i].state;
                                struct intel_ringbuffer *ringbuf =
                                        ctx->engine[i].ringbuf;

                                seq_printf(m, "%s: ", ring->name);
                                if (ctx_obj)
                                        describe_obj(m, ctx_obj);
                                if (ringbuf)
                                        describe_ctx_ringbuf(m, ringbuf);
                                seq_putc(m, '\n');
                        }
                } else {
                        describe_obj(m, ctx->legacy_hw_ctx.rcs_state);
                }

                seq_putc(m, '\n');
        }

        mutex_unlock(&dev->struct_mutex);

        return 0;
}

static void i915_dump_lrc_obj(struct seq_file *m,
                              struct intel_context *ctx,
                              struct intel_engine_cs *ring)
{
        struct page *page;

        uint32_t *reg_state;
        int j;
        struct drm_i915_gem_object *ctx_obj = ctx->engine[ring->id].state;
        unsigned long ggtt_offset = 0;

        if (ctx_obj == NULL) {
                seq_printf(m, "Context on %s with no gem object\n",
                           ring->name);
                return;
        }

        seq_printf(m, "CONTEXT: %s %u\n", ring->name,
                   intel_execlists_ctx_id(ctx, ring));

        if (!i915_gem_obj_ggtt_bound(ctx_obj))
                seq_puts(m, "\tNot bound in GGTT\n");
        else
                ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj);

        if (i915_gem_object_get_pages(ctx_obj)) {
                seq_puts(m, "\tFailed to get pages for context object\n");
                return;
        }

        page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
        if (!WARN_ON(page == NULL)) {
                reg_state = kmap_atomic(page);

                for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
                        seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
                                   ggtt_offset + 4096 + (j * 4),
                                   reg_state[j], reg_state[j + 1],
                                   reg_state[j + 2], reg_state[j + 3]);
                }
                kunmap_atomic(reg_state);
        }

        seq_putc(m, '\n');
}

static int i915_dump_lrc(struct seq_file *m, void *unused)
{
        struct drm_info_node *node = (struct drm_info_node *) m->private;
        struct drm_device *dev = node->minor->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct intel_engine_cs *ring;
        struct intel_context *ctx;
        int ret, i;

        if (!i915.enable_execlists) {
                seq_printf(m, "Logical Ring Contexts are disabled\n");
                return 0;
        }

        ret = mutex_lock_interruptible(&dev->struct_mutex);
        if (ret)
                return ret;

        list_for_each_entry(ctx, &dev_priv->context_list, link)
                if (ctx != dev_priv->kernel_context)
                        for_each_ring(ring, dev_priv, i)
                                i915_dump_lrc_obj(m, ctx, ring);

        mutex_unlock(&dev->struct_mutex);

        return 0;
}

static int i915_execlists(struct seq_file *m, void *data)
{
        struct drm_info_node *node = (struct drm_info_node *)m->private;
        struct drm_device *dev = node->minor->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct intel_engine_cs *ring;
        u32 status_pointer;
        u8 read_pointer;
        u8 write_pointer;
        u32 status;
        u32 ctx_id;
        struct list_head *cursor;
        int ring_id, i;
        int ret;

        if (!i915.enable_execlists) {
                seq_puts(m, "Logical Ring Contexts are disabled\n");
                return 0;
        }

        ret = mutex_lock_interruptible(&dev->struct_mutex);
        if (ret)
                return ret;

        intel_runtime_pm_get(dev_priv);

        for_each_ring(ring, dev_priv, ring_id) {
                struct drm_i915_gem_request *head_req = NULL;
                int count = 0;
                unsigned long flags;

                seq_printf(m, "%s\n", ring->name);

                status = I915_READ(RING_EXECLIST_STATUS_LO(ring));
                ctx_id = I915_READ(RING_EXECLIST_STATUS_HI(ring));
                seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
                           status, ctx_id);

                status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
                seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);

                read_pointer = ring->next_context_status_buffer;
                write_pointer = GEN8_CSB_WRITE_PTR(status_pointer);
                if (read_pointer > write_pointer)
                        write_pointer += GEN8_CSB_ENTRIES;
                seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
                           read_pointer, write_pointer);

                for (i = 0; i < GEN8_CSB_ENTRIES; i++) {
                        status = I915_READ(RING_CONTEXT_STATUS_BUF_LO(ring, i));
                        ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF_HI(ring, i));

                        seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
                                   i, status, ctx_id);
                }

                spin_lock_irqsave(&ring->execlist_lock, flags);
                list_for_each(cursor, &ring->execlist_queue)
                        count++;
                head_req = list_first_entry_or_null(&ring->execlist_queue,
                                struct drm_i915_gem_request, execlist_link);
                spin_unlock_irqrestore(&ring->execlist_lock, flags);

                seq_printf(m, "\t%d requests in queue\n", count);
                if (head_req) {
                        seq_printf(m, "\tHead request id: %u\n",
                                   intel_execlists_ctx_id(head_req->ctx, ring));
                        seq_printf(m, "\tHead request tail: %u\n",
                                   head_req->tail);
                }

                seq_putc(m, '\n');
        }

        intel_runtime_pm_put(dev_priv);
        mutex_unlock(&dev->struct_mutex);

        return 0;
}

static const char *swizzle_string(unsigned swizzle)
{
        switch (swizzle) {
        case I915_BIT_6_SWIZZLE_NONE:
                return "none";
        case I915_BIT_6_SWIZZLE_9:
                return "bit9";
        case I915_BIT_6_SWIZZLE_9_10:
                return "bit9/bit10";
        case I915_BIT_6_SWIZZLE_9_11:
                return "bit9/bit11";
        case I915_BIT_6_SWIZZLE_9_10_11:
                return "bit9/bit10/bit11";
        case I915_BIT_6_SWIZZLE_9_17:
                return "bit9/bit17";
        case I915_BIT_6_SWIZZLE_9_10_17:
                return "bit9/bit10/bit17";
        case I915_BIT_6_SWIZZLE_UNKNOWN:
                return "unknown";
        }

        return "bug";
}

static int i915_swizzle_info(struct seq_file *m, void *data)
{
        struct drm_info_node *node = m->private;
        struct drm_device *dev = node->minor->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        int ret;

        ret = mutex_lock_interruptible(&dev->struct_mutex);
        if (ret)
                return ret;
        intel_runtime_pm_get(dev_priv);

        seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
                   swizzle_string(dev_priv->mm.bit_6_swizzle_x));
        seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
                   swizzle_string(dev_priv->mm.bit_6_swizzle_y));

        if (IS_GEN3(dev) || IS_GEN4(dev)) {
                seq_printf(m, "DDC = 0x%08x\n",
                           I915_READ(DCC));
                seq_printf(m, "DDC2 = 0x%08x\n",
                           I915_READ(DCC2));
                seq_printf(m, "C0DRB3 = 0x%04x\n",
                           I915_READ16(C0DRB3));
                seq_printf(m, "C1DRB3 = 0x%04x\n",
                           I915_READ16(C1DRB3));
        } else if (INTEL_INFO(dev)->gen >= 6) {
                seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
                           I915_READ(MAD_DIMM_C0));
                seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
                           I915_READ(MAD_DIMM_C1));
                seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
                           I915_READ(MAD_DIMM_C2));
                seq_printf(m, "TILECTL = 0x%08x\n",
                           I915_READ(TILECTL));
                if (INTEL_INFO(dev)->gen >= 8)
                        seq_printf(m, "GAMTARBMODE = 0x%08x\n",
                                   I915_READ(GAMTARBMODE));
                else
                        seq_printf(m, "ARB_MODE = 0x%08x\n",
                                   I915_READ(ARB_MODE));
                seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
                           I915_READ(DISP_ARB_CTL));
        }

        if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
                seq_puts(m, "L-shaped memory detected\n");

        intel_runtime_pm_put(dev_priv);
        mutex_unlock(&dev->struct_mutex);

        return 0;
}

static int per_file_ctx(int id, void *ptr, void *data)
{
        struct intel_context *ctx = ptr;
        struct seq_file *m = data;
        struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;

        if (!ppgtt) {
                seq_printf(m, "  no ppgtt for context %d\n",
                           ctx->user_handle);
                return 0;
        }

        if (i915_gem_context_is_default(ctx))
                seq_puts(m, "  default context:\n");
        else
                seq_printf(m, "  context %d:\n", ctx->user_handle);
        ppgtt->debug_dump(ppgtt, m);

        return 0;
}

static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
{
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct intel_engine_cs *ring;
        struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
        int unused, i;

        if (!ppgtt)
                return;

        for_each_ring(ring, dev_priv, unused) {
                seq_printf(m, "%s\n", ring->name);
                for (i = 0; i < 4; i++) {
                        u64 pdp = I915_READ(GEN8_RING_PDP_UDW(ring, i));
                        pdp <<= 32;
                        pdp |= I915_READ(GEN8_RING_PDP_LDW(ring, i));
                        seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
                }
        }
}

static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
{
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct intel_engine_cs *ring;
        int i;

        if (INTEL_INFO(dev)->gen == 6)
                seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));

        for_each_ring(ring, dev_priv, i) {
                seq_printf(m, "%s\n", ring->name);
                if (INTEL_INFO(dev)->gen == 7)
                        seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
                seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
                seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
                seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
        }
        if (dev_priv->mm.aliasing_ppgtt) {
                struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;

                seq_puts(m, "aliasing PPGTT:\n");
                seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);

                ppgtt->debug_dump(ppgtt, m);
        }

        seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
}

static int i915_ppgtt_info(struct seq_file *m, void *data)
{
        struct drm_info_node *node = m->private;
        struct drm_device *dev = node->minor->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct drm_file *file;

        int ret = mutex_lock_interruptible(&dev->struct_mutex);
        if (ret)
                return ret;
        intel_runtime_pm_get(dev_priv);

        if (INTEL_INFO(dev)->gen >= 8)
                gen8_ppgtt_info(m, dev);
        else if (INTEL_INFO(dev)->gen >= 6)
                gen6_ppgtt_info(m, dev);

        list_for_each_entry_reverse(file, &dev->filelist, lhead) {
                struct drm_i915_file_private *file_priv = file->driver_priv;
                struct task_struct *task;

                task = get_pid_task(file->pid, PIDTYPE_PID);
                if (!task) {
                        ret = -ESRCH;
                        goto out_put;
                }
                seq_printf(m, "\nproc: %s\n", task->comm);
                put_task_struct(task);
                idr_for_each(&file_priv->context_idr, per_file_ctx,
                             (void *)(unsigned long)m);
        }

out_put:
        intel_runtime_pm_put(dev_priv);
        mutex_unlock(&dev->struct_mutex);

        return ret;
}

static int count_irq_waiters(struct drm_i915_private *i915)
{
        struct intel_engine_cs *ring;
        int count = 0;
        int i;

        for_each_ring(ring, i915, i)
                count += ring->irq_refcount;

        return count;
}

static int i915_rps_boost_info(struct seq_file *m, void *data)
{
        struct drm_info_node *node = m->private;
        struct drm_device *dev = node->minor->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct drm_file *file;

        seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
        seq_printf(m, "GPU busy? %d\n", dev_priv->mm.busy);
        seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
        seq_printf(m, "Frequency requested %d; min hard:%d, soft:%d; max soft:%d, hard:%d\n",
                   intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
                   intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
                   intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit),
                   intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit),
                   intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
        spin_lock(&dev_priv->rps.client_lock);
        list_for_each_entry_reverse(file, &dev->filelist, lhead) {
                struct drm_i915_file_private *file_priv = file->driver_priv;
                struct task_struct *task;

                rcu_read_lock();
                task = pid_task(file->pid, PIDTYPE_PID);
                seq_printf(m, "%s [%d]: %d boosts%s\n",
                           task ? task->comm : "<unknown>",
                           task ? task->pid : -1,
                           file_priv->rps.boosts,
                           list_empty(&file_priv->rps.link) ? "" : ", active");
                rcu_read_unlock();
        }
        seq_printf(m, "Semaphore boosts: %d%s\n",
                   dev_priv->rps.semaphores.boosts,
                   list_empty(&dev_priv->rps.semaphores.link) ? "" : ", active");
        seq_printf(m, "MMIO flip boosts: %d%s\n",
                   dev_priv->rps.mmioflips.boosts,
                   list_empty(&dev_priv->rps.mmioflips.link) ? "" : ", active");
        seq_printf(m, "Kernel boosts: %d\n", dev_priv->rps.boosts);
        spin_unlock(&dev_priv->rps.client_lock);

        return 0;
}

static int i915_llc(struct seq_file *m, void *data)
{
        struct drm_info_node *node = m->private;
        struct drm_device *dev = node->minor->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;

        /* Size calculation for LLC is a bit of a pain. Ignore for now. */
        seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
        seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);

        return 0;
}

static int i915_guc_load_status_info(struct seq_file *m, void *data)
{
        struct drm_info_node *node = m->private;
        struct drm_i915_private *dev_priv = node->minor->dev->dev_private;
        struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
        u32 tmp, i;

        if (!HAS_GUC_UCODE(dev_priv->dev))
                return 0;

        seq_printf(m, "GuC firmware status:\n");
        seq_printf(m, "\tpath: %s\n",
                guc_fw->guc_fw_path);
        seq_printf(m, "\tfetch: %s\n",
                intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
        seq_printf(m, "\tload: %s\n",
                intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
        seq_printf(m, "\tversion wanted: %d.%d\n",
                guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
        seq_printf(m, "\tversion found: %d.%d\n",
                guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
        seq_printf(m, "\theader: offset is %d; size = %d\n",
                guc_fw->header_offset, guc_fw->header_size);
        seq_printf(m, "\tuCode: offset is %d; size = %d\n",
                guc_fw->ucode_offset, guc_fw->ucode_size);
        seq_printf(m, "\tRSA: offset is %d; size = %d\n",
                guc_fw->rsa_offset, guc_fw->rsa_size);

        tmp = I915_READ(GUC_STATUS);

        seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
        seq_printf(m, "\tBootrom status = 0x%x\n",
                (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
        seq_printf(m, "\tuKernel status = 0x%x\n",
                (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
        seq_printf(m, "\tMIA Core status = 0x%x\n",
                (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);
        seq_puts(m, "\nScratch registers:\n");
        for (i = 0; i < 16; i++)
                seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));

        return 0;
}

static void i915_guc_client_info(struct seq_file *m,
                                 struct drm_i915_private *dev_priv,
                                 struct i915_guc_client *client)
{
        struct intel_engine_cs *ring;
        uint64_t tot = 0;
        uint32_t i;

        seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",
                client->priority, client->ctx_index, client->proc_desc_offset);
        seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n",
                client->doorbell_id, client->doorbell_offset, client->cookie);
        seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n",
                client->wq_size, client->wq_offset, client->wq_tail);

        seq_printf(m, "\tFailed to queue: %u\n", client->q_fail);
        seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail);
        seq_printf(m, "\tLast submission result: %d\n", client->retcode);

        for_each_ring(ring, dev_priv, i) {
                seq_printf(m, "\tSubmissions: %llu %s\n",
                                client->submissions[ring->guc_id],
                                ring->name);
                tot += client->submissions[ring->guc_id];
        }
        seq_printf(m, "\tTotal: %llu\n", tot);
}

static int i915_guc_info(struct seq_file *m, void *data)
{
        struct drm_info_node *node = m->private;
        struct drm_device *dev = node->minor->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct intel_guc guc;
        struct i915_guc_client client = {};
        struct intel_engine_cs *ring;
        enum intel_ring_id i;
        u64 total = 0;

        if (!HAS_GUC_SCHED(dev_priv->dev))
                return 0;

        if (mutex_lock_interruptible(&dev->struct_mutex))
                return 0;

        /* Take a local copy of the GuC data, so we can dump it at leisure */
        guc = dev_priv->guc;
        if (guc.execbuf_client)
                client = *guc.execbuf_client;

        mutex_unlock(&dev->struct_mutex);

        seq_printf(m, "GuC total action count: %llu\n", guc.action_count);
        seq_printf(m, "GuC action failure count: %u\n", guc.action_fail);
        seq_printf(m, "GuC last action command: 0x%x\n", guc.action_cmd);
        seq_printf(m, "GuC last action status: 0x%x\n", guc.action_status);
        seq_printf(m, "GuC last action error code: %d\n", guc.action_err);

        seq_printf(m, "\nGuC submissions:\n");
        for_each_ring(ring, dev_priv, i) {
                seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x\n",
                        ring->name, guc.submissions[ring->guc_id],
                        guc.last_seqno[ring->guc_id]);
                total += guc.submissions[ring->guc_id];
        }
        seq_printf(m, "\t%s: %llu\n", "Total", total);

        seq_printf(m, "\nGuC execbuf client @ %p:\n", guc.execbuf_client);
        i915_guc_client_info(m, dev_priv, &client);

        /* Add more as required ... */

        return 0;
}

static int i915_guc_log_dump(struct seq_file *m, void *data)
{
        struct drm_info_node *node = m->private;
        struct drm_device *dev = node->minor->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct drm_i915_gem_object *log_obj = dev_priv->guc.log_obj;
        u32 *log;
        int i = 0, pg;

        if (!log_obj)
                return 0;

        for (pg = 0; pg < log_obj->base.size / PAGE_SIZE; pg++) {
                log = kmap_atomic(i915_gem_object_get_page(log_obj, pg));

                for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4)
                        seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
                                   *(log + i), *(log + i + 1),
                                   *(log + i + 2), *(log + i + 3));

                kunmap_atomic(log);
        }

        seq_putc(m, '\n');

        return 0;
}

static int i915_edp_psr_status(struct seq_file *m, void *data)
{
        struct drm_info_node *node = m->private;
        struct drm_device *dev = node->minor->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        u32 psrperf = 0;
        u32 stat[3];
        enum pipe pipe;
        bool enabled = false;

        if (!HAS_PSR(dev)) {
                seq_puts(m, "PSR not supported\n");
                return 0;
        }

        intel_runtime_pm_get(dev_priv);

        mutex_lock(&dev_priv->psr.lock);
        seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
        seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
        seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
        seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
        seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
                   dev_priv->psr.busy_frontbuffer_bits);
        seq_printf(m, "Re-enable work scheduled: %s\n",
                   yesno(work_busy(&dev_priv->psr.work.work)));

        if (HAS_DDI(dev))
                enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
        else {
                for_each_pipe(dev_priv, pipe) {
                        stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
                                VLV_EDP_PSR_CURR_STATE_MASK;
                        if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
                            (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
                                enabled = true;
                }
        }

        seq_printf(m, "Main link in standby mode: %s\n",
                   yesno(dev_priv->psr.link_standby));

        seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));

        if (!HAS_DDI(dev))
                for_each_pipe(dev_priv, pipe) {
                        if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
                            (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
                                seq_printf(m, " pipe %c", pipe_name(pipe));
                }
        seq_puts(m, "\n");

        /*
         * VLV/CHV PSR has no kind of performance counter
         * SKL+ Perf counter is reset to 0 everytime DC state is entered
         */
        if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
                psrperf = I915_READ(EDP_PSR_PERF_CNT) &
                        EDP_PSR_PERF_CNT_MASK;

                seq_printf(m, "Performance_Counter: %u\n", psrperf);
        }
        mutex_unlock(&dev_priv->psr.lock);

        intel_runtime_pm_put(dev_priv);
        return 0;
}

static int i915_sink_crc(struct seq_file *m, void *data)
{
        struct drm_info_node *node = m->private;
        struct drm_device *dev = node->minor->dev;
        struct intel_encoder *encoder;
        struct intel_connector *connector;
        struct intel_dp *intel_dp = NULL;
        int ret;
        u8 crc[6];

        drm_modeset_lock_all(dev);
        for_each_intel_connector(dev, connector) {

                if (connector->base.dpms != DRM_MODE_DPMS_ON)
                        continue;

                if (!connector->base.encoder)
                        continue;

                encoder = to_intel_encoder(connector->base.encoder);
                if (encoder->type != INTEL_OUTPUT_EDP)
                        continue;

                intel_dp = enc_to_intel_dp(&encoder->base);

                ret = intel_dp_sink_crc(intel_dp, crc);
                if (ret)
                        goto out;

                seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
                           crc[0], crc[1], crc[2],
                           crc[3], crc[4], crc[5]);
                goto out;
        }
        ret = -ENODEV;
out:
        drm_modeset_unlock_all(dev);
        return ret;
}

static int i915_energy_uJ(struct seq_file *m, void *data)
{
        struct drm_info_node *node = m->private;
        struct drm_device *dev = node->minor->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        u64 power;
        u32 units;

        if (INTEL_INFO(dev)->gen < 6)
                return -ENODEV;

        intel_runtime_pm_get(dev_priv);

        rdmsrl(MSR_RAPL_POWER_UNIT, power);
        power = (power & 0x1f00) >> 8;
        units = 1000000 / (1 << power); /* convert to uJ */
        power = I915_READ(MCH_SECP_NRG_STTS);
        power *= units;

        intel_runtime_pm_put(dev_priv);

        seq_printf(m, "%llu", (long long unsigned)power);

        return 0;
}

static int i915_runtime_pm_status(struct seq_file *m, void *unused)
{
        struct drm_info_node *node = m->private;
        struct drm_device *dev = node->minor->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;

        if (!HAS_RUNTIME_PM(dev)) {
                seq_puts(m, "not supported\n");
                return 0;
        }

        seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
        seq_printf(m, "IRQs disabled: %s\n",
                   yesno(!intel_irqs_enabled(dev_priv)));
#ifdef CONFIG_PM
        seq_printf(m, "Usage count: %d\n",
                   atomic_read(&dev->dev->power.usage_count));
#else
        seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
#endif

        return 0;
}

static int i915_power_domain_info(struct seq_file *m, void *unused)
{
        struct drm_info_node *node = m->private;
        struct drm_device *dev = node->minor->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct i915_power_domains *power_domains = &dev_priv->power_domains;
        int i;

        mutex_lock(&power_domains->lock);

        seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
        for (i = 0; i < power_domains->power_well_count; i++) {
                struct i915_power_well *power_well;
                enum intel_display_power_domain power_domain;

                power_well = &power_domains->power_wells[i];
                seq_printf(m, "%-25s %d\n", power_well->name,
                           power_well->count);

                for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
                     power_domain++) {
                        if (!(BIT(power_domain) & power_well->domains))
                                continue;

                        seq_printf(m, "  %-23s %d\n",
                                 intel_display_power_domain_str(power_domain),
                                 power_domains->domain_use_count[power_domain]);
                }
        }

        mutex_unlock(&power_domains->lock);

        return 0;
}

static int i915_dmc_info(struct seq_file *m, void *unused)
{
        struct drm_info_node *node = m->private;
        struct drm_device *dev = node->minor->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct intel_csr *csr;

        if (!HAS_CSR(dev)) {
                seq_puts(m, "not supported\n");
                return 0;
        }

        csr = &dev_priv->csr;

        intel_runtime_pm_get(dev_priv);

        seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
        seq_printf(m, "path: %s\n", csr->fw_path);

        if (!csr->dmc_payload)
                goto out;

        seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
                   CSR_VERSION_MINOR(csr->version));

        if (IS_SKYLAKE(dev) && csr->version >= CSR_VERSION(1, 6)) {
                seq_printf(m, "DC3 -> DC5 count: %d\n",
                           I915_READ(SKL_CSR_DC3_DC5_COUNT));
                seq_printf(m, "DC5 -> DC6 count: %d\n",
                           I915_READ(SKL_CSR_DC5_DC6_COUNT));
        } else if (IS_BROXTON(dev) && csr->version >= CSR_VERSION(1, 4)) {
                seq_printf(m, "DC3 -> DC5 count: %d\n",
                           I915_READ(BXT_CSR_DC3_DC5_COUNT));
        }

out:
        seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
        seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
        seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));

        intel_runtime_pm_put(dev_priv);

        return 0;
}

static void intel_seq_print_mode(struct seq_file *m, int tabs,
                                 struct drm_display_mode *mode)
{
        int i;

        for (i = 0; i < tabs; i++)
                seq_putc(m, '\t');

        seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
                   mode->base.id, mode->name,
                   mode->vrefresh, mode->clock,
                   mode->hdisplay, mode->hsync_start,
                   mode->hsync_end, mode->htotal,
                   mode->vdisplay, mode->vsync_start,
                   mode->vsync_end, mode->vtotal,
                   mode->type, mode->flags);
}

static void intel_encoder_info(struct seq_file *m,
                               struct intel_crtc *intel_crtc,
                               struct intel_encoder *intel_encoder)
{
        struct drm_info_node *node = m->private;
        struct drm_device *dev = node->minor->dev;
        struct drm_crtc *crtc = &intel_crtc->base;
        struct intel_connector *intel_connector;
        struct drm_encoder *encoder;

        encoder = &intel_encoder->base;
        seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
                   encoder->base.id, encoder->name);
        for_each_connector_on_encoder(dev, encoder, intel_connector) {
                struct drm_connector *connector = &intel_connector->base;
                seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
                           connector->base.id,
                           connector->name,
                           drm_get_connector_status_name(connector->status));
                if (connector->status == connector_status_connected) {
                        struct drm_display_mode *mode = &crtc->mode;
                        seq_printf(m, ", mode:\n");
                        intel_seq_print_mode(m, 2, mode);
                } else {
                        seq_putc(m, '\n');
                }
        }
}

static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
{
        struct drm_info_node *node = m->private;
        struct drm_device *dev = node->minor->dev;
        struct drm_crtc *crtc = &intel_crtc->base;
        struct intel_encoder *intel_encoder;
        struct drm_plane_state *plane_state = crtc->primary->state;
        struct drm_framebuffer *fb = plane_state->fb;

        if (fb)
                seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
                           fb->base.id, plane_state->src_x >> 16,
                           plane_state->src_y >> 16, fb->width, fb->height);
        else
                seq_puts(m, "\tprimary plane disabled\n");
        for_each_encoder_on_crtc(dev, crtc, intel_encoder)
                intel_encoder_info(m, intel_crtc, intel_encoder);
}

static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
{
        struct drm_display_mode *mode = panel->fixed_mode;

        seq_printf(m, "\tfixed mode:\n");
        intel_seq_print_mode(m, 2, mode);
}

static void intel_dp_info(struct seq_file *m,
                          struct intel_connector *intel_connector)
{
        struct intel_encoder *intel_encoder = intel_connector->encoder;
        struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);

        seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
        seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
        if (intel_encoder->type == INTEL_OUTPUT_EDP)
                intel_panel_info(m, &intel_connector->panel);
}

static void intel_hdmi_info(struct seq_file *m,
                            struct intel_connector *intel_connector)
{
        struct intel_encoder *intel_encoder = intel_connector->encoder;
        struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);

        seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));
}

static void intel_lvds_info(struct seq_file *m,
                            struct intel_connector *intel_connector)
{
        intel_panel_info(m, &intel_connector->panel);
}

static void intel_connector_info(struct seq_file *m,
                                 struct drm_connector *connector)
{
        struct intel_connector *intel_connector = to_intel_connector(connector);
        struct intel_encoder *intel_encoder = intel_connector->encoder;
        struct drm_display_mode *mode;

        seq_printf(m, "connector %d: type %s, status: %s\n",
                   connector->base.id, connector->name,
                   drm_get_connector_status_name(connector->status));
        if (connector->status == connector_status_connected) {
                seq_printf(m, "\tname: %s\n", connector->display_info.name);
                seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
                           connector->display_info.width_mm,
                           connector->display_info.height_mm);
                seq_printf(m, "\tsubpixel order: %s\n",
                           drm_get_subpixel_order_name(connector->display_info.subpixel_order));
                seq_printf(m, "\tCEA rev: %d\n",
                           connector->display_info.cea_rev);
        }
        if (intel_encoder) {
                if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
                    intel_encoder->type == INTEL_OUTPUT_EDP)
                        intel_dp_info(m, intel_connector);
                else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
                        intel_hdmi_info(m, intel_connector);
                else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
                        intel_lvds_info(m, intel_connector);
        }

        seq_printf(m, "\tmodes:\n");
        list_for_each_entry(mode, &connector->modes, head)
                intel_seq_print_mode(m, 2, mode);
}

static bool cursor_active(struct drm_device *dev, int pipe)
{
        struct drm_i915_private *dev_priv = dev->dev_private;
        u32 state;

        if (IS_845G(dev) || IS_I865G(dev))
                state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
        else
                state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;

        return state;
}

static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
{
        struct drm_i915_private *dev_priv = dev->dev_private;
        u32 pos;

        pos = I915_READ(CURPOS(pipe));

        *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
        if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
                *x = -*x;

        *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
        if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
                *y = -*y;

        return cursor_active(dev, pipe);
}

static const char *plane_type(enum drm_plane_type type)
{
        switch (type) {
        case DRM_PLANE_TYPE_OVERLAY:
                return "OVL";
        case DRM_PLANE_TYPE_PRIMARY:
                return "PRI";
        case DRM_PLANE_TYPE_CURSOR:
                return "CUR";
        /*
         * Deliberately omitting default: to generate compiler warnings
         * when a new drm_plane_type gets added.
         */
        }

        return "unknown";
}

static const char *plane_rotation(unsigned int rotation)
{
        static char buf[48];
        /*
         * According to doc only one DRM_ROTATE_ is allowed but this
         * will print them all to visualize if the values are misused
         */
        snprintf(buf, sizeof(buf),
                 "%s%s%s%s%s%s(0x%08x)",
                 (rotation & BIT(DRM_ROTATE_0)) ? "0 " : "",
                 (rotation & BIT(DRM_ROTATE_90)) ? "90 " : "",
                 (rotation & BIT(DRM_ROTATE_180)) ? "180 " : "",
                 (rotation & BIT(DRM_ROTATE_270)) ? "270 " : "",
                 (rotation & BIT(DRM_REFLECT_X)) ? "FLIPX " : "",
                 (rotation & BIT(DRM_REFLECT_Y)) ? "FLIPY " : "",
                 rotation);

        return buf;
}

static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc)
{
        struct drm_info_node *node = m->private;
        struct drm_device *dev = node->minor->dev;
        struct intel_plane *intel_plane;

        for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {