LXR linux/drivers/gpu/drm/msm/mdp/mdp4/mdp4

   1/*
   2 * Copyright (C) 2013 Red Hat
   3 * Author: Rob Clark <robdclark@gmail.com>
   4 *
   5 * This program is free software; you can redistribute it and/or modify it
   6 * under the terms of the GNU General Public License version 2 as published by
   7 * the Free Software Foundation.
   8 *
   9 * This program is distributed in the hope that it will be useful, but WITHOUT
  10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12 * more details.
  13 *
  14 * You should have received a copy of the GNU General Public License along with
  15 * this program.  If not, see <http://www.gnu.org/licenses/>.
  16 */
  17
  18#ifndef __MDP4_KMS_H__
  19#define __MDP4_KMS_H__
  20
  21#include "msm_drv.h"
  22#include "msm_kms.h"
  23#include "mdp/mdp_kms.h"
  24#include "mdp4.xml.h"
  25
  26#include "drm_panel.h"
  27
  28struct mdp4_kms {
  29        struct mdp_kms base;
  30
  31        struct drm_device *dev;
  32
  33        int rev;
  34
  35        /* mapper-id used to request GEM buffer mapped for scanout: */
  36        int id;
  37
  38        void __iomem *mmio;
  39
  40        struct regulator *dsi_pll_vdda;
  41        struct regulator *dsi_pll_vddio;
  42        struct regulator *vdd;
  43
  44        struct clk *clk;
  45        struct clk *pclk;
  46        struct clk *lut_clk;
  47        struct clk *axi_clk;
  48        struct msm_mmu *mmu;
  49
  50        struct mdp_irq error_handler;
  51
  52        /* empty/blank cursor bo to use when cursor is "disabled" */
  53        struct drm_gem_object *blank_cursor_bo;
  54        uint32_t blank_cursor_iova;
  55};
  56#define to_mdp4_kms(x) container_of(x, struct mdp4_kms, base)
  57
  58/* platform config data (ie. from DT, or pdata) */
  59struct mdp4_platform_config {
  60        struct iommu_domain *iommu;
  61        uint32_t max_clk;
  62};
  63
  64static inline void mdp4_write(struct mdp4_kms *mdp4_kms, u32 reg, u32 data)
  65{
  66        msm_writel(data, mdp4_kms->mmio + reg);
  67}
  68
  69static inline u32 mdp4_read(struct mdp4_kms *mdp4_kms, u32 reg)
  70{
  71        return msm_readl(mdp4_kms->mmio + reg);
  72}
  73
  74static inline uint32_t pipe2flush(enum mdp4_pipe pipe)
  75{
  76        switch (pipe) {
  77        case VG1:      return MDP4_OVERLAY_FLUSH_VG1;
  78        case VG2:      return MDP4_OVERLAY_FLUSH_VG2;
  79        case RGB1:     return MDP4_OVERLAY_FLUSH_RGB1;
  80        case RGB2:     return MDP4_OVERLAY_FLUSH_RGB2;
  81        default:       return 0;
  82        }
  83}
  84
  85static inline uint32_t ovlp2flush(int ovlp)
  86{
  87        switch (ovlp) {
  88        case 0:        return MDP4_OVERLAY_FLUSH_OVLP0;
  89        case 1:        return MDP4_OVERLAY_FLUSH_OVLP1;
  90        default:       return 0;
  91        }
  92}
  93
  94static inline uint32_t dma2irq(enum mdp4_dma dma)
  95{
  96        switch (dma) {
  97        case DMA_P:    return MDP4_IRQ_DMA_P_DONE;
  98        case DMA_S:    return MDP4_IRQ_DMA_S_DONE;
  99        case DMA_E:    return MDP4_IRQ_DMA_E_DONE;
 100        default:       return 0;
 101        }
 102}
 103
 104static inline uint32_t dma2err(enum mdp4_dma dma)
 105{
 106        switch (dma) {
 107        case DMA_P:    return MDP4_IRQ_PRIMARY_INTF_UDERRUN;
 108        case DMA_S:    return 0;  // ???
 109        case DMA_E:    return MDP4_IRQ_EXTERNAL_INTF_UDERRUN;
 110        default:       return 0;
 111        }
 112}
 113
 114static inline uint32_t mixercfg(uint32_t mixer_cfg, int mixer,
 115                enum mdp4_pipe pipe, enum mdp_mixer_stage_id stage)
 116{
 117        switch (pipe) {
 118        case VG1:
 119                mixer_cfg &= ~(MDP4_LAYERMIXER_IN_CFG_PIPE0__MASK |
 120                                MDP4_LAYERMIXER_IN_CFG_PIPE0_MIXER1);
 121                mixer_cfg |= MDP4_LAYERMIXER_IN_CFG_PIPE0(stage) |
 122                        COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE0_MIXER1);
 123                break;
 124        case VG2:
 125                mixer_cfg &= ~(MDP4_LAYERMIXER_IN_CFG_PIPE1__MASK |
 126                                MDP4_LAYERMIXER_IN_CFG_PIPE1_MIXER1);
 127                mixer_cfg |= MDP4_LAYERMIXER_IN_CFG_PIPE1(stage) |
 128                        COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE1_MIXER1);
 129                break;
 130        case RGB1:
 131                mixer_cfg &= ~(MDP4_LAYERMIXER_IN_CFG_PIPE2__MASK |
 132                                MDP4_LAYERMIXER_IN_CFG_PIPE2_MIXER1);
 133                mixer_cfg |= MDP4_LAYERMIXER_IN_CFG_PIPE2(stage) |
 134                        COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE2_MIXER1);
 135                break;
 136        case RGB2:
 137                mixer_cfg &= ~(MDP4_LAYERMIXER_IN_CFG_PIPE3__MASK |
 138                                MDP4_LAYERMIXER_IN_CFG_PIPE3_MIXER1);
 139                mixer_cfg |= MDP4_LAYERMIXER_IN_CFG_PIPE3(stage) |
 140                        COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE3_MIXER1);
 141                break;
 142        case RGB3:
 143                mixer_cfg &= ~(MDP4_LAYERMIXER_IN_CFG_PIPE4__MASK |
 144                                MDP4_LAYERMIXER_IN_CFG_PIPE4_MIXER1);
 145                mixer_cfg |= MDP4_LAYERMIXER_IN_CFG_PIPE4(stage) |
 146                        COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE4_MIXER1);
 147                break;
 148        case VG3:
 149                mixer_cfg &= ~(MDP4_LAYERMIXER_IN_CFG_PIPE5__MASK |
 150                                MDP4_LAYERMIXER_IN_CFG_PIPE5_MIXER1);
 151                mixer_cfg |= MDP4_LAYERMIXER_IN_CFG_PIPE5(stage) |
 152                        COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE5_MIXER1);
 153                break;
 154        case VG4:
 155                mixer_cfg &= ~(MDP4_LAYERMIXER_IN_CFG_PIPE6__MASK |
 156                                MDP4_LAYERMIXER_IN_CFG_PIPE6_MIXER1);
 157                mixer_cfg |= MDP4_LAYERMIXER_IN_CFG_PIPE6(stage) |
 158                        COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE6_MIXER1);
 159                break;
 160        default:
 161                WARN(1, "invalid pipe");
 162                break;
 163        }
 164
 165        return mixer_cfg;
 166}
 167
 168int mdp4_disable(struct mdp4_kms *mdp4_kms);
 169int mdp4_enable(struct mdp4_kms *mdp4_kms);
 170
 171void mdp4_set_irqmask(struct mdp_kms *mdp_kms, uint32_t irqmask,
 172                uint32_t old_irqmask);
 173void mdp4_irq_preinstall(struct msm_kms *kms);
 174int mdp4_irq_postinstall(struct msm_kms *kms);
 175void mdp4_irq_uninstall(struct msm_kms *kms);
 176irqreturn_t mdp4_irq(struct msm_kms *kms);
 177int mdp4_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc);
 178void mdp4_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc);
 179
 180static inline uint32_t mdp4_pipe_caps(enum mdp4_pipe pipe)
 181{
 182        switch (pipe) {
 183        case VG1:
 184        case VG2:
 185        case VG3:
 186        case VG4:
 187                return MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
 188                                MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC;
 189        case RGB1:
 190        case RGB2:
 191        case RGB3:
 192                return MDP_PIPE_CAP_SCALE;
 193        default:
 194                return 0;
 195        }
 196}
 197
 198enum mdp4_pipe mdp4_plane_pipe(struct drm_plane *plane);
 199struct drm_plane *mdp4_plane_init(struct drm_device *dev,
 200                enum mdp4_pipe pipe_id, bool private_plane);
 201
 202uint32_t mdp4_crtc_vblank(struct drm_crtc *crtc);
 203void mdp4_crtc_set_config(struct drm_crtc *crtc, uint32_t config);
 204void mdp4_crtc_set_intf(struct drm_crtc *crtc, enum mdp4_intf intf, int mixer);
 205void mdp4_crtc_wait_for_commit_done(struct drm_crtc *crtc);
 206struct drm_crtc *mdp4_crtc_init(struct drm_device *dev,
 207                struct drm_plane *plane, int id, int ovlp_id,
 208                enum mdp4_dma dma_id);
 209
 210long mdp4_dtv_round_pixclk(struct drm_encoder *encoder, unsigned long rate);
 211struct drm_encoder *mdp4_dtv_encoder_init(struct drm_device *dev);
 212
 213long mdp4_lcdc_round_pixclk(struct drm_encoder *encoder, unsigned long rate);
 214struct drm_encoder *mdp4_lcdc_encoder_init(struct drm_device *dev,
 215                struct device_node *panel_node);
 216
 217struct drm_connector *mdp4_lvds_connector_init(struct drm_device *dev,
 218                struct device_node *panel_node, struct drm_encoder *encoder);
 219
 220#ifdef CONFIG_DRM_MSM_DSI
 221struct drm_encoder *mdp4_dsi_encoder_init(struct drm_device *dev);
 222#else
 223static inline struct drm_encoder *mdp4_dsi_encoder_init(struct drm_device *dev)
 224{
 225        return ERR_PTR(-ENODEV);
 226}
 227#endif
 228
 229#ifdef CONFIG_COMMON_CLK
 230struct clk *mpd4_lvds_pll_init(struct drm_device *dev);
 231#else
 232static inline struct clk *mpd4_lvds_pll_init(struct drm_device *dev)
 233{
 234        return ERR_PTR(-ENODEV);
 235}
 236#endif
 237
 238#ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING
 239static inline int match_dev_name(struct device *dev, void *data)
 240{
 241        return !strcmp(dev_name(dev), data);
 242}
 243/* bus scaling data is associated with extra pointless platform devices,
 244 * "dtv", etc.. this is a bit of a hack, but we need a way for encoders
 245 * to find their pdata to make the bus-scaling stuff work.
 246 */
 247static inline void *mdp4_find_pdata(const char *devname)
 248{
 249        struct device *dev;
 250        dev = bus_find_device(&platform_bus_type, NULL,
 251                        (void *)devname, match_dev_name);
 252        return dev ? dev->platform_data : NULL;
 253}
 254#endif
 255
 256#endif /* __MDP4_KMS_H__ */
 257